From 90eb10774f1c53d2364eacf9fa8f0c7a92b1b824 Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Mon, 10 Oct 2022 14:59:24 -0700 Subject: [PATCH] 520.61.05 --- CHANGELOG.md | 14 + Makefile | 26 +- README.md | 8 +- kernel-open/Kbuild | 2 +- kernel-open/common/inc/cpuopsys.h | 16 - kernel-open/common/inc/nv-linux.h | 106 +- kernel-open/common/inc/nv-mm.h | 101 +- kernel-open/common/inc/nv-proto.h | 3 - kernel-open/common/inc/nv.h | 93 +- kernel-open/common/inc/nv_uvm_interface.h | 185 +- kernel-open/common/inc/nv_uvm_types.h | 65 +- kernel-open/common/inc/nvkms-kapi.h | 12 + kernel-open/common/inc/nvlimits.h | 7 - kernel-open/common/inc/os-interface.h | 27 +- kernel-open/common/inc/rm-gpu-ops.h | 13 +- kernel-open/conftest.sh | 152 +- kernel-open/count-lines.mk | 25 + .../nvidia-drm/nvidia-drm-gem-nvkms-memory.c | 8 + kernel-open/nvidia-drm/nvidia-drm-ioctl.h | 3 + kernel-open/nvidia-drm/nvidia-drm-linux.c | 4 - .../nvidia-modeset/nvidia-modeset-linux.c | 110 +- kernel-open/nvidia-peermem/nv-p2p.h | 4 - kernel-open/nvidia-uvm/cla16f.h | 10 +- kernel-open/nvidia-uvm/clc86f.h | 375 + kernel-open/nvidia-uvm/clc8b5.h | 430 + kernel-open/nvidia-uvm/ctrl2080mc.h | 11 +- .../nvidia-uvm/hwref/hopper/gh100/dev_fault.h | 508 + .../nvidia-uvm/hwref/hopper/gh100/dev_mmu.h | 560 + .../nvidia-uvm/nvidia-uvm-sources.Kbuild | 6 + kernel-open/nvidia-uvm/uvm.c | 4 +- kernel-open/nvidia-uvm/uvm.h | 26 - kernel-open/nvidia-uvm/uvm_ada.c | 95 + kernel-open/nvidia-uvm/uvm_ada_fault_buffer.h | 84 + kernel-open/nvidia-uvm/uvm_ampere.c | 4 +- kernel-open/nvidia-uvm/uvm_ampere_host.c | 12 +- kernel-open/nvidia-uvm/uvm_ats.c | 28 - kernel-open/nvidia-uvm/uvm_ats.h | 20 - kernel-open/nvidia-uvm/uvm_ce_test.c | 12 +- kernel-open/nvidia-uvm/uvm_channel.c | 356 +- kernel-open/nvidia-uvm/uvm_channel.h | 101 +- kernel-open/nvidia-uvm/uvm_channel_test.c | 201 +- kernel-open/nvidia-uvm/uvm_forward_decl.h | 3 - kernel-open/nvidia-uvm/uvm_global.c | 14 +- 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src/common/inc/displayport/dpcd20.h | 5 +- src/common/inc/nvBldVer.h | 22 +- src/common/inc/nvUnixVersion.h | 2 +- .../published/ampere/ga100/dev_falcon_v4.h | 4 - .../published/ampere/ga102/dev_falcon_v4.h | 4 - .../swref/published/disp/v04_00/dev_disp.h | 4 + .../inc/swref/published/hopper/gh100/dev_ce.h | 29 + .../published/hopper/gh100/dev_falcon_v4.h | 100 + .../swref/published/hopper/gh100/dev_fault.h | 29 + .../inc/swref/published/hopper/gh100/dev_fb.h | 32 + .../published/hopper/gh100/dev_fsp_addendum.h | 78 + .../published/hopper/gh100/dev_fsp_pri.h | 68 + .../published/hopper/gh100/dev_gc6_island.h | 37 + .../hopper/gh100/dev_gc6_island_addendum.h | 29 + .../swref/published/hopper/gh100/dev_gsp.h | 33 + .../swref/published/hopper/gh100/dev_mmu.h | 194 + .../hopper/gh100/dev_nv_xal_addendum.h | 31 + .../swref/published/hopper/gh100/dev_pmc.h | 27 + .../swref/published/hopper/gh100/dev_ram.h | 29 + .../published/hopper/gh100/dev_riscv_pri.h | 72 + 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.../src/kernel/gpu/gsp/message_queue_cpu.c | 9 +- .../gpu/hwpm/profiler_v2/kern_profiler_v2.c | 5 +- .../kernel/gpu/intr/arch/hopper/intr_gh100.c | 160 + src/nvidia/src/kernel/gpu/intr/intr.c | 4 +- src/nvidia/src/kernel/gpu/mc/kernel_mc.c | 82 + .../gpu/mem_mgr/arch/ada/mem_mgr_ad102.c | 56 + .../gpu/mem_mgr/arch/hopper/mem_utils_gh100.c | 73 + .../arch/hopper/virt_mem_allocator_gh100.c | 214 + .../mem_mgr/arch/maxwell/mem_utils_gm107.c | 30 + .../arch/maxwell/virt_mem_allocator_gm107.c | 48 + .../src/kernel/gpu/mem_mgr/context_dma.c | 73 +- src/nvidia/src/kernel/gpu/mem_mgr/heap.c | 7 + src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c | 12 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c | 86 +- .../kernel/gpu/mem_mgr/mem_mgr_gsp_client.c | 14 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c | 138 + .../phys_mem_allocator_util.c | 2 +- .../src/kernel/gpu/mem_mgr/vaspace_api.c | 10 + .../mem_sys/arch/hopper/kern_mem_sys_gh100.c | 493 + .../src/kernel/gpu/mem_sys/kern_mem_sys.c | 7 +- .../gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c | 143 + .../kernel/gpu/mig_mgr/kernel_mig_manager.c | 256 +- .../gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c | 170 + .../gpu/mmu/arch/hopper/kern_gmmu_gh100.c | 340 + .../gpu/mmu/arch/maxwell/kern_gmmu_gm107.c | 3 + src/nvidia/src/kernel/gpu/mmu/bar2_walk.c | 11 + src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c | 59 + src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c | 18 + src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c | 82 + .../nvdec/arch/ampere/kernel_nvdec_ga100.c | 107 - .../nvdec/arch/ampere/kernel_nvdec_ga102.c | 73 - .../nvdec/arch/turing/kernel_nvdec_tu102.c | 95 - .../src/kernel/gpu/nvdec/kernel_nvdec.c | 80 - .../kernel/gpu/nvdec/kernel_nvdec_engdesc.c | 4 + .../kernel/gpu/nvenc/kernel_nvenc_engdesc.c | 2 + .../kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c | 6 + .../nvlink/arch/ampere/kernel_nvlink_ga100.c | 32 +- .../nvlink/arch/hopper/kernel_nvlink_gh100.c | 296 + .../nvlink/arch/volta/kernel_minion_gv100.c | 68 + .../src/kernel/gpu/nvlink/kernel_nvlink.c | 198 +- .../src/kernel/gpu/nvlink/kernel_nvlinkapi.c | 54 +- .../kernel/gpu/nvlink/kernel_nvlinkcorelib.c | 5 + .../gpu/nvlink/kernel_nvlinkcorelibcallback.c | 87 + .../gpu/nvlink/kernel_nvlinkcorelibtrain.c | 367 +- .../gpu/nvlink/kernel_nvlinkoverrides.c | 12 + .../kernel/gpu/nvlink/kernel_nvlinkstate.c | 165 +- src/nvidia/src/kernel/gpu/pmu/kern_pmu.c | 2 +- src/nvidia/src/kernel/gpu/rc/kernel_rc.c | 5 +- .../src/kernel/gpu/rc/kernel_rc_watchdog.c | 2 + .../gpu/rc/kernel_rc_watchdog_callback.c | 3 +- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 13 - .../gpu/subdevice/subdevice_ctrl_gpu_smc.c | 36 + .../gpu/timer/arch/hopper/timer_gh100.c | 153 + src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c | 107 +- src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c | 6 +- .../src/kernel/mem_mgr/fabric_vaspace.c | 15 +- src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c | 119 +- src/nvidia/src/kernel/mem_mgr/mem_fabric.c | 56 +- src/nvidia/src/kernel/mem_mgr/pool_alloc.c | 21 + src/nvidia/src/kernel/mem_mgr/vaddr_list.c | 6 +- src/nvidia/src/kernel/mem_mgr/virtual_mem.c | 8 +- src/nvidia/src/kernel/os/os_init.c | 21 + src/nvidia/src/kernel/os/os_sanity.c | 3 +- src/nvidia/src/kernel/os/os_stubs.c | 162 +- .../src/kernel/platform/chipset/chipset.c | 1 + .../kernel/platform/chipset/chipset_info.c | 39 + .../kernel/platform/chipset/chipset_pcie.c | 242 + src/nvidia/src/kernel/platform/p2p/p2p_caps.c | 7 +- src/nvidia/src/kernel/rmapi/alloc_free.c | 10 - src/nvidia/src/kernel/rmapi/client_resource.c | 5 +- src/nvidia/src/kernel/rmapi/control.c | 4 - .../src/kernel/rmapi/embedded_param_copy.c | 24 +- src/nvidia/src/kernel/rmapi/entry_points.c | 4 +- src/nvidia/src/kernel/rmapi/entry_points.h | 27 + .../src/kernel/rmapi/event_notification.c | 30 + src/nvidia/src/kernel/rmapi/mapping_cpu.c | 80 +- src/nvidia/src/kernel/rmapi/nv_gpu_ops.c | 157 +- src/nvidia/src/kernel/rmapi/resource_list.h | 181 + src/nvidia/src/kernel/rmapi/rmapi.c | 1 + src/nvidia/src/kernel/rmapi/sharing.c | 6 - src/nvidia/src/lib/base_utils.c | 17 +- src/nvidia/src/libraries/mmu/gmmu_fmt.c | 7 + src/nvidia/src/libraries/nvoc/src/runtime.c | 9 + .../libraries/nvport/memory/memory_tracking.c | 19 +- src/nvidia/srcs.mk | 33 +- version.mk | 2 +- 758 files changed, 88026 insertions(+), 26136 deletions(-) create mode 100644 kernel-open/count-lines.mk create mode 100644 kernel-open/nvidia-uvm/clc86f.h create mode 100644 kernel-open/nvidia-uvm/clc8b5.h create mode 100644 kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_fault.h create mode 100644 kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h create mode 100644 kernel-open/nvidia-uvm/uvm_ada.c create mode 100644 kernel-open/nvidia-uvm/uvm_ada_fault_buffer.h create mode 100644 kernel-open/nvidia-uvm/uvm_hopper.c create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_ce.c create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.c create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.h create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_host.c create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_mmu.c create mode 100644 kernel-open/nvidia/nvlink_inband_drv_header.h create mode 100644 kernel-open/nvidia/nvlink_inband_msg.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_ce.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fault.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fb.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_gsp.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_mmu.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_pmc.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_ram.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_riscv_pri.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_therm.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_therm_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_timer.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_vm.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h create mode 100644 src/common/inc/swref/published/hopper/gh100/hwproject.h create mode 100644 src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h create mode 100644 src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h create mode 100644 src/common/modeset/hdmipacket/nvhdmipkt_C771.c create mode 100644 src/common/sdk/nvidia/inc/class/cl0000_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl0005_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl0080_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl30f1_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl5070_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl5080_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/cl9072_notification.h create mode 100644 src/common/sdk/nvidia/inc/class/clb8b0.h create mode 100644 src/common/sdk/nvidia/inc/class/clb8d1.h create mode 100644 src/common/sdk/nvidia/inc/class/clb8fa.h create mode 100644 src/common/sdk/nvidia/inc/class/clc661.h create mode 100644 src/common/sdk/nvidia/inc/class/clc771.h create mode 100644 src/common/sdk/nvidia/inc/class/clc773.h create mode 100644 src/common/sdk/nvidia/inc/class/clc77d.h create mode 100644 src/common/sdk/nvidia/inc/class/clc86f.h create mode 100644 src/common/sdk/nvidia/inc/class/clc86fsw.h create mode 100644 src/common/sdk/nvidia/inc/class/clc8b5.h create mode 100644 src/common/sdk/nvidia/inc/class/clc997.h create mode 100644 src/common/sdk/nvidia/inc/class/clc9b0.h create mode 100644 src/common/sdk/nvidia/inc/class/clc9b7.h create mode 100644 src/common/sdk/nvidia/inc/class/clc9c0.h create mode 100644 src/common/sdk/nvidia/inc/class/clc9d1.h create mode 100644 src/common/sdk/nvidia/inc/class/clc9fa.h create mode 100644 src/common/sdk/nvidia/inc/class/clcb97.h create mode 100644 src/common/sdk/nvidia/inc/class/clcbc0.h create mode 100644 src/common/sdk/nvidia/inc/class/clcbca.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrla083.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h create mode 100644 src/common/sdk/nvidia/inc/nvcfg_sdk.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c create mode 100644 src/nvidia/generated/g_kern_fsp_nvoc.c create mode 100644 src/nvidia/generated/g_kern_fsp_nvoc.h create mode 100644 src/nvidia/generated/g_kernel_ccu_api_nvoc.c create mode 100644 src/nvidia/generated/g_kernel_ccu_api_nvoc.h create mode 100644 src/nvidia/generated/g_kernel_ccu_nvoc.c create mode 100644 src/nvidia/generated/g_kernel_ccu_nvoc.h delete mode 100644 src/nvidia/generated/g_kernel_nvdec_nvoc.c delete mode 100644 src/nvidia/generated/g_kernel_nvdec_nvoc.h create mode 100644 src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h create mode 100644 src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h create mode 100644 src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h create mode 100644 src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h delete mode 100644 src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h create mode 100644 src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h create mode 100644 src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h delete mode 100644 src/nvidia/inc/physical/gpu/disp/disp.h create mode 100644 src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c create mode 100644 src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c create mode 100644 src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c create mode 100644 src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c create mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/fsp/kern_fsp.c create mode 100644 src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c create mode 100644 src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c delete mode 100644 src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga100.c delete mode 100644 src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga102.c delete mode 100644 src/nvidia/src/kernel/gpu/nvdec/arch/turing/kernel_nvdec_tu102.c delete mode 100644 src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec.c create mode 100644 src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c create mode 100644 src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c diff --git a/CHANGELOG.md b/CHANGELOG.md index a2949b51e..306fa0a48 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,19 @@ # Changelog +## Release 520 Entries + +### [520.61.05] 2022-10-10 + +#### Added + +- Introduce support for NVIDIA H100 GPUs. + +#### Fixed + +- Fix/Improve Makefile, [#308](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/308/) by @izenynn +- Make nvLogBase2 more efficient, [#177](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/177/) by @DMaroo +- nv-pci: fixed always true expression, [#195](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/195/) by @ValZapod + ## Release 515 Entries ### [515.76] 2022-09-20 diff --git a/Makefile b/Makefile index 0ad5aa90a..449c7f585 100644 --- a/Makefile +++ b/Makefile @@ -6,9 +6,9 @@ # To install the build kernel modules: run (as root) `make modules_install` ########################################################################### -include utils.mk - -all: modules +########################################################################### +# variables +########################################################################### nv_kernel_o = src/nvidia/$(OUTPUTDIR)/nv-kernel.o nv_kernel_o_binary = kernel-open/nvidia/nv-kernel.o_binary @@ -16,13 +16,20 @@ nv_kernel_o_binary = kernel-open/nvidia/nv-kernel.o_binary nv_modeset_kernel_o = src/nvidia-modeset/$(OUTPUTDIR)/nv-modeset-kernel.o nv_modeset_kernel_o_binary = kernel-open/nvidia-modeset/nv-modeset-kernel.o_binary -.PHONY: $(nv_kernel_o) $(nv_modeset_kernel_o) modules modules_install +########################################################################### +# rules +########################################################################### +include utils.mk + +.PHONY: all +all: modules ########################################################################### # nv-kernel.o is the OS agnostic portion of nvidia.ko ########################################################################### +.PHONY: $(nv_kernel_o) $(nv_kernel_o): $(MAKE) -C src/nvidia @@ -34,6 +41,7 @@ $(nv_kernel_o_binary): $(nv_kernel_o) # nv-modeset-kernel.o is the OS agnostic portion of nvidia-modeset.ko ########################################################################### +.PHONY: $(nv_modeset_kernel_o) $(nv_modeset_kernel_o): $(MAKE) -C src/nvidia-modeset @@ -46,31 +54,33 @@ $(nv_modeset_kernel_o_binary): $(nv_modeset_kernel_o) # the kernel modules with kbuild. ########################################################################### +.PHONY: modules modules: $(nv_kernel_o_binary) $(nv_modeset_kernel_o_binary) $(MAKE) -C kernel-open modules - ########################################################################### # Install the built kernel modules using kbuild. ########################################################################### +.PHONY: modules_install modules_install: $(MAKE) -C kernel-open modules_install - ########################################################################### # clean ########################################################################### -.PHONY: clean nvidia.clean nvidia-modeset.clean kernel-open.clean - +.PHONY: clean clean: nvidia.clean nvidia-modeset.clean kernel-open.clean +.PHONY: nvidia.clean nvidia.clean: $(MAKE) -C src/nvidia clean +.PHONY: nvidia-modeset.clean nvidia-modeset.clean: $(MAKE) -C src/nvidia-modeset clean +.PHONY: kernel-open.clean kernel-open.clean: $(MAKE) -C kernel-open clean diff --git a/README.md b/README.md index e40cd4c41..d53fd2d5b 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 515.76. +version 520.61.05. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with gsp.bin firmware and user-space NVIDIA GPU driver components from a corresponding -515.76 driver release. This can be achieved by installing +520.61.05 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -167,7 +167,7 @@ for the target kernel. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 515.76 release, +(see the table below). However, in the 520.61.05 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/515.76/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/520.61.05/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 42c14d686..320e8ea8f 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"515.76\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"520.61.05\" EXTRA_CFLAGS += -Wno-unused-function diff --git a/kernel-open/common/inc/cpuopsys.h b/kernel-open/common/inc/cpuopsys.h index 4b2ef6fb5..9be69fb36 100644 --- a/kernel-open/common/inc/cpuopsys.h +++ b/kernel-open/common/inc/cpuopsys.h @@ -101,13 +101,6 @@ # define NV_ANDROID #endif - - - - - - - #if defined(DceCore) && !defined(NV_DCECORE) # define NV_DCECORE #endif @@ -355,15 +348,6 @@ #define NVOS_IS_INTEGRITY 0 #endif - - - - - - - - - #if defined(NVCPU_X86) #define NVCPU_IS_X86 1 #else diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index dcfac7d03..e3ac4d519 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -1037,6 +1037,32 @@ static inline vm_fault_t nv_insert_pfn(struct vm_area_struct *vma, return VM_FAULT_SIGBUS; } +/* Converts BAR index to Linux specific PCI BAR index */ +static inline NvU8 nv_bar_index_to_os_bar_index +( + struct pci_dev *dev, + NvU8 nv_bar_index +) +{ + NvU8 bar_index = 0; + NvU8 i; + + BUG_ON(nv_bar_index >= NV_GPU_NUM_BARS); + + for (i = 0; i < nv_bar_index; i++) + { + if (NV_PCI_RESOURCE_FLAGS(dev, bar_index) & PCI_BASE_ADDRESS_MEM_TYPE_64) + { + bar_index += 2; + } + else + { + bar_index++; + } + } + + return bar_index; +} #define NV_PAGE_MASK (NvU64)(long)PAGE_MASK @@ -1161,16 +1187,6 @@ typedef struct nvidia_pte_s { unsigned int page_count; } nvidia_pte_t; - - - - - - - - - - typedef struct nv_alloc_s { struct nv_alloc_s *next; struct device *dev; @@ -1413,34 +1429,6 @@ struct os_wait_queue { struct completion q; }; - - - - - - - - - - - - - - - - - - - - - - - - - - - - /* * To report error in msi/msix when unhandled count reaches a threshold */ @@ -1464,19 +1452,6 @@ struct nv_dma_device { NvBool nvlink; }; - - - - - - - - - - - - - /* linux-specific version of old nv_state_t */ /* this is a general os-specific state structure. the first element *must* be the general state structure, for the generic unix-based code */ @@ -1492,11 +1467,6 @@ typedef struct nv_linux_state_s { /* IBM-NPU info associated with this GPU */ nv_ibmnpu_info_t *npu; - - - - - /* NUMA node information for the platforms where GPU memory is presented * as a NUMA node to the kernel */ struct { @@ -1576,23 +1546,6 @@ typedef struct nv_linux_state_s { /* Per-device notifier block for ACPI events */ struct notifier_block acpi_nb; - - - - - - - - - - - - - - - - - /* Lock serializing ISRs for different SOC vectors */ nv_spinlock_t soc_isr_lock; @@ -1760,12 +1713,10 @@ static inline struct kmem_cache *nv_kmem_cache_create(const char *name, unsigned return cache; } - #if defined(CONFIG_PCI_IOV) #define NV_PCI_SRIOV_SUPPORT #endif /* CONFIG_PCI_IOV */ - #define NV_PCIE_CFG_MAX_OFFSET 0x1000 #include "nv-proto.h" @@ -1959,11 +1910,6 @@ static inline NvU32 nv_default_irq_flags(nv_state_t *nv) NvS32 nv_request_soc_irq(nv_linux_state_t *, NvU32, nv_soc_irq_type_t, NvU32, NvU32); - - - - - static inline void nv_mutex_destroy(struct mutex *lock) { mutex_destroy(lock); diff --git a/kernel-open/common/inc/nv-mm.h b/kernel-open/common/inc/nv-mm.h index 0b70f30ca..21ad97c9a 100644 --- a/kernel-open/common/inc/nv-mm.h +++ b/kernel-open/common/inc/nv-mm.h @@ -47,55 +47,37 @@ typedef int vm_fault_t; * */ -#if defined(NV_GET_USER_PAGES_HAS_TASK_STRUCT) - #if defined(NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS) - #define NV_GET_USER_PAGES(start, nr_pages, write, force, pages, vmas) \ - get_user_pages(current, current->mm, start, nr_pages, write, force, pages, vmas) - #else - #include - #include - - static inline long NV_GET_USER_PAGES(unsigned long start, - unsigned long nr_pages, - int write, - int force, - struct page **pages, - struct vm_area_struct **vmas) - { - unsigned int flags = 0; - - if (write) - flags |= FOLL_WRITE; - if (force) - flags |= FOLL_FORCE; - - return get_user_pages(current, current->mm, start, nr_pages, flags, - pages, vmas); - } - #endif +#if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE) + #define NV_GET_USER_PAGES get_user_pages +#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE) + #define NV_GET_USER_PAGES(start, nr_pages, write, force, pages, vmas) \ + get_user_pages(current, current->mm, start, nr_pages, write, force, pages, vmas) #else - #if defined(NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS) - #define NV_GET_USER_PAGES get_user_pages + #include + #include + + static inline long NV_GET_USER_PAGES(unsigned long start, + unsigned long nr_pages, + int write, + int force, + struct page **pages, + struct vm_area_struct **vmas) + { + unsigned int flags = 0; + + if (write) + flags |= FOLL_WRITE; + if (force) + flags |= FOLL_FORCE; + + #if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS) + return get_user_pages(current, current->mm, start, nr_pages, flags, + pages, vmas); #else - #include - - static inline long NV_GET_USER_PAGES(unsigned long start, - unsigned long nr_pages, - int write, - int force, - struct page **pages, - struct vm_area_struct **vmas) - { - unsigned int flags = 0; - - if (write) - flags |= FOLL_WRITE; - if (force) - flags |= FOLL_FORCE; - - return get_user_pages(start, nr_pages, flags, pages, vmas); - } + // remaining defination(NV_GET_USER_PAGES_HAS_ARGS_FLAGS) + return get_user_pages(start, nr_pages, flags, pages, vmas); #endif + } #endif /* @@ -131,7 +113,7 @@ typedef int vm_fault_t; */ #if defined(NV_GET_USER_PAGES_REMOTE_PRESENT) - #if defined(NV_GET_USER_PAGES_REMOTE_HAS_WRITE_AND_FORCE_ARGS) + #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE) #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote #else static inline long NV_GET_USER_PAGES_REMOTE(struct task_struct *tsk, @@ -150,26 +132,21 @@ typedef int vm_fault_t; if (force) flags |= FOLL_FORCE; - #if defined(NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG) - #if defined (NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG) - return get_user_pages_remote(tsk, mm, start, nr_pages, flags, - pages, vmas, NULL); - #else - return get_user_pages_remote(mm, start, nr_pages, flags, - pages, vmas, NULL); - #endif - + #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS) + return get_user_pages_remote(tsk, mm, start, nr_pages, flags, + pages, vmas); + #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED) + return get_user_pages_remote(tsk, mm, start, nr_pages, flags, + pages, vmas, NULL); #else - - return get_user_pages_remote(tsk, mm, start, nr_pages, flags, - pages, vmas); - + // remaining defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED) + return get_user_pages_remote(mm, start, nr_pages, flags, + pages, vmas, NULL); #endif - } #endif #else - #if defined(NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS) + #if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE) #define NV_GET_USER_PAGES_REMOTE get_user_pages #else #include diff --git a/kernel-open/common/inc/nv-proto.h b/kernel-open/common/inc/nv-proto.h index ebb2873e4..b7434ccef 100644 --- a/kernel-open/common/inc/nv-proto.h +++ b/kernel-open/common/inc/nv-proto.h @@ -27,9 +27,6 @@ #include "nv-pci.h" #include "nv-register-module.h" - - - extern const char *nv_device_name; extern nvidia_module_t nv_fops; diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 568dfdf13..ea85afeb6 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -47,11 +47,6 @@ extern nv_cap_t *nvidia_caps_root; extern const NvBool nv_is_rm_firmware_supported_os; - - - - - #include /* NVIDIA's reserved major character device number (Linux). */ @@ -286,6 +281,7 @@ typedef struct nv_usermap_access_params_s NvU64 access_size; NvU64 remap_prot_extra; NvBool contig; + NvU32 caching; } nv_usermap_access_params_t; /* @@ -303,6 +299,7 @@ typedef struct nv_alloc_mapping_context_s { NvU64 remap_prot_extra; NvU32 prot; NvBool valid; + NvU32 caching; } nv_alloc_mapping_context_t; typedef enum @@ -331,6 +328,9 @@ typedef struct nv_soc_irq_info_s { #define NV_MAX_DPAUX_NUM_DEVICES 4 #define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING +#define NV_IGPU_LEGACY_STALL_IRQ 70 +#define NV_IGPU_MAX_STALL_IRQS 3 +#define NV_IGPU_MAX_NONSTALL_IRQS 1 /* * per device state */ @@ -367,6 +367,7 @@ typedef struct nv_state_t nv_aperture_t *hdacodec_regs; nv_aperture_t *mipical_regs; nv_aperture_t *fb, ud; + nv_aperture_t *simregs; NvU32 num_dpaux_instance; NvU32 interrupt_line; @@ -379,6 +380,11 @@ typedef struct nv_state_t NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; + NvU32 igpu_nonstall_irq; + NvU32 num_stall_irqs; + NvU64 dma_mask; + NvBool primary_vga; NvU32 sim_env; @@ -456,6 +462,9 @@ typedef struct nv_state_t NvBool printed_openrm_enable_unsupported_gpus_error; + /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ + NvBool nvpcf_dsm_in_gpu_scope; + } nv_state_t; // These define need to be in sync with defines in system.h @@ -520,7 +529,7 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64); #define NV_FLAG_USES_MSIX 0x0040 #define NV_FLAG_PASSTHRU 0x0080 #define NV_FLAG_SUSPENDED 0x0100 -// Unused 0x0200 +#define NV_FLAG_SOC_IGPU 0x0200 // Unused 0x0400 #define NV_FLAG_PERSISTENT_SW_STATE 0x0800 #define NV_FLAG_IN_RECOVERY 0x1000 @@ -569,6 +578,9 @@ typedef enum #define NV_IS_SOC_DISPLAY_DEVICE(nv) \ ((nv)->flags & NV_FLAG_SOC_DISPLAY) +#define NV_IS_SOC_IGPU_DEVICE(nv) \ + ((nv)->flags & NV_FLAG_SOC_IGPU) + #define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) @@ -627,18 +639,12 @@ typedef enum static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { return ((offset >= nv->regs->cpu_address) && - - - ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1)))); } static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { return ((nv->fb) && (offset >= nv->fb->cpu_address) && - - - ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); } @@ -646,9 +652,6 @@ static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) && (offset >= nv->ud.cpu_address) && - - - ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1)))); } @@ -657,9 +660,6 @@ static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && - - - ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))); } @@ -799,7 +799,7 @@ void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); -NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -850,11 +850,9 @@ void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *); void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *); - NvBool NV_API_CALL nv_platform_supports_s0ix (void); NvBool NV_API_CALL nv_s2idle_pm_configured (void); - NvBool NV_API_CALL nv_is_chassis_notebook (void); void NV_API_CALL nv_allow_runtime_suspend (nv_state_t *nv); void NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv); @@ -864,45 +862,6 @@ typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *) NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *); NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - /* * --------------------------------------------------------------------------- * @@ -1019,7 +978,7 @@ void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 **, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); @@ -1045,18 +1004,6 @@ static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv) return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL; } - - - - - - - - - - - - #if defined(NVCPU_X86_64) static inline NvU64 nv_rdtsc(void) diff --git a/kernel-open/common/inc/nv_uvm_interface.h b/kernel-open/common/inc/nv_uvm_interface.h index 86a6b2e07..9587e4236 100644 --- a/kernel-open/common/inc/nv_uvm_interface.h +++ b/kernel-open/common/inc/nv_uvm_interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -201,7 +201,8 @@ void nvUvmInterfaceAddressSpaceDestroy(uvmGpuAddressSpaceHandle vaSpace); and will return a unique GPU virtual address. The default page size will be the small page size (as returned by query - caps). The Alignment will also be enforced to small page size(64K/128K). + caps). The physical alignment will also be enforced to small page + size(64K/128K). Arguments: vaSpace[IN] - Pointer to vaSpace object @@ -211,15 +212,15 @@ void nvUvmInterfaceAddressSpaceDestroy(uvmGpuAddressSpaceHandle vaSpace); contains below given fields allocInfo Members: - rangeBegin[IN] - Allocation will be made between rangeBegin - rangeEnd[IN] and rangeEnd(both inclusive). Default will be - no-range limitation. gpuPhysOffset[OUT] - Physical offset of allocation returned only if contiguous allocation is requested. + pageSize[IN] - Override the default page size (see above). + alignment[IN] - gpuPointer GPU VA alignment. 0 means 4KB + alignment. bContiguousPhysAlloc[IN] - Flag to request contiguous allocation. Default will follow the vidHeapControl default policy. - bHandleProvided [IN] - Flag to signify that the client has provided - the handle for phys allocation. + bMemGrowsDown[IN] + bPersistentVidmem[IN] - Allocate persistent vidmem. hPhysHandle[IN/OUT] - The handle will be used in allocation if provided. If not provided; allocator will return the handle it used eventually. @@ -247,7 +248,6 @@ NV_STATUS nvUvmInterfaceMemoryAllocFB(uvmGpuAddressSpaceHandle vaSpace, and will return a unique GPU virtual address. The default page size will be the small page size (as returned by query caps) - The Alignment will also be enforced to small page size. Arguments: vaSpace[IN] - Pointer to vaSpace object @@ -257,15 +257,15 @@ NV_STATUS nvUvmInterfaceMemoryAllocFB(uvmGpuAddressSpaceHandle vaSpace, contains below given fields allocInfo Members: - rangeBegin[IN] - Allocation will be made between rangeBegin - rangeEnd[IN] and rangeEnd(both inclusive). Default will be - no-range limitation. gpuPhysOffset[OUT] - Physical offset of allocation returned only if contiguous allocation is requested. + pageSize[IN] - Override the default page size (see above). + alignment[IN] - gpuPointer GPU VA alignment. 0 means 4KB + alignment. bContiguousPhysAlloc[IN] - Flag to request contiguous allocation. Default will follow the vidHeapControl default policy. - bHandleProvided [IN] - Flag to signify that the client has provided - the handle for phys allocation. + bMemGrowsDown[IN] + bPersistentVidmem[IN] - Allocate persistent vidmem. hPhysHandle[IN/OUT] - The handle will be used in allocation if provided. If not provided; allocator will return the handle it used eventually. @@ -671,14 +671,16 @@ NV_STATUS nvUvmInterfaceUnsetPageDirectory(uvmGpuAddressSpaceHandle vaSpace); For duplication of physical memory use nvUvmInterfaceDupMemory. Arguments: - srcVaSpace[IN] - Source VA space. - srcAddress[IN] - GPU VA in the source VA space. The provided address - should match one previously returned by - nvUvmInterfaceMemoryAllocFB or - nvUvmInterfaceMemoryAllocSys. - dstVaSpace[IN] - Destination VA space where the new mapping will be - created. - dstAddress[OUT] - Pointer to the GPU VA in the destination VA space. + srcVaSpace[IN] - Source VA space. + srcAddress[IN] - GPU VA in the source VA space. The provided address + should match one previously returned by + nvUvmInterfaceMemoryAllocFB or + nvUvmInterfaceMemoryAllocSys. + dstVaSpace[IN] - Destination VA space where the new mapping will be + created. + dstVaAlignment[IN] - Alignment of the GPU VA in the destination VA + space. 0 means 4KB alignment. + dstAddress[OUT] - Pointer to the GPU VA in the destination VA space. Error codes: NV_ERR_INVALID_ARGUMENT - If any of the inputs is invalid, or the source @@ -692,6 +694,7 @@ NV_STATUS nvUvmInterfaceUnsetPageDirectory(uvmGpuAddressSpaceHandle vaSpace); NV_STATUS nvUvmInterfaceDupAllocation(uvmGpuAddressSpaceHandle srcVaSpace, NvU64 srcAddress, uvmGpuAddressSpaceHandle dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress); /******************************************************************************* @@ -1068,10 +1071,6 @@ void nvUvmInterfaceP2pObjectDestroy(uvmGpuSessionHandle session, NV_ERR_NOT_READY - Returned when querying the PTEs requires a deferred setup which has not yet completed. It is expected that the caller will reattempt the call until a different code is returned. - - - - */ NV_STATUS nvUvmInterfaceGetExternalAllocPtes(uvmGpuAddressSpaceHandle vaSpace, NvHandle hMemory, @@ -1260,7 +1259,7 @@ void nvUvmInterfacePagingChannelDestroy(UvmGpuPagingChannelHandle channel); device[IN] - device under which paging channels were allocated dstAddress[OUT] - a virtual address that is valid (i.e. is mapped) in all the paging channels allocated under the given vaSpace. - + Error codes: NV_ERR_INVALID_ARGUMENT - Invalid parameter/s is passed. NV_ERR_NOT_SUPPORTED - SR-IOV heavy mode is disabled. @@ -1373,7 +1372,7 @@ void nvUvmInterfacePagingChannelsUnmap(uvmGpuAddressSpaceHandle srcVaSpace, methodStreamSize[IN] - Size of methodStream, in bytes. The maximum push size is 128KB. - + Error codes: NV_ERR_INVALID_ARGUMENT - Invalid parameter/s is passed. NV_ERR_NOT_SUPPORTED - SR-IOV heavy mode is disabled. @@ -1382,136 +1381,4 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe char *methodStream, NvU32 methodStreamSize); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #endif // _NV_UVM_INTERFACE_H_ diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index 865bf7ef0..dc3a4dc15 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -217,12 +217,6 @@ typedef struct UvmGpuChannelInstanceInfo_tag // Out: Type of the engine the channel is bound to NvU32 channelEngineType; - // Out: Channel handle required to ring the doorbell - NvU32 workSubmissionToken; - - // Out: Address of the doorbell - volatile NvU32 *workSubmissionOffset; - // Out: Channel handle to be used in the CLEAR_FAULTED method NvU32 clearFaultedToken; @@ -231,6 +225,10 @@ typedef struct UvmGpuChannelInstanceInfo_tag // Ampere+ GPUs volatile NvU32 *pChramChannelRegister; + // Out: Address of the Runlist PRI Base Register required to ring the + // doorbell after clearing the faulted bit. + volatile NvU32 *pRunlistPRIBaseRegister; + // Out: SMC engine id to which the GR channel is bound, or zero if the GPU // does not support SMC or it is a CE channel NvU32 smcEngineId; @@ -372,10 +370,8 @@ typedef enum UVM_LINK_TYPE_NVLINK_1, UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, - - - - + UVM_LINK_TYPE_NVLINK_4, + UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag @@ -433,19 +429,13 @@ typedef struct UvmGpuAddressSpaceInfo_tag typedef struct UvmGpuAllocInfo_tag { - NvU64 rangeBegin; // Allocation will be made between - NvU64 rangeEnd; // rangeBegin & rangeEnd both included NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M - NvU64 alignment; // Alignment of allocation + NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved - - - - } UvmGpuAllocInfo; typedef enum @@ -576,10 +566,8 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - - - - + // Out: AMD SEV (Secure Encrypted Virtualization) is enabled + NvBool sevEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -589,24 +577,6 @@ typedef struct UvmGpuClientInfo_tag NvHandle hSmcPartRef; } UvmGpuClientInfo; - - - - - - - - - - - - - - - - - - #define UVM_GPU_NAME_LENGTH 0x40 typedef struct UvmGpuInfo_tag @@ -671,10 +641,6 @@ typedef struct UvmGpuInfo_tag UvmGpuClientInfo smcUserClientInfo; - - - - } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -717,11 +683,6 @@ typedef struct UvmPmaStatistics_tag volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions - - - - - } UvmPmaStatistics; /******************************************************************************* @@ -961,10 +922,4 @@ typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; - - - - - - #endif // _NV_UVM_TYPES_H_ diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index b9fdd1b7c..a63d8dfdf 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -416,6 +416,12 @@ struct NvKmsKapiCreateSurfaceParams { NvU8 log2GobsPerBlockY; }; +enum NvKmsKapiAllocationType { + NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT = 0, + NVKMS_KAPI_ALLOCATION_TYPE_NOTIFIER = 1, + NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2, +}; + struct NvKmsKapiFunctionsTable { /*! @@ -609,6 +615,8 @@ struct NvKmsKapiFunctionsTable { * \param [in] device A device allocated using allocateDevice(). * * \param [in] layout BlockLinear or Pitch. + * + * \param [in] type Allocation type. * * \param [in] size Size, in bytes, of the memory to allocate. * @@ -624,6 +632,7 @@ struct NvKmsKapiFunctionsTable { ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ); @@ -637,6 +646,8 @@ struct NvKmsKapiFunctionsTable { * \param [in] device A device allocated using allocateDevice(). * * \param [in] layout BlockLinear or Pitch. + * + * \param [in] type Allocation type. * * \param [in] size Size, in bytes, of the memory to allocate. * @@ -652,6 +663,7 @@ struct NvKmsKapiFunctionsTable { ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ); diff --git a/kernel-open/common/inc/nvlimits.h b/kernel-open/common/inc/nvlimits.h index e119f676b..a896adf00 100644 --- a/kernel-open/common/inc/nvlimits.h +++ b/kernel-open/common/inc/nvlimits.h @@ -31,13 +31,6 @@ - - - - - - - /* * This is the maximum number of GPUs supported in a single system. */ diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 7163bea0e..0aaf20521 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -125,6 +125,7 @@ NvU32 NV_API_CALL os_get_cpu_number (void); void NV_API_CALL os_disable_console_access (void); void NV_API_CALL os_enable_console_access (void); NV_STATUS NV_API_CALL os_registry_init (void); +NvU64 NV_API_CALL os_get_max_user_va (void); NV_STATUS NV_API_CALL os_schedule (void); NV_STATUS NV_API_CALL os_alloc_spinlock (void **); void NV_API_CALL os_free_spinlock (void *); @@ -193,19 +194,12 @@ void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *); int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int); void NV_API_CALL os_nv_cap_close_fd (int); - - - - - - - - - - - - - +enum os_pci_req_atomics_type { + OS_INTF_PCIE_REQ_ATOMICS_32BIT, + OS_INTF_PCIE_REQ_ATOMICS_64BIT, + OS_INTF_PCIE_REQ_ATOMICS_128BIT +}; +NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); extern NvU32 os_page_size; extern NvU64 os_page_mask; @@ -245,11 +239,4 @@ int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); #define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO 0x00000000 #define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES 0x00000001 - - - - - - - #endif /* OS_INTERFACE_H */ diff --git a/kernel-open/common/inc/rm-gpu-ops.h b/kernel-open/common/inc/rm-gpu-ops.h index 2e97de475..7aa09151b 100644 --- a/kernel-open/common/inc/rm-gpu-ops.h +++ b/kernel-open/common/inc/rm-gpu-ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -63,7 +63,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *, nvgpuDeviceHandle NV_STATUS NV_API_CALL rm_gpu_ops_query_ces_caps(nvidia_stack_t *sp, nvgpuDeviceHandle_t, nvgpuCesCaps_t); NV_STATUS NV_API_CALL rm_gpu_ops_get_gpu_info(nvidia_stack_t *, const NvProcessorUuid *pUuid, const nvgpuClientInfo_t *, nvgpuInfo_t *); NV_STATUS NV_API_CALL rm_gpu_ops_service_device_interrupts_rm(nvidia_stack_t *, nvgpuDeviceHandle_t); -NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuAddressSpaceHandle_t, NvU64 *); +NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuAddressSpaceHandle_t, NvU64, NvU64 *); NV_STATUS NV_API_CALL rm_gpu_ops_dup_memory (nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle, NvHandle, NvHandle *, nvgpuMemoryInfo_t); @@ -98,13 +98,4 @@ NV_STATUS NV_API_CALL rm_gpu_ops_paging_channels_map(nvidia_stack_t *, nvgpuAdd void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32); - - - - - - - - - #endif diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 5ec66bf37..89b3c6cb1 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -2357,10 +2357,41 @@ compile_test() { # linux-4.4.168 cherry-picked commit 768ae309a961 without # c12d2da56d0e which is covered in Conftest #3. # + + # + # This function sets the NV_GET_USER_PAGES_* macros as per the below + # passing conftest's + # + set_get_user_pages_defines () { + if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" ]; then + echo "#define NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" ]; then + echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" ]; then + echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_FLAGS" ]; then + echo "#define NV_GET_USER_PAGES_HAS_ARGS_FLAGS" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_HAS_ARGS_FLAGS" | append_conftest "functions" + fi + } + # Conftest #1: Check if get_user_pages accepts 6 arguments. # Return if true. # Fall through to conftest #2 on failure. - # + echo "$CONFTEST_PREAMBLE #include long get_user_pages(unsigned long start, @@ -2375,8 +2406,7 @@ compile_test() { $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#define NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_HAS_TASK_STRUCT" | append_conftest "functions" + set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" rm -f conftest$$.o return fi @@ -2401,8 +2431,7 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#undef NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_HAS_TASK_STRUCT" | append_conftest "functions" + set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_FLAGS" rm -f conftest$$.o return fi @@ -2429,14 +2458,12 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#undef NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#define NV_GET_USER_PAGES_HAS_TASK_STRUCT" | append_conftest "functions" + set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" rm -f conftest$$.o return fi - echo "#define NV_GET_USER_PAGES_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#define NV_GET_USER_PAGES_HAS_TASK_STRUCT" | append_conftest "functions" + set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" return ;; @@ -2463,10 +2490,47 @@ compile_test() { # commit 64019a2e467a ("mm/gup: remove task_struct pointer for # all gup code") in v5.9-rc1 (2020-08-11). # + + # + # This function sets the NV_GET_USER_PAGES_REMOTE_* macros as per + # the below passing conftest's + # + set_get_user_pages_remote_defines () { + if [ "$1" = "" ]; then + echo "#undef NV_GET_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" + else + echo "#define NV_GET_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" ]; then + echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" ]; then + echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" ]; then + echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" | append_conftest "functions" + fi + + if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" ]; then + echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" | append_conftest "functions" + else + echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" | append_conftest "functions" + fi + } + # conftest #1: check if get_user_pages_remote() is available # return if not available. # Fall through to conftest #2 if it is present - # + echo "$CONFTEST_PREAMBLE #include void conftest_get_user_pages_remote(void) { @@ -2477,10 +2541,7 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#undef NV_GET_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG" | append_conftest "functions" + set_get_user_pages_remote_defines "" rm -f conftest$$.o return fi @@ -2490,7 +2551,6 @@ compile_test() { # force arguments. Return if these arguments are present # Fall through to conftest #3 if these args are absent. # - echo "#define NV_GET_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" echo "$CONFTEST_PREAMBLE #include long get_user_pages_remote(struct task_struct *tsk, @@ -2508,18 +2568,40 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG" | append_conftest "functions" - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG" | append_conftest "functions" + set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" rm -f conftest$$.o return fi - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_WRITE_AND_FORCE_ARGS" | append_conftest "functions" + # + # conftest #3: check if get_user_pages_remote() has gpu_flags + # arguments. Return if these arguments are present + # Fall through to conftest #4 if these args are absent. + # + echo "$CONFTEST_PREAMBLE + #include + long get_user_pages_remote(struct task_struct *tsk, + struct mm_struct *mm, + unsigned long start, + unsigned long nr_pages, + unsigned int gpu_flags, + struct page **pages, + struct vm_area_struct **vmas) { + return 0; + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" + rm -f conftest$$.o + return + fi # - # conftest #3: check if get_user_pages_remote() has locked argument - # Return if these arguments are present. Fall through to conftest #4 + # conftest #4: check if get_user_pages_remote() has locked argument + # Return if these arguments are present. Fall through to conftest #5 # if these args are absent. # echo "$CONFTEST_PREAMBLE @@ -2539,14 +2621,13 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG" | append_conftest "functions" - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG" | append_conftest "functions" + set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" rm -f conftest$$.o return fi # - # conftest #4: check if get_user_pages_remote() does not take + # conftest #5: check if get_user_pages_remote() does not take # tsk argument. # echo "$CONFTEST_PREAMBLE @@ -2565,13 +2646,8 @@ compile_test() { rm -f conftest$$.c if [ -f conftest$$.o ]; then - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG" | append_conftest "functions" - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG" | append_conftest "functions" + set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" rm -f conftest$$.o - else - - echo "#define NV_GET_USER_PAGES_REMOTE_HAS_TSK_ARG" | append_conftest "functions" - echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_LOCKED_ARG" | append_conftest "functions" fi ;; @@ -5185,6 +5261,22 @@ compile_test() { rm -f conftest$$.c ;; + platform_irq_count) + # + # Determine if the platform_irq_count() function is present + # + # platform_irq_count was added by commit + # 4b83555d5098e73cf2c5ca7f86c17ca0ba3b968e ("driver-core: platform: Add platform_irq_count()") + # in 4.5-rc1 (2016-01-07) + # + CODE=" + #include + int conftest_platform_irq_count(void) { + return platform_irq_count(); + }" + compile_check_conftest "$CODE" "NV_PLATFORM_IRQ_COUNT_PRESENT" "" "functions" + ;; + dma_resv_add_fence) # # Determine if the dma_resv_add_fence() function is present. diff --git a/kernel-open/count-lines.mk b/kernel-open/count-lines.mk new file mode 100644 index 000000000..397db0a38 --- /dev/null +++ b/kernel-open/count-lines.mk @@ -0,0 +1,25 @@ +count: + @echo "conftests:$(words $(ALL_CONFTESTS))" \ + "objects:$(words $(NV_OBJECTS_DEPEND_ON_CONFTEST))" \ + "modules:$(words $(NV_KERNEL_MODULES))" + +.PHONY: count + +# Include the top-level makefile to get $(NV_KERNEL_MODULES) +include Makefile + +# Set $(src) for the to-be-included nvidia*.Kbuild files +src := $(CURDIR) + +# Include nvidia*.Kbuild and append the nvidia*-y objects to ALL_OBJECTS +$(foreach _module, $(NV_KERNEL_MODULES), \ + $(eval include $(_module)/$(_module).Kbuild) \ + ) + +# Concatenate all of the conftest lists; use $(sort ) to remove duplicates +ALL_CONFTESTS := $(sort $(NV_CONFTEST_FUNCTION_COMPILE_TESTS) \ + $(NV_CONFTEST_GENERIC_COMPILE_TESTS) \ + $(NV_CONFTEST_MACRO_COMPILE_TESTS) \ + $(NV_CONFTEST_SYMBOL_COMPILE_TESTS) \ + $(NV_CONFTEST_TYPE_COMPILE_TESTS) \ + ) diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index 1d047f2b1..b0e87d165 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -285,11 +285,13 @@ int nv_drm_dumb_create( if (nv_dev->hasVideoMemory) { pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice, NvKmsSurfaceMemoryLayoutPitch, + NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT, args->size, &compressible); } else { pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice, NvKmsSurfaceMemoryLayoutPitch, + NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT, args->size, &compressible); } @@ -441,6 +443,7 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev, struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = NULL; struct NvKmsKapiMemory *pMemory; enum NvKmsSurfaceMemoryLayout layout; + enum NvKmsKapiAllocationType type; int ret = 0; if (!drm_core_check_feature(dev, DRIVER_MODESET)) { @@ -449,6 +452,7 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev, } if (p->__pad != 0) { + ret = -EINVAL; NV_DRM_DEV_LOG_ERR(nv_dev, "non-zero value in padding field"); goto failed; } @@ -461,15 +465,19 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev, layout = p->block_linear ? NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch; + type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ? + NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN : NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT; if (nv_dev->hasVideoMemory) { pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice, layout, + type, p->memory_size, &p->compressible); } else { pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice, layout, + type, p->memory_size, &p->compressible); } diff --git a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h index 1a377b11f..9cfca16f1 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h +++ b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h @@ -199,6 +199,8 @@ struct drm_nvidia_gem_map_offset_params { uint64_t offset; /* OUT Fake offset */ }; +#define NV_GEM_ALLOC_NO_SCANOUT (1 << 0) + struct drm_nvidia_gem_alloc_nvkms_memory_params { uint32_t handle; /* OUT */ uint8_t block_linear; /* IN */ @@ -206,6 +208,7 @@ struct drm_nvidia_gem_alloc_nvkms_memory_params { uint16_t __pad; uint64_t memory_size; /* IN */ + uint32_t flags; /* IN */ }; struct drm_nvidia_gem_export_dmabuf_memory_params { diff --git a/kernel-open/nvidia-drm/nvidia-drm-linux.c b/kernel-open/nvidia-drm/nvidia-drm-linux.c index 6bdf40a44..069814de2 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-linux.c +++ b/kernel-open/nvidia-drm/nvidia-drm-linux.c @@ -175,11 +175,7 @@ module_init(nv_linux_drm_init); module_exit(nv_linux_drm_exit); #if defined(MODULE_LICENSE) - MODULE_LICENSE("Dual MIT/GPL"); - - - #endif #if defined(MODULE_INFO) MODULE_INFO(supported, "external"); diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index 383af3de7..53b9b4a27 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -59,7 +59,7 @@ #define NVKMS_LOG_PREFIX "nvidia-modeset: " -static bool output_rounding_fix = false; +static bool output_rounding_fix = true; module_param_named(output_rounding_fix, output_rounding_fix, bool, 0400); /* These parameters are used for fault injection tests. Normally the defaults @@ -85,110 +85,6 @@ NvBool nvkms_output_rounding_fix(void) * NVKMS interface for nvhost unit for sync point APIs. *************************************************************************/ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #ifdef NVKMS_SYNCPT_STUBS_NEEDED /* Unsupported STUB for nvkms_syncpt APIs */ NvBool nvkms_syncpt_op( @@ -1735,11 +1631,7 @@ module_init(nvkms_init); module_exit(nvkms_exit); #if defined(MODULE_LICENSE) - MODULE_LICENSE("Dual MIT/GPL"); - - - #endif #if defined(MODULE_INFO) MODULE_INFO(supported, "external"); diff --git a/kernel-open/nvidia-peermem/nv-p2p.h b/kernel-open/nvidia-peermem/nv-p2p.h index c2059145d..a9469bdbb 100644 --- a/kernel-open/nvidia-peermem/nv-p2p.h +++ b/kernel-open/nvidia-peermem/nv-p2p.h @@ -177,11 +177,7 @@ struct nvidia_p2p_page_table { * This means the pages underlying the range of GPU virtual memory * will persist until explicitly freed by nvidia_p2p_put_pages(). * Persistent GPU memory mappings are not supported on PowerPC, - - - * MIG-enabled devices and vGPU. - * @param[in] data * A non-NULL opaque pointer to private data to be passed to the * callback function. diff --git a/kernel-open/nvidia-uvm/cla16f.h b/kernel-open/nvidia-uvm/cla16f.h index 356bfe67f..742baa96a 100644 --- a/kernel-open/nvidia-uvm/cla16f.h +++ b/kernel-open/nvidia-uvm/cla16f.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -116,6 +116,14 @@ extern "C" { #define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000 #define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 #define NVA16F_GP_ENTRY1_LENGTH 30:10 +#define NVA16F_GP_ENTRY1_SYNC 31:31 +#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE 7:0 +#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* dma method formats */ #define NVA16F_DMA_METHOD_ADDRESS 11:0 diff --git a/kernel-open/nvidia-uvm/clc86f.h b/kernel-open/nvidia-uvm/clc86f.h new file mode 100644 index 000000000..dbb911eab --- /dev/null +++ b/kernel-open/nvidia-uvm/clc86f.h @@ -0,0 +1,375 @@ +/******************************************************************************* + Copyright (c) 2012-2015 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef _clc86f_h_ +#define _clc86f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class HOPPER_CHANNEL_GPFIFO */ +/* + * Documentation for HOPPER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F) + +#define NVC86F_TYPEDEF HOPPER_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc86fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc86fControl, HopperAControlGPFifo; + +/* fields and values */ +#define NVC86F_NUMBER_OF_SUBCHANNELS (8) +#define NVC86F_SET_OBJECT (0x00000000) +#define NVC86F_SET_OBJECT_NVCLASS 15:0 +#define NVC86F_SET_OBJECT_ENGINE 20:16 +#define NVC86F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC86F_ILLEGAL (0x00000004) +#define NVC86F_ILLEGAL_HANDLE 31:0 +#define NVC86F_NOP (0x00000008) +#define NVC86F_NOP_HANDLE 31:0 +#define NVC86F_SEMAPHOREA (0x00000010) +#define NVC86F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC86F_SEMAPHOREB (0x00000014) +#define NVC86F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC86F_SEMAPHOREC (0x00000018) +#define NVC86F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC86F_SEMAPHORED (0x0000001C) +#define NVC86F_SEMAPHORED_OPERATION 4:0 +#define NVC86F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC86F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC86F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC86F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC86F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC86F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC86F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC86F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC86F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC86F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC86F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC86F_SEMAPHORED_REDUCTION 30:27 +#define NVC86F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC86F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC86F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC86F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC86F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC86F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC86F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC86F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC86F_SEMAPHORED_FORMAT 31:31 +#define NVC86F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC86F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC86F_NON_STALL_INTERRUPT (0x00000020) +#define NVC86F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC86F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC86F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC86F_MEM_OP_A (0x00000028) +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 8:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC86F_MEM_OP_B (0x0000002c) +#define NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC86F_MEM_OP_C (0x00000030) +#define NVC86F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC86F_MEM_OP_D (0x00000034) +#define NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_D_OPERATION 31:27 +#define NVC86F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION 0x0000000b +#define NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE 23:20 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001 +#define NVC86F_SET_REFERENCE (0x00000050) +#define NVC86F_SET_REFERENCE_COUNT 31:0 +#define NVC86F_SEM_ADDR_LO (0x0000005c) +#define NVC86F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC86F_SEM_ADDR_HI (0x00000060) +#define NVC86F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC86F_SEM_PAYLOAD_LO (0x00000064) +#define NVC86F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC86F_SEM_PAYLOAD_HI (0x00000068) +#define NVC86F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC86F_SEM_EXECUTE (0x0000006c) +#define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC86F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC86F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC86F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC86F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC86F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC86F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC86F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC86F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC86F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC86F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC86F_WFI (0x00000078) +#define NVC86F_WFI_SCOPE 0:0 +#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC86F_WFI_SCOPE_ALL 0x00000001 +#define NVC86F_YIELD (0x00000080) +#define NVC86F_YIELD_OP 1:0 +#define NVC86F_YIELD_OP_NOP 0x00000000 +#define NVC86F_YIELD_OP_TSG 0x00000003 +#define NVC86F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC86F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC86F_CLEAR_FAULTED_TYPE 31:31 +#define NVC86F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC86F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 +#define NVC86F_QUADRO_VERIFY (0x000000a0) + + +/* GPFIFO entry format */ +#define NVC86F_GP_ENTRY__SIZE 8 +#define NVC86F_GP_ENTRY0_FETCH 0:0 +#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC86F_GP_ENTRY0_GET 31:2 +#define NVC86F_GP_ENTRY0_OPERAND 31:0 +#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC86F_GP_ENTRY1_GET_HI 7:0 +#define NVC86F_GP_ENTRY1_LEVEL 9:9 +#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC86F_GP_ENTRY1_LENGTH 30:10 +#define NVC86F_GP_ENTRY1_SYNC 31:31 +#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE 7:0 +#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +/* dma method formats */ +#define NVC86F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC86F_DMA_METHOD_ADDRESS 11:0 +#define NVC86F_DMA_SUBDEVICE_MASK 15:4 +#define NVC86F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC86F_DMA_TERT_OP 17:16 +#define NVC86F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC86F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC86F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC86F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC86F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC86F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC86F_DMA_METHOD_COUNT 28:16 +#define NVC86F_DMA_IMMD_DATA 28:16 +#define NVC86F_DMA_SEC_OP 31:29 +#define NVC86F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC86F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC86F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC86F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC86F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC86F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC86F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC86F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC86F_DMA_INCR_ADDRESS 11:0 +#define NVC86F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC86F_DMA_INCR_COUNT 28:16 +#define NVC86F_DMA_INCR_OPCODE 31:29 +#define NVC86F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC86F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC86F_DMA_NONINCR_ADDRESS 11:0 +#define NVC86F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC86F_DMA_NONINCR_COUNT 28:16 +#define NVC86F_DMA_NONINCR_OPCODE 31:29 +#define NVC86F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC86F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC86F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC86F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC86F_DMA_ONEINCR_COUNT 28:16 +#define NVC86F_DMA_ONEINCR_OPCODE 31:29 +#define NVC86F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC86F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC86F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC86F_DMA_IMMD_ADDRESS 11:0 +#define NVC86F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC86F_DMA_IMMD_DATA 28:16 +#define NVC86F_DMA_IMMD_OPCODE 31:29 +#define NVC86F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC86F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC86F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC86F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC86F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC86F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC86F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC86F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC86F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC86F_DMA_ENDSEG_OPCODE 31:29 +#define NVC86F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC86F_DMA_ADDRESS 12:2 +#define NVC86F_DMA_SUBCH 15:13 +#define NVC86F_DMA_OPCODE3 17:16 +#define NVC86F_DMA_OPCODE3_NONE (0x00000000) +#define NVC86F_DMA_COUNT 28:18 +#define NVC86F_DMA_OPCODE 31:29 +#define NVC86F_DMA_OPCODE_METHOD (0x00000000) +#define NVC86F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC86F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc86f_h_ */ diff --git a/kernel-open/nvidia-uvm/clc8b5.h b/kernel-open/nvidia-uvm/clc8b5.h new file mode 100644 index 000000000..9e728c6b3 --- /dev/null +++ b/kernel-open/nvidia-uvm/clc8b5.h @@ -0,0 +1,430 @@ +/******************************************************************************* + Copyright (c) 1993-2004 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#include "nvtypes.h" + +#ifndef _clc8b5_h_ +#define _clc8b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_DMA_COPY_A (0x0000C8B5) + +typedef volatile struct _clc8b5_tag0 { + NvV32 Reserved00[0x40]; + NvV32 Nop; // 0x00000100 - 0x00000103 + NvV32 Reserved01[0xF]; + NvV32 PmTrigger; // 0x00000140 - 0x00000143 + NvV32 Reserved02[0x36]; + NvV32 SetMonitoredFenceType; // 0x0000021C - 0x0000021F + NvV32 SetMonitoredFenceSignalAddrBaseUpper; // 0x00000220 - 0x00000223 + NvV32 SetMonitoredFenceSignalAddrBaseLower; // 0x00000224 - 0x00000227 + NvV32 Reserved03[0x6]; + NvV32 SetSemaphoreA; // 0x00000240 - 0x00000243 + NvV32 SetSemaphoreB; // 0x00000244 - 0x00000247 + NvV32 SetSemaphorePayload; // 0x00000248 - 0x0000024B + NvV32 SetSemaphorePayloadUpper; // 0x0000024C - 0x0000024F + NvV32 Reserved04[0x1]; + NvV32 SetRenderEnableA; // 0x00000254 - 0x00000257 + NvV32 SetRenderEnableB; // 0x00000258 - 0x0000025B + NvV32 SetRenderEnableC; // 0x0000025C - 0x0000025F + NvV32 SetSrcPhysMode; // 0x00000260 - 0x00000263 + NvV32 SetDstPhysMode; // 0x00000264 - 0x00000267 + NvV32 Reserved05[0x26]; + NvV32 LaunchDma; // 0x00000300 - 0x00000303 + NvV32 Reserved06[0x3F]; + NvV32 OffsetInUpper; // 0x00000400 - 0x00000403 + NvV32 OffsetInLower; // 0x00000404 - 0x00000407 + NvV32 OffsetOutUpper; // 0x00000408 - 0x0000040B + NvV32 OffsetOutLower; // 0x0000040C - 0x0000040F + NvV32 PitchIn; // 0x00000410 - 0x00000413 + NvV32 PitchOut; // 0x00000414 - 0x00000417 + NvV32 LineLengthIn; // 0x00000418 - 0x0000041B + NvV32 LineCount; // 0x0000041C - 0x0000041F + NvV32 Reserved07[0x38]; + NvV32 SetSecureCopyMode; // 0x00000500 - 0x00000503 + NvV32 SetDecryptIv0; // 0x00000504 - 0x00000507 + NvV32 SetDecryptIv1; // 0x00000508 - 0x0000050B + NvV32 SetDecryptIv2; // 0x0000050C - 0x0000050F + NvV32 Reserved_SetAESCounter; // 0x00000510 - 0x00000513 + NvV32 SetDecryptAuthTagCompareAddrUpper; // 0x00000514 - 0x00000517 + NvV32 SetDecryptAuthTagCompareAddrLower; // 0x00000518 - 0x0000051B + NvV32 Reserved08[0x5]; + NvV32 SetEncryptAuthTagAddrUpper; // 0x00000530 - 0x00000533 + NvV32 SetEncryptAuthTagAddrLower; // 0x00000534 - 0x00000537 + NvV32 SetEncryptIvAddrUpper; // 0x00000538 - 0x0000053B + NvV32 SetEncryptIvAddrLower; // 0x0000053C - 0x0000053F + NvV32 Reserved09[0x6F]; + NvV32 SetMemoryScrubParameters; // 0x000006FC - 0x000006FF + NvV32 SetRemapConstA; // 0x00000700 - 0x00000703 + NvV32 SetRemapConstB; // 0x00000704 - 0x00000707 + NvV32 SetRemapComponents; // 0x00000708 - 0x0000070B + NvV32 SetDstBlockSize; // 0x0000070C - 0x0000070F + NvV32 SetDstWidth; // 0x00000710 - 0x00000713 + NvV32 SetDstHeight; // 0x00000714 - 0x00000717 + NvV32 SetDstDepth; // 0x00000718 - 0x0000071B + NvV32 SetDstLayer; // 0x0000071C - 0x0000071F + NvV32 SetDstOrigin; // 0x00000720 - 0x00000723 + NvV32 Reserved10[0x1]; + NvV32 SetSrcBlockSize; // 0x00000728 - 0x0000072B + NvV32 SetSrcWidth; // 0x0000072C - 0x0000072F + NvV32 SetSrcHeight; // 0x00000730 - 0x00000733 + NvV32 SetSrcDepth; // 0x00000734 - 0x00000737 + NvV32 SetSrcLayer; // 0x00000738 - 0x0000073B + NvV32 SetSrcOrigin; // 0x0000073C - 0x0000073F + NvV32 Reserved11[0x1]; + NvV32 SrcOriginX; // 0x00000744 - 0x00000747 + NvV32 SrcOriginY; // 0x00000748 - 0x0000074B + NvV32 DstOriginX; // 0x0000074C - 0x0000074F + NvV32 DstOriginY; // 0x00000750 - 0x00000753 + NvV32 Reserved12[0x270]; + NvV32 PmTriggerEnd; // 0x00001114 - 0x00001117 + NvV32 Reserved13[0x3BA]; +} hopper_dma_copy_aControlPio; + +#define NVC8B5_NOP (0x00000100) +#define NVC8B5_NOP_PARAMETER 31:0 +#define NVC8B5_PM_TRIGGER (0x00000140) +#define NVC8B5_PM_TRIGGER_V 31:0 +#define NVC8B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 24:0 +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC8B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC8B5_SET_RENDER_ENABLE_A_UPPER 24:0 +#define NVC8B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC8B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC8B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC8B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC8B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC8B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20 +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_RESERVED (0x00000003) +#define NVC8B5_LAUNCH_DMA_VPRMODE 22:22 +#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC8B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC8B5_OFFSET_IN_UPPER (0x00000400) +#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_IN_LOWER (0x00000404) +#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_PITCH_IN (0x00000410) +#define NVC8B5_PITCH_IN_VALUE 31:0 +#define NVC8B5_PITCH_OUT (0x00000414) +#define NVC8B5_PITCH_OUT_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC8B5_LINE_COUNT (0x0000041C) +#define NVC8B5_LINE_COUNT_VALUE 31:0 +#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0 +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET 20:19 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID 23:21 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA 24:24 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET 26:25 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID 29:27 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA 30:30 +#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY 31:31 +#define NVC8B5_SET_DECRYPT_IV0 (0x00000504) +#define NVC8B5_SET_DECRYPT_IV0_VALUE 31:0 +#define NVC8B5_SET_DECRYPT_IV1 (0x00000508) +#define NVC8B5_SET_DECRYPT_IV1_VALUE 31:0 +#define NVC8B5_SET_DECRYPT_IV2 (0x0000050C) +#define NVC8B5_SET_DECRYPT_IV2_VALUE 31:0 +#define NVC8B5_RESERVED_SET_AESCOUNTER (0x00000510) +#define NVC8B5_RESERVED_SET_AESCOUNTER_VALUE 31:0 +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE (0x00000001) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_A_V 31:0 +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_CONST_B_V 31:0 +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC8B5_SET_DST_WIDTH (0x00000710) +#define NVC8B5_SET_DST_WIDTH_V 31:0 +#define NVC8B5_SET_DST_HEIGHT (0x00000714) +#define NVC8B5_SET_DST_HEIGHT_V 31:0 +#define NVC8B5_SET_DST_DEPTH (0x00000718) +#define NVC8B5_SET_DST_DEPTH_V 31:0 +#define NVC8B5_SET_DST_LAYER (0x0000071C) +#define NVC8B5_SET_DST_LAYER_V 31:0 +#define NVC8B5_SET_DST_ORIGIN (0x00000720) +#define NVC8B5_SET_DST_ORIGIN_X 15:0 +#define NVC8B5_SET_DST_ORIGIN_Y 31:16 +#define NVC8B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC8B5_SET_SRC_WIDTH (0x0000072C) +#define NVC8B5_SET_SRC_WIDTH_V 31:0 +#define NVC8B5_SET_SRC_HEIGHT (0x00000730) +#define NVC8B5_SET_SRC_HEIGHT_V 31:0 +#define NVC8B5_SET_SRC_DEPTH (0x00000734) +#define NVC8B5_SET_SRC_DEPTH_V 31:0 +#define NVC8B5_SET_SRC_LAYER (0x00000738) +#define NVC8B5_SET_SRC_LAYER_V 31:0 +#define NVC8B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC8B5_SET_SRC_ORIGIN_X 15:0 +#define NVC8B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC8B5_SRC_ORIGIN_X (0x00000744) +#define NVC8B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC8B5_SRC_ORIGIN_Y (0x00000748) +#define NVC8B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC8B5_DST_ORIGIN_X (0x0000074C) +#define NVC8B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC8B5_DST_ORIGIN_Y (0x00000750) +#define NVC8B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC8B5_PM_TRIGGER_END (0x00001114) +#define NVC8B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc8b5_h + diff --git a/kernel-open/nvidia-uvm/ctrl2080mc.h b/kernel-open/nvidia-uvm/ctrl2080mc.h index d9815affd..99f32fab8 100644 --- a/kernel-open/nvidia-uvm/ctrl2080mc.h +++ b/kernel-open/nvidia-uvm/ctrl2080mc.h @@ -32,15 +32,8 @@ #define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100 (0x00000140) #define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160) #define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) - - - - - - - - - +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 (0x00000180) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190) /* valid ARCHITECTURE_GP10x implementation values */ #define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GP100 (0x00000000) diff --git a/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_fault.h b/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_fault.h new file mode 100644 index 000000000..83f79cb6d --- /dev/null +++ b/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_fault.h @@ -0,0 +1,508 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gh100_dev_fault_h__ +#define __gh100_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT /* ----G */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 55 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF1 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF2 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF3 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF4 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF5 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF6 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF7 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF8 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC3 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC4 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC5 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC6 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC7 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG1 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG2 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG3 30 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG4 31 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG5 32 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG6 33 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG7 34 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 45 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 46 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 47 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 48 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 49 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 50 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 51 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE9 52 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 35 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 36 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 37 /* */ +#define NV_PFAULT_MMU_ENG_ID_OFA0 53 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 65 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 66 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 67 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 68 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 69 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 70 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 71 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 72 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 73 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 74 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST11 75 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST12 76 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST13 77 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST14 78 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST15 79 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST16 80 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST17 81 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST18 82 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST19 83 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST20 84 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST21 85 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST22 86 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST23 87 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST24 88 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST25 89 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST26 90 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST27 91 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST28 92 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST29 93 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST30 94 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST31 95 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST32 96 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST33 97 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST34 98 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST35 99 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST36 100 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST37 101 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST38 102 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST39 103 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST40 104 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST41 105 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST42 106 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST43 107 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST44 108 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 256 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 257 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 258 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 259 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 260 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 261 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 262 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 263 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 264 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 265 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 266 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 267 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 268 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 269 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 270 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 271 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 272 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 273 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 274 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 275 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 276 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 277 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 278 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 279 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 280 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 281 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 282 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 283 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 284 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 285 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 286 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 287 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 288 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 289 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 290 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 291 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 292 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 293 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 294 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 295 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 296 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 297 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 298 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 299 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 300 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 301 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 302 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 303 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 304 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 305 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 306 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 307 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 308 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 309 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 310 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 311 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 312 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 313 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 314 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 315 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 316 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 317 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 318 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 319 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 320 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 321 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 322 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 323 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 324 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 325 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 326 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 327 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 328 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 329 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 330 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 331 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 332 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 333 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 334 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 335 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 336 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 337 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 338 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 339 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 340 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 341 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 342 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 343 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 344 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 345 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 346 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 347 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 348 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 349 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 350 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 351 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 352 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 353 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 354 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 355 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 356 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 357 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 358 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 359 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 360 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 361 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 362 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 363 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 364 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 365 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 366 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 367 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 368 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 369 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 370 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 371 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 372 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 373 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 374 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 375 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 376 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 377 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 378 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 379 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 380 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 381 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 382 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 383 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */ +#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X8 0x00000046 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X9 0x00000047 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X10 0x00000048 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X11 0x00000049 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X12 0x0000004A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X13 0x0000004B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X14 0x0000004C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X15 0x0000004D /* */ +#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */ +#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */ +#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */ +#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */ +#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */ +#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */ +#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */ +#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */ +#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */ +#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */ +#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */ +#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC5 0x0000006F /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC6 0x00000070 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC7 0x00000071 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG4 0x00000075 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG5 0x00000076 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG6 0x00000077 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG7 0x00000078 /* */ +#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */ +#define NV_PFAULT_ACCESS_TYPE 19:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#define NV_PFAULT_PROTECTED_MODE 29:29 /* */ +#define NV_PFAULT_REPLAYABLE_FAULT_EN 30:30 /* */ +#define NV_PFAULT_VALID 31:31 /* */ +#endif // __gh100_dev_fault_h__ diff --git a/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h b/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h new file mode 100644 index 000000000..42b11fead --- /dev/null +++ b/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h @@ -0,0 +1,560 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gh100_dev_mmu_h__ +#define __gh100_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+7):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */ +#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */ +#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */ +#define NV_MMU_VER1_PDE /* ----G */ +#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PDE__SIZE 8 +#define NV_MMU_VER1_PTE /* ----G */ +#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PTE__SIZE 8 +#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_NEW_PDE /* ----G */ +#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PDE__SIZE 8 +#define NV_MMU_NEW_DUAL_PDE /* ----G */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_NEW_DUAL_PDE__SIZE 16 +#define NV_MMU_NEW_PTE /* ----G */ +#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_NEW_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PTE__SIZE 8 +#define NV_MMU_VER2_PDE /* ----G */ +#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PDE__SIZE 8 +#define NV_MMU_VER2_DUAL_PDE /* ----G */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER2_DUAL_PDE__SIZE 16 +#define NV_MMU_VER2_PTE /* ----G */ +#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER2_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PTE__SIZE 8 +#define NV_MMU_VER3_PDE /* ----G */ +#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PDE__SIZE 8 +#define NV_MMU_VER3_DUAL_PDE /* ----G */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER3_DUAL_PDE__SIZE 16 +#define NV_MMU_VER3_PTE /* ----G */ +#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */ +#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE 0x0000000A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE 0x0000000B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE 0x0000000E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000F /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD 0x00000013 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD 0x00000014 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD 0x00000015 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD 0x00000016 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD 0x00000017 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD 0x0000001A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD 0x0000001B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD 0x0000001E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */ +#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PTE__SIZE 8 +#define NV_MMU_CLIENT /* ----G */ +#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */ +#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */ +#endif // __gh100_dev_mmu_h__ diff --git a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild index f8666478f..705421fef 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild @@ -1,6 +1,12 @@ NVIDIA_UVM_SOURCES ?= NVIDIA_UVM_SOURCES_CXX ?= +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_fault_buffer.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_ce.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_host.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_mmu.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ada.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_common.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_linux.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_debug_optimized.c diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index 476c12548..6985dc56a 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -1094,7 +1094,6 @@ static int uvm_init(void) if (uvm_enable_builtin_tests) pr_info("Built-in UVM tests are enabled. This is a security risk.\n"); - // After Open RM is released, both the enclosing "#if" and this comment // block should be removed, because the uvm_hmm_is_enabled_system_wide() // check is both necessary and sufficient for reporting functionality. @@ -1104,7 +1103,6 @@ static int uvm_init(void) if (uvm_hmm_is_enabled_system_wide()) UVM_INFO_PRINT("HMM (Heterogeneous Memory Management) is enabled in the UVM driver.\n"); - return 0; error: @@ -1146,4 +1144,4 @@ module_exit(uvm_exit_entry); MODULE_LICENSE("Dual MIT/GPL"); MODULE_INFO(supported, "external"); - +MODULE_VERSION(NV_VERSION_STRING); diff --git a/kernel-open/nvidia-uvm/uvm.h b/kernel-open/nvidia-uvm/uvm.h index 32922fb7d..69c25677e 100644 --- a/kernel-open/nvidia-uvm/uvm.h +++ b/kernel-open/nvidia-uvm/uvm.h @@ -216,12 +216,6 @@ NV_STATUS UvmDeinitialize(void); // Note that it is not required to release VA ranges that were reserved with // UvmReserveVa(). // - - - - - - // UvmReopen() closes the open file returned by UvmGetFileDescriptor() and // replaces it with a new open file with the same name. // @@ -416,14 +410,6 @@ NV_STATUS UvmRegisterGpuSmc(const NvProcessorUuid *gpuUuid, // location will have their range group association changed to // UVM_RANGE_GROUP_ID_NONE. // - - - - - - - - // Arguments: // gpuUuid: (INPUT) // UUID of the GPU to unregister. @@ -1276,14 +1262,6 @@ NV_STATUS UvmCleanUpZombieResources(void); // // The VA range can be unmapped and freed via a call to UvmFree. // - - - - - - - - // Arguments: // base: (INPUT) // Base address of the virtual address range. @@ -1320,10 +1298,6 @@ NV_STATUS UvmCleanUpZombieResources(void); // NV_ERR_INVALID_ARGUMENT: // perGpuAttribs is NULL but gpuAttribsCount is non-zero or vice-versa, // or caching is requested on more than one GPU. - - - - // // NV_ERR_NOT_SUPPORTED: // The current process is not the one which called UvmInitialize, and diff --git a/kernel-open/nvidia-uvm/uvm_ada.c b/kernel-open/nvidia-uvm/uvm_ada.c new file mode 100644 index 000000000..820ac0e14 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_ada.c @@ -0,0 +1,95 @@ +/******************************************************************************* + Copyright (c) 2021 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_global.h" +#include "uvm_hal.h" +#include "uvm_gpu.h" +#include "uvm_mem.h" +#include "uvm_ada_fault_buffer.h" + +void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu) +{ + parent_gpu->tlb_batch.va_invalidate_supported = true; + + parent_gpu->tlb_batch.va_range_invalidate_supported = true; + + // TODO: Bug 1767241: Run benchmarks to figure out a good number + parent_gpu->tlb_batch.max_ranges = 8; + + parent_gpu->utlb_per_gpc_count = uvm_ada_get_utlbs_per_gpc(parent_gpu); + + parent_gpu->fault_buffer_info.replayable.utlb_count = parent_gpu->rm_info.maxGpcCount * + parent_gpu->utlb_per_gpc_count; + { + uvm_fault_buffer_entry_t *dummy; + UVM_ASSERT(parent_gpu->fault_buffer_info.replayable.utlb_count <= (1 << (sizeof(dummy->fault_source.utlb_id) * + 8))); + } + + // A single top level PDE on Ada covers 128 TB and that's the minimum size + // that can be used. + parent_gpu->rm_va_base = 0; + parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + + parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + + parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; + + // Not all units on Ada support 49-bit addressing, including those which + // access channel buffers. + parent_gpu->max_channel_va = 1ULL << 40; + + parent_gpu->max_host_va = 1ULL << 40; + + // Ada can map sysmem with any page size + parent_gpu->can_map_sysmem_with_large_pages = true; + + // Prefetch instructions will generate faults + parent_gpu->prefetch_fault_supported = true; + + // Ada can place GPFIFO in vidmem + parent_gpu->gpfifo_in_vidmem_supported = true; + + parent_gpu->replayable_faults_supported = true; + + parent_gpu->non_replayable_faults_supported = true; + + parent_gpu->access_counters_supported = true; + + parent_gpu->fault_cancel_va_supported = true; + + parent_gpu->scoped_atomics_supported = true; + + parent_gpu->has_clear_faulted_channel_sw_method = true; + + parent_gpu->has_clear_faulted_channel_method = false; + + parent_gpu->smc.supported = true; + + parent_gpu->sparse_mappings_supported = true; + + parent_gpu->map_remap_larger_page_promotion = false; + + parent_gpu->plc_supported = true; +} diff --git a/kernel-open/nvidia-uvm/uvm_ada_fault_buffer.h b/kernel-open/nvidia-uvm/uvm_ada_fault_buffer.h new file mode 100644 index 000000000..48c7ae17c --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_ada_fault_buffer.h @@ -0,0 +1,84 @@ +/******************************************************************************* + Copyright (c) 2021 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_HAL_ADA_FAULT_BUFFER_H__ +#define __UVM_HAL_ADA_FAULT_BUFFER_H__ + +#include "nvtypes.h" +#include "uvm_common.h" +#include "uvm_gpu.h" + +// There are up to 6 TPCs per GPC in Ada, and there are 2 LTP uTLB per TPC. +// Besides, there is one RGG uTLB per GPC. Each TPC has a number of clients +// that can make requests to its uTLBs: 1xTPCCS, 1xPE, 2xT1. Requests from +// these units are routed as follows to the 2 LTP uTLBs: +// +// -------- --------- +// | T1_0 | -----------------> | uTLB0 | +// -------- --------- +// +// -------- --------- +// | T1_1 | -----------------> | uTLB1 | +// -------- --------> --------- +// | ^ +// ------- | | +// | PE | ----------- | +// ------- | +// | +// --------- | +// | TPCCS | ----------------------- +// --------- +// +// +// The client ids are local to their GPC and the id mapping is linear across +// TPCs: TPC_n has TPCCS_n, PE_n, T1_p, and T1_q, where p=2*n and q=p+1. +// +// NV_PFAULT_CLIENT_GPC_LTP_UTLB_n and NV_PFAULT_CLIENT_GPC_RGG_UTLB enums can +// be ignored. These will never be reported in a fault message, and should +// never be used in an invalidate. Therefore, we define our own values. +typedef enum { + UVM_ADA_GPC_UTLB_ID_RGG = 0, + UVM_ADA_GPC_UTLB_ID_LTP0 = 1, + UVM_ADA_GPC_UTLB_ID_LTP1 = 2, + UVM_ADA_GPC_UTLB_ID_LTP2 = 3, + UVM_ADA_GPC_UTLB_ID_LTP3 = 4, + UVM_ADA_GPC_UTLB_ID_LTP4 = 5, + UVM_ADA_GPC_UTLB_ID_LTP5 = 6, + UVM_ADA_GPC_UTLB_ID_LTP6 = 7, + UVM_ADA_GPC_UTLB_ID_LTP7 = 8, + UVM_ADA_GPC_UTLB_ID_LTP8 = 9, + UVM_ADA_GPC_UTLB_ID_LTP9 = 10, + UVM_ADA_GPC_UTLB_ID_LTP10 = 11, + UVM_ADA_GPC_UTLB_ID_LTP11 = 12, + + UVM_ADA_GPC_UTLB_COUNT, +} uvm_ada_gpc_utlb_id_t; + +static NvU32 uvm_ada_get_utlbs_per_gpc(uvm_parent_gpu_t *parent_gpu) +{ + NvU32 utlbs = parent_gpu->rm_info.maxTpcPerGpcCount * 2 + 1; + UVM_ASSERT(utlbs <= UVM_ADA_GPC_UTLB_COUNT); + return utlbs; +} + +#endif diff --git a/kernel-open/nvidia-uvm/uvm_ampere.c b/kernel-open/nvidia-uvm/uvm_ampere.c index 6cbb8c8fa..e949c80f1 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere.c +++ b/kernel-open/nvidia-uvm/uvm_ampere.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2021 NVIDIA Corporation + Copyright (c) 2018-20221 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -53,7 +53,7 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; // See uvm_mmu.h for mapping placement - parent_gpu->flat_vidmem_va_base = 132ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->flat_vidmem_va_base = 136ull * 1024 * 1024 * 1024 * 1024; parent_gpu->flat_sysmem_va_base = 256ull * 1024 * 1024 * 1024 * 1024; parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; diff --git a/kernel-open/nvidia-uvm/uvm_ampere_host.c b/kernel-open/nvidia-uvm/uvm_ampere_host.c index dc1ec0638..1c5053a23 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_host.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_host.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2021 NVIDIA Corporation + Copyright (c) 2018-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -107,6 +107,8 @@ void uvm_hal_ampere_host_clear_faulted_channel_register(uvm_user_channel_t *user uvm_spin_loop_t spin; NvU32 channel_faulted_mask = 0; NvU32 clear_type_value = 0; + NvU32 doorbell_value = 0; + volatile NvU32 *doorbell_ptr; UVM_ASSERT(!user_channel->gpu->parent->has_clear_faulted_channel_method); @@ -123,6 +125,12 @@ void uvm_hal_ampere_host_clear_faulted_channel_register(uvm_user_channel_t *user uvm_mmu_engine_type_string(fault->fault_source.mmu_engine_type)); } + doorbell_ptr = (NvU32 *)((NvU8 *)user_channel->runlist_pri_base_register + NV_RUNLIST_INTERNAL_DOORBELL); + + // GFID is not required since we clear faulted channel with a SW method on + // SRIOV. On baremetal, GFID is always zero. + doorbell_value = HWVALUE(_RUNLIST, INTERNAL_DOORBELL, CHID, user_channel->hw_channel_id); + // Wait for the channel to have the FAULTED bit set as this can race with // interrupt notification UVM_SPIN_WHILE(!(UVM_GPU_READ_ONCE(*user_channel->chram_channel_register) & channel_faulted_mask), &spin); @@ -131,7 +139,7 @@ void uvm_hal_ampere_host_clear_faulted_channel_register(uvm_user_channel_t *user wmb(); - UVM_GPU_WRITE_ONCE(*user_channel->work_submission_offset, user_channel->work_submission_token); + UVM_GPU_WRITE_ONCE(*doorbell_ptr, doorbell_value); } static NvU32 instance_ptr_aperture_type_to_hw_value(uvm_aperture_t aperture) diff --git a/kernel-open/nvidia-uvm/uvm_ats.c b/kernel-open/nvidia-uvm/uvm_ats.c index 1b5d6c5e3..0dcd5e6dd 100644 --- a/kernel-open/nvidia-uvm/uvm_ats.c +++ b/kernel-open/nvidia-uvm/uvm_ats.c @@ -58,12 +58,6 @@ NV_STATUS uvm_ats_add_gpu(uvm_parent_gpu_t *parent_gpu) return uvm_ats_ibm_add_gpu(parent_gpu); } - - - - - - return NV_OK; } @@ -77,12 +71,6 @@ void uvm_ats_remove_gpu(uvm_parent_gpu_t *parent_gpu) uvm_ats_ibm_remove_gpu(parent_gpu); } - - - - - - } NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) @@ -100,10 +88,6 @@ NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_bind_gpu(gpu_va_space); - - - - return status; } @@ -116,10 +100,6 @@ void uvm_ats_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unbind_gpu(gpu_va_space); - - - - } NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) @@ -147,10 +127,6 @@ NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_register_gpu_va_space(gpu_va_space); - - - - if (status == NV_OK) uvm_processor_mask_set(&va_space->ats.registered_gpu_va_spaces, gpu_id); @@ -173,10 +149,6 @@ void uvm_ats_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unregister_gpu_va_space(gpu_va_space); - - - - uvm_va_space_down_write(va_space); uvm_processor_mask_clear(&va_space->ats.registered_gpu_va_spaces, gpu_id); uvm_va_space_up_write(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_ats.h b/kernel-open/nvidia-uvm/uvm_ats.h index ad8c514aa..2d4d8f336 100644 --- a/kernel-open/nvidia-uvm/uvm_ats.h +++ b/kernel-open/nvidia-uvm/uvm_ats.h @@ -29,14 +29,8 @@ #include "uvm_ats_ibm.h" #include "nv_uvm_types.h" - - - - - #define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED()) - typedef struct { // Mask of gpu_va_spaces which are registered for ATS access. The mask is @@ -47,11 +41,6 @@ typedef struct { uvm_ibm_va_space_t ibm; - - - - - }; } uvm_ats_va_space_t; @@ -69,11 +58,6 @@ typedef struct { uvm_ibm_gpu_va_space_t ibm; - - - - - }; } uvm_ats_gpu_va_space_t; @@ -106,10 +90,6 @@ void uvm_ats_remove_gpu(uvm_parent_gpu_t *parent_gpu); // LOCKING: mmap_lock must be lockable. // VA space lock must be lockable. // gpu_va_space->gpu must be retained. - - - - NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space); // Decrements the refcount on the {gpu, mm} pair. Removes the binding from the diff --git a/kernel-open/nvidia-uvm/uvm_ce_test.c b/kernel-open/nvidia-uvm/uvm_ce_test.c index dd1ba52dd..e12242f97 100644 --- a/kernel-open/nvidia-uvm/uvm_ce_test.c +++ b/kernel-open/nvidia-uvm/uvm_ce_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -52,13 +52,13 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) uvm_push_t push; bool is_proxy; - status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, CE_TEST_MEM_SIZE, &host_mem); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, CE_TEST_MEM_SIZE, 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); memset(host_ptr, 0, CE_TEST_MEM_SIZE); for (i = 0; i < CE_TEST_MEM_COUNT; ++i) { - status = uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, CE_TEST_MEM_SIZE, &mem[i]); + status = uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, CE_TEST_MEM_SIZE, 0, &mem[i]); TEST_CHECK_GOTO(status == NV_OK, done); } @@ -167,7 +167,7 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu) uvm_push_t push; NvU32 value; - status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(NvU32), &host_mem); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(NvU32), 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); *host_ptr = 0; @@ -429,13 +429,13 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) gpu_addresses[1] = uvm_mem_gpu_address_physical(gpu_uvm_mem, gpu, 0, size); // Virtual address (in UVM's internal address space) backed by vidmem - TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, size, &gpu_rm_mem), done); + TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, size, 0, &gpu_rm_mem), done); is_proxy_va_space = false; gpu_va = uvm_rm_mem_get_gpu_va(gpu_rm_mem, gpu, is_proxy_va_space); gpu_addresses[2] = uvm_gpu_address_virtual(gpu_va); // Virtual address (in UVM's internal address space) backed by sysmem - TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, &sys_rm_mem), done); + TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &sys_rm_mem), done); gpu_va = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); gpu_addresses[3] = uvm_gpu_address_virtual(gpu_va); diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index b1b2177f8..18611cfbd 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -97,8 +97,11 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, if (mode == UVM_CHANNEL_UPDATE_MODE_COMPLETED && entry->tracking_semaphore_value > completed_value) break; - uvm_pushbuffer_mark_completed(channel->pool->manager->pushbuffer, entry); - list_add_tail(&entry->push_info->available_list_node, &channel->available_push_infos); + if (entry->type == UVM_GPFIFO_ENTRY_TYPE_NORMAL) { + uvm_pushbuffer_mark_completed(channel->pool->manager->pushbuffer, entry); + list_add_tail(&entry->push_info->available_list_node, &channel->available_push_infos); + } + gpu_get = (gpu_get + 1) % channel->num_gpfifo_entries; ++completed_count; } @@ -150,25 +153,31 @@ NvU32 uvm_channel_manager_update_progress(uvm_channel_manager_t *channel_manager return pending_gpfifos; } -static bool channel_is_available(uvm_channel_t *channel) +static bool channel_is_available(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { - NvU32 next_put; + NvU32 pending_entries; uvm_assert_spinlock_locked(&channel->pool->lock); - next_put = (channel->cpu_put + channel->current_pushes_count + 1) % channel->num_gpfifo_entries; + if (channel->cpu_put >= channel->gpu_get) + pending_entries = channel->cpu_put - channel->gpu_get; + else + pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; - return (next_put != channel->gpu_get); + return (pending_entries + channel->current_gpfifo_count + num_gpfifo_entries < channel->num_gpfifo_entries); } -static bool try_claim_channel(uvm_channel_t *channel) +static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { bool claimed = false; + UVM_ASSERT(num_gpfifo_entries > 0); + UVM_ASSERT(num_gpfifo_entries < channel->num_gpfifo_entries); + uvm_spin_lock(&channel->pool->lock); - if (channel_is_available(channel)) { - ++channel->current_pushes_count; + if (channel_is_available(channel, num_gpfifo_entries)) { + channel->current_gpfifo_count += num_gpfifo_entries; claimed = true; } @@ -179,26 +188,14 @@ static bool try_claim_channel(uvm_channel_t *channel) static void lock_push(uvm_channel_t *channel) { - - - - } static void unlock_push(uvm_channel_t *channel) { - - - - } static bool trylock_push(uvm_channel_t *channel) { - - - - return true; } @@ -212,13 +209,8 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t uvm_for_each_channel_in_pool(channel, pool) { // TODO: Bug 1764953: Prefer idle/less busy channels - - - - - if (trylock_push(channel)) { - if (try_claim_channel(channel)) { + if (try_claim_channel(channel, 1)) { *channel_out = channel; return NV_OK; } @@ -235,7 +227,7 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t uvm_channel_update_progress(channel); - if (try_claim_channel(channel)) { + if (try_claim_channel(channel, 1)) { lock_push(channel); *channel_out = channel; @@ -319,13 +311,6 @@ NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) manager = channel->pool->manager; - - - - - - - status = uvm_pushbuffer_begin_push(manager->pushbuffer, push); if (status != NV_OK) return status; @@ -407,10 +392,6 @@ static void uvm_channel_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, if (uvm_channel_is_ce(push->channel)) gpu->parent->ce_hal->semaphore_release(push, semaphore_va, new_payload); - - - - else UVM_ASSERT_MSG(0, "Semaphore release on an unsupported channel.\n"); } @@ -447,9 +428,10 @@ void uvm_channel_end_push(uvm_push_t *push) entry->pushbuffer_offset = uvm_pushbuffer_get_offset_for_push(pushbuffer, push); entry->pushbuffer_size = push_size; entry->push_info = &channel->push_infos[push->push_info_index]; + entry->type = UVM_GPFIFO_ENTRY_TYPE_NORMAL; - UVM_ASSERT(channel->current_pushes_count > 0); - --channel->current_pushes_count; + UVM_ASSERT(channel->current_gpfifo_count > 0); + --channel->current_gpfifo_count; if (uvm_channel_is_proxy(channel)) proxy_channel_submit_work(push, push_size); @@ -477,18 +459,116 @@ void uvm_channel_end_push(uvm_push_t *push) push->channel_tracking_value = new_tracking_value; } -NV_STATUS uvm_channel_reserve(uvm_channel_t *channel) +// The caller must submit a normal GPFIFO entry with a semaphore release +// following the control GPFIFO, refer to uvm_channel_write_ctrl_gpfifo() for an +// example. +static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value) +{ + uvm_gpfifo_entry_t *entry; + NvU64 *gpfifo_entry; + NvU32 cpu_put; + NvU32 new_cpu_put; + uvm_gpu_t *gpu = channel->pool->manager->gpu; + + uvm_spin_lock(&channel->pool->lock); + + cpu_put = channel->cpu_put; + new_cpu_put = (cpu_put + 1) % channel->num_gpfifo_entries; + + entry = &channel->gpfifo_entries[cpu_put]; + memset(entry, 0, sizeof(*entry)); + entry->type = UVM_GPFIFO_ENTRY_TYPE_CONTROL; + + // Control GPFIFO entries are followed by a semaphore_release push in UVM. + // We add the tracking semaphore value of the next GPFIFO entry, + // potentially the associated semaphore release push. Even if a different + // GPFIFO entry sneaks in, the purposes of signaling that this control + // GPFIFO entry has been processed is accomplished. + entry->tracking_semaphore_value = channel->tracking_sem.queued_value + 1; + + UVM_ASSERT(channel->current_gpfifo_count > 1); + --channel->current_gpfifo_count; + + gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; + *gpfifo_entry = ctrl_fifo_entry_value; + + // Need to make sure all the GPFIFO entries writes complete before updating + // GPPUT. We also don't want any reads to be moved after the GPPut write as + // the GPU might modify the data they read as soon as the GPPut write + // happens. + mb(); + + gpu->parent->host_hal->write_gpu_put(channel, new_cpu_put); + + channel->cpu_put = new_cpu_put; + + // The moment the channel is unlocked uvm_channel_update_progress_with_max() + // may notice the GPU work to be completed and hence all state tracking the + // push must be updated before that. + uvm_spin_unlock(&channel->pool->lock); + unlock_push(channel); + + // This memory barrier is borrowed from CUDA, as it supposedly fixes perf + // issues on some systems. Comment from CUDA: "fixes throughput-related + // performance problems, e.g. bugs 626179, 593841. This may be related to + // bug 124888, which GL works around by doing a clflush" + wmb(); +} + +NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value) +{ + NV_STATUS status; + uvm_gpu_t *gpu = channel->pool->manager->gpu; + uvm_push_t push; + + UVM_ASSERT(!uvm_channel_is_proxy(channel)); + + // We reserve two GPFIFO entries, i.e., the control GPFIFO entry and the + // subsequent semaphore_release push. There is, however, a potential case + // for GPFIFO control submission starvation. This may happen because a + // GPFIFO control submission requires two available GPFIFO entries. If you + // have a full GPFIFO ring buffer that frees one entry at a time, while + // there is another thread consuming this recently released entry at the + // same rate, a concurrent thread trying to reserve two entries for a GPFIFO + // control submission may starve. We could handle this by imposing minimal + // release entries in uvm_channel.c:uvm_channel_update_progress(). Instead, + // we don't deal with this potential starvation case because: + // - Control GPFIFO are rarely used. + // - By default, we release up to 8 GPFIFO entries at a time, except if the + // release rate is constrained by lengthy pushbuffers -- another rare + // situation. + // - It would add unnecessary complexity to channel_update_progress(). + status = uvm_channel_reserve(channel, 2); + if (status != NV_OK) + return status; + + write_ctrl_gpfifo(channel, ctrl_fifo_entry_value); + + status = uvm_push_begin_on_reserved_channel(channel, &push, "write_ctrl_GPFIFO"); + if (status != NV_OK) { + UVM_ERR_PRINT("Failed to begin push on channel: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + return status; + } + + // This is an empty push, the push's embedded semaphore_release signals that + // the GPFIFO control entry has been processed. + uvm_push_end(&push); + + return NV_OK; +} + +NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { NV_STATUS status = NV_OK; uvm_spin_loop_t spin; - if (try_claim_channel(channel)) + if (try_claim_channel(channel, num_gpfifo_entries)) goto out; uvm_channel_update_progress(channel); uvm_spin_loop_init(&spin); - while (!try_claim_channel(channel) && status == NV_OK) { + while (!try_claim_channel(channel, num_gpfifo_entries) && status == NV_OK) { UVM_SPIN_LOOP(&spin); status = uvm_channel_check_errors(channel); uvm_channel_update_progress(channel); @@ -568,12 +648,28 @@ NV_STATUS uvm_channel_check_errors(uvm_channel_t *channel) fatal_entry = uvm_channel_get_fatal_entry(channel); if (fatal_entry != NULL) { - uvm_push_info_t *push_info = fatal_entry->push_info; - UVM_ERR_PRINT("Channel error likely caused by push '%s' started at %s:%d in %s()\n", - push_info->description, push_info->filename, push_info->line, push_info->function); + if (fatal_entry->type == UVM_GPFIFO_ENTRY_TYPE_NORMAL) { + uvm_push_info_t *push_info = fatal_entry->push_info; + UVM_ERR_PRINT("Channel error likely caused by push '%s' started at %s:%d in %s()\n", + push_info->description, + push_info->filename, + push_info->line, + push_info->function); + } + else { + NvU64 *gpfifo_entry; + + UVM_ASSERT(!uvm_channel_is_proxy(channel)); + + gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + (fatal_entry - channel->gpfifo_entries); + UVM_ERR_PRINT("Channel error likely caused by GPFIFO control entry, data: 0x%llx, gpu_get: %d\n", + *gpfifo_entry, + channel->gpu_get); + } } uvm_global_set_fatal_error(status); + return status; } @@ -608,40 +704,6 @@ NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel) return uvm_gpu_tracking_semaphore_update_completed_value(&channel->tracking_sem); } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) { UVM_ASSERT(pool->num_channels > 0); @@ -667,10 +729,6 @@ static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) uvm_kvfree(channel->gpfifo_entries); - - - - if (uvm_channel_is_proxy(channel)) uvm_rm_locked_call_void(nvUvmInterfacePagingChannelDestroy(channel->proxy.handle)); else @@ -694,11 +752,6 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine if (uvm_channel_is_ce(channel)) { UVM_ASSERT(channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); - - - - - } memset(&channel_alloc_params, 0, sizeof(channel_alloc_params)); @@ -710,10 +763,6 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine if (uvm_channel_is_ce(channel)) channel_alloc_params.engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_CE; - - - - status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(gpu->rm_address_space, &channel_alloc_params, &channel->handle, @@ -732,11 +781,7 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine channel_info->hwChannelId, channel_info->hwRunlistId, channel_info->hwChannelId, - - - "CE", - engine_index); return NV_OK; @@ -803,12 +848,6 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel if (status != NV_OK) goto error; - - - - - - channel->num_gpfifo_entries = manager->conf.num_gpfifo_entries; channel->gpfifo_entries = uvm_kvmalloc_zero(sizeof(*channel->gpfifo_entries) * channel->num_gpfifo_entries); if (channel->gpfifo_entries == NULL) { @@ -858,8 +897,25 @@ static NV_STATUS init_channel(uvm_channel_t *channel) { uvm_push_t push; uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - NV_STATUS status = uvm_push_begin_on_channel(channel, &push, "Init channel"); + NV_STATUS status; + NvU32 num_entries = 1; + if (uvm_gpu_has_pushbuffer_segments(gpu)) + num_entries++; + + status = uvm_channel_reserve(channel, num_entries); + if (status != NV_OK) + return status; + + if (uvm_gpu_has_pushbuffer_segments(gpu)) { + NvU64 gpfifo_entry; + uvm_pushbuffer_t *pushbuffer = channel->pool->manager->pushbuffer; + gpu->parent->host_hal->set_gpfifo_pushbuffer_segment_base(&gpfifo_entry, + uvm_pushbuffer_get_gpu_va_base(pushbuffer)); + write_ctrl_gpfifo(channel, gpfifo_entry); + } + + status = uvm_push_begin_on_reserved_channel(channel, &push, "Init channel"); if (status != NV_OK) { UVM_ERR_PRINT("Failed to begin push on channel: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); return status; @@ -868,10 +924,6 @@ static NV_STATUS init_channel(uvm_channel_t *channel) if (uvm_channel_is_ce(channel)) gpu->parent->ce_hal->init(&push); - - - - gpu->parent->host_hal->init(&push); status = uvm_push_end_and_wait(&push); @@ -1348,12 +1400,6 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) num_channel_pools++; - - - - - - manager->channel_pools = uvm_kvmalloc_zero(sizeof(*manager->channel_pools) * num_channel_pools); if (!manager->channel_pools) return NV_ERR_NO_MEMORY; @@ -1384,17 +1430,6 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) manager->pool_to_use.default_for_type[channel_type] = pool; } - - - - - - - - - - - return NV_OK; } @@ -1520,39 +1555,25 @@ uvm_channel_t *uvm_channel_any_of_type(uvm_channel_manager_t *manager, NvU32 poo const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type) { - - - BUILD_BUG_ON(UVM_CHANNEL_TYPE_COUNT != 5); - switch (channel_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_CPU_TO_GPU); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_TO_CPU); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_INTERNAL); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_MEMOPS); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_TO_GPU); - - - UVM_ENUM_STRING_DEFAULT(); } } const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type) { - - - BUILD_BUG_ON(UVM_CHANNEL_POOL_TYPE_COUNT != 2); - switch (channel_pool_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE); UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE_PROXY); - - - UVM_ENUM_STRING_DEFAULT(); } } @@ -1630,26 +1651,41 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c if (entry->tracking_semaphore_value + finished_pushes_count <= completed_value) continue; - // Obtain the value acquire tracking information from the push_info index - if (uvm_push_info_is_tracking_acquires()) { - NvU32 push_info_index = push_info - channel->push_infos; - UVM_ASSERT(push_info_index < channel->num_gpfifo_entries); + if (entry->type == UVM_GPFIFO_ENTRY_TYPE_CONTROL) { + NvU64 *gpfifo_entry; + + UVM_ASSERT(!uvm_channel_is_proxy(channel)); - push_acquire_info = &channel->push_acquire_infos[push_info_index]; + gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + gpu_get; + UVM_SEQ_OR_DBG_PRINT(seq, + " control GPFIFO entry - data: 0x%llx, gpu_get: %d\n", + *gpfifo_entry, + gpu_get); } + else { - UVM_SEQ_OR_DBG_PRINT(seq, - " %s push '%s' started at %s:%d in %s() releasing value %llu%s", - entry->tracking_semaphore_value <= completed_value ? "finished" : "pending", - push_info->description, - push_info->filename, - push_info->line, - push_info->function, - entry->tracking_semaphore_value, - !push_acquire_info || push_acquire_info->num_values == 0? "\n" : ""); - - if (push_acquire_info) - channel_print_push_acquires(push_acquire_info, seq); + // Obtain the value acquire tracking information from the push_info + // index + if (uvm_push_info_is_tracking_acquires()) { + NvU32 push_info_index = push_info - channel->push_infos; + UVM_ASSERT(push_info_index < channel->num_gpfifo_entries); + + push_acquire_info = &channel->push_acquire_infos[push_info_index]; + } + + UVM_SEQ_OR_DBG_PRINT(seq, + " %s push '%s' started at %s:%d in %s() releasing value %llu%s", + entry->tracking_semaphore_value <= completed_value ? "finished" : "pending", + push_info->description, + push_info->filename, + push_info->line, + push_info->function, + entry->tracking_semaphore_value, + !push_acquire_info || push_acquire_info->num_values == 0 ? "\n" : ""); + + if (push_acquire_info) + channel_print_push_acquires(push_acquire_info, seq); + } } uvm_spin_unlock(&channel->pool->lock); } @@ -1694,7 +1730,7 @@ static int nv_procfs_read_manager_pending_pushes(struct seq_file *s, void *v) uvm_channel_manager_t *manager = (uvm_channel_manager_t *)s->private; if (!uvm_down_read_trylock(&g_uvm_global.pm.lock)) - return -EAGAIN; + return -EAGAIN; channel_manager_print_pending_pushes(manager, s); @@ -1733,7 +1769,7 @@ static int nv_procfs_read_channel_info(struct seq_file *s, void *v) uvm_channel_t *channel = (uvm_channel_t *)s->private; if (!uvm_down_read_trylock(&g_uvm_global.pm.lock)) - return -EAGAIN; + return -EAGAIN; uvm_channel_print_info(channel, s); @@ -1754,7 +1790,7 @@ static int nv_procfs_read_channel_pushes(struct seq_file *s, void *v) uvm_channel_t *channel = (uvm_channel_t *)s->private; if (!uvm_down_read_trylock(&g_uvm_global.pm.lock)) - return -EAGAIN; + return -EAGAIN; // Include up to 5 finished pushes for some context channel_print_pushes(channel, 5, s); diff --git a/kernel-open/nvidia-uvm/uvm_channel.h b/kernel-open/nvidia-uvm/uvm_channel.h index fadc4b3c1..30bf74d6d 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.h +++ b/kernel-open/nvidia-uvm/uvm_channel.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -83,18 +83,7 @@ typedef enum // ^^^^^^ // Channel types backed by a CE. - - - - - - - - - - UVM_CHANNEL_TYPE_COUNT = UVM_CHANNEL_TYPE_CE_COUNT, - } uvm_channel_type_t; typedef enum @@ -112,34 +101,43 @@ typedef enum // There is a single proxy pool and channel per GPU. UVM_CHANNEL_POOL_TYPE_CE_PROXY = (1 << 1), - - - - - - - UVM_CHANNEL_POOL_TYPE_COUNT = 2, - // A mask used to select pools of any type. UVM_CHANNEL_POOL_TYPE_MASK = ((1U << UVM_CHANNEL_POOL_TYPE_COUNT) - 1) } uvm_channel_pool_type_t; +typedef enum +{ + // Push-based GPFIFO entry + UVM_GPFIFO_ENTRY_TYPE_NORMAL, + + // Control GPFIFO entry, i.e., the LENGTH field is zero, not associated with + // a push. + UVM_GPFIFO_ENTRY_TYPE_CONTROL +} uvm_gpfifo_entry_type_t; + struct uvm_gpfifo_entry_struct { - // Offset of the pushbuffer in the pushbuffer allocation used by this entry + uvm_gpfifo_entry_type_t type; + + // Channel tracking semaphore value that indicates completion of + // this entry. + NvU64 tracking_semaphore_value; + + // The following fields are only valid when type is + // UVM_GPFIFO_ENTRY_TYPE_NORMAL. + + // Offset of the pushbuffer in the pushbuffer allocation used by + // this entry. NvU32 pushbuffer_offset; - // Size of the pushbuffer used for this entry + // Size of the pushbuffer used for this entry. NvU32 pushbuffer_size; // List node used by the pushbuffer tracking struct list_head pending_list_node; - // Channel tracking semaphore value that indicates completion of this entry - NvU64 tracking_semaphore_value; - // Push info for the pending push that used this GPFIFO entry uvm_push_info_t *push_info; }; @@ -193,10 +191,10 @@ struct uvm_channel_struct // for completion. NvU32 gpu_get; - // Number of currently on-going pushes on this channel - // A new push is only allowed to begin on the channel if there is a free - // GPFIFO entry for it. - NvU32 current_pushes_count; + // Number of currently on-going gpfifo entries on this channel + // A new push or control GPFIFO is only allowed to begin on the channel if + // there is a free GPFIFO entry for it. + NvU32 current_gpfifo_count; // Array of uvm_push_info_t for all pending pushes on the channel uvm_push_info_t *push_infos; @@ -211,30 +209,10 @@ struct uvm_channel_struct // been marked as completed. struct list_head available_push_infos; - // GPU tracking semaphore tracking the work in the channel + // GPU tracking semaphore tracking the work in the channel. // Each push on the channel increments the semaphore, see // uvm_channel_end_push(). uvm_gpu_tracking_semaphore_t tracking_sem; - - - - - - - - - - - - - - - - - - - - // RM channel information union @@ -343,14 +321,6 @@ static bool uvm_channel_is_ce(uvm_channel_t *channel) return (channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_is_proxy(channel); } - - - - - - - - // Proxy channels are used to push page tree related methods, so their channel // type is UVM_CHANNEL_TYPE_MEMOPS. static uvm_channel_type_t uvm_channel_proxy_channel_type(void) @@ -437,8 +407,8 @@ NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *channel_manager, uvm_gpu_t *dst_gpu, uvm_channel_t **channel_out); -// Reserve a specific channel for a push -NV_STATUS uvm_channel_reserve(uvm_channel_t *channel); +// Reserve a specific channel for a push or for a control GPFIFO entry. +NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries); // Set optimal CE for P2P transfers between manager->gpu and peer void uvm_channel_manager_set_p2p_ce(uvm_channel_manager_t *manager, uvm_gpu_t *peer, NvU32 optimal_ce); @@ -451,6 +421,17 @@ NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push); // Should be used by uvm_push_end() only. void uvm_channel_end_push(uvm_push_t *push); +// Write/send a control GPFIFO to channel. This is not supported by proxy +// channels. +// Ordering guarantees: +// Input: Control GPFIFO entries are guaranteed to be processed by ESCHED after +// all prior GPFIFO entries and pushbuffers have been fetched, but not +// necessarily completed. +// Output ordering: A caller can wait for this control entry to complete with +// uvm_channel_manager_wait(), or by waiting for any later push in the same +// channel to complete. +NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value); + const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type); const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type); diff --git a/kernel-open/nvidia-uvm/uvm_channel_test.c b/kernel-open/nvidia-uvm/uvm_channel_test.c index 2b7d78359..c1e481ce9 100644 --- a/kernel-open/nvidia-uvm/uvm_channel_test.c +++ b/kernel-open/nvidia-uvm/uvm_channel_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -60,7 +60,7 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) gpu = uvm_va_space_find_first_gpu(va_space); TEST_CHECK_RET(gpu != NULL); - status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, buffer_size, &mem); + status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, buffer_size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); host_mem = (NvU32*)uvm_rm_mem_get_cpu_va(mem); @@ -306,7 +306,6 @@ static NV_STATUS test_rc(uvm_va_space_t *va_space) return NV_OK; } - typedef struct { uvm_push_t push; @@ -481,12 +480,14 @@ static NV_STATUS stress_test_all_gpus_in_va(uvm_va_space_t *va_space, status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, MAX_COUNTER_REPEAT_COUNT * sizeof(NvU32), + 0, &stream->counter_mem); TEST_CHECK_GOTO(status == NV_OK, done); status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, TEST_SNAPSHOT_SIZE(iterations_per_stream), + 0, &stream->counter_snapshots_mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -495,6 +496,7 @@ static NV_STATUS stress_test_all_gpus_in_va(uvm_va_space_t *va_space, status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, TEST_SNAPSHOT_SIZE(iterations_per_stream), + 0, &stream->other_stream_counter_snapshots_mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -565,6 +567,7 @@ static NV_STATUS stress_test_all_gpus_in_va(uvm_va_space_t *va_space, stream->counter_snapshots_mem, i, stream->queued_counter_repeat); + // Set a random number [2, MAX_COUNTER_REPEAT_COUNT] of counters stream->queued_counter_repeat = uvm_test_rng_range_32(&rng, 2, MAX_COUNTER_REPEAT_COUNT); set_counter(&stream->push, @@ -669,61 +672,215 @@ static NV_STATUS stress_test_all_gpus_in_va(uvm_va_space_t *va_space, return status; } +NV_STATUS test_write_ctrl_gpfifo_noop(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_manager_t *manager = gpu->channel_manager; + uvm_channel_pool_t *pool; + uvm_for_each_pool(pool, manager) { + uvm_channel_t *channel; + uvm_for_each_channel_in_pool(channel, pool) { + NvU32 i; + if (uvm_channel_is_proxy(channel)) + continue; + // We submit 8x the channel's GPFIFO entries to force a few + // complete loops in the GPFIFO circular buffer. + for (i = 0; i < 8 * channel->num_gpfifo_entries; i++) { + NvU64 entry; + gpu->parent->host_hal->set_gpfifo_noop(&entry); + TEST_NV_CHECK_RET(uvm_channel_write_ctrl_gpfifo(channel, entry)); + } + } + } + } + return NV_OK; +} +NV_STATUS test_write_ctrl_gpfifo_and_pushes(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_manager_t *manager = gpu->channel_manager; + uvm_channel_pool_t *pool; + + uvm_for_each_pool(pool, manager) { + uvm_channel_t *channel; + + uvm_for_each_channel_in_pool(channel, pool) { + NvU32 i; + uvm_push_t push; + + if (uvm_channel_is_proxy(channel)) + continue; + + // We submit 8x the channel's GPFIFO entries to force a few + // complete loops in the GPFIFO circular buffer. + for (i = 0; i < 8 * channel->num_gpfifo_entries; i++) { + if (i % 2 == 0) { + NvU64 entry; + gpu->parent->host_hal->set_gpfifo_noop(&entry); + TEST_NV_CHECK_RET(uvm_channel_write_ctrl_gpfifo(channel, entry)); + } + else { + TEST_NV_CHECK_RET(uvm_push_begin_on_channel(channel, &push, "gpfifo ctrl and push test")); + uvm_push_end(&push); + } + } + + TEST_NV_CHECK_RET(uvm_push_wait(&push)); + } + } + } + return NV_OK; +} +static NvU32 get_available_gpfifo_entries(uvm_channel_t *channel) +{ + NvU32 pending_entries; + uvm_spin_lock(&channel->pool->lock); + if (channel->cpu_put >= channel->gpu_get) + pending_entries = channel->cpu_put - channel->gpu_get; + else + pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; + uvm_spin_unlock(&channel->pool->lock); + return channel->num_gpfifo_entries - pending_entries - 1; +} +NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) +{ + NV_STATUS status = NV_OK; + uvm_gpu_t *gpu; + uvm_channel_t *channel; + uvm_rm_mem_t *mem; + NvU32 *cpu_ptr; + NvU64 gpu_va; + NvU32 i; + NvU64 entry; + uvm_push_t push; + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_manager_t *manager = gpu->channel_manager; + gpu = manager->gpu; + TEST_NV_CHECK_RET(uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(*cpu_ptr), 0, &mem)); + cpu_ptr = uvm_rm_mem_get_cpu_va(mem); + gpu_va = uvm_rm_mem_get_gpu_uvm_va(mem, gpu); + *cpu_ptr = 0; + // This semaphore acquire takes 1 GPFIFO entries. + TEST_NV_CHECK_GOTO(uvm_push_begin(manager, UVM_CHANNEL_TYPE_GPU_TO_GPU, &push, "gpfifo ctrl tight test acq"), + error); + channel = push.channel; + UVM_ASSERT(!uvm_channel_is_proxy(channel)); + gpu->parent->host_hal->semaphore_acquire(&push, gpu_va, 1); + uvm_push_end(&push); + // Populate the remaining GPFIFO entries, leaving 2 slots available. + // 2 available entries + 1 semaphore acquire (above) + 1 spare entry to + // indicate a terminal condition for the GPFIFO ringbuffer, therefore we + // push num_gpfifo_entries-4. + for (i = 0; i < channel->num_gpfifo_entries - 4; i++) { + TEST_NV_CHECK_GOTO(uvm_push_begin_on_channel(channel, &push, "gpfifo ctrl tight test populate"), error); + uvm_push_end(&push); + } + TEST_CHECK_GOTO(get_available_gpfifo_entries(channel) == 2, error); + // We should have room for the control GPFIFO and the subsequent + // semaphore release. + gpu->parent->host_hal->set_gpfifo_noop(&entry); + TEST_NV_CHECK_GOTO(uvm_channel_write_ctrl_gpfifo(channel, entry), error); + // Release the semaphore. + UVM_WRITE_ONCE(*cpu_ptr, 1); + TEST_NV_CHECK_GOTO(uvm_push_wait(&push), error); + uvm_rm_mem_free(mem); + } + return NV_OK; +error: + uvm_rm_mem_free(mem); + return status; +} +// This test is inspired by the test_rc (above). +// The test recreates the GPU's channel manager forcing its pushbuffer to be +// mapped on a non-zero 1TB segment. This exercises work submission from +// pushbuffers whose VAs are greater than 1TB. +static NV_STATUS test_channel_pushbuffer_extension_base(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + NV_STATUS status = NV_OK; + uvm_assert_mutex_locked(&g_uvm_global.global_lock); + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_manager_t *manager; + uvm_channel_pool_t *pool; + if (!uvm_gpu_has_pushbuffer_segments(gpu)) + continue; + // The GPU channel manager pushbuffer is destroyed and then re-created + // after testing a non-zero pushbuffer extension base, so this test + // requires exclusive access to the GPU. + TEST_CHECK_RET(uvm_gpu_retained_count(gpu) == 1); + gpu->uvm_test_force_upper_pushbuffer_segment = 1; + uvm_channel_manager_destroy(gpu->channel_manager); + TEST_NV_CHECK_GOTO(uvm_channel_manager_create(gpu, &gpu->channel_manager), error); + gpu->uvm_test_force_upper_pushbuffer_segment = 0; + manager = gpu->channel_manager; + TEST_CHECK_GOTO(uvm_pushbuffer_get_gpu_va_base(manager->pushbuffer) >= (1ull << 40), error); + // Submit a few pushes with the recently allocated + // channel_manager->pushbuffer. + uvm_for_each_pool(pool, manager) { + uvm_channel_t *channel; + uvm_for_each_channel_in_pool(channel, pool) { + NvU32 i; + uvm_push_t push; + for (i = 0; i < channel->num_gpfifo_entries; i++) { + TEST_NV_CHECK_GOTO(uvm_push_begin_on_channel(channel, &push, "pushbuffer extension push test"), + error); + uvm_push_end(&push); + } + TEST_NV_CHECK_GOTO(uvm_push_wait(&push), error); + } + } + } + return NV_OK; +error: + gpu->uvm_test_force_upper_pushbuffer_segment = 0; - - - - - - - - - - - + return status; +} NV_STATUS uvm_test_channel_sanity(UVM_TEST_CHANNEL_SANITY_PARAMS *params, struct file *filp) { @@ -737,11 +894,23 @@ NV_STATUS uvm_test_channel_sanity(UVM_TEST_CHANNEL_SANITY_PARAMS *params, struct if (status != NV_OK) goto done; + status = test_write_ctrl_gpfifo_noop(va_space); + if (status != NV_OK) + goto done; + status = test_write_ctrl_gpfifo_and_pushes(va_space); + if (status != NV_OK) + goto done; + status = test_write_ctrl_gpfifo_tight(va_space); + if (status != NV_OK) + goto done; - - + // The following tests have side effects, they reset the GPU's + // channel_manager. + status = test_channel_pushbuffer_extension_base(va_space); + if (status != NV_OK) + goto done; g_uvm_global.disable_fatal_error_assert = true; uvm_release_asserts_set_global_error_for_tests = true; diff --git a/kernel-open/nvidia-uvm/uvm_forward_decl.h b/kernel-open/nvidia-uvm/uvm_forward_decl.h index a2a28608b..6c4a16e38 100644 --- a/kernel-open/nvidia-uvm/uvm_forward_decl.h +++ b/kernel-open/nvidia-uvm/uvm_forward_decl.h @@ -35,9 +35,6 @@ typedef struct uvm_ce_hal_struct uvm_ce_hal_t; typedef struct uvm_arch_hal_struct uvm_arch_hal_t; typedef struct uvm_fault_buffer_hal_struct uvm_fault_buffer_hal_t; typedef struct uvm_access_counter_buffer_hal_struct uvm_access_counter_buffer_hal_t; - - - typedef struct uvm_gpu_semaphore_struct uvm_gpu_semaphore_t; typedef struct uvm_gpu_tracking_semaphore_struct uvm_gpu_tracking_semaphore_t; typedef struct uvm_gpu_semaphore_pool_struct uvm_gpu_semaphore_pool_t; diff --git a/kernel-open/nvidia-uvm/uvm_global.c b/kernel-open/nvidia-uvm/uvm_global.c index 6759a54ff..42af70ef7 100644 --- a/kernel-open/nvidia-uvm/uvm_global.c +++ b/kernel-open/nvidia-uvm/uvm_global.c @@ -71,12 +71,10 @@ static void uvm_unregister_callbacks(void) } } - - - - - - +static void sev_init(const UvmPlatformInfo *platform_info) +{ + g_uvm_global.sev_enabled = platform_info->sevEnabled; +} NV_STATUS uvm_global_init(void) { @@ -127,9 +125,7 @@ NV_STATUS uvm_global_init(void) uvm_ats_init(&platform_info); g_uvm_global.num_simulated_devices = 0; - - - + sev_init(&platform_info); status = uvm_gpu_init(); if (status != NV_OK) { diff --git a/kernel-open/nvidia-uvm/uvm_global.h b/kernel-open/nvidia-uvm/uvm_global.h index ae31d8ea3..8ef734530 100644 --- a/kernel-open/nvidia-uvm/uvm_global.h +++ b/kernel-open/nvidia-uvm/uvm_global.h @@ -143,12 +143,11 @@ struct uvm_global_struct struct page *page; } unload_state; - - - - - - + // AMD Secure Encrypted Virtualization (SEV) status. True if VM has SEV + // enabled. This field is set once during global initialization + // (uvm_global_init), and can be read afterwards without acquiring any + // locks. + bool sev_enabled; }; // Initialize global uvm state diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 6ed161022..93202b7d4 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -42,9 +42,6 @@ #include "uvm_ats.h" #include "uvm_test.h" - - - #include "uvm_linux.h" #define UVM_PROC_GPUS_PEER_DIR_NAME "peers" @@ -95,12 +92,10 @@ static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) return UVM_GPU_LINK_NVLINK_2; case UVM_LINK_TYPE_NVLINK_3: return UVM_GPU_LINK_NVLINK_3; - - - - - - + case UVM_LINK_TYPE_NVLINK_4: + return UVM_GPU_LINK_NVLINK_4; + case UVM_LINK_TYPE_C2C: + return UVM_GPU_LINK_C2C; default: return UVM_GPU_LINK_INVALID; } @@ -356,11 +351,7 @@ static const char *uvm_gpu_virt_type_string(UVM_VIRT_MODE virtMode) static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) { - - - - BUILD_BUG_ON(UVM_GPU_LINK_MAX != 5); - + BUILD_BUG_ON(UVM_GPU_LINK_MAX != 7); switch (link_type) { UVM_ENUM_STRING_CASE(UVM_GPU_LINK_INVALID); @@ -368,10 +359,8 @@ static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_1); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_2); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_3); - - - - + UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_4); + UVM_ENUM_STRING_CASE(UVM_GPU_LINK_C2C); UVM_ENUM_STRING_DEFAULT(); } } @@ -519,12 +508,6 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) gpu_info_print_ce_caps(gpu, s); - - - - - - } static void @@ -1038,15 +1021,6 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, return status; } - - - - - - - - - parent_gpu->pci_dev = gpu_platform_info->pci_dev; parent_gpu->closest_cpu_numa_node = dev_to_node(&parent_gpu->pci_dev->dev); parent_gpu->dma_addressable_start = gpu_platform_info->dma_addressable_start; @@ -1208,16 +1182,6 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) return status; } - - - - - - - - - - status = init_procfs_files(gpu); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init procfs files: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1393,10 +1357,6 @@ static void remove_gpus_from_gpu(uvm_gpu_t *gpu) // Sync all trackers in PMM uvm_pmm_gpu_sync(&gpu->pmm); - - - - } // Remove all references to the given GPU from its parent, since it is being @@ -1530,13 +1490,6 @@ static void remove_gpu(uvm_gpu_t *gpu) if (free_parent) destroy_nvlink_peers(gpu); - - - - - - - // TODO: Bug 2844714: If the parent is not being freed, the following // gpu_table_lock is only needed to protect concurrent // find_first_valid_gpu() in BH from the __clear_bit here. After @@ -2212,16 +2165,12 @@ static NV_STATUS init_peer_access(uvm_gpu_t *gpu0, { NV_STATUS status; - - - + UVM_ASSERT(p2p_caps_params->p2pLink != UVM_LINK_TYPE_C2C); // check for peer-to-peer compatibility (PCI-E or NvLink). peer_caps->link_type = get_gpu_link_type(p2p_caps_params->p2pLink); if (peer_caps->link_type == UVM_GPU_LINK_INVALID - - - + || peer_caps->link_type == UVM_GPU_LINK_C2C ) return NV_ERR_NOT_SUPPORTED; diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 0048326ad..8ec172e0c 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -46,9 +46,6 @@ #include "uvm_rb_tree.h" #include "nv-kthread-q.h" - - - // Buffer length to store uvm gpu id, RM device name and gpu uuid. #define UVM_GPU_NICE_NAME_BUFFER_LENGTH (sizeof("ID 999: : ") + \ UVM_GPU_NAME_LENGTH + UVM_GPU_UUID_TEXT_BUFFER_LENGTH) @@ -508,10 +505,8 @@ typedef enum UVM_GPU_LINK_NVLINK_1, UVM_GPU_LINK_NVLINK_2, UVM_GPU_LINK_NVLINK_3, - - - - + UVM_GPU_LINK_NVLINK_4, + UVM_GPU_LINK_C2C, UVM_GPU_LINK_MAX } uvm_gpu_link_type_t; @@ -684,10 +679,6 @@ struct uvm_gpu_struct // mappings (instead of kernel), and it is used in most configurations. uvm_pmm_sysmem_mappings_t pmm_reverse_sysmem_mappings; - - - - // ECC handling // In order to trap ECC errors as soon as possible the driver has the hw // interrupt register mapped directly. If an ECC interrupt is ever noticed @@ -742,6 +733,9 @@ struct uvm_gpu_struct // Placeholder for per-GPU performance heuristics information uvm_perf_module_data_desc_t perf_modules_data[UVM_PERF_MODULE_TYPE_COUNT]; + + // Force pushbuffer's GPU VA to be >= 1TB; used only for testing purposes. + bool uvm_test_force_upper_pushbuffer_segment; }; struct uvm_parent_gpu_struct @@ -823,9 +817,6 @@ struct uvm_parent_gpu_struct uvm_fault_buffer_hal_t *fault_buffer_hal; uvm_access_counter_buffer_hal_t *access_counter_buffer_hal; - - - uvm_gpu_peer_copy_mode_t peer_copy_mode; // Virtualization mode of the GPU. @@ -1360,14 +1351,13 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); -static bool uvm_gpu_supports_eviction(uvm_gpu_t *gpu) +static bool uvm_gpu_has_pushbuffer_segments(uvm_gpu_t *gpu) { + return gpu->parent->max_host_va > (1ull << 40); +} - - - - - +static bool uvm_gpu_supports_eviction(uvm_gpu_t *gpu) +{ // Eviction is supported only if the GPU supports replayable faults return gpu->parent->replayable_faults_supported; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c index 9ae32eeb3..5c4683b48 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -134,7 +134,11 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) pool_page->pool = pool; - status = uvm_rm_mem_alloc_and_map_all(pool->gpu, UVM_RM_MEM_TYPE_SYS, UVM_SEMAPHORE_PAGE_SIZE, &pool_page->memory); + status = uvm_rm_mem_alloc_and_map_all(pool->gpu, + UVM_RM_MEM_TYPE_SYS, + UVM_SEMAPHORE_PAGE_SIZE, + 0, + &pool_page->memory); if (status != NV_OK) goto error; @@ -321,7 +325,7 @@ NV_STATUS uvm_gpu_semaphore_pool_map_gpu(uvm_gpu_semaphore_pool_t *pool, uvm_gpu uvm_mutex_lock(&pool->mutex); list_for_each_entry(page, &pool->pages, all_pages_node) { - status = uvm_rm_mem_map_gpu(page->memory, gpu); + status = uvm_rm_mem_map_gpu(page->memory, gpu, 0); if (status != NV_OK) goto done; } diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index c27fbe112..2188a949b 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -41,10 +41,8 @@ #include "clc6b5.h" #include "clc56f.h" #include "clc7b5.h" - - - - +#include "clc86f.h" +#include "clc8b5.h" #define CE_OP_COUNT (sizeof(uvm_ce_hal_t) / sizeof(void *)) #define HOST_OP_COUNT (sizeof(uvm_host_hal_t) / sizeof(void *)) @@ -52,9 +50,6 @@ #define FAULT_BUFFER_OP_COUNT (sizeof(uvm_fault_buffer_hal_t) / sizeof(void *)) #define ACCESS_COUNTER_BUFFER_OP_COUNT (sizeof(uvm_access_counter_buffer_hal_t) / sizeof(void *)) - - - // Table for copy engine functions. // Each entry is associated with a copy engine class through the 'class' field. // By setting the 'parent_class' field, a class will inherit the parent class's @@ -133,22 +128,20 @@ static uvm_hal_class_ops_t ce_table[] = .memset_validate = uvm_hal_ce_memset_validate_stub, }, }, - - - - - - - - - - - - - - - - + { + .id = HOPPER_DMA_COPY_A, + .parent_id = AMPERE_DMA_COPY_B, + .u.ce_ops = { + .semaphore_release = uvm_hal_hopper_ce_semaphore_release, + .semaphore_timestamp = uvm_hal_hopper_ce_semaphore_timestamp, + .semaphore_reduction_inc = uvm_hal_hopper_ce_semaphore_reduction_inc, + .offset_out = uvm_hal_hopper_ce_offset_out, + .offset_in_out = uvm_hal_hopper_ce_offset_in_out, + .memset_1 = uvm_hal_hopper_ce_memset_1, + .memset_4 = uvm_hal_hopper_ce_memset_4, + .memset_8 = uvm_hal_hopper_ce_memset_8, + }, + }, }; // Table for GPFIFO functions. Same idea as the copy engine table. @@ -171,6 +164,8 @@ static uvm_hal_class_ops_t host_table[] = .semaphore_release = uvm_hal_maxwell_host_semaphore_release, .semaphore_timestamp = uvm_hal_maxwell_host_semaphore_timestamp, .set_gpfifo_entry = uvm_hal_maxwell_host_set_gpfifo_entry, + .set_gpfifo_noop = uvm_hal_maxwell_host_set_gpfifo_noop, + .set_gpfifo_pushbuffer_segment_base = uvm_hal_maxwell_host_set_gpfifo_pushbuffer_segment_base_unsupported, .write_gpu_put = uvm_hal_maxwell_host_write_gpu_put, .tlb_invalidate_all = uvm_hal_maxwell_host_tlb_invalidate_all_a16f, .tlb_invalidate_va = uvm_hal_maxwell_host_tlb_invalidate_va, @@ -249,23 +244,23 @@ static uvm_hal_class_ops_t host_table[] = .tlb_invalidate_test = uvm_hal_ampere_host_tlb_invalidate_test, } }, - - - - - - - - - - - - - - - - - + { + .id = HOPPER_CHANNEL_GPFIFO_A, + .parent_id = AMPERE_CHANNEL_GPFIFO_A, + .u.host_ops = { + .method_validate = uvm_hal_method_validate_stub, + .sw_method_validate = uvm_hal_method_validate_stub, + .semaphore_acquire = uvm_hal_hopper_host_semaphore_acquire, + .semaphore_release = uvm_hal_hopper_host_semaphore_release, + .semaphore_timestamp = uvm_hal_hopper_host_semaphore_timestamp, + .tlb_invalidate_all = uvm_hal_hopper_host_tlb_invalidate_all, + .tlb_invalidate_va = uvm_hal_hopper_host_tlb_invalidate_va, + .tlb_invalidate_test = uvm_hal_hopper_host_tlb_invalidate_test, + .cancel_faults_va = uvm_hal_hopper_cancel_faults_va, + .set_gpfifo_entry = uvm_hal_hopper_host_set_gpfifo_entry, + .set_gpfifo_pushbuffer_segment_base = uvm_hal_hopper_host_set_gpfifo_pushbuffer_segment_base, + } + }, }; static uvm_hal_class_ops_t arch_table[] = @@ -326,43 +321,23 @@ static uvm_hal_class_ops_t arch_table[] = .mmu_client_id_to_utlb_id = uvm_hal_ampere_mmu_client_id_to_utlb_id, }, }, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .u.arch_ops = { + .init_properties = uvm_hal_ada_arch_init_properties, + }, + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .u.arch_ops = { + .init_properties = uvm_hal_hopper_arch_init_properties, + .mmu_mode_hal = uvm_hal_mmu_mode_hopper, + .mmu_engine_id_to_type = uvm_hal_hopper_mmu_engine_id_to_type, + .mmu_client_id_to_utlb_id = uvm_hal_hopper_mmu_client_id_to_utlb_id, + }, + }, }; static uvm_hal_class_ops_t fault_buffer_table[] = @@ -430,33 +405,18 @@ static uvm_hal_class_ops_t fault_buffer_table[] = .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, .u.fault_buffer_ops = {} }, - - - - - - - - - - - - - - - - - - - - - - - - - - - + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .u.fault_buffer_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .u.fault_buffer_ops = { + .get_ve_id = uvm_hal_hopper_fault_buffer_get_ve_id, + } + }, }; static uvm_hal_class_ops_t access_counter_buffer_table[] = @@ -509,105 +469,18 @@ static uvm_hal_class_ops_t access_counter_buffer_table[] = .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, .u.access_counter_buffer_ops = {} }, - - - - - - - - - - - - - - - - - - - - - - - - - + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .u.access_counter_buffer_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .u.access_counter_buffer_ops = {} + }, }; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - static inline uvm_hal_class_ops_t *ops_find_by_id(uvm_hal_class_ops_t *table, NvU32 row_count, NvU32 id) { NvLength i; @@ -711,17 +584,6 @@ NV_STATUS uvm_hal_init_table(void) return status; } - - - - - - - - - - - return NV_OK; } @@ -772,16 +634,6 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counter_buffer_hal = &class_ops->u.access_counter_buffer_ops; - - - - - - - - - - return NV_OK; } diff --git a/kernel-open/nvidia-uvm/uvm_hal.h b/kernel-open/nvidia-uvm/uvm_hal.h index 2ddfce9df..4f09734ff 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.h +++ b/kernel-open/nvidia-uvm/uvm_hal.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -41,10 +41,6 @@ void uvm_hal_maxwell_ce_init(uvm_push_t *push); void uvm_hal_maxwell_host_init_noop(uvm_push_t *push); void uvm_hal_pascal_host_init(uvm_push_t *push); - - - - // Host method validation typedef bool (*uvm_hal_host_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data); @@ -118,12 +114,10 @@ void uvm_hal_ampere_host_tlb_invalidate_all(uvm_push_t *push, uvm_gpu_phys_address_t pdb, NvU32 depth, uvm_membar_t membar); - - - - - - +void uvm_hal_hopper_host_tlb_invalidate_all(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + uvm_membar_t membar); // Issue a TLB invalidate applying to the specified VA range in a PDB. // @@ -183,15 +177,13 @@ void uvm_hal_ampere_host_tlb_invalidate_va(uvm_push_t *push, NvU64 size, NvU32 page_size, uvm_membar_t membar); - - - - - - - - - +void uvm_hal_hopper_host_tlb_invalidate_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + NvU64 base, + NvU64 size, + NvU32 page_size, + uvm_membar_t membar); typedef void (*uvm_hal_host_tlb_invalidate_test_t)(uvm_push_t *push, uvm_gpu_phys_address_t pdb, @@ -205,11 +197,9 @@ void uvm_hal_pascal_host_tlb_invalidate_test(uvm_push_t *push, void uvm_hal_ampere_host_tlb_invalidate_test(uvm_push_t *push, uvm_gpu_phys_address_t pdb, UVM_TEST_INVALIDATE_TLB_PARAMS *params); - - - - - +void uvm_hal_hopper_host_tlb_invalidate_test(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + UVM_TEST_INVALIDATE_TLB_PARAMS *params); // By default all semaphore release operations include a membar sys before the // operation. This can be affected by using UVM_PUSH_FLAG_NEXT_* flags with @@ -217,18 +207,10 @@ void uvm_hal_ampere_host_tlb_invalidate_test(uvm_push_t *push, typedef void (*uvm_hal_semaphore_release_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); - - - void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); - - - - - - - +void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); // Release a semaphore including a timestamp at the specific GPU VA. // @@ -238,31 +220,28 @@ void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 typedef void (*uvm_hal_semaphore_timestamp_t)(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); - - - +void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_volta_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); - - - - - - - - +void uvm_hal_hopper_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); typedef void (*uvm_hal_semaphore_acquire_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); - - - +void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); typedef void (*uvm_hal_host_set_gpfifo_entry_t)(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); + +typedef void (*uvm_hal_host_set_gpfifo_noop_t)(NvU64 *fifo_entry); +void uvm_hal_maxwell_host_set_gpfifo_noop(NvU64 *fifo_entry); + +typedef void (*uvm_hal_host_set_gpfifo_pushbuffer_segment_base_t)(NvU64 *fifo_entry, NvU64 pushbuffer_va); +void uvm_hal_maxwell_host_set_gpfifo_pushbuffer_segment_base_unsupported(NvU64 *fifo_entry, NvU64 pushbuffer_va); +void uvm_hal_hopper_host_set_gpfifo_pushbuffer_segment_base(NvU64 *fifo_entry, NvU64 pushbuffer_va); typedef void (*uvm_hal_host_write_gpu_put_t)(uvm_channel_t *channel, NvU32 gpu_put); void uvm_hal_maxwell_host_write_gpu_put(uvm_channel_t *channel, NvU32 gpu_put); @@ -277,16 +256,12 @@ NvU64 uvm_hal_maxwell_get_time(uvm_gpu_t *gpu); typedef void (*uvm_hal_ce_offset_out_t)(uvm_push_t *push, NvU64 offset); void uvm_hal_maxwell_ce_offset_out(uvm_push_t *push, NvU64 offset); void uvm_hal_pascal_ce_offset_out(uvm_push_t *push, NvU64 offset); - - - +void uvm_hal_hopper_ce_offset_out(uvm_push_t *push, NvU64 offset); typedef void (*uvm_hal_ce_offset_in_out_t)(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out); void uvm_hal_maxwell_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out); void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out); - - - +void uvm_hal_hopper_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out); typedef NvU32 (*uvm_hal_ce_phys_mode_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); NvU32 uvm_hal_maxwell_ce_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); @@ -354,11 +329,9 @@ void uvm_hal_maxwell_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 void uvm_hal_maxwell_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, size_t size); - - - - - +void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size); +void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); +void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); // Increments the semaphore by 1, or resets to 0 if the incremented value would // exceed the payload. @@ -369,9 +342,7 @@ void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, typedef void (*uvm_hal_semaphore_reduction_inc_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); - - - +void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); // Initialize GPU architecture dependent properties typedef void (*uvm_hal_arch_init_properties_t)(uvm_parent_gpu_t *parent_gpu); @@ -380,12 +351,8 @@ void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu); void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu); void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu); - - - - - - +void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu); +void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu); // Retrieve the page-tree HAL for a given big page size typedef uvm_mmu_mode_hal_t *(*uvm_hal_lookup_mode_hal_t)(NvU32 big_page_size); @@ -396,9 +363,7 @@ uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_pascal(NvU32 big_page_size); uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_volta(NvU32 big_page_size); uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_turing(NvU32 big_page_size); uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_ampere(NvU32 big_page_size); - - - +uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_hopper(NvU32 big_page_size); void uvm_hal_maxwell_mmu_enable_prefetch_faults_unsupported(uvm_parent_gpu_t *parent_gpu); void uvm_hal_maxwell_mmu_disable_prefetch_faults_unsupported(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu); @@ -412,18 +377,14 @@ uvm_mmu_engine_type_t uvm_hal_maxwell_mmu_engine_id_to_type_unsupported(NvU16 mm uvm_mmu_engine_type_t uvm_hal_volta_mmu_engine_id_to_type(NvU16 mmu_engine_id); uvm_mmu_engine_type_t uvm_hal_turing_mmu_engine_id_to_type(NvU16 mmu_engine_id); uvm_mmu_engine_type_t uvm_hal_ampere_mmu_engine_id_to_type(NvU16 mmu_engine_id); - - - +uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id); typedef NvU16 (*uvm_hal_mmu_client_id_to_utlb_id_t)(NvU16 client_id); NvU16 uvm_hal_maxwell_mmu_client_id_to_utlb_id_unsupported(NvU16 client_id); NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id); NvU16 uvm_hal_volta_mmu_client_id_to_utlb_id(NvU16 client_id); NvU16 uvm_hal_ampere_mmu_client_id_to_utlb_id(NvU16 client_id); - - - +NvU16 uvm_hal_hopper_mmu_client_id_to_utlb_id(NvU16 client_id); // Replayable faults typedef void (*uvm_hal_enable_replayable_faults_t)(uvm_parent_gpu_t *parent_gpu); @@ -477,9 +438,7 @@ void uvm_hal_volta_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, uvm_fault_buffer_entry_t *buffer_entry); void uvm_hal_turing_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get); - - - +NvU8 uvm_hal_hopper_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); bool uvm_hal_maxwell_fault_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index); void uvm_hal_maxwell_fault_buffer_entry_clear_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index); @@ -529,12 +488,10 @@ void uvm_hal_volta_cancel_faults_va(uvm_push_t *push, const uvm_fault_buffer_entry_t *fault_entry, uvm_fault_cancel_va_mode_t cancel_va_mode); - - - - - - +void uvm_hal_hopper_cancel_faults_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + const uvm_fault_buffer_entry_t *fault_entry, + uvm_fault_cancel_va_mode_t cancel_va_mode); typedef void (*uvm_hal_host_clear_faulted_channel_method_t)(uvm_push_t *push, uvm_user_channel_t *user_channel, @@ -619,39 +576,6 @@ void uvm_hal_volta_access_counter_clear_targeted(uvm_push_t *push, void uvm_hal_turing_disable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_access_counter_notifications(uvm_parent_gpu_t *parent_gpu, NvU32 get); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - struct uvm_host_hal_struct { uvm_hal_init_t init; @@ -666,6 +590,8 @@ struct uvm_host_hal_struct uvm_hal_semaphore_acquire_t semaphore_acquire; uvm_hal_semaphore_timestamp_t semaphore_timestamp; uvm_hal_host_set_gpfifo_entry_t set_gpfifo_entry; + uvm_hal_host_set_gpfifo_noop_t set_gpfifo_noop; + uvm_hal_host_set_gpfifo_pushbuffer_segment_base_t set_gpfifo_pushbuffer_segment_base; uvm_hal_host_write_gpu_put_t write_gpu_put; uvm_hal_host_tlb_invalidate_all_t tlb_invalidate_all; uvm_hal_host_tlb_invalidate_va_t tlb_invalidate_va; @@ -742,17 +668,6 @@ struct uvm_access_counter_buffer_hal_struct uvm_hal_access_counter_buffer_entry_size_t entry_size; }; - - - - - - - - - - - typedef struct { // id is either a hardware class or GPU architecture @@ -775,10 +690,6 @@ typedef struct // access_counter_buffer_ops: id is an architecture uvm_access_counter_buffer_hal_t access_counter_buffer_ops; - - - - } u; } uvm_hal_class_ops_t; diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 8c1937aa9..00e8633a0 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -31,7 +31,6 @@ MODULE_PARM_DESC(uvm_disable_hmm, "HMM is not supported in the driver, or if ATS settings " "conflict with HMM."); - #if UVM_IS_CONFIG_HMM() #include @@ -785,6 +784,60 @@ NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, return NV_OK; } -#endif // UVM_IS_CONFIG_HMM() +static NV_STATUS hmm_clear_thrashing_policy(uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context) +{ + uvm_va_policy_t *policy; + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + NV_STATUS status = NV_OK; + + uvm_mutex_lock(&va_block->lock); + + uvm_for_each_va_policy_in(policy, va_block, va_block->start, va_block->end, node, region) { + block_context->policy = policy; + + // Unmap may split PTEs and require a retry. Needs to be called + // before the pinned pages information is destroyed. + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, + NULL, + unmap_remote_pinned_pages_from_all_processors(va_block, + block_context, + region)); + + uvm_perf_thrashing_info_destroy(va_block); + if (status != NV_OK) + break; + } + + uvm_mutex_unlock(&va_block->lock); + + return status; +} + +NV_STATUS uvm_hmm_clear_thrashing_policy(uvm_va_space_t *va_space) +{ + uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, NULL); + uvm_range_tree_node_t *node, *next; + uvm_va_block_t *va_block; + NV_STATUS status = NV_OK; + + if (!uvm_hmm_is_enabled(va_space)) + return NV_OK; + + uvm_assert_rwsem_locked_write(&va_space->lock); + + uvm_range_tree_for_each_safe(node, next, &va_space->hmm.blocks) { + va_block = hmm_va_block_from_node(node); + + status = hmm_clear_thrashing_policy(va_block, block_context); + if (status != NV_OK) + break; + } + + return status; +} + +#endif // UVM_IS_CONFIG_HMM() diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index 88c63e975..b31de4488 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -185,6 +185,10 @@ typedef struct uvm_page_index_t page_index, uvm_page_index_t *outerp); + // Clear thrashing policy information from all HMM va_blocks. + // Locking: va_space lock must be held in write mode. + NV_STATUS uvm_hmm_clear_thrashing_policy(uvm_va_space_t *va_space); + #else // UVM_IS_CONFIG_HMM() static bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) @@ -282,6 +286,11 @@ typedef struct return NV_OK; } + static NV_STATUS uvm_hmm_clear_thrashing_policy(uvm_va_space_t *va_space) + { + return NV_OK; + } + #endif // UVM_IS_CONFIG_HMM() #endif // _UVM_HMM_H_ diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c new file mode 100644 index 000000000..a08d1522d --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -0,0 +1,96 @@ +/******************************************************************************* + Copyright (c) 2020-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_global.h" +#include "uvm_hal.h" +#include "uvm_gpu.h" +#include "uvm_mem.h" +#include "uvm_hopper_fault_buffer.h" + +void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) +{ + parent_gpu->tlb_batch.va_invalidate_supported = true; + + parent_gpu->tlb_batch.va_range_invalidate_supported = true; + + // TODO: Bug 1767241: Run benchmarks to figure out a good number + parent_gpu->tlb_batch.max_ranges = 8; + + parent_gpu->utlb_per_gpc_count = uvm_hopper_get_utlbs_per_gpc(parent_gpu); + + parent_gpu->fault_buffer_info.replayable.utlb_count = parent_gpu->rm_info.maxGpcCount * + parent_gpu->utlb_per_gpc_count; + { + uvm_fault_buffer_entry_t *dummy; + UVM_ASSERT(parent_gpu->fault_buffer_info.replayable.utlb_count <= (1 << + (sizeof(dummy->fault_source.utlb_id) * 8))); + } + + // A single top level PDE on Hopper covers 64 PB and that's the minimum + // size that can be used. + parent_gpu->rm_va_base = 0; + parent_gpu->rm_va_size = 64ull * 1024 * 1024 * 1024 * 1024 * 1024; + + parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + + parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; + + // All GR context buffers may be mapped to 57b wide VAs. All "compute" units + // accessing GR context buffers support the 57-bit VA range. + parent_gpu->max_channel_va = 1ull << 57; + + parent_gpu->max_host_va = 1ull << 57; + + // Hopper can map sysmem with any page size + parent_gpu->can_map_sysmem_with_large_pages = true; + + // Prefetch instructions will generate faults + parent_gpu->prefetch_fault_supported = true; + + // Hopper can place GPFIFO in vidmem + parent_gpu->gpfifo_in_vidmem_supported = true; + + parent_gpu->replayable_faults_supported = true; + + parent_gpu->non_replayable_faults_supported = true; + + parent_gpu->access_counters_supported = true; + + parent_gpu->fault_cancel_va_supported = true; + + parent_gpu->scoped_atomics_supported = true; + + parent_gpu->has_clear_faulted_channel_sw_method = true; + + parent_gpu->has_clear_faulted_channel_method = false; + + parent_gpu->smc.supported = true; + + parent_gpu->sparse_mappings_supported = true; + + parent_gpu->map_remap_larger_page_promotion = false; + + parent_gpu->plc_supported = true; +} + diff --git a/kernel-open/nvidia-uvm/uvm_hopper_ce.c b/kernel-open/nvidia-uvm/uvm_hopper_ce.c new file mode 100644 index 000000000..3d6c34ad1 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_ce.c @@ -0,0 +1,339 @@ +/******************************************************************************* + Copyright (c) 2020 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_push.h" +#include "clc8b5.h" + +static void hopper_membar_after_transfer(uvm_push_t *push) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + return; + + // TODO: [UVM-Volta] Remove Host WFI + Membar WAR for CE flush-only bug + // http://nvbugs/1734761 + gpu->parent->host_hal->wait_for_idle(push); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + gpu->parent->host_hal->membar_gpu(push); + else + gpu->parent->host_hal->membar_sys(push); +} + +static NvU32 ce_aperture(uvm_aperture_t aperture) +{ + BUILD_BUG_ON(HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) != + HWCONST(C8B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); + BUILD_BUG_ON(HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM) != + HWCONST(C8B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); + BUILD_BUG_ON(HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, PEERMEM) != + HWCONST(C8B5, SET_DST_PHYS_MODE, TARGET, PEERMEM)); + + if (aperture == UVM_APERTURE_SYS) { + return HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM); + } + else if (aperture == UVM_APERTURE_VID) { + return HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB); + } + else { + return HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, PEERMEM) | + HWVALUE(C8B5, SET_SRC_PHYS_MODE, FLA, 0) | + HWVALUE(C8B5, SET_SRC_PHYS_MODE, PEER_ID, UVM_APERTURE_PEER_ID(aperture)); + } +} + +void uvm_hal_hopper_ce_offset_out(uvm_push_t *push, NvU64 offset_out) +{ + NV_PUSH_2U(C8B5, OFFSET_OUT_UPPER, HWVALUE(C8B5, OFFSET_OUT_UPPER, UPPER, NvOffset_HI32(offset_out)), + OFFSET_OUT_LOWER, HWVALUE(C8B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); +} + +void uvm_hal_hopper_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out) +{ + NV_PUSH_4U(C8B5, OFFSET_IN_UPPER, HWVALUE(C8B5, OFFSET_IN_UPPER, UPPER, NvOffset_HI32(offset_in)), + OFFSET_IN_LOWER, HWVALUE(C8B5, OFFSET_IN_LOWER, VALUE, NvOffset_LO32(offset_in)), + OFFSET_OUT_UPPER, HWVALUE(C8B5, OFFSET_OUT_UPPER, UPPER, NvOffset_HI32(offset_out)), + OFFSET_OUT_LOWER, HWVALUE(C8B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); +} + +// Perform an appropriate membar before a semaphore operation. Returns whether +// the semaphore operation should include a flush. +static bool hopper_membar_before_semaphore(uvm_push_t *push) +{ + uvm_gpu_t *gpu; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { + // No MEMBAR requested, don't use a flush. + return false; + } + + if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { + // By default do a MEMBAR SYS and for that we can just use flush on the + // semaphore operation. + return true; + } + + // TODO: Bug 1734761: Remove the HOST WFI+membar WAR, i.e, perform the CE + // flush when MEMBAR GPU is requested. + gpu = uvm_push_get_gpu(push); + gpu->parent->host_hal->wait_for_idle(push); + gpu->parent->host_hal->membar_gpu(push); + + return false; +} + +void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 flush_value; + NvU32 launch_dma_plc_mode; + bool use_flush; + + use_flush = hopper_membar_before_semaphore(push); + + if (use_flush) + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + else + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 flush_value; + NvU32 launch_dma_plc_mode; + bool use_flush; + + use_flush = hopper_membar_before_semaphore(push); + + if (use_flush) + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + else + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) | + launch_dma_plc_mode); +} + +void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) +{ + uvm_gpu_t *gpu; + NvU32 flush_value; + NvU32 launch_dma_plc_mode; + bool use_flush; + + use_flush = hopper_membar_before_semaphore(push); + + if (use_flush) + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + else + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, 0xdeadbeef); + + gpu = uvm_push_get_gpu(push); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +static NvU32 hopper_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) +{ + if (dst.is_virtual) + return HWCONST(C8B5, LAUNCH_DMA, DST_TYPE, VIRTUAL); + + NV_PUSH_1U(C8B5, SET_DST_PHYS_MODE, ce_aperture(dst.aperture)); + return HWCONST(C8B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); +} + +static bool hopper_scrub_enable(uvm_gpu_address_t dst, size_t size) +{ + return !dst.is_virtual && + dst.aperture == UVM_APERTURE_VID && + IS_ALIGNED(dst.address, UVM_PAGE_SIZE_4K) && + IS_ALIGNED(size, UVM_PAGE_SIZE_4K); +} + +static void hopper_memset_common(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t memset_element_size) +{ + // If >4GB memsets ever become an important use case, this function should + // use multi-line transfers so we don't have to iterate (bug 1766588). + static const size_t max_single_memset = 0xFFFFFFFF; + + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 pipelined_value; + NvU32 launch_dma_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 launch_dma_remap_enable; + NvU32 launch_dma_scrub_enable; + + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_validate(push, dst, memset_element_size), + "Memset validation failed in channel %s, GPU %s", + push->channel->name, + uvm_gpu_name(gpu)); + + launch_dma_dst_type = hopper_memset_push_phys_mode(push, dst); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + if (memset_element_size == 8 && hopper_scrub_enable(dst, num_elements * memset_element_size)) { + launch_dma_remap_enable = HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, FALSE); + launch_dma_scrub_enable = HWCONST(C8B5, LAUNCH_DMA, MEMORY_SCRUB_ENABLE, TRUE); + + NV_PUSH_1U(C8B5, SET_MEMORY_SCRUB_PARAMETERS, + HWCONST(C8B5, SET_MEMORY_SCRUB_PARAMETERS, DISCARDABLE, FALSE)); + + // Scrub requires disabling remap, and with remap disabled the element + // size is 1. + num_elements *= memset_element_size; + memset_element_size = 1; + } + else { + launch_dma_remap_enable = HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, TRUE); + launch_dma_scrub_enable = HWCONST(C8B5, LAUNCH_DMA, MEMORY_SCRUB_ENABLE, FALSE); + } + + do { + NvU32 memset_this_time = (NvU32)min(num_elements, max_single_memset); + + gpu->parent->ce_hal->offset_out(push, dst.address); + + NV_PUSH_1U(C8B5, LINE_LENGTH_IN, memset_this_time); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, + HWCONST(C8B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE) | + launch_dma_remap_enable | + launch_dma_scrub_enable | + launch_dma_dst_type | + launch_dma_plc_mode | + pipelined_value); + + dst.address += memset_this_time * memset_element_size; + num_elements -= memset_this_time; + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + } while (num_elements > 0); + + hopper_membar_after_transfer(push); +} + +void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size) +{ + UVM_ASSERT_MSG(size % 8 == 0, "size: %zd\n", size); + + size /= 8; + + NV_PUSH_3U(C8B5, SET_REMAP_CONST_A, (NvU32)value, + SET_REMAP_CONST_B, (NvU32)(value >> 32), + SET_REMAP_COMPONENTS, + HWCONST(C8B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO)); + + hopper_memset_common(push, dst, size, 8); +} + +void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size) +{ + if (hopper_scrub_enable(dst, size)) { + NvU64 value64 = value; + + value64 |= value64 << 8; + value64 |= value64 << 16; + value64 |= value64 << 32; + + uvm_hal_hopper_ce_memset_8(push, dst, value64, size); + return; + } + + NV_PUSH_2U(C8B5, SET_REMAP_CONST_B, (NvU32)value, + SET_REMAP_COMPONENTS, + HWCONST(C8B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, ONE) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + hopper_memset_common(push, dst, size, 1); +} + +void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size) +{ + UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size); + + if (hopper_scrub_enable(dst, size)) { + NvU64 value64 = value; + + value64 |= value64 << 32; + + uvm_hal_hopper_ce_memset_8(push, dst, value64, size); + return; + } + + size /= 4; + + NV_PUSH_2U(C8B5, SET_REMAP_CONST_B, value, + SET_REMAP_COMPONENTS, + HWCONST(C8B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C8B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + hopper_memset_common(push, dst, size, 4); +} diff --git a/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.c new file mode 100644 index 000000000..64262b9ba --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.c @@ -0,0 +1,42 @@ +/******************************************************************************* + Copyright (c) 2020 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal_types.h" +#include "hwref/hopper/gh100/dev_fault.h" + +// TODO: Bug 1835884: [uvm] Query the maximum number of subcontexts from RM +// ... to validate the ve_id +#define MAX_SUBCONTEXTS 64 +NvU8 uvm_hal_hopper_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type) +{ + // Only graphics engines can generate MMU faults from different subcontexts + if (mmu_engine_type == UVM_MMU_ENGINE_TYPE_GRAPHICS) { + NvU16 ve_id = mmu_engine_id - NV_PFAULT_MMU_ENG_ID_GRAPHICS; + UVM_ASSERT(ve_id < MAX_SUBCONTEXTS); + + return (NvU8)ve_id; + } + else { + return 0; + } +} diff --git a/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.h b/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.h new file mode 100644 index 000000000..55e83be45 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_fault_buffer.h @@ -0,0 +1,90 @@ +/******************************************************************************* + Copyright (c) 2020 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_HAL_HOPPER_FAULT_BUFFER_H__ +#define __UVM_HAL_HOPPER_FAULT_BUFFER_H__ + +#include "nvtypes.h" +#include "uvm_common.h" +#include "uvm_gpu.h" + +// There are up to 9 TPCs per GPC in Hopper, and there are 2 LTP uTLBs per TPC. +// Besides, there is one active RGG uTLB per GPC. Each TPC has a number of +// clients that can make requests to its uTLBs: 1xTPCCS, 1xPE, 2xT1. Requests +// from these units are routed as follows to the 2 LTP uTLBs: +// +// -------- --------- +// | T1_0 | -----------------> | uTLB0 | +// -------- --------- +// +// -------- --------- +// | T1_1 | -----------------> | uTLB1 | +// -------- --------> --------- +// | ^ +// ------- | | +// | PE | ----------- | +// ------- | +// | +// --------- | +// | TPCCS | ----------------------- +// --------- +// +// +// The client ids are local to their GPC and the id mapping is linear across +// TPCs: TPC_n has TPCCS_n, PE_n, T1_p, and T1_q, where p=2*n and q=p+1. +// +// NV_PFAULT_CLIENT_GPC_LTP_UTLB_n and NV_PFAULT_CLIENT_GPC_RGG_UTLB enums can +// be ignored. These will never be reported in a fault message, and should +// never be used in an invalidate. Therefore, we define our own values. +typedef enum { + UVM_HOPPER_GPC_UTLB_ID_RGG = 0, + UVM_HOPPER_GPC_UTLB_ID_LTP0 = 1, + UVM_HOPPER_GPC_UTLB_ID_LTP1 = 2, + UVM_HOPPER_GPC_UTLB_ID_LTP2 = 3, + UVM_HOPPER_GPC_UTLB_ID_LTP3 = 4, + UVM_HOPPER_GPC_UTLB_ID_LTP4 = 5, + UVM_HOPPER_GPC_UTLB_ID_LTP5 = 6, + UVM_HOPPER_GPC_UTLB_ID_LTP6 = 7, + UVM_HOPPER_GPC_UTLB_ID_LTP7 = 8, + UVM_HOPPER_GPC_UTLB_ID_LTP8 = 9, + UVM_HOPPER_GPC_UTLB_ID_LTP9 = 10, + UVM_HOPPER_GPC_UTLB_ID_LTP10 = 11, + UVM_HOPPER_GPC_UTLB_ID_LTP11 = 12, + UVM_HOPPER_GPC_UTLB_ID_LTP12 = 13, + UVM_HOPPER_GPC_UTLB_ID_LTP13 = 14, + UVM_HOPPER_GPC_UTLB_ID_LTP14 = 15, + UVM_HOPPER_GPC_UTLB_ID_LTP15 = 16, + UVM_HOPPER_GPC_UTLB_ID_LTP16 = 17, + UVM_HOPPER_GPC_UTLB_ID_LTP17 = 18, + + UVM_HOPPER_GPC_UTLB_COUNT, +} uvm_hopper_gpc_utlb_id_t; + +static NvU32 uvm_hopper_get_utlbs_per_gpc(uvm_parent_gpu_t *parent_gpu) +{ + NvU32 utlbs = parent_gpu->rm_info.maxTpcPerGpcCount * 2 + 1; + UVM_ASSERT(utlbs <= UVM_HOPPER_GPC_UTLB_COUNT); + return utlbs; +} + +#endif diff --git a/kernel-open/nvidia-uvm/uvm_hopper_host.c b/kernel-open/nvidia-uvm/uvm_hopper_host.c new file mode 100644 index 000000000..d24a23651 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_host.c @@ -0,0 +1,412 @@ +/******************************************************************************* + Copyright (c) 2020-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_push.h" +#include "uvm_push_macros.h" +#include "clc86f.h" + +// TODO: Bug 3210931: Rename HOST references and files to ESCHED. + +void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + NvU32 sem_lo; + UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET))); + sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET); + + uvm_hal_wfi_membar(push, uvm_push_get_and_reset_membar_flag(push)); + + NV_PUSH_5U(C86F, SEM_ADDR_LO, HWVALUE(C86F, SEM_ADDR_LO, OFFSET, sem_lo), + SEM_ADDR_HI, HWVALUE(C86F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)), + SEM_PAYLOAD_LO, payload, + SEM_PAYLOAD_HI, 0, + SEM_EXECUTE, HWCONST(C86F, SEM_EXECUTE, OPERATION, RELEASE) | + HWCONST(C86F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | + HWCONST(C86F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS) | + HWCONST(C86F, SEM_EXECUTE, RELEASE_WFI, DIS)); +} + +void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + NvU32 sem_lo; + UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET))); + sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET); + NV_PUSH_5U(C86F, SEM_ADDR_LO, HWVALUE(C86F, SEM_ADDR_LO, OFFSET, sem_lo), + SEM_ADDR_HI, HWVALUE(C86F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)), + SEM_PAYLOAD_LO, payload, + SEM_PAYLOAD_HI, 0, + SEM_EXECUTE, HWCONST(C86F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) | + HWCONST(C86F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | + HWCONST(C86F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN)); +} + +void uvm_hal_hopper_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) +{ + NvU32 sem_lo; + UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET))); + sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET); + + uvm_hal_wfi_membar(push, uvm_push_get_and_reset_membar_flag(push)); + + NV_PUSH_5U(C86F, SEM_ADDR_LO, HWVALUE(C86F, SEM_ADDR_LO, OFFSET, sem_lo), + SEM_ADDR_HI, HWVALUE(C86F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)), + SEM_PAYLOAD_LO, 0xdeadbeef, + SEM_PAYLOAD_HI, 0, + SEM_EXECUTE, HWCONST(C86F, SEM_EXECUTE, OPERATION, RELEASE) | + HWCONST(C86F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | + HWCONST(C86F, SEM_EXECUTE, RELEASE_TIMESTAMP, EN) | + HWCONST(C86F, SEM_EXECUTE, RELEASE_WFI, DIS)); +} + +static NvU32 fault_cancel_va_mode_to_cancel_access_type(uvm_fault_cancel_va_mode_t cancel_va_mode) +{ + // There are only two logical cases from the perspective of UVM. Accesses to + // an invalid address, which will cancel all accesses on the page, and + // accesses with an invalid type on a read-only page, which will cancel all + // write/atomic accesses on the page. + switch (cancel_va_mode) + { + case UVM_FAULT_CANCEL_VA_MODE_ALL: + return HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACCESS_TYPE, VIRT_ALL); + case UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC: + return HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACCESS_TYPE, VIRT_WRITE_AND_ATOMIC); + default: + UVM_ASSERT_MSG(false, "Invalid cancel_va_mode %d\n", cancel_va_mode); + } + + return 0; +} + +void uvm_hal_hopper_cancel_faults_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + const uvm_fault_buffer_entry_t *fault_entry, + uvm_fault_cancel_va_mode_t cancel_va_mode) +{ + NvU32 aperture_value; + NvU32 pdb_lo; + NvU32 pdb_hi; + NvU32 addr_lo; + NvU32 addr_hi; + NvU32 access_type_value; + NvU64 addr = fault_entry->fault_address; + NvU32 mmu_engine_id = fault_entry->fault_source.mmu_engine_id; + + UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture); + + if (pdb.aperture == UVM_APERTURE_VID) + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM); + else + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT); + + UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx not aligned to 4KB\n", pdb.address); + pdb.address >>= 12; + + pdb_lo = pdb.address & HWMASK(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + pdb_hi = pdb.address >> HWSIZE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + + access_type_value = fault_cancel_va_mode_to_cancel_access_type(cancel_va_mode); + + UVM_ASSERT_MSG(IS_ALIGNED(addr, 1 << 12), "addr 0x%llx not aligned to 4KB\n", addr); + addr >>= 12; + + addr_lo = addr & HWMASK(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + addr_hi = addr >> HWSIZE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + + NV_PUSH_4U(C86F, MEM_OP_A, HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) | + HWVALUE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, addr_lo) | + HWVALUE(C86F, MEM_OP_A, TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID, mmu_engine_id), + MEM_OP_B, HWVALUE(C86F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, addr_hi), + MEM_OP_C, HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_REPLAY, CANCEL_VA_GLOBAL) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, NONE) | + access_type_value | + aperture_value, + MEM_OP_D, HWCONST(C86F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) | + HWVALUE(C86F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); +} + +void uvm_hal_hopper_host_tlb_invalidate_all(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + uvm_membar_t membar) +{ + NvU32 aperture_value; + NvU32 page_table_level; + NvU32 pdb_lo; + NvU32 pdb_hi; + NvU32 ack_value = 0; + + UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture); + + if (pdb.aperture == UVM_APERTURE_VID) + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM); + else + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT); + + UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address); + pdb.address >>= 12; + + pdb_lo = pdb.address & HWMASK(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + pdb_hi = pdb.address >> HWSIZE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + + // PDE4 is the highest level on Hopper, see the comment in uvm_hopper_mmu.c + // for details. + UVM_ASSERT_MSG(depth < NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4, "depth %u", depth); + page_table_level = NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 - depth; + + if (membar != UVM_MEMBAR_NONE) { + // If a GPU or SYS membar is needed, ACK_TYPE needs to be set to + // GLOBALLY to make sure all the pending accesses can be picked up by + // the membar. + ack_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY); + } + + NV_PUSH_4U(C86F, MEM_OP_A, HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) | + HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_INVAL_SCOPE, NON_LINK_TLBS), + MEM_OP_B, 0, + MEM_OP_C, HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) | + aperture_value | + ack_value, + MEM_OP_D, HWCONST(C86F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE) | + HWVALUE(C86F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); + + uvm_hal_tlb_invalidate_membar(push, membar); +} + +void uvm_hal_hopper_host_tlb_invalidate_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + NvU64 base, + NvU64 size, + NvU32 page_size, + uvm_membar_t membar) +{ + NvU32 aperture_value; + NvU32 page_table_level; + NvU32 pdb_lo; + NvU32 pdb_hi; + NvU32 ack_value = 0; + NvU32 va_lo; + NvU32 va_hi; + NvU64 end; + NvU64 actual_base; + NvU64 actual_size; + NvU64 actual_end; + NvU32 log2_invalidation_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT_MSG(IS_ALIGNED(page_size, 1 << 12), "page_size 0x%x\n", page_size); + UVM_ASSERT_MSG(IS_ALIGNED(base, page_size), "base 0x%llx page_size 0x%x\n", base, page_size); + UVM_ASSERT_MSG(IS_ALIGNED(size, page_size), "size 0x%llx page_size 0x%x\n", size, page_size); + UVM_ASSERT_MSG(size > 0, "size 0x%llx\n", size); + + // The invalidation size must be a power-of-two number of pages containing + // the passed interval + end = base + size - 1; + log2_invalidation_size = __fls((unsigned long)(end ^ base)) + 1; + + if (log2_invalidation_size == 64) { + // Invalidate everything + gpu->parent->host_hal->tlb_invalidate_all(push, pdb, depth, membar); + return; + } + + // The hardware aligns the target address down to the invalidation size. + actual_size = 1ULL << log2_invalidation_size; + actual_base = UVM_ALIGN_DOWN(base, actual_size); + actual_end = actual_base + actual_size - 1; + UVM_ASSERT(actual_end >= end); + + // The invalidation size field expects log2(invalidation size in 4K), not + // log2(invalidation size in bytes) + log2_invalidation_size -= 12; + + // Address to invalidate, as a multiple of 4K. + base >>= 12; + va_lo = base & HWMASK(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + va_hi = base >> HWSIZE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + + UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture); + + if (pdb.aperture == UVM_APERTURE_VID) + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM); + else + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT); + + UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address); + pdb.address >>= 12; + + pdb_lo = pdb.address & HWMASK(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + pdb_hi = pdb.address >> HWSIZE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + + // PDE4 is the highest level on Hopper, see the comment in uvm_hopper_mmu.c + // for details. + UVM_ASSERT_MSG(depth < NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4, "depth %u", depth); + page_table_level = NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 - depth; + + if (membar != UVM_MEMBAR_NONE) { + // If a GPU or SYS membar is needed, ACK_TYPE needs to be set to + // GLOBALLY to make sure all the pending accesses can be picked up by + // the membar. + ack_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY); + } + + NV_PUSH_4U(C86F, MEM_OP_A, HWVALUE(C86F, MEM_OP_A, TLB_INVALIDATE_INVALIDATION_SIZE, log2_invalidation_size) | + HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) | + HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_INVAL_SCOPE, NON_LINK_TLBS) | + HWVALUE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo), + MEM_OP_B, HWVALUE(C86F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi), + MEM_OP_C, HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) | + aperture_value | + ack_value, + MEM_OP_D, HWCONST(C86F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) | + HWVALUE(C86F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); + + uvm_hal_tlb_invalidate_membar(push, membar); +} + +void uvm_hal_hopper_host_tlb_invalidate_test(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + UVM_TEST_INVALIDATE_TLB_PARAMS *params) +{ + NvU32 ack_value = 0; + NvU32 invalidate_gpc_value = 0; + NvU32 aperture_value = 0; + NvU32 pdb_lo = 0; + NvU32 pdb_hi = 0; + NvU32 page_table_level = 0; + uvm_membar_t membar; + + UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture); + if (pdb.aperture == UVM_APERTURE_VID) + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM); + else + aperture_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT); + + UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address); + pdb.address >>= 12; + + pdb_lo = pdb.address & HWMASK(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + pdb_hi = pdb.address >> HWSIZE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO); + + if (params->page_table_level != UvmInvalidatePageTableLevelAll) { + // PDE4 is the highest level on Hopper, see the comment in + // uvm_hopper_mmu.c for details. + page_table_level = min((NvU32)UvmInvalidatePageTableLevelPde4, params->page_table_level) - 1; + } + + if (params->membar != UvmInvalidateTlbMemBarNone) { + // If a GPU or SYS membar is needed, ack_value needs to be set to + // GLOBALLY to make sure all the pending accesses can be picked up by + // the membar. + ack_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY); + } + + if (params->disable_gpc_invalidate) + invalidate_gpc_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_GPC, DISABLE); + else + invalidate_gpc_value = HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE); + + if (params->target_va_mode == UvmTargetVaModeTargeted) { + NvU64 va = params->va >> 12; + + NvU32 va_lo = va & HWMASK(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + NvU32 va_hi = va >> HWSIZE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO); + + NV_PUSH_4U(C86F, MEM_OP_A, HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) | + HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_INVAL_SCOPE, NON_LINK_TLBS) | + HWVALUE(C86F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo), + MEM_OP_B, HWVALUE(C86F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi), + MEM_OP_C, HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) | + invalidate_gpc_value | + aperture_value | + ack_value, + MEM_OP_D, HWCONST(C86F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) | + HWVALUE(C86F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); + } + else { + NV_PUSH_4U(C86F, MEM_OP_A, HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) | + HWCONST(C86F, MEM_OP_A, TLB_INVALIDATE_INVAL_SCOPE, NON_LINK_TLBS), + MEM_OP_B, 0, + MEM_OP_C, HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) | + HWCONST(C86F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) | + HWVALUE(C86F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) | + invalidate_gpc_value | + aperture_value | + ack_value, + MEM_OP_D, HWCONST(C86F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE) | + HWVALUE(C86F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi)); + } + + if (params->membar == UvmInvalidateTlbMemBarSys) + membar = UVM_MEMBAR_SYS; + else if (params->membar == UvmInvalidateTlbMemBarLocal) + membar = UVM_MEMBAR_GPU; + else + membar = UVM_MEMBAR_NONE; + + uvm_hal_tlb_invalidate_membar(push, membar); +} + +void uvm_hal_hopper_host_set_gpfifo_pushbuffer_segment_base(NvU64 *fifo_entry, NvU64 pushbuffer_va) +{ + UVM_ASSERT(!uvm_global_is_suspended()); + UVM_ASSERT((pushbuffer_va >> 40) == ((NvU64)(pushbuffer_va + UVM_PUSHBUFFER_SIZE) >> 40)); + + *fifo_entry = HWVALUE(C86F, GP_ENTRY0, PB_EXTENDED_BASE_OPERAND, (pushbuffer_va >> 40)); + *fifo_entry |= (NvU64)(HWCONST(C86F, GP_ENTRY1, OPCODE, SET_PB_SEGMENT_EXTENDED_BASE)) << 32; +} + +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +{ + NvU64 fifo_entry_value; + NvU64 pb_low_bits_mask = (1ull << 40) - 1; + + UVM_ASSERT(!uvm_global_is_suspended()); + UVM_ASSERT_MSG(IS_ALIGNED(pushbuffer_va, 4), "pushbuffer va unaligned: %llu\n", pushbuffer_va); + UVM_ASSERT_MSG(IS_ALIGNED(pushbuffer_length, 4), "pushbuffer length unaligned: %u\n", pushbuffer_length); + + // The PBDMA/Esched fetches the lower 40-bits of a pushbuffer VA from the + // GPFIFO entry. The VA upper bits are stored internally by Esched and set + // by uvm_channel_write_ctrl_gpfifo()/set_gpfifo_pushbuffer_segment_base(). + pushbuffer_va &= pb_low_bits_mask; + fifo_entry_value = HWVALUE(C86F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); + fifo_entry_value |= (NvU64)(HWVALUE(C86F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | + HWVALUE(C86F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2)) << 32; + + *fifo_entry = fifo_entry_value; +} diff --git a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c new file mode 100644 index 000000000..092a7e2ba --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c @@ -0,0 +1,501 @@ +/******************************************************************************* + Copyright (c) 2020-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +// For Hopper, the UVM page tree 'depth' maps to hardware as follows: +// +// UVM depth HW level VA bits +// 0 PDE4 56:56 +// 1 PDE3 55:47 +// 2 PDE2 46:38 +// 3 PDE1 (or 512M PTE) 37:29 +// 4 PDE0 (dual 64k/4k PDE, or 2M PTE) 28:21 +// 5 PTE_64K / PTE_4K 20:16 / 20:12 + +#include "uvm_types.h" +#include "uvm_global.h" +#include "uvm_hal.h" +#include "uvm_hal_types.h" +#include "uvm_hopper_fault_buffer.h" +#include "hwref/hopper/gh100/dev_fault.h" +#include "hwref/hopper/gh100/dev_mmu.h" + +#define MMU_BIG 0 +#define MMU_SMALL 1 + +uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id) +{ + if (mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_HOST0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_HOST44) + return UVM_MMU_ENGINE_TYPE_HOST; + + if (mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_CE0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_CE9) + return UVM_MMU_ENGINE_TYPE_CE; + + // We shouldn't be servicing faults from any other engines + UVM_ASSERT_MSG(mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_GRAPHICS, "Unexpected engine ID: 0x%x\n", mmu_engine_id); + + return UVM_MMU_ENGINE_TYPE_GRAPHICS; +} + +static NvU32 page_table_depth_hopper(NvU32 page_size) +{ + // The common-case is page_size == UVM_PAGE_SIZE_2M, hence the first check + if (page_size == UVM_PAGE_SIZE_2M) + return 4; + else if (page_size == UVM_PAGE_SIZE_512M) + return 3; + return 5; +} + +static NvU32 entries_per_index_hopper(NvU32 depth) +{ + UVM_ASSERT(depth < 6); + if (depth == 4) + return 2; + return 1; +} + +static NvLength entry_offset_hopper(NvU32 depth, NvU32 page_size) +{ + UVM_ASSERT(depth < 6); + if ((page_size == UVM_PAGE_SIZE_4K) && (depth == 4)) + return MMU_SMALL; + return MMU_BIG; +} + +static NvLength entry_size_hopper(NvU32 depth) +{ + return entries_per_index_hopper(depth) * 8; +} + +static NvU32 index_bits_hopper(NvU32 depth, NvU32 page_size) +{ + static const NvU32 bit_widths[] = {1, 9, 9, 9, 8}; + + // some code paths keep on querying this until they get a 0, meaning only + // the page offset remains. + UVM_ASSERT(depth < 6); + if (depth < 5) { + return bit_widths[depth]; + } + else if (depth == 5) { + switch (page_size) { + case UVM_PAGE_SIZE_4K: + return 9; + case UVM_PAGE_SIZE_64K: + return 5; + default: + break; + } + } + return 0; +} + +static NvU32 num_va_bits_hopper(void) +{ + return 57; +} + +static NvLength allocation_size_hopper(NvU32 depth, NvU32 page_size) +{ + UVM_ASSERT(depth < 6); + if (depth == 5 && page_size == UVM_PAGE_SIZE_64K) + return 256; + + // depth 0 requires only a 16-byte allocation, but it must be 4k aligned. + return 4096; +} + +// PTE Permission Control Flags +static NvU64 pte_pcf(uvm_prot_t prot, NvU64 flags) +{ + bool ac = !(flags & UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED); + bool cached = flags & UVM_MMU_PTE_FLAGS_CACHED; + + UVM_ASSERT(prot != UVM_PROT_NONE); + UVM_ASSERT((flags & ~UVM_MMU_PTE_FLAGS_MASK) == 0); + + if (ac) { + switch (prot) { + case UVM_PROT_READ_ONLY: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE : + NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE; + case UVM_PROT_READ_WRITE: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE : + NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE; + case UVM_PROT_READ_WRITE_ATOMIC: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE : + NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE; + default: + break; + } + } + else { + switch (prot) { + case UVM_PROT_READ_ONLY: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD : + NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD; + case UVM_PROT_READ_WRITE: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD : + NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD; + case UVM_PROT_READ_WRITE_ATOMIC: + return cached ? NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD : + NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD; + default: + break; + } + } + + // Unsupported PCF + UVM_ASSERT_MSG(0, "Unsupported PTE PCF: prot: %s, ac: %d, cached: %d\n", uvm_prot_string(prot), ac, cached); + + return NV_MMU_VER3_PTE_PCF_INVALID; +} + +static NvU64 make_pte_hopper(uvm_aperture_t aperture, NvU64 address, uvm_prot_t prot, NvU64 flags) +{ + NvU8 aperture_bits = 0; + NvU64 pte_bits = 0; + + // valid 0:0 + pte_bits |= HWCONST64(_MMU_VER3, PTE, VALID, TRUE); + + // aperture 2:1 + if (aperture == UVM_APERTURE_SYS) + aperture_bits = NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY; + else if (aperture == UVM_APERTURE_VID) + aperture_bits = NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY; + else if (aperture >= UVM_APERTURE_PEER_0 && aperture <= UVM_APERTURE_PEER_7) + aperture_bits = NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY; + else + UVM_ASSERT_MSG(0, "Invalid aperture: %d\n", aperture); + + pte_bits |= HWVALUE64(_MMU_VER3, PTE, APERTURE, aperture_bits); + + // PCF (permission control flags) 7:3 + pte_bits |= HWVALUE64(_MMU_VER3, PTE, PCF, pte_pcf(prot, flags)); + + // kind 11:8 + pte_bits |= HWVALUE64(_MMU_VER3, PTE, KIND, NV_MMU_PTE_KIND_GENERIC_MEMORY); + + address >>= NV_MMU_VER3_PTE_ADDRESS_SHIFT; + + if (aperture == UVM_APERTURE_VID) { + // vid address 39:12 + pte_bits |= HWVALUE64(_MMU_VER3, PTE, ADDRESS_VID, address); + } + else { + // sys/peer address 51:12 + pte_bits |= HWVALUE64(_MMU_VER3, PTE, ADDRESS, address); + + // peer id 63:61 + if (aperture >= UVM_APERTURE_PEER_0 && aperture <= UVM_APERTURE_PEER_7) + pte_bits |= HWVALUE64(_MMU_VER3, PTE, PEER_ID, UVM_APERTURE_PEER_ID(aperture)); + } + + return pte_bits; +} + +static NvU64 make_sked_reflected_pte_hopper(void) +{ + return HWCONST64(_MMU_VER3, PTE, VALID, TRUE) | + HWVALUE64(_MMU_VER3, PTE, PCF, pte_pcf(UVM_PROT_READ_WRITE_ATOMIC, UVM_MMU_PTE_FLAGS_NONE)) | + HWVALUE64(_MMU_VER3, PTE, KIND, NV_MMU_PTE_KIND_SMSKED_MESSAGE); +} + +static NvU64 make_sparse_pte_hopper(void) +{ + return HWCONST64(_MMU_VER3, PTE, VALID, FALSE) | + HWCONST64(_MMU_VER3, PTE, PCF, SPARSE); +} + +static NvU64 unmapped_pte_hopper(NvU32 page_size) +{ + // Setting PCF to NO_VALID_4KB_PAGE on an otherwise-zeroed big PTE causes + // the corresponding 4k PTEs to be ignored. This allows the invalidation of + // a mixed PDE range to be much faster. + if (page_size != UVM_PAGE_SIZE_64K) + return 0; + + // When VALID == 0, GMMU still reads the PCF field, which indicates the PTE + // is sparse (make_sparse_pte_hopper) or an unmapped big-page PTE. + return HWCONST64(_MMU_VER3, PTE, VALID, FALSE) | + HWCONST64(_MMU_VER3, PTE, PCF, NO_VALID_4KB_PAGE); +} + +static NvU64 poisoned_pte_hopper(void) +{ + // An invalid PTE won't be fatal from faultable units like SM, which is the + // most likely source of bad PTE accesses. + + // Engines with priv accesses won't fault on the priv PTE, so add a backup + // mechanism using an impossible memory address. MMU will trigger an + // interrupt when it detects a bad physical address, i.e., a physical + // address > GPU memory size. + // + // This address has to fit within 38 bits (max address width of vidmem) and + // be aligned to page_size. + NvU64 phys_addr = 0x2bad000000ULL; + + NvU64 pte_bits = make_pte_hopper(UVM_APERTURE_VID, phys_addr, UVM_PROT_READ_ONLY, UVM_MMU_PTE_FLAGS_NONE); + return WRITE_HWCONST64(pte_bits, _MMU_VER3, PTE, PCF, PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD); +} + +static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 depth) +{ + NvU64 pde_bits = 0; + + if (phys_alloc != NULL) { + NvU64 address = phys_alloc->addr.address >> NV_MMU_VER3_PDE_ADDRESS_SHIFT; + pde_bits |= HWCONST64(_MMU_VER3, PDE, IS_PTE, FALSE); + + switch (phys_alloc->addr.aperture) { + case UVM_APERTURE_SYS: + pde_bits |= HWCONST64(_MMU_VER3, PDE, APERTURE, SYSTEM_COHERENT_MEMORY); + break; + case UVM_APERTURE_VID: + pde_bits |= HWCONST64(_MMU_VER3, PDE, APERTURE, VIDEO_MEMORY); + break; + default: + UVM_ASSERT_MSG(0, "Invalid aperture: %d\n", phys_alloc->addr.aperture); + break; + } + + // PCF (permission control flags) 5:3 + // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both + // ATS and GMMU page tables. For managed memory we need to prevent this + // parallel lookup since we would not get any GPU fault if the CPU has + // a valid mapping. Also, for external ranges that are known to be + // mapped entirely on the GMMU page table we can skip the ATS lookup + // for performance reasons. Parallel ATS lookup is disabled in PDE1 + // (depth 3) and, therefore, it applies to the underlying 512MB VA + // range. + // + // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. + // This is fine because CUDA ensures that all managed and external + // allocations are properly compartmentalized in 512MB-aligned VA + // regions. For cudaHostRegister CUDA cannot control the VA range, but + // we rely on ATS for those allocations so they can't choose the + // ATS_NOT_ALLOWED mode. + // + // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range + // to PTEs. + if (depth == 3 && g_uvm_global.ats.enabled) + pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_NOT_ALLOWED); + else + pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_ALLOWED); + + // address 51:12 + pde_bits |= HWVALUE64(_MMU_VER3, PDE, ADDRESS, address); + } + + return pde_bits; +} + +static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +{ + NvU64 pde_bits = 0; + + if (phys_alloc != NULL) { + NvU64 address = phys_alloc->addr.address >> NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT; + + switch (phys_alloc->addr.aperture) { + case UVM_APERTURE_SYS: + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_BIG, SYSTEM_COHERENT_MEMORY); + break; + case UVM_APERTURE_VID: + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_BIG, VIDEO_MEMORY); + break; + default: + UVM_ASSERT_MSG(0, "Invalid big aperture %d\n", phys_alloc->addr.aperture); + break; + } + + // PCF (permission control flags) 5:3 + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_BIG, VALID_UNCACHED_ATS_NOT_ALLOWED); + + // address 51:8 + pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_BIG, address); + } + + return pde_bits; +} + +static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +{ + NvU64 pde_bits = 0; + + if (phys_alloc != NULL) { + NvU64 address = phys_alloc->addr.address >> NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT; + + switch (phys_alloc->addr.aperture) { + case UVM_APERTURE_SYS: + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_SMALL, SYSTEM_COHERENT_MEMORY); + break; + case UVM_APERTURE_VID: + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_SMALL, VIDEO_MEMORY); + break; + default: + UVM_ASSERT_MSG(0, "Invalid small aperture %d\n", phys_alloc->addr.aperture); + break; + } + + // PCF (permission control flags) 69:67 [5:3] + pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_SMALL, VALID_UNCACHED_ATS_NOT_ALLOWED); + + // address 115:76 [51:12] + pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_SMALL, address); + } + return pde_bits; +} + +static void make_pde_hopper(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +{ + NvU32 entry_count = entries_per_index_hopper(depth); + NvU64 *entry_bits = (NvU64 *)entry; + + if (entry_count == 1) { + *entry_bits = single_pde_hopper(*phys_allocs, depth); + } + else if (entry_count == 2) { + entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG]); + entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL]); + + // This entry applies to the whole dual PDE but is stored in the lower + // bits + entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER3, DUAL_PDE, IS_PTE, FALSE); + } + else { + UVM_ASSERT_MSG(0, "Invalid number of entries per index: %d\n", entry_count); + } +} + +static uvm_mmu_mode_hal_t hopper_mmu_mode_hal; + +uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_hopper(NvU32 big_page_size) +{ + static bool initialized = false; + + UVM_ASSERT(big_page_size == UVM_PAGE_SIZE_64K || big_page_size == UVM_PAGE_SIZE_128K); + + // TODO: Bug 1789555: RM should reject the creation of GPU VA spaces with + // 128K big page size for Pascal+ GPUs + if (big_page_size == UVM_PAGE_SIZE_128K) + return NULL; + + if (!initialized) { + uvm_mmu_mode_hal_t *ampere_mmu_mode_hal = uvm_hal_mmu_mode_ampere(big_page_size); + UVM_ASSERT(ampere_mmu_mode_hal); + + // The assumption made is that arch_hal->mmu_mode_hal() will be called + // under the global lock the first time, so check it here. + uvm_assert_mutex_locked(&g_uvm_global.global_lock); + + hopper_mmu_mode_hal = *ampere_mmu_mode_hal; + hopper_mmu_mode_hal.entry_size = entry_size_hopper; + hopper_mmu_mode_hal.index_bits = index_bits_hopper; + hopper_mmu_mode_hal.entries_per_index = entries_per_index_hopper; + hopper_mmu_mode_hal.entry_offset = entry_offset_hopper; + hopper_mmu_mode_hal.num_va_bits = num_va_bits_hopper; + hopper_mmu_mode_hal.allocation_size = allocation_size_hopper; + hopper_mmu_mode_hal.page_table_depth = page_table_depth_hopper; + hopper_mmu_mode_hal.make_pte = make_pte_hopper; + hopper_mmu_mode_hal.make_sked_reflected_pte = make_sked_reflected_pte_hopper; + hopper_mmu_mode_hal.make_sparse_pte = make_sparse_pte_hopper; + hopper_mmu_mode_hal.unmapped_pte = unmapped_pte_hopper; + hopper_mmu_mode_hal.poisoned_pte = poisoned_pte_hopper; + hopper_mmu_mode_hal.make_pde = make_pde_hopper; + + initialized = true; + } + + return &hopper_mmu_mode_hal; +} + +NvU16 uvm_hal_hopper_mmu_client_id_to_utlb_id(NvU16 client_id) +{ + switch (client_id) { + case NV_PFAULT_CLIENT_GPC_RAST: + case NV_PFAULT_CLIENT_GPC_GCC: + case NV_PFAULT_CLIENT_GPC_GPCCS: + return UVM_HOPPER_GPC_UTLB_ID_RGG; + case NV_PFAULT_CLIENT_GPC_T1_0: + return UVM_HOPPER_GPC_UTLB_ID_LTP0; + case NV_PFAULT_CLIENT_GPC_T1_1: + case NV_PFAULT_CLIENT_GPC_PE_0: + case NV_PFAULT_CLIENT_GPC_TPCCS_0: + return UVM_HOPPER_GPC_UTLB_ID_LTP1; + case NV_PFAULT_CLIENT_GPC_T1_2: + return UVM_HOPPER_GPC_UTLB_ID_LTP2; + case NV_PFAULT_CLIENT_GPC_T1_3: + case NV_PFAULT_CLIENT_GPC_PE_1: + case NV_PFAULT_CLIENT_GPC_TPCCS_1: + return UVM_HOPPER_GPC_UTLB_ID_LTP3; + case NV_PFAULT_CLIENT_GPC_T1_4: + return UVM_HOPPER_GPC_UTLB_ID_LTP4; + case NV_PFAULT_CLIENT_GPC_T1_5: + case NV_PFAULT_CLIENT_GPC_PE_2: + case NV_PFAULT_CLIENT_GPC_TPCCS_2: + return UVM_HOPPER_GPC_UTLB_ID_LTP5; + case NV_PFAULT_CLIENT_GPC_T1_6: + return UVM_HOPPER_GPC_UTLB_ID_LTP6; + case NV_PFAULT_CLIENT_GPC_T1_7: + case NV_PFAULT_CLIENT_GPC_PE_3: + case NV_PFAULT_CLIENT_GPC_TPCCS_3: + return UVM_HOPPER_GPC_UTLB_ID_LTP7; + case NV_PFAULT_CLIENT_GPC_T1_8: + return UVM_HOPPER_GPC_UTLB_ID_LTP8; + case NV_PFAULT_CLIENT_GPC_T1_9: + case NV_PFAULT_CLIENT_GPC_PE_4: + case NV_PFAULT_CLIENT_GPC_TPCCS_4: + return UVM_HOPPER_GPC_UTLB_ID_LTP9; + case NV_PFAULT_CLIENT_GPC_T1_10: + return UVM_HOPPER_GPC_UTLB_ID_LTP10; + case NV_PFAULT_CLIENT_GPC_T1_11: + case NV_PFAULT_CLIENT_GPC_PE_5: + case NV_PFAULT_CLIENT_GPC_TPCCS_5: + return UVM_HOPPER_GPC_UTLB_ID_LTP11; + case NV_PFAULT_CLIENT_GPC_T1_12: + return UVM_HOPPER_GPC_UTLB_ID_LTP12; + case NV_PFAULT_CLIENT_GPC_T1_13: + case NV_PFAULT_CLIENT_GPC_PE_6: + case NV_PFAULT_CLIENT_GPC_TPCCS_6: + return UVM_HOPPER_GPC_UTLB_ID_LTP13; + case NV_PFAULT_CLIENT_GPC_T1_14: + return UVM_HOPPER_GPC_UTLB_ID_LTP14; + case NV_PFAULT_CLIENT_GPC_T1_15: + case NV_PFAULT_CLIENT_GPC_PE_7: + case NV_PFAULT_CLIENT_GPC_TPCCS_7: + return UVM_HOPPER_GPC_UTLB_ID_LTP15; + case NV_PFAULT_CLIENT_GPC_T1_16: + return UVM_HOPPER_GPC_UTLB_ID_LTP16; + case NV_PFAULT_CLIENT_GPC_T1_17: + case NV_PFAULT_CLIENT_GPC_PE_8: + case NV_PFAULT_CLIENT_GPC_TPCCS_8: + return UVM_HOPPER_GPC_UTLB_ID_LTP17; + + default: + UVM_ASSERT_MSG(false, "Invalid client value: 0x%x\n", client_id); + } + + return 0; +} diff --git a/kernel-open/nvidia-uvm/uvm_host_test.c b/kernel-open/nvidia-uvm/uvm_host_test.c index adee750e7..4c4a65b0d 100644 --- a/kernel-open/nvidia-uvm/uvm_host_test.c +++ b/kernel-open/nvidia-uvm/uvm_host_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2021 NVIDIA Corporation + Copyright (c) 2020-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -46,7 +46,7 @@ static NV_STATUS test_semaphore_alloc_uvm_rm_mem(uvm_gpu_t *gpu, const size_t si uvm_rm_mem_t *mem = NULL; NvU64 gpu_va; - status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, &mem); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); TEST_NV_CHECK_RET(status); gpu_va = uvm_rm_mem_get_gpu_uvm_va(mem, gpu); diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index ddbcc67b2..675901737 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -88,16 +88,12 @@ #include "nv-kthread-q.h" - #if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 && defined(NV_CPUMASK_OF_NODE_PRESENT) #define UVM_THREAD_AFFINITY_SUPPORTED() 1 #else #define UVM_THREAD_AFFINITY_SUPPORTED() 0 #endif - - - // The ARM arch lacks support for cpumask_of_node() until kernel 4.7. It was // added via commit1a2db300348b ("arm64, numa: Add NUMA support for arm64 // platforms.") Callers should either check UVM_THREAD_AFFINITY_SUPPORTED() @@ -112,16 +108,12 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #endif } - #if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MAKE_DEVICE_EXCLUSIVE_RANGE_PRESENT) #define UVM_IS_CONFIG_HMM() 1 #else #define UVM_IS_CONFIG_HMM() 0 #endif - - - // Various issues prevent us from using mmu_notifiers in older kernels. These // include: // - ->release being called under RCU instead of SRCU: fixed by commit @@ -137,21 +129,12 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) // // The callback was added in commit 0f0a327fa12cd55de5e7f8c05a70ac3d047f405e, // v3.19 (2014-11-13). - #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) #define UVM_CAN_USE_MMU_NOTIFIERS() 1 #else #define UVM_CAN_USE_MMU_NOTIFIERS() 0 #endif - - - - - - - - // See bug 1707453 for further details about setting the minimum kernel version. #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32) # error This driver does not support kernels older than 2.6.32! @@ -543,7 +526,6 @@ typedef struct struct mem_cgroup *old_memcg; } uvm_memcg_context_t; - // cgroup support requires set_active_memcg(). set_active_memcg() is an // inline function that requires int_active_memcg per-cpu symbol when called // from interrupt context. int_active_memcg is only exported by commit @@ -585,29 +567,13 @@ typedef struct } #endif // NV_IS_EXPORT_SYMBOL_PRESENT_int_active_memcg +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) + #include +#endif - - - - - - - - - - - - - - - - - - - - - - +#if !defined(PAGE_KERNEL_NOENC) + #define PAGE_KERNEL_NOENC PAGE_KERNEL +#endif // Commit 1dff8083a024650c75a9c961c38082473ceae8cf (v4.7). // diff --git a/kernel-open/nvidia-uvm/uvm_lock.c b/kernel-open/nvidia-uvm/uvm_lock.c index 3b89da612..2b5bfd68f 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.c +++ b/kernel-open/nvidia-uvm/uvm_lock.c @@ -27,12 +27,8 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) { - - - BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 26); - switch (lock_order) { UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_INVALID); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_GLOBAL_PM); @@ -48,14 +44,8 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_API); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_GPUS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_BLOCK); - - - UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHUNK_MAPPING); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PAGE_TREE); - - - UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PUSH); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_PMA); diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index b2b139230..fe4f114bc 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -276,16 +276,6 @@ // Operations not allowed while holding the lock: // - GPU memory allocation which can evict memory (would require nesting // block locks) - - - - - - - - - - // - Chunk mapping lock (gpu->root_chunk_mappings.bitlocks and // gpu->sysmem_mappings.bitlock) // Order: UVM_LOCK_ORDER_CHUNK_MAPPING @@ -320,20 +310,6 @@ // Operations not allowed while holding this lock // - GPU memory allocation which can evict // - - - - - - - - - - - - - - // - Concurrent push semaphore // Order: UVM_LOCK_ORDER_PUSH // Semaphore (uvm_semaphore_t) @@ -408,14 +384,8 @@ typedef enum UVM_LOCK_ORDER_RM_API, UVM_LOCK_ORDER_RM_GPUS, UVM_LOCK_ORDER_VA_BLOCK, - - - UVM_LOCK_ORDER_CHUNK_MAPPING, UVM_LOCK_ORDER_PAGE_TREE, - - - UVM_LOCK_ORDER_PUSH, UVM_LOCK_ORDER_PMM, UVM_LOCK_ORDER_PMM_PMA, diff --git a/kernel-open/nvidia-uvm/uvm_map_external.c b/kernel-open/nvidia-uvm/uvm_map_external.c index 3b3a09c37..3b2752b2e 100644 --- a/kernel-open/nvidia-uvm/uvm_map_external.c +++ b/kernel-open/nvidia-uvm/uvm_map_external.c @@ -636,19 +636,6 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, { uvm_gpu_t *owning_gpu; - - - - - - - - - - - - - // This is a local or peer allocation, so the owning GPU must have been // registered. owning_gpu = uvm_va_space_get_gpu_by_uuid(va_space, &mem_info->uuid); diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_host.c b/kernel-open/nvidia-uvm/uvm_maxwell_host.c index 74c8a6cce..56d4b9e81 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_host.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_host.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -233,6 +233,19 @@ void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_v *fifo_entry = fifo_entry_value; } +void uvm_hal_maxwell_host_set_gpfifo_noop(NvU64 *fifo_entry) +{ + UVM_ASSERT(!uvm_global_is_suspended()); + + // A NOOP control GPFIFO does not require a GP_ENTRY0. + *fifo_entry = (NvU64)(HWVALUE(A16F, GP_ENTRY1, LENGTH, 0) | HWCONST(A16F, GP_ENTRY1, OPCODE, NOP)) << 32; +} + +void uvm_hal_maxwell_host_set_gpfifo_pushbuffer_segment_base_unsupported(NvU64 *fifo_entry, NvU64 pushbuffer_va) +{ + UVM_ASSERT_MSG(false, "host set_gpfifo_pushbuffer_segment_base called on Maxwell GPU\n"); +} + void uvm_hal_maxwell_host_write_gpu_put(uvm_channel_t *channel, NvU32 gpu_put) { UVM_GPU_WRITE_ONCE(*channel->channel_info.gpPut, gpu_put); diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 460f786da..455506239 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -71,11 +71,9 @@ static bool sysmem_can_be_mapped(uvm_mem_t *sysmem) { UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - - - - - + // If SEV is enabled, only unprotected memory can be mapped + if (g_uvm_global.sev_enabled) + return uvm_mem_is_sysmem_dma(sysmem); return true; } @@ -451,11 +449,6 @@ static gfp_t sysmem_allocation_gfp_flags(int order, bool zero) return gfp_flags; } - - - - - // There is a tighter coupling between allocation and mapping because of the // allocator UVM must use. Hence, this function does the equivalent of // uvm_mem_map_gpu_phys(). @@ -731,10 +724,8 @@ static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) pages[page_index] = mem_cpu_page(mem, page_index * PAGE_SIZE); } - - - - + if (g_uvm_global.sev_enabled) + prot = PAGE_KERNEL_NOENC; mem->kernel.cpu_addr = vmap(pages, num_pages, VM_MAP, prot); @@ -1068,18 +1059,6 @@ static NV_STATUS mem_map_gpu(uvm_mem_t *mem, page_size = mem_pick_gpu_page_size(mem, gpu, tree); UVM_ASSERT_MSG(uvm_mmu_page_size_supported(tree, page_size), "page_size 0x%x\n", page_size); - - - - - - - - - - - - status = uvm_page_table_range_vec_create(tree, gpu_va, mem->physical_allocation_size, diff --git a/kernel-open/nvidia-uvm/uvm_mem.h b/kernel-open/nvidia-uvm/uvm_mem.h index 62ebfc7bb..def67cc6b 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_mem.h @@ -161,10 +161,6 @@ struct uvm_mem_struct // lifetime of the GPU. For CPU allocations there is no lifetime limitation. uvm_gpu_t *backing_gpu; - - - - uvm_gpu_t *dma_owner; // Size of the physical chunks. @@ -396,14 +392,12 @@ static NV_STATUS uvm_mem_alloc_sysmem_and_map_cpu_kernel(NvU64 size, struct mm_s return NV_OK; } - - - - - - - - +// Helper for allocating sysmem DMA and mapping it on the CPU. This is useful +// for certain systems where the main system memory is encrypted +// (e.g., AMD SEV) and cannot be read from IO devices unless specially +// allocated using the DMA APIs. +// +// See uvm_mem_alloc() static NV_STATUS uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(NvU64 size, uvm_gpu_t *gpu, struct mm_struct *mm, diff --git a/kernel-open/nvidia-uvm/uvm_mem_test.c b/kernel-open/nvidia-uvm/uvm_mem_test.c index 53e7ac623..fcf1279e3 100644 --- a/kernel-open/nvidia-uvm/uvm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_mem_test.c @@ -25,9 +25,6 @@ #include "uvm_kvmalloc.h" #include "uvm_mem.h" #include "uvm_push.h" - - - #include "uvm_test.h" #include "uvm_test_ioctl.h" #include "uvm_va_space.h" @@ -46,14 +43,10 @@ static NvU32 first_page_size(NvU32 page_sizes) static inline NV_STATUS __alloc_map_sysmem(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **sys_mem) { - - - - - - - return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); - + if (g_uvm_global.sev_enabled) + return uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, sys_mem); + else + return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); } static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) @@ -94,12 +87,8 @@ static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) sys_mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(sys_mem, gpu); sys_mem_gpu_address.address += offset; - - - should_use_pa = uvm_channel_is_privileged(push.channel); - if (should_use_pa) { mem_gpu_address = uvm_mem_gpu_address_physical(mem, gpu, offset, size_this_time); } @@ -348,10 +337,8 @@ static NV_STATUS test_alloc_vidmem(uvm_gpu_t *gpu, NvU32 page_size, size_t size, static bool should_test_page_size(size_t alloc_size, NvU32 page_size) { - - - - + if (g_uvm_global.sev_enabled) + return false; if (g_uvm_global.num_simulated_devices == 0) return true; @@ -543,45 +530,6 @@ static NV_STATUS test_basic_sysmem_dma(uvm_gpu_t *gpu) return status; } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - static NV_STATUS test_basic(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; @@ -591,9 +539,6 @@ static NV_STATUS test_basic(uvm_va_space_t *va_space) for_each_va_space_gpu(gpu, va_space) { TEST_CHECK_RET(test_basic_vidmem(gpu) == NV_OK); TEST_CHECK_RET(test_basic_sysmem_dma(gpu) == NV_OK); - - - } return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index bc5e949d8..d1bfbf21b 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -35,15 +35,9 @@ #include "uvm_va_space.h" - - - - - -// The page tree has 5 levels on Pascal, and the root is never freed by a normal -// 'put' operation which leaves a maximum of 4 levels -#define MAX_OPERATION_DEPTH 4 - +// The page tree has 6 levels on Hopper+ GPUs, and the root is never freed by a +// normal 'put' operation which leaves a maximum of 5 levels. +#define MAX_OPERATION_DEPTH 5 // Wrappers for push begin handling channel_manager not being there when running // the page tree unit test @@ -720,11 +714,7 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // default | vidmem || vidmem | false // default | sysmem || sysmem | false // - - - -// (1) The fallback to sysmem is always enabled. - +// (1) When SEV mode is enabled, the fallback path is disabled. // // In SR-IOV heavy the the page tree must be in vidmem, to prevent guest drivers // from updating GPU page tables without hypervisor knowledge. @@ -753,12 +743,8 @@ static void page_tree_set_location(uvm_page_tree_t *tree, uvm_aperture_t locatio if (page_table_aperture == UVM_APERTURE_DEFAULT) { tree->location = UVM_APERTURE_VID; - - - - - tree->location_sys_fallback = true; - + // See the comment (1) above. + tree->location_sys_fallback = !g_uvm_global.sev_enabled; } else { tree->location = page_table_aperture; @@ -1803,11 +1789,7 @@ static void destroy_identity_mapping(uvm_gpu_identity_mapping_t *mapping) bool uvm_mmu_gpu_needs_static_vidmem_mapping(uvm_gpu_t *gpu) { - - - return false; - } bool uvm_mmu_gpu_needs_dynamic_vidmem_mapping(uvm_gpu_t *gpu) diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index d76a0dbd7..8e80ab68f 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -37,27 +37,25 @@ // Memory layout of UVM's kernel VA space. // The following memory regions are not to scale. - - - - - - - - - - - - - - - - - - - - - +// Hopper: +// +----------------+ 128PB +// | | +// | (not used) | +// | | +// ------------------ +// |uvm_mem_t(128GB)| (uvm_mem_va_size) +// ------------------ 64PB + 384TB (uvm_mem_va_base) +// | | +// | (not used) | +// | | +// ------------------ 64PB + 8TB +// |peer ident. maps| +// |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE +// ------------------ 64PB +// | | +// | rm_mem(64PB) | (rm_va_size) +// | | +// +----------------+ 0 (rm_va_base) // // Pascal-Ampere: // +----------------+ 512TB @@ -74,13 +72,13 @@ // | | // | (not used) | // | | -// ------------------ 132TB + 128GB (UVM_GPU_MAX_PHYS_MEM) +// ------------------ 136TB + 256GB (UVM_GPU_MAX_PHYS_MEM) // | vidmem | // | flat mapping | ==> UVM_GPU_MAX_PHYS_MEM -// | (128GB) | -// ------------------ 132TB (flat_vidmem_va_base) +// | (256GB) | +// ------------------ 136TB (flat_vidmem_va_base) // |peer ident. maps| -// |32 * 128GB = 4TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE +// |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE // ------------------ 128TB // | | // | rm_mem(128TB) | (rm_va_size) @@ -105,7 +103,7 @@ // +----------------+ 0 (rm_va_base) // Maximum memory of any GPU. -#define UVM_GPU_MAX_PHYS_MEM (128ull * 1024 * 1024 * 1024) +#define UVM_GPU_MAX_PHYS_MEM (256ull * 1024 * 1024 * 1024) // The size of VA that should be reserved per peer identity mapping. // This should be at least the maximum amount of memory of any GPU. diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index 67ded36ee..1e5e81ecb 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -43,11 +43,9 @@ // AMPERE_* #include "clc56f.h" #include "clc6b5.h" - - - - - +// HOPPER_* +#include "clc8b5.h" +#include "clc86f.h" // ARCHITECTURE_* #include "ctrl2080mc.h" @@ -407,33 +405,31 @@ static NV_STATUS alloc_64k_memory(uvm_gpu_t *gpu) return NV_OK; } +static NV_STATUS alloc_64k_memory_57b_va(uvm_gpu_t *gpu) +{ + uvm_page_tree_t tree; + uvm_page_table_range_t range; + NvLength size = 64 * 1024; + MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, 0x100000000000000ULL, size, &range), NV_OK); + TEST_CHECK_RET(range.entry_count == 1); + TEST_CHECK_RET(range.table->depth == 5); + TEST_CHECK_RET(range.start_index == 0); + TEST_CHECK_RET(range.page_size == UVM_PAGE_SIZE_64K); + TEST_CHECK_RET(tree.root->ref_count == 1); + TEST_CHECK_RET(tree.root->entries[1]->ref_count == 1); + TEST_CHECK_RET(tree.root->entries[1]->entries[0]->ref_count == 1); + TEST_CHECK_RET(tree.root->entries[1]->entries[0]->entries[0]->ref_count == 1); + TEST_CHECK_RET(tree.root->entries[1]->entries[0]->entries[0]->entries[0]->ref_count == 1); + TEST_CHECK_RET(tree.root->entries[1]->entries[0]->entries[0]->entries[0]->entries[0]->ref_count == 1); + TEST_CHECK_RET(range.table == tree.root->entries[1]->entries[0]->entries[0]->entries[0]->entries[0]); + uvm_page_tree_put_ptes(&tree, &range); + UVM_ASSERT(tree.root->ref_count == 0); + uvm_page_tree_deinit(&tree); - - - - - - - - - - - - - - - - - - - - - - - - - + return NV_OK; +} static NV_STATUS alloc_adjacent_64k_memory(uvm_gpu_t *gpu) { @@ -1513,20 +1509,18 @@ static NV_STATUS entry_test_page_size_ampere(uvm_gpu_t *gpu, size_t page_size) return entry_test_page_size_volta(gpu, page_size); } +static NV_STATUS entry_test_page_size_hopper(uvm_gpu_t *gpu, size_t page_size) +{ + uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + // Page table entries + if (page_size == UVM_PAGE_SIZE_64K) + TEST_CHECK_RET(hal->unmapped_pte(page_size) == 0x18); + else + TEST_CHECK_RET(hal->unmapped_pte(page_size) == 0); - - - - - - - - - - - - + return NV_OK; +} typedef NV_STATUS (*entry_test_page_size_func)(uvm_gpu_t *gpu, size_t page_size); @@ -1783,109 +1777,107 @@ static NV_STATUS entry_test_ampere(uvm_gpu_t *gpu, entry_test_page_size_func ent return NV_OK; } +static NV_STATUS entry_test_hopper(uvm_gpu_t *gpu, entry_test_page_size_func entry_test_page_size) +{ + NvU32 page_sizes[MAX_NUM_PAGE_SIZES]; + NvU64 pde_bits[2]; + size_t i, num_page_sizes; + uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; + uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999000LL); + uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBB000LL); + // big versions have [11:8] set as well to test the page table merging + uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999900LL); + uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBBB00LL); + uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + // Make sure cleared PDEs work as expected + hal->make_pde(pde_bits, phys_allocs, 0); + TEST_CHECK_RET(pde_bits[0] == 0); + // Cleared PDEs work as expected for big and small PDEs. + memset(pde_bits, 0xFF, sizeof(pde_bits)); + hal->make_pde(pde_bits, phys_allocs, 4); + TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); + // Sys and vidmem PDEs, uncached ATS allowed. + phys_allocs[0] = &alloc_sys; + hal->make_pde(pde_bits, phys_allocs, 0); + TEST_CHECK_RET(pde_bits[0] == 0x999999999900C); + phys_allocs[0] = &alloc_vid; + hal->make_pde(pde_bits, phys_allocs, 0); + TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBB00A); + // Dual PDEs, uncached. + phys_allocs[0] = &alloc_big_sys; + phys_allocs[1] = &alloc_vid; + hal->make_pde(pde_bits, phys_allocs, 4); + TEST_CHECK_RET(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A); + phys_allocs[0] = &alloc_big_vid; + phys_allocs[1] = &alloc_sys; + hal->make_pde(pde_bits, phys_allocs, 4); + TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C); + // uncached, i.e., the sysmem data is not cached in GPU's L2 cache, and + // access counters disabled. + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D); + // change to cached. + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == + 0x9999999999685); + // enable access counters. + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605); + // remove atomic + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645); + // read only + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665); + // local video + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_VID, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661); + // peer 1 + TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_PEER_1, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663); + // sparse + TEST_CHECK_RET(hal->make_sparse_pte() == 0x8); + // sked reflected + TEST_CHECK_RET(hal->make_sked_reflected_pte() == 0xF09); + num_page_sizes = get_page_sizes(gpu, page_sizes); + for (i = 0; i < num_page_sizes; i++) + TEST_NV_CHECK_RET(entry_test_page_size(gpu, page_sizes[i])); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + return NV_OK; +} static NV_STATUS alloc_4k_maxwell(uvm_gpu_t *gpu) { @@ -2121,15 +2113,13 @@ static NV_STATUS fake_gpu_init_ampere(uvm_gpu_t *fake_gpu) fake_gpu); } - - - - - - - - - +static NV_STATUS fake_gpu_init_hopper(uvm_gpu_t *fake_gpu) +{ + return fake_gpu_init(HOPPER_CHANNEL_GPFIFO_A, + HOPPER_DMA_COPY_A, + NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + fake_gpu); +} static NV_STATUS maxwell_test_page_tree(uvm_gpu_t *maxwell) { @@ -2271,17 +2261,15 @@ static NV_STATUS ampere_test_page_tree(uvm_gpu_t *ampere) return NV_OK; } +static NV_STATUS hopper_test_page_tree(uvm_gpu_t *hopper) +{ + TEST_CHECK_RET(fake_gpu_init_hopper(hopper) == NV_OK); + MEM_NV_CHECK_RET(entry_test_hopper(hopper, entry_test_page_size_hopper), NV_OK); + MEM_NV_CHECK_RET(alloc_64k_memory_57b_va(hopper), NV_OK); - - - - - - - - - + return NV_OK; +} NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *filp) { @@ -2315,9 +2303,7 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil TEST_NV_CHECK_GOTO(pascal_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(volta_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(ampere_test_page_tree(gpu), done); - - - + TEST_NV_CHECK_GOTO(hopper_test_page_tree(gpu), done); done: fake_tlb_invals_free(); diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index 79a060b4e..7d14c93e2 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -653,7 +653,7 @@ static block_thrashing_info_t *thrashing_info_get_create(uvm_va_block_t *va_bloc static void thrashing_reset_pages_in_region(uvm_va_block_t *va_block, NvU64 address, NvU64 bytes); // Destroy the thrashing detection struct for the given block -static void thrashing_info_destroy(uvm_va_block_t *va_block) +void uvm_perf_thrashing_info_destroy(uvm_va_block_t *va_block) { block_thrashing_info_t *block_thrashing = thrashing_info_get(va_block); @@ -687,7 +687,7 @@ void thrashing_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t if (!va_block) return; - thrashing_info_destroy(va_block); + uvm_perf_thrashing_info_destroy(va_block); } // Sanity checks of the thrashing tracking state @@ -1118,9 +1118,9 @@ static NV_STATUS unmap_remote_pinned_pages_from_processors(uvm_va_block_t *va_bl // Unmap remote mappings from all processors on the pinned pages // described by region and block_thrashing->pinned pages. -static NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) +NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { block_thrashing_info_t *block_thrashing; uvm_processor_mask_t unmap_processors; @@ -2111,7 +2111,7 @@ NV_STATUS uvm_test_set_page_thrashing_policy(UVM_TEST_SET_PAGE_THRASHING_POLICY_ block_context, va_block_region)); - thrashing_info_destroy(va_block); + uvm_perf_thrashing_info_destroy(va_block); uvm_mutex_unlock(&va_block->lock); @@ -2123,6 +2123,15 @@ NV_STATUS uvm_test_set_page_thrashing_policy(UVM_TEST_SET_PAGE_THRASHING_POLICY_ } } } + + status = uvm_hmm_clear_thrashing_policy(va_space); + + // Re-enable thrashing on failure to avoid getting asserts + // about having state while thrashing is disabled + if (status != NV_OK) { + va_space_thrashing->params.enable = true; + goto done_unlock_va_space; + } } done_unlock_va_space: diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h index 596c97e54..cba9174b3 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h @@ -103,4 +103,13 @@ NV_STATUS uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *g void uvm_perf_thrashing_stop(uvm_va_space_t *va_space); void uvm_perf_thrashing_unload(uvm_va_space_t *va_space); +// Destroy the thrashing detection struct for the given block. +void uvm_perf_thrashing_info_destroy(uvm_va_block_t *va_block); + +// Unmap remote mappings from all processors on the pinned pages +// described by region and block_thrashing->pinned pages. +NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); + #endif diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index 34ac47ccf..cca6e52b9 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -173,9 +173,6 @@ #include "uvm_test.h" #include "uvm_linux.h" - - - static int uvm_global_oversubscription = 1; module_param(uvm_global_oversubscription, int, S_IRUGO); MODULE_PARM_DESC(uvm_global_oversubscription, "Enable (1) or disable (0) global oversubscription support."); @@ -245,21 +242,11 @@ const char *uvm_pmm_gpu_memory_type_string(uvm_pmm_gpu_memory_type_t type) { switch (type) { UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_USER); - - - UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_KERNEL); - - - UVM_ENUM_STRING_DEFAULT(); } - - - BUILD_BUG_ON(UVM_PMM_GPU_MEMORY_TYPE_COUNT != 2); - } const char *uvm_pmm_gpu_chunk_state_string(uvm_pmm_gpu_chunk_state_t state) @@ -461,31 +448,13 @@ bool uvm_pmm_gpu_memory_type_is_user(uvm_pmm_gpu_memory_type_t type) UVM_ASSERT(type < UVM_PMM_GPU_MEMORY_TYPE_COUNT); switch (type) { - - - - case UVM_PMM_GPU_MEMORY_TYPE_USER: - return true; default: return false; } } - - - - - - - - - - - - - static void uvm_gpu_chunk_set_in_eviction(uvm_gpu_chunk_t *chunk, bool in_eviction) { UVM_ASSERT(uvm_pmm_gpu_memory_type_is_user(chunk->type)); @@ -545,20 +514,7 @@ void uvm_pmm_gpu_sync(uvm_pmm_gpu_t *pmm) static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { - - - - - - - - - - - - return type; - } NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, @@ -647,10 +603,6 @@ NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, size_t i; uvm_pmm_gpu_memory_type_t memory_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL; - - - - status = uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); if (status != NV_OK) return status; @@ -1715,11 +1667,6 @@ void uvm_pmm_gpu_mark_root_chunk_unused(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chu root_chunk_update_eviction_list(pmm, chunk, &pmm->root_chunks.va_block_unused); } - - - - - static uvm_gpu_root_chunk_t *pick_root_chunk_to_evict(uvm_pmm_gpu_t *pmm) { uvm_gpu_chunk_t *chunk; @@ -2192,13 +2139,6 @@ NV_STATUS alloc_root_chunk(uvm_pmm_gpu_t *pmm, if (gpu->parent->numa_info.enabled) flags |= UVM_PMM_ALLOC_FLAGS_DONT_BATCH; - - - - - - - if (!gpu->parent->rm_info.isSimulated && !(options.flags & UVM_PMA_ALLOCATE_PINNED) && !(flags & UVM_PMM_ALLOC_FLAGS_DONT_BATCH)) { @@ -2449,14 +2389,6 @@ static bool check_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) UVM_ASSERT(uvm_global_id_equal(uvm_global_gpu_id_from_index(chunk->gpu_global_index), gpu->global_id)); - - - - - - - - if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) UVM_ASSERT(chunk_size > uvm_chunk_find_first_size(chunk_sizes)); @@ -2766,13 +2698,6 @@ static bool uvm_pmm_should_inject_pma_eviction_error(uvm_pmm_gpu_t *pmm) return false; } - - - - - - - // See the documentation of pmaEvictPagesCb_t in pma.h for details of the // expected semantics. static NV_STATUS uvm_pmm_gpu_pma_evict_pages(void *void_pmm, @@ -3312,16 +3237,8 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); const uvm_chunk_sizes_mask_t chunk_size_init[][UVM_PMM_GPU_MEMORY_TYPE_COUNT] = { - - - - - - - { gpu->parent->mmu_user_chunk_sizes, gpu->parent->mmu_kernel_chunk_sizes }, { 0, uvm_mem_kernel_chunk_sizes(gpu)}, - }; NV_STATUS status = NV_OK; size_t i, j, k; diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h index ee254e292..b48314d66 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h @@ -95,22 +95,9 @@ typedef enum // Memory type for backing user pages. On Pascal+ it can be evicted. UVM_PMM_GPU_MEMORY_TYPE_USER, - - - - - - - // Memory type for internal UVM allocations. It cannot be evicted. UVM_PMM_GPU_MEMORY_TYPE_KERNEL, - - - - - - // Number of types - MUST BE LAST. UVM_PMM_GPU_MEMORY_TYPE_COUNT } uvm_pmm_gpu_memory_type_t; @@ -447,10 +434,6 @@ NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, // // Internally calls uvm_pmm_gpu_alloc() and sets the state of all chunks to // allocated on success. - - - - NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, @@ -466,11 +449,6 @@ NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, // If the memory returned by the PMM allocator cannot be physically addressed, // the MMU interface provides user chunk mapping and unmapping functions // (uvm_mmu_chunk_map/unmap) that enable virtual addressing. - - - - - static NV_STATUS uvm_pmm_gpu_alloc_user(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, diff --git a/kernel-open/nvidia-uvm/uvm_pmm_test.c b/kernel-open/nvidia-uvm/uvm_pmm_test.c index 0fc76e1b1..4f3bb2e4f 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_test.c @@ -101,24 +101,6 @@ typedef enum static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { - - - - - - - - - - - - - - - - - - return type; } @@ -324,14 +306,6 @@ static NV_STATUS gpu_mem_check(uvm_gpu_t *gpu, NvU32 *verif_cpu_addr = uvm_mem_get_cpu_addr_kernel(verif_mem); size_t i; - - - - - - - - UVM_ASSERT(verif_mem->size >= size); memset(verif_cpu_addr, 0, size); @@ -537,11 +511,7 @@ static NV_STATUS basic_test(uvm_va_space_t *va_space, uvm_gpu_t *gpu, if (mode == UvmTestPmmSanityModeBasic) { first_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; - - - last_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; - first_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; last_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; } @@ -897,10 +867,6 @@ NV_STATUS uvm_test_pmm_check_leak(UVM_TEST_PMM_CHECK_LEAK_PARAMS *params, struct uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; - - - - if (params->alloc_limit < -1) return NV_ERR_INVALID_ARGUMENT; @@ -1036,10 +1002,6 @@ NV_STATUS uvm_test_pmm_async_alloc(UVM_TEST_PMM_ASYNC_ALLOC_PARAMS *params, stru uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; - - - - uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu) { @@ -1237,9 +1199,7 @@ static NV_STATUS test_indirect_peers(uvm_gpu_t *owning_gpu, uvm_gpu_t *accessing if (!chunks) return NV_ERR_NO_MEMORY; - - - + UVM_ASSERT(!g_uvm_global.sev_enabled); TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_CHUNK_SIZE_MAX, current->mm, &verif_mem), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, owning_gpu), out); diff --git a/kernel-open/nvidia-uvm/uvm_push.c b/kernel-open/nvidia-uvm/uvm_push.c index 423b6175d..1762cba84 100644 --- a/kernel-open/nvidia-uvm/uvm_push.c +++ b/kernel-open/nvidia-uvm/uvm_push.c @@ -259,7 +259,7 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, va_list args; NV_STATUS status; - status = uvm_channel_reserve(channel); + status = uvm_channel_reserve(channel, 1); if (status != NV_OK) return status; @@ -270,6 +270,25 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, return status; } +__attribute__ ((format(printf, 7, 8))) +NV_STATUS __uvm_push_begin_acquire_on_reserved_channel_with_info(uvm_channel_t *channel, + uvm_tracker_t *tracker, + uvm_push_t *push, + const char *filename, + const char *function, + int line, + const char *format, ...) +{ + va_list args; + NV_STATUS status; + + va_start(args, format); + status = push_begin_acquire_with_info(channel, tracker, push, filename, function, line, format, args); + va_end(args); + + return status; +} + bool uvm_push_info_is_tracking_descriptions() { return uvm_debug_enable_push_desc != 0; @@ -422,10 +441,6 @@ NvU64 *uvm_push_timestamp(uvm_push_t *push) if (uvm_channel_is_ce(push->channel)) gpu->parent->ce_hal->semaphore_timestamp(push, address.address); - - - - else UVM_ASSERT_MSG(0, "Semaphore release timestamp on an unsupported channel.\n"); diff --git a/kernel-open/nvidia-uvm/uvm_push.h b/kernel-open/nvidia-uvm/uvm_push.h index 931006e64..0cd72752a 100644 --- a/kernel-open/nvidia-uvm/uvm_push.h +++ b/kernel-open/nvidia-uvm/uvm_push.h @@ -35,10 +35,6 @@ // This is the storage required by a semaphore release. #define UVM_PUSH_CE_END_SIZE 24 - - - - // The max amount of inline push data is limited by how much space can be jumped // over with a single NOOP method. #define UVM_PUSH_INLINE_DATA_MAX_SIZE (UVM_METHOD_COUNT_MAX * UVM_METHOD_SIZE) @@ -200,6 +196,15 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, int line, const char *format, ...); +// Internal helper for uvm_push_begin_on_reserved channel +__attribute__ ((format(printf, 7, 8))) +NV_STATUS __uvm_push_begin_acquire_on_reserved_channel_with_info(uvm_channel_t *channel, + uvm_tracker_t *tracker, + uvm_push_t *push, + const char *filename, + const char *function, + int line, + const char *format, ...); // Begin a push on a channel of channel_type type // Picks the first available channel. If all channels of the given type are // busy, spin waits for one to become available. @@ -207,20 +212,22 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, // Notably requires a description of the push to be provided. This is currently // unused, but will be in the future for tracking push history. // -// Locking: on success acquires the concurrent push semaphore until uvm_push_end() +// Locking: on success acquires the concurrent push semaphore until +// uvm_push_end() #define uvm_push_begin(manager, type, push, format, ...) \ __uvm_push_begin_acquire_with_info((manager), (type), NULL, NULL, (push), \ __FILE__, __FUNCTION__, __LINE__, (format), ##__VA_ARGS__) -// Begin a push on a channel of channel_type type with dependencies in the tracker -// This is equivalent to starting a push and acquiring the tracker, but in the -// future it will have the ability to pick the channel to do a push on in a -// smarter way based on its dependencies. +// Begin a push on a channel of channel_type type with dependencies in the +// tracker. This is equivalent to starting a push and acquiring the tracker, but +// in the future it will have the ability to pick the channel to do a push on in +// a smarter way based on its dependencies. // // Same as for uvm_push_acquire_tracker(), the tracker can be NULL. In this case // this will be equivalent to just uvm_push_begin(). // -// Locking: on success acquires the concurrent push semaphore until uvm_push_end() +// Locking: on success acquires the concurrent push semaphore until +// uvm_push_end() #define uvm_push_begin_acquire(manager, type, tracker, push, format, ...) \ __uvm_push_begin_acquire_with_info((manager), (type), NULL, (tracker), (push), \ __FILE__, __FUNCTION__, __LINE__, (format), ##__VA_ARGS__) @@ -241,11 +248,20 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, // Begin a push on a specific channel // If the channel is busy, spin wait for it to become available. // -// Locking: on success acquires the concurrent push semaphore until uvm_push_end() +// Locking: on success acquires the concurrent push semaphore until +// uvm_push_end() #define uvm_push_begin_on_channel(channel, push, format, ...) \ __uvm_push_begin_acquire_on_channel_with_info((channel), NULL, (push), \ __FILE__, __FUNCTION__, __LINE__, (format), ##__VA_ARGS__) +// Begin a push on a specific pre-reserved channel +// +// Locking: on success acquires the concurrent push semaphore until +// uvm_push_end() +#define uvm_push_begin_on_reserved_channel(channel, push, format, ...) \ + __uvm_push_begin_acquire_on_reserved_channel_with_info((channel), NULL, (push), \ + __FILE__, __FUNCTION__, __LINE__, (format), ##__VA_ARGS__) + // Same as uvm_push_begin_on_channel except it also acquires the input tracker // for the caller #define uvm_push_begin_acquire_on_channel(channel, tracker, push, format, ...) \ diff --git a/kernel-open/nvidia-uvm/uvm_push_macros.h b/kernel-open/nvidia-uvm/uvm_push_macros.h index 5f07a4c8a..4c6aae4aa 100644 --- a/kernel-open/nvidia-uvm/uvm_push_macros.h +++ b/kernel-open/nvidia-uvm/uvm_push_macros.h @@ -97,21 +97,14 @@ #define UVM_SUBCHANNEL_C56F UVM_SUBCHANNEL_HOST #define UVM_SUBCHANNEL_C6B5 UVM_SUBCHANNEL_CE - - - - +#define UVM_SUBCHANNEL_C86F UVM_SUBCHANNEL_HOST +#define UVM_SUBCHANNEL_C8B5 UVM_SUBCHANNEL_CE // Channel for UVM SW methods. This is defined in nv_uvm_types.h. RM does not // care about the specific number as long as it's bigger than the largest HW // value. For example, Kepler reserves subchannels 5-7 for software objects. #define UVM_SUBCHANNEL_C076 UVM_SW_OBJ_SUBCHANNEL - - - - - #define UVM_METHOD_SIZE 4 #define UVM_METHOD_COUNT_MAX HWMASK(B06F, DMA, INCR_COUNT) #if HWMASK(B06F, DMA, INCR_COUNT) != HWMASK(B06F, DMA, NONINCR_COUNT) diff --git a/kernel-open/nvidia-uvm/uvm_push_test.c b/kernel-open/nvidia-uvm/uvm_push_test.c index ed5a5d823..22a1953a9 100644 --- a/kernel-open/nvidia-uvm/uvm_push_test.c +++ b/kernel-open/nvidia-uvm/uvm_push_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -43,16 +43,9 @@ static NvU32 get_push_end_size(uvm_channel_t *channel) if (uvm_channel_is_ce(channel)) return UVM_PUSH_CE_END_SIZE; - - - - return 0; } - - - static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) { NV_STATUS status = NV_OK; @@ -66,10 +59,6 @@ static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) NvU32 push_end_size; uvm_channel_type_t type = i; - - - - status = uvm_push_begin(gpu->channel_manager, type, &push, "type %u\n", (unsigned)type); TEST_CHECK_GOTO(status == NV_OK, done); @@ -302,7 +291,7 @@ static NV_STATUS test_push_interleaving_on_gpu(uvm_gpu_t* gpu) // single thread. uvm_thread_context_lock_disable_tracking(); - status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, &mem); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); host_va = (NvU32*)uvm_rm_mem_get_cpu_va(mem); gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(channel)); @@ -559,10 +548,6 @@ static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_cha static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) { - - - - TEST_NV_CHECK_RET(test_max_pushes_on_gpu_and_channel_type(gpu, UVM_CHANNEL_TYPE_GPU_INTERNAL)); return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.c b/kernel-open/nvidia-uvm/uvm_pushbuffer.c index 324eef737..c48a3d6aa 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.c +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -80,6 +80,7 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push NV_STATUS status; int i; uvm_gpu_t *gpu = channel_manager->gpu; + NvU64 pushbuffer_alignment; uvm_pushbuffer_t *pushbuffer = uvm_kvmalloc_zero(sizeof(*pushbuffer)); if (pushbuffer == NULL) @@ -96,15 +97,32 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push UVM_ASSERT(channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS || channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_VID); + // The pushbuffer allocation is aligned to UVM_PUSHBUFFER_SIZE and its size + // (UVM_PUSHBUFFER_SIZE) is a power of 2. These constraints guarantee that + // the entire pushbuffer belongs to a 1TB (2^40) segment. Thus, we can set + // the Esched/PBDMA segment base for all channels during their + // initialization and it is immutable for the entire channels' lifetime. + BUILD_BUG_ON_NOT_POWER_OF_2(UVM_PUSHBUFFER_SIZE); + BUILD_BUG_ON(UVM_PUSHBUFFER_SIZE >= (1ull << 40)); + + if (gpu->uvm_test_force_upper_pushbuffer_segment) + pushbuffer_alignment = (1ull << 40); + else + pushbuffer_alignment = UVM_PUSHBUFFER_SIZE; + status = uvm_rm_mem_alloc_and_map_cpu(gpu, - (channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS)? + (channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS) ? UVM_RM_MEM_TYPE_SYS: UVM_RM_MEM_TYPE_GPU, UVM_PUSHBUFFER_SIZE, + pushbuffer_alignment, &pushbuffer->memory); if (status != NV_OK) goto error; + // Verify the GPU can access the pushbuffer. + UVM_ASSERT(uvm_pushbuffer_get_gpu_va_base(pushbuffer) + UVM_PUSHBUFFER_SIZE < gpu->parent->max_host_va); + bitmap_fill(pushbuffer->idle_chunks, UVM_PUSHBUFFER_CHUNKS); bitmap_fill(pushbuffer->available_chunks, UVM_PUSHBUFFER_CHUNKS); @@ -375,10 +393,14 @@ static uvm_pushbuffer_chunk_t *gpfifo_to_chunk(uvm_pushbuffer_t *pushbuffer, uvm void uvm_pushbuffer_mark_completed(uvm_pushbuffer_t *pushbuffer, uvm_gpfifo_entry_t *gpfifo) { - uvm_pushbuffer_chunk_t *chunk = gpfifo_to_chunk(pushbuffer, gpfifo); + uvm_pushbuffer_chunk_t *chunk; uvm_push_info_t *push_info = gpfifo->push_info; bool need_to_update_chunk = false; + UVM_ASSERT(gpfifo->type == UVM_GPFIFO_ENTRY_TYPE_NORMAL); + + chunk = gpfifo_to_chunk(pushbuffer, gpfifo); + if (push_info->on_complete != NULL) push_info->on_complete(push_info->on_complete_data); @@ -486,3 +508,8 @@ void uvm_pushbuffer_print(uvm_pushbuffer_t *pushbuffer) { return uvm_pushbuffer_print_common(pushbuffer, NULL); } + +NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer) +{ + return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory, pushbuffer->channel_manager->gpu); +} diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.h b/kernel-open/nvidia-uvm/uvm_pushbuffer.h index f9b80aa3b..9b43fb672 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.h +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -236,4 +236,7 @@ bool uvm_pushbuffer_has_space(uvm_pushbuffer_t *pushbuffer); // Helper to print pushbuffer state for debugging void uvm_pushbuffer_print(uvm_pushbuffer_t *pushbuffer); +// Helper to retrieve the pushbuffer->memory GPU VA. +NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer); + #endif // __UVM_PUSHBUFFER_H__ diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.c b/kernel-open/nvidia-uvm/uvm_rm_mem.c index 25ab08fe5..5a6f424b7 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -179,11 +179,16 @@ static void rm_mem_unmap_gpu_proxy(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) rm_mem_clear_gpu_proxy_va(rm_mem, gpu); } -NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out) + +NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out) { NV_STATUS status = NV_OK; uvm_rm_mem_t *rm_mem; - UvmGpuAllocInfo alloc_info = {0}; + UvmGpuAllocInfo alloc_info = { 0 }; NvU64 gpu_va; UVM_ASSERT(gpu); @@ -194,12 +199,7 @@ NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size if (rm_mem == NULL) return NV_ERR_NO_MEMORY; - - - - - - + alloc_info.alignment = gpu_alignment; if (type == UVM_RM_MEM_TYPE_SYS) status = uvm_rm_locked_call(nvUvmInterfaceMemoryAllocSys(gpu->rm_address_space, size, &gpu_va, &alloc_info)); @@ -274,7 +274,7 @@ void uvm_rm_mem_unmap_cpu(uvm_rm_mem_t *rm_mem) rm_mem_clear_cpu_va(rm_mem); } -NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) +NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 gpu_alignment) { NV_STATUS status; uvm_gpu_t *gpu_owner; @@ -296,6 +296,7 @@ NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) status = uvm_rm_locked_call(nvUvmInterfaceDupAllocation(gpu_owner->rm_address_space, gpu_owner_va, gpu->rm_address_space, + gpu_alignment, &gpu_va)); if (status != NV_OK) { UVM_ERR_PRINT("nvUvmInterfaceDupAllocation() failed: %s, src GPU %s, dest GPU %s\n", @@ -374,12 +375,16 @@ void uvm_rm_mem_free(uvm_rm_mem_t *rm_mem) uvm_kvfree(rm_mem); } -NV_STATUS uvm_rm_mem_alloc_and_map_cpu(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out) +NV_STATUS uvm_rm_mem_alloc_and_map_cpu(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out) { uvm_rm_mem_t *rm_mem; NV_STATUS status; - status = uvm_rm_mem_alloc(gpu, type, size, &rm_mem); + status = uvm_rm_mem_alloc(gpu, type, size, gpu_alignment, &rm_mem); if (status != NV_OK) return status; @@ -396,32 +401,36 @@ NV_STATUS uvm_rm_mem_alloc_and_map_cpu(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, N return status; } -NV_STATUS uvm_rm_mem_map_all_gpus(uvm_rm_mem_t *rm_mem) +NV_STATUS uvm_rm_mem_map_all_gpus(uvm_rm_mem_t *rm_mem, NvU64 gpu_alignment) { uvm_gpu_t *gpu; UVM_ASSERT(rm_mem); for_each_global_gpu(gpu) { - NV_STATUS status = uvm_rm_mem_map_gpu(rm_mem, gpu); + NV_STATUS status = uvm_rm_mem_map_gpu(rm_mem, gpu, gpu_alignment); if (status != NV_OK) return status; } return NV_OK; } -NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out) +NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out) { uvm_rm_mem_t *rm_mem; NV_STATUS status; UVM_ASSERT(gpu); - status = uvm_rm_mem_alloc_and_map_cpu(gpu, type, size, &rm_mem); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, type, size, gpu_alignment, &rm_mem); if (status != NV_OK) return status; - status = uvm_rm_mem_map_all_gpus(rm_mem); + status = uvm_rm_mem_map_all_gpus(rm_mem, gpu_alignment); if (status != NV_OK) goto error; diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.h b/kernel-open/nvidia-uvm/uvm_rm_mem.h index a83801453..43e0f0e13 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -71,11 +71,18 @@ struct uvm_rm_mem_struct // mapping created and removed dynamically with the uvm_rm_mem_(un)map_gpu() // functions. // +// Alignment affects only the GPU VA mapping. If gpu_alignment is 0, then 4K +// alignment is enforced. +// // Locking: // - Internally acquires: // - RM API lock // - RM GPUs lock -NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out); +NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out); // Free the memory. // Clear all mappings and free the memory @@ -89,16 +96,26 @@ NV_STATUS uvm_rm_mem_map_cpu(uvm_rm_mem_t *rm_mem); void uvm_rm_mem_unmap_cpu(uvm_rm_mem_t *rm_mem); // Shortcut for uvm_rm_mem_alloc() + uvm_rm_mem_map_cpu(). -// The function fails and nothing is allocated if any of the intermediate steps fail. +// The function fails and nothing is allocated if any of the intermediate steps +// fail. // // Locking same as uvm_rm_mem_alloc() -NV_STATUS uvm_rm_mem_alloc_and_map_cpu(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out); +NV_STATUS uvm_rm_mem_alloc_and_map_cpu(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out); // Shortcut for uvm_rm_mem_alloc_and_map_cpu() + uvm_rm_mem_map_all_gpus() -// The function fails and nothing is allocated if any of the intermediate steps fail. +// The function fails and nothing is allocated if any of the intermediate steps +// fail. // // Locking same as uvm_rm_mem_alloc() -NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, NvLength size, uvm_rm_mem_t **rm_mem_out); +NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, + uvm_rm_mem_type_t type, + NvLength size, + NvU64 gpu_alignment, + uvm_rm_mem_t **rm_mem_out); // Map/Unmap on UVM's internal address space of a GPU. In SR-IOV heavy the // operation is also applied on the GPU's proxy address space. @@ -107,7 +124,7 @@ NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, uvm_rm_mem_type_t type, N // from the one the memory was originally allocated for. // // Locking same as uvm_rm_mem_alloc() -NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu); +NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 gpu_alignment); void uvm_rm_mem_unmap_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu); // Map on UVM's internal address space of all GPUs retained by the UVM driver @@ -115,7 +132,7 @@ void uvm_rm_mem_unmap_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu); // also mapped on the proxy address space of all GPUs. // // Locking same as uvm_rm_mem_alloc() -NV_STATUS uvm_rm_mem_map_all_gpus(uvm_rm_mem_t *rm_mem); +NV_STATUS uvm_rm_mem_map_all_gpus(uvm_rm_mem_t *rm_mem, NvU64 gpu_alignment); // Get the CPU VA, GPU VA (UVM internal/kernel address space), or GPU (proxy // address space) @@ -125,7 +142,9 @@ NvU64 uvm_rm_mem_get_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu); // Get the GPU VA of the given memory in UVM's internal address space (if the // flag is false), or proxy address space (if flag is true). -NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space); +NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, + uvm_gpu_t *gpu, + bool is_proxy_va_space); // Query if the memory is mapped on the CPU, GPU (UVM internal/kernel address // space), or GPU (proxy address space) diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c index 252a75474..3356be4a8 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -40,6 +40,7 @@ static NV_STATUS map_cpu(uvm_rm_mem_t *rm_mem) // Unmap uvm_rm_mem_unmap_cpu(rm_mem); + // Unmapping already unmapped also OK uvm_rm_mem_unmap_cpu(rm_mem); @@ -59,9 +60,10 @@ static NV_STATUS map_cpu(uvm_rm_mem_t *rm_mem) return NV_OK; } -static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem) +static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) { uvm_gpu_t *gpu = rm_mem->gpu_owner; + NvU64 gpu_va; // The memory should have been automatically mapped in the GPU owner TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); @@ -71,26 +73,31 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem) // located in vidmem. TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + if (alignment) + TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + // Explicitly mapping or unmapping to the GPU that owns the allocation is // not allowed, so the testing related to GPU owners is simpler than that of // other GPUs. return NV_OK; } -static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space) +static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space, NvU64 alignment) { uvm_gpu_t *gpu_owner = rm_mem->gpu_owner; uvm_gpu_t *gpu; + NvU64 gpu_va; for_each_va_space_gpu(gpu, va_space) { if (gpu == gpu_owner) continue; - TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu)); + TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); // Mappings are not ref counted, so additional map calls are no-ops - TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu)); + TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); // The previous GPU map calls added mappings to the proxy VA space // when in SR-IOV heavy mode @@ -107,10 +114,14 @@ static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space) TEST_CHECK_RET(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); // Subsequent mappings should behave as they did in the beginning. - TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu)); + TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + + gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + if (alignment) + TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); } return NV_OK; @@ -124,33 +135,45 @@ static NV_STATUS test_all_gpus_in_va(uvm_va_space_t *va_space) // Create allocations of these types static const uvm_rm_mem_type_t mem_types[] = { UVM_RM_MEM_TYPE_SYS, UVM_RM_MEM_TYPE_GPU }; + // Create allocations of these sizes - static const size_t sizes[] = {1, 4, 16, 128, 1024, 4096, 1024 * 1024, 4 * 1024 * 1024}; + static const size_t sizes[] = { 1, 4, 16, 128, 1024, 4096, 1024 * 1024, 4 * 1024 * 1024 }; + static const NvU64 alignments[] = { 0, + 8, + UVM_PAGE_SIZE_4K >> 1, + UVM_PAGE_SIZE_4K, + UVM_PAGE_SIZE_4K << 1, + UVM_PAGE_SIZE_64K, + UVM_PAGE_SIZE_2M, + UVM_PAGE_SIZE_2M << 3, + UVM_PAGE_SIZE_2M << 5 }; uvm_assert_rwsem_locked(&va_space->lock); TEST_CHECK_RET(!uvm_processor_mask_empty(&va_space->registered_gpus)); for_each_va_space_gpu(gpu, va_space) { - int i, j; + int i, j, k; for (i = 0; i < ARRAY_SIZE(sizes); ++i) { for (j = 0; j < ARRAY_SIZE(mem_types); ++j) { + for (k = 0; k < ARRAY_SIZE(alignments); ++k) { - // Create an allocation in the GPU's address space - TEST_NV_CHECK_RET(uvm_rm_mem_alloc(gpu, mem_types[j], sizes[i], &rm_mem)); + // Create an allocation in the GPU's address space + TEST_NV_CHECK_RET(uvm_rm_mem_alloc(gpu, mem_types[j], sizes[i], alignments[k], &rm_mem)); - // Test CPU mappings - TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); + // Test CPU mappings + TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); - // Test mappings in the GPU owning the allocation - TEST_NV_CHECK_GOTO(map_gpu_owner(rm_mem), error); + // Test mappings in the GPU owning the allocation + TEST_NV_CHECK_GOTO(map_gpu_owner(rm_mem, alignments[k]), error); - // For sysmem allocations, test mappings on all other GPUs - if (rm_mem->type == UVM_RM_MEM_TYPE_SYS) - TEST_NV_CHECK_GOTO(map_other_gpus(rm_mem, va_space), error); + // For sysmem allocations, test mappings on all other GPUs + if (rm_mem->type == UVM_RM_MEM_TYPE_SYS) + TEST_NV_CHECK_GOTO(map_other_gpus(rm_mem, va_space, alignments[k]), error); - uvm_rm_mem_free(rm_mem); + uvm_rm_mem_free(rm_mem); + } } } } diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index a738a1e34..2b71594fa 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -327,9 +327,6 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_RANGE_INJECT_ADD_GPU_VA_SPACE_ERROR, uvm_test_va_range_inject_add_gpu_va_space_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY, uvm_test_destroy_gpu_va_space_delay); - - - UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); } diff --git a/kernel-open/nvidia-uvm/uvm_test.h b/kernel-open/nvidia-uvm/uvm_test.h index 8b7b56a1b..f79a52f5d 100644 --- a/kernel-open/nvidia-uvm/uvm_test.h +++ b/kernel-open/nvidia-uvm/uvm_test.h @@ -188,7 +188,4 @@ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_B NV_STATUS uvm_test_rb_tree_directed(UVM_TEST_RB_TREE_DIRECTED_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_random(UVM_TEST_RB_TREE_RANDOM_PARAMS *params, struct file *filp); NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *filp); - - - #endif diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index be3925a25..b127aa8f2 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -1390,14 +1390,6 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY_PARAMS; - - - - - - - - #define UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED UVM_TEST_IOCTL_BASE(96) typedef struct { diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.c b/kernel-open/nvidia-uvm/uvm_user_channel.c index a2234f256..a6fbcefc9 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.c +++ b/kernel-open/nvidia-uvm/uvm_user_channel.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -168,10 +168,9 @@ static NV_STATUS uvm_user_channel_create(uvm_va_space_t *va_space, user_channel->tsg.valid = channel_info->bTsgChannel == NV_TRUE; user_channel->tsg.id = channel_info->tsgId; user_channel->tsg.max_subctx_count = channel_info->tsgMaxSubctxCount; - user_channel->work_submission_token = channel_info->workSubmissionToken; - user_channel->work_submission_offset = channel_info->workSubmissionOffset; user_channel->clear_faulted_token = channel_info->clearFaultedToken; user_channel->chram_channel_register = channel_info->pChramChannelRegister; + user_channel->runlist_pri_base_register = channel_info->pRunlistPRIBaseRegister; user_channel->smc_engine_id = channel_info->smcEngineId; user_channel->smc_engine_ve_id_offset = channel_info->smcEngineVeIdOffset; diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.h b/kernel-open/nvidia-uvm/uvm_user_channel.h index 214140fe3..76f8175b4 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.h +++ b/kernel-open/nvidia-uvm/uvm_user_channel.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -98,17 +98,11 @@ struct uvm_user_channel_struct // If valid is true, tsg_id contains the ID of the TSG NvU32 id; - // If valid is true, this is the maximum number of subcontexts in the TSG + // If valid is true, this is the maximum number of subcontexts in the + // TSG NvU32 max_subctx_count; } tsg; - // This is the value that needs to be used when ringing the channel's - // doorbell - NvU32 work_submission_token; - - // This is the address of the channel's doorbell - volatile NvU32 *work_submission_offset; - // On Turing+, the CLEAR_FAULTED method requires passing a RM-provided // handle to identify the channel. NvU32 clear_faulted_token; @@ -117,9 +111,11 @@ struct uvm_user_channel_struct // channel removal uvm_tracker_t clear_faulted_tracker; - // Address of the NV_CHRAM_CHANNEL register. Only valid on GPUs with - // non_replayable_faults_supported && !has_clear_faulted_channel_method + // Address of the NV_CHRAM_CHANNEL register and the runlist PRI base + // register. Only valid on GPUs with + // non_replayable_faults_supported && !has_clear_faulted_channel_method. volatile NvU32 *chram_channel_register; + volatile NvU32 *runlist_pri_base_register; // Id of the SMC engine this channel is bound to, or zero if the GPU // does not support SMC or it is a CE channel diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index 6aa0c5e1d..f549b5289 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -40,9 +40,6 @@ #include "uvm_va_space_mm.h" #include "uvm_test_ioctl.h" - - - typedef enum { BLOCK_PTE_OP_MAP, @@ -584,7 +581,6 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, { uvm_va_block_t *block = NULL; NvU64 size = end - start + 1; - NV_STATUS status; UVM_ASSERT(PAGE_ALIGNED(start)); UVM_ASSERT(PAGE_ALIGNED(end + 1)); @@ -612,10 +608,8 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, block = nv_kmem_cache_zalloc(g_uvm_va_block_cache, NV_UVM_GFP_FLAGS); } - if (!block) { - status = NV_ERR_NO_MEMORY; - goto error; - } + if (!block) + return NV_ERR_NO_MEMORY; nv_kref_init(&block->kref); uvm_mutex_init(&block->lock, UVM_LOCK_ORDER_VA_BLOCK); @@ -628,10 +622,6 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, *out_block = block; return NV_OK; - -error: - uvm_va_block_release(block); - return status; } static void block_gpu_unmap_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) @@ -2584,10 +2574,6 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - - - - copying_gpu->parent->ce_hal->memcopy(&push, dst_address, src_address, contig_region_size); } @@ -6883,8 +6869,11 @@ static void block_destroy_gpu_state(uvm_va_block_t *block, uvm_gpu_id_t id) // Unmap PTEs and free page tables gpu = uvm_va_space_get_gpu(va_space, id); gpu_va_space = uvm_gpu_va_space_get(va_space, gpu); - if (gpu_va_space) - uvm_va_block_remove_gpu_va_space(block, gpu_va_space, NULL); + if (gpu_va_space) { + uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, NULL); + + uvm_va_block_remove_gpu_va_space(block, gpu_va_space, block_context); + } UVM_ASSERT(!uvm_processor_mask_test(&block->mapped, id)); @@ -6962,10 +6951,10 @@ NV_STATUS uvm_va_block_add_gpu_va_space(uvm_va_block_t *va_block, uvm_gpu_va_spa return block_pre_populate_pde1_gpu(va_block, gpu_va_space, NULL); } -void uvm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, uvm_gpu_va_space_t *gpu_va_space, struct mm_struct *mm) +void uvm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_context_t *block_context) { - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, mm); uvm_pte_batch_t *pte_batch = &block_context->mapping.pte_batch; uvm_tlb_batch_t *tlb_batch = &block_context->mapping.tlb_batch; uvm_gpu_t *gpu = gpu_va_space->gpu; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index 3ea0e992d..e5858d920 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -440,11 +440,9 @@ struct uvm_va_block_struct #if UVM_IS_CONFIG_HMM() struct { - // The MMU notifier is registered per va_block. struct mmu_interval_notifier notifier; - // Parent VA space pointer. It is NULL for UVM managed blocks or if // the HMM block is dead. This field can be read while holding the // block lock and is only modified while holding the va_space write @@ -551,6 +549,11 @@ static inline void uvm_va_block_retain(uvm_va_block_t *va_block) nv_kref_get(&va_block->kref); } +// Locking: The va_block lock must not be held. +// The va_space lock must be held in write mode unless it is the special case +// that the block has no GPU state; for example, right after calling +// uvm_va_block_create(). In that case, the va_space lock can be held in read +// mode. static inline void uvm_va_block_release(uvm_va_block_t *va_block) { if (va_block) { @@ -986,9 +989,11 @@ NV_STATUS uvm_va_block_add_gpu_va_space(uvm_va_block_t *va_block, uvm_gpu_va_spa // If mm != NULL, that mm is used for any CPU mappings which may be created as // a result of this call. See uvm_va_block_context_t::mm for details. // -// LOCKING: The caller must hold the va_block lock. If mm != NULL, the caller -// must hold mm->mmap_lock in at least read mode. -void uvm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, uvm_gpu_va_space_t *gpu_va_space, struct mm_struct *mm); +// LOCKING: The caller must hold the va_block lock. If block_context->mm is not +// NULL, the caller must hold mm->mmap_lock in at least read mode. +void uvm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_context_t *block_context); // Creates any mappings necessary in this VA block between the two GPUs, in // either direction. diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index d83862d66..bda9a3062 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -254,7 +254,6 @@ typedef struct uvm_va_policy_t *policy; - #if UVM_IS_CONFIG_HMM() struct { @@ -263,7 +262,6 @@ typedef struct } hmm; #endif - // Convenience buffer for page mask prints char page_mask_string_buffer[UVM_PAGE_MASK_PRINT_MIN_BUFFER_SIZE]; } uvm_va_block_context_t; diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.c b/kernel-open/nvidia-uvm/uvm_va_policy.c index 770a9c06b..fd4e67b04 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.c +++ b/kernel-open/nvidia-uvm/uvm_va_policy.c @@ -172,6 +172,102 @@ uvm_va_policy_node_t *uvm_va_policy_node_iter_next(uvm_va_block_t *va_block, return uvm_va_policy_node_container(tree_node); } +uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region) +{ + uvm_range_tree_node_t *tree_node; + uvm_va_policy_node_t *node; + uvm_va_policy_t *policy; + uvm_va_block_region_t region; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(start >= va_block->start); + UVM_ASSERT(end <= va_block->end); + UVM_ASSERT(start < end); + + region.first = uvm_va_block_cpu_page_index(va_block, start); + + // Even if no policy is found, we return the default policy and loop + // one time. + tree_node = uvm_range_tree_iter_first(&va_block->hmm.va_policy_tree, start, end); + if (tree_node) { + node = uvm_va_policy_node_container(tree_node); + if (node->node.start <= start) { + policy = &node->policy; + region.outer = uvm_va_block_cpu_page_index(va_block, min(end, node->node.end)) + 1; + } + else { + // This node starts after the requested start so use the default, + // then use this policy node. + policy = &uvm_va_policy_default; + region.outer = uvm_va_block_cpu_page_index(va_block, node->node.start - 1) + 1; + } + } + else { + node = NULL; + policy = &uvm_va_policy_default; + region.outer = uvm_va_block_cpu_page_index(va_block, end) + 1; + } + + *out_node = node; + *out_region = region; + return policy; +} + +uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region) +{ + uvm_va_policy_node_t *node = *inout_node; + uvm_va_policy_node_t *next; + uvm_va_block_region_t region; + + if (!node) + return NULL; + + next = uvm_va_policy_node_iter_next(va_block, node, end); + + if (policy == &uvm_va_policy_default) { + // We haven't used the current policy node yet so use it now. + next = node; + policy = &node->policy; + region = uvm_va_block_region_from_start_end(va_block, + node->node.start, + min(end, node->node.end)); + } + else if (!next) { + if (node->node.end >= end) + return NULL; + policy = &uvm_va_policy_default; + region.first = inout_region->outer; + region.outer = uvm_va_block_cpu_page_index(va_block, end) + 1; + } + else { + region.first = inout_region->outer; + + if (next->node.start <= uvm_va_block_region_start(va_block, region)) { + policy = &next->policy; + region.outer = uvm_va_block_cpu_page_index(va_block, min(end, next->node.end)) + 1; + } + else { + // There is a gap between the last node and next so use the + // default policy. + policy = &uvm_va_policy_default; + region.outer = uvm_va_block_cpu_page_index(va_block, next->node.start - 1) + 1; + } + } + + *inout_node = next; + *inout_region = region; + return policy; +} + NV_STATUS uvm_va_policy_node_split(uvm_va_block_t *va_block, uvm_va_policy_node_t *old, NvU64 new_end, diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index b9e84cf3e..2d3159980 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -28,6 +28,7 @@ #include "uvm_forward_decl.h" #include "uvm_processors.h" #include "uvm_range_tree.h" +#include "uvm_va_block_types.h" // This enum must be kept in sync with UVM_TEST_READ_DUPLICATION_POLICY in // uvm_test_ioctl.h @@ -168,6 +169,31 @@ uvm_va_policy_node_t *uvm_va_policy_node_iter_next(uvm_va_block_t *va_block, uvm (node); \ (node) = (next)) +// Returns the first policy in the range [start, end], if any. +// Locking: The va_block lock must be held. +uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region); + +// Returns the next VA policy following the provided policy in address order, +// if that policy's start <= the provided end. +// Locking: The va_block lock must be held. +uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region); + +// Note that policy and region are set and usable in the loop body. +// The 'node' variable is used to retain loop state and 'policy' doesn't +// necessarily match &node->policy. +#define uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) \ + for ((policy) = uvm_va_policy_iter_first((va_block), (start), (end), &(node), &(region)); \ + (policy); \ + (policy) = uvm_va_policy_iter_next((va_block), (policy), (end), &(node), &(region))) + #else // UVM_IS_CONFIG_HMM() static NV_STATUS uvm_va_policy_init(void) diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index be000f7e7..f585aa2dc 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -30,9 +30,6 @@ #include "uvm_kvmalloc.h" #include "uvm_map_external.h" #include "uvm_perf_thrashing.h" - - - #include "nv_uvm_interface.h" static struct kmem_cache *g_uvm_va_range_cache __read_mostly; @@ -378,10 +375,8 @@ NV_STATUS uvm_va_range_create_semaphore_pool(uvm_va_space_t *va_space, if (status != NV_OK) goto error; - - - - + if (i == 0 && g_uvm_global.sev_enabled) + mem_alloc_params.dma_owner = gpu; if (attrs.is_cacheable) { // At most 1 GPU can have this memory cached, in which case it is @@ -702,7 +697,7 @@ static void va_range_remove_gpu_va_space_managed(uvm_va_range_t *va_range, for_each_va_block_in_va_range(va_range, va_block) { uvm_mutex_lock(&va_block->lock); - uvm_va_block_remove_gpu_va_space(va_block, gpu_va_space, mm); + uvm_va_block_remove_gpu_va_space(va_block, gpu_va_space, va_block_context); uvm_mutex_unlock(&va_block->lock); if (should_enable_read_duplicate) @@ -732,14 +727,7 @@ static void va_range_remove_gpu_va_space_semaphore_pool(uvm_va_range_t *va_range { UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_SEMAPHORE_POOL); - - - - - - uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); - } void uvm_va_range_remove_gpu_va_space(uvm_va_range_t *va_range, @@ -1896,10 +1884,8 @@ NV_STATUS uvm_api_alloc_semaphore_pool(UVM_ALLOC_SEMAPHORE_POOL_PARAMS *params, if (params->gpuAttributesCount > UVM_MAX_GPUS) return NV_ERR_INVALID_ARGUMENT; - - - - + if (g_uvm_global.sev_enabled && params->gpuAttributesCount == 0) + return NV_ERR_INVALID_ARGUMENT; // The mm needs to be locked in order to remove stale HMM va_blocks. mm = uvm_va_space_mm_retain_lock(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index c767003a6..72790c784 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -365,13 +365,6 @@ static void unregister_gpu(uvm_va_space_t *va_space, } } - - - - - - - va_space_check_processors_masks(va_space); } @@ -751,17 +744,6 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, goto done; } - - - - - - - - - - - uvm_processor_mask_set(&va_space->registered_gpus, gpu->id); va_space->registered_gpus_table[uvm_id_gpu_index(gpu->id)] = gpu; @@ -774,9 +756,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, // All GPUs have native atomics on their own memory processor_mask_array_set(va_space->has_native_atomics, gpu->id, gpu->id); - - - + // TODO: Bug 3252572: Support the new link type UVM_GPU_LINK_C2C if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_1) { processor_mask_array_set(va_space->has_nvlink, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_nvlink, UVM_ID_CPU, gpu->id); @@ -796,17 +776,11 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, processor_mask_array_set(va_space->can_access, gpu->id, gpu->id); processor_mask_array_set(va_space->accessible_from, gpu->id, gpu->id); - - - - - - - - // All GPUs have direct access to sysmem - processor_mask_array_set(va_space->can_access, gpu->id, UVM_ID_CPU); - processor_mask_array_set(va_space->accessible_from, UVM_ID_CPU, gpu->id); - + // All GPUs have direct access to sysmem, unless we're in SEV mode + if (!g_uvm_global.sev_enabled) { + processor_mask_array_set(va_space->can_access, gpu->id, UVM_ID_CPU); + processor_mask_array_set(va_space->accessible_from, UVM_ID_CPU, gpu->id); + } processor_mask_array_set(va_space->can_copy_from, gpu->id, gpu->id); processor_mask_array_set(va_space->can_copy_from, gpu->id, UVM_ID_CPU); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 92b680bc8..6ff843244 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -44,9 +44,6 @@ #include "uvm_ats.h" #include "uvm_va_space_mm.h" - - - // uvm_deferred_free_object provides a mechanism for building and later freeing // a list of objects which are owned by a VA space, but can't be freed while the // VA space lock is held. @@ -280,13 +277,6 @@ struct uvm_va_space_struct // stored in the VA space to avoid taking the global lock. uvm_cpu_gpu_affinity_t gpu_cpu_numa_affinity[UVM_ID_MAX_GPUS]; - - - - - - - // Array of GPU VA spaces uvm_gpu_va_space_t *gpu_va_spaces[UVM_ID_MAX_GPUS]; diff --git a/kernel-open/nvidia/nv-dma.c b/kernel-open/nvidia/nv-dma.c index 201d3b76e..8d66b6139 100644 --- a/kernel-open/nvidia/nv-dma.c +++ b/kernel-open/nvidia/nv-dma.c @@ -806,13 +806,14 @@ NV_STATUS NV_API_CALL nv_dma_map_peer ( nv_dma_device_t *dma_dev, nv_dma_device_t *peer_dma_dev, - NvU8 bar_index, + NvU8 nv_bar_index, NvU64 page_count, NvU64 *va ) { struct pci_dev *peer_pci_dev = to_pci_dev(peer_dma_dev->dev); struct resource *res; + NvU8 bar_index; NV_STATUS status; if (peer_pci_dev == NULL) @@ -822,7 +823,7 @@ NV_STATUS NV_API_CALL nv_dma_map_peer return NV_ERR_INVALID_REQUEST; } - BUG_ON(bar_index >= NV_GPU_NUM_BARS); + bar_index = nv_bar_index_to_os_bar_index(peer_pci_dev, nv_bar_index); res = &peer_pci_dev->resource[bar_index]; if (res->start == 0) { @@ -1089,187 +1090,6 @@ void NV_API_CALL nv_dma_release_sgt #endif /* NV_LINUX_DMA_BUF_H_PRESENT && NV_DRM_AVAILABLE && NV_DRM_DRM_GEM_H_PRESENT */ #if defined(NV_LINUX_DMA_BUF_H_PRESENT) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #endif /* NV_LINUX_DMA_BUF_H_PRESENT */ #ifndef IMPORT_DMABUF_FUNCTIONS_DEFINED diff --git a/kernel-open/nvidia/nv-dmabuf.c b/kernel-open/nvidia/nv-dmabuf.c index 84d3146a4..e28f37c3f 100644 --- a/kernel-open/nvidia/nv-dmabuf.c +++ b/kernel-open/nvidia/nv-dmabuf.c @@ -23,8 +23,6 @@ #include #include "nv-dmabuf.h" - - #if defined(CONFIG_DMA_SHARED_BUFFER) typedef struct nv_dma_buf_mem_handle { @@ -796,7 +794,6 @@ nv_dma_buf_reuse( return NV_ERR_OPERATING_SYSTEM; } - if (buf->ops != &nv_dma_buf_ops) { nv_printf(NV_DBG_ERRORS, "NVRM: Invalid dma-buf fd\n"); @@ -804,7 +801,6 @@ nv_dma_buf_reuse( goto cleanup_dmabuf; } - priv = buf->priv; if (priv == NULL) @@ -820,13 +816,8 @@ nv_dma_buf_reuse( goto cleanup_dmabuf; } - - - - if (params->index > (priv->total_objects - params->numObjects)) { - status = NV_ERR_INVALID_ARGUMENT; goto unlock_priv; } @@ -900,15 +891,3 @@ nv_dma_buf_export( #endif // CONFIG_DMA_SHARED_BUFFER } - - - - - - - - - - - - diff --git a/kernel-open/nvidia/nv-frontend.c b/kernel-open/nvidia/nv-frontend.c index 3aa684ef8..b3dedd6e6 100644 --- a/kernel-open/nvidia/nv-frontend.c +++ b/kernel-open/nvidia/nv-frontend.c @@ -27,11 +27,7 @@ #include "nv-frontend.h" #if defined(MODULE_LICENSE) - MODULE_LICENSE("Dual MIT/GPL"); - - - #endif #if defined(MODULE_INFO) MODULE_INFO(supported, "external"); @@ -50,14 +46,12 @@ MODULE_ALIAS_CHARDEV_MAJOR(NV_MAJOR_DEVICE_NUMBER); */ #if defined(MODULE_IMPORT_NS) - /* * DMA_BUF namespace is added by commit id 16b0314aa746 * ("dma-buf: move dma-buf symbols into the DMA_BUF module namespace") in 5.16 */ MODULE_IMPORT_NS(DMA_BUF); - #endif static NvU32 nv_num_instances; diff --git a/kernel-open/nvidia/nv-i2c.c b/kernel-open/nvidia/nv-i2c.c index f227d180e..0bfb18e9c 100644 --- a/kernel-open/nvidia/nv-i2c.c +++ b/kernel-open/nvidia/nv-i2c.c @@ -140,8 +140,9 @@ static int nv_i2c_algo_smbus_xfer( case I2C_SMBUS_WORD_DATA: if (read_write != I2C_SMBUS_READ) { - data->block[1] = (data->word & 0xff); - data->block[2] = (data->word >> 8); + u16 word = data->word; + data->block[1] = (word & 0xff); + data->block[2] = (word >> 8); } rmStatus = rm_i2c_transfer(sp, nv, (void *)adapter, @@ -273,246 +274,6 @@ void NV_API_CALL nv_i2c_del_adapter(nv_state_t *nv, void *data) } } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #else // defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) void NV_API_CALL nv_i2c_del_adapter(nv_state_t *nv, void *data) @@ -524,29 +285,4 @@ void* NV_API_CALL nv_i2c_add_adapter(nv_state_t *nv, NvU32 port) return NULL; } - - - - - - - - - - - - - - - - - - - - - - - - - #endif // defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index b62719cda..606ac0728 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -132,13 +132,6 @@ nvidia_vma_access( pageIndex = ((addr - vma->vm_start) >> PAGE_SHIFT); pageOffset = (addr & ~PAGE_MASK); - - - - - - - if (!mmap_context->valid) { nv_printf(NV_DBG_ERRORS, "NVRM: VM: invalid mmap context\n"); @@ -326,6 +319,7 @@ int nv_encode_caching( break; #if defined(NV_PGPROT_WRITE_COMBINED) && \ defined(NV_PGPROT_WRITE_COMBINED_DEVICE) + case NV_MEMORY_DEFAULT: case NV_MEMORY_WRITECOMBINED: if (NV_ALLOW_WRITE_COMBINING(memory_type)) { @@ -516,13 +510,6 @@ int nvidia_mmap_helper( NvU64 access_start = mmap_context->access_start; NvU64 access_len = mmap_context->access_size; - - - - - - - if (IS_REG_OFFSET(nv, access_start, access_len)) { if (nv_encode_caching(&vma->vm_page_prot, NV_MEMORY_UNCACHED, @@ -544,7 +531,7 @@ int nvidia_mmap_helper( else { if (nv_encode_caching(&vma->vm_page_prot, - rm_disable_iomap_wc() ? NV_MEMORY_UNCACHED : NV_MEMORY_WRITECOMBINED, + rm_disable_iomap_wc() ? NV_MEMORY_UNCACHED : mmap_context->caching, NV_MEMORY_TYPE_FRAMEBUFFER)) { if (nv_encode_caching(&vma->vm_page_prot, diff --git a/kernel-open/nvidia/nv-p2p.h b/kernel-open/nvidia/nv-p2p.h index c2059145d..a9469bdbb 100644 --- a/kernel-open/nvidia/nv-p2p.h +++ b/kernel-open/nvidia/nv-p2p.h @@ -177,11 +177,7 @@ struct nvidia_p2p_page_table { * This means the pages underlying the range of GPU virtual memory * will persist until explicitly freed by nvidia_p2p_put_pages(). * Persistent GPU memory mappings are not supported on PowerPC, - - - * MIG-enabled devices and vGPU. - * @param[in] data * A non-NULL opaque pointer to private data to be passed to the * callback function. diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index 5d3e4be87..7544de27f 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -99,7 +99,7 @@ static void nv_init_dynamic_power_management NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev)); - if (ret > 0 || ret < sizeof(filename)) + if (ret > 0 && ret < sizeof(filename)) { struct file *file = filp_open(filename, O_RDONLY, 0); if (!IS_ERR(file)) @@ -156,75 +156,6 @@ static void nv_init_dynamic_power_management rm_init_dynamic_power_management(sp, nv, pr3_acpi_method_present); } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - /* find nvidia devices and set initial state */ static int nv_pci_probe @@ -250,7 +181,6 @@ nv_pci_probe return -1; } - #ifdef NV_PCI_SRIOV_SUPPORT if (pci_dev->is_virtfn) { @@ -296,7 +226,6 @@ nv_pci_probe } #endif /* NV_PCI_SRIOV_SUPPORT */ - if (!rm_is_supported_pci_device( (pci_dev->class >> 16) & 0xFF, (pci_dev->class >> 8) & 0xFF, @@ -498,20 +427,11 @@ nv_pci_probe nv_init_ibmnpu_info(nv); - - - - #if defined(NVCPU_PPC64LE) // Use HW NUMA support as a proxy for ATS support. This is true in the only // PPC64LE platform where ATS is currently supported (IBM P9). nv_ats_supported &= nv_platform_supports_numa(nvl); #else - - - - - #endif if (nv_ats_supported) { @@ -589,19 +509,19 @@ nv_pci_probe /* Parse and set any per-GPU registry keys specified. */ nv_parse_per_device_option_string(sp); + rm_set_rm_firmware_requested(sp, nv); + #if defined(NV_VGPU_KVM_BUILD) if (nvidia_vgpu_vfio_probe(nvl->pci_dev) != NV_OK) { NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "Failed to register device to vGPU VFIO module"); nvidia_frontend_remove_device((void *)&nv_fops, nvl); - goto err_remove_device; + goto err_vgpu_kvm; } #endif nv_check_and_exclude_gpu(sp, nv); - rm_set_rm_firmware_requested(sp, nv); - #if defined(DPM_FLAG_NO_DIRECT_COMPLETE) dev_pm_set_driver_flags(nvl->dev, DPM_FLAG_NO_DIRECT_COMPLETE); #elif defined(DPM_FLAG_NEVER_SKIP) @@ -619,11 +539,18 @@ nv_pci_probe return 0; +#if defined(NV_VGPU_KVM_BUILD) +err_vgpu_kvm: +#endif + nv_procfs_remove_gpu(nvl); + rm_cleanup_dynamic_power_management(sp, nv); +#if defined(NV_PM_VT_SWITCH_REQUIRED_PRESENT) + pm_vt_switch_unregister(nvl->dev); +#endif err_remove_device: LOCK_NV_LINUX_DEVICES(); nv_linux_remove_device_locked(nvl); UNLOCK_NV_LINUX_DEVICES(); - rm_cleanup_dynamic_power_management(sp, nv); err_zero_dev: rm_free_private_state(sp, nv); err_not_supported: @@ -654,7 +581,6 @@ nv_pci_remove(struct pci_dev *pci_dev) NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); - #ifdef NV_PCI_SRIOV_SUPPORT if (pci_dev->is_virtfn) { @@ -666,7 +592,6 @@ nv_pci_remove(struct pci_dev *pci_dev) } #endif /* NV_PCI_SRIOV_SUPPORT */ - if (nv_kmem_cache_alloc_stack(&sp) != 0) { return; diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index 1e67890f1..31d3560f5 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -566,7 +566,6 @@ #define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS \ NV_REG_STRING(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS) - /* * Option: EnableS0ixPowerManagement * @@ -615,7 +614,6 @@ #define NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ NV_REG_STRING(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) - /* * Option: DynamicPowerManagement * @@ -847,10 +845,8 @@ NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT); NV_DEFINE_REG_ENTRY(__NV_ENABLE_STREAM_MEMOPS, 0); NV_DEFINE_REG_ENTRY(__NV_RM_PROFILING_ADMIN_ONLY_PARAMETER, 1); NV_DEFINE_REG_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, 0); - NV_DEFINE_REG_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT, 0); NV_DEFINE_REG_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 256); - NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); @@ -864,11 +860,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_VMALLOC_HEAP_MAX_SIZE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); - - - NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); - NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); @@ -912,10 +904,8 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(__NV_RM_PROFILING_ADMIN_ONLY, __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS), - NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), - NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), diff --git a/kernel-open/nvidia/nv-usermap.c b/kernel-open/nvidia/nv-usermap.c index 2d1a84c9d..47361f731 100644 --- a/kernel-open/nvidia/nv-usermap.c +++ b/kernel-open/nvidia/nv-usermap.c @@ -84,6 +84,7 @@ NV_STATUS NV_API_CALL nv_add_mapping_context_to_file( nvamc->prot = prot; nvamc->valid = NV_TRUE; + nvamc->caching = nvuap->caching; done: nv_put_file_private(priv); diff --git a/kernel-open/nvidia/nv-vm.c b/kernel-open/nvidia/nv-vm.c index f59e81023..d333a6930 100644 --- a/kernel-open/nvidia/nv-vm.c +++ b/kernel-open/nvidia/nv-vm.c @@ -222,7 +222,7 @@ static NvU64 nv_get_max_sysmem_address(void) for_each_online_node(node_id) { - global_max_pfn = max(global_max_pfn, node_end_pfn(node_id)); + global_max_pfn = max(global_max_pfn, (NvU64)node_end_pfn(node_id)); } return ((global_max_pfn + 1) << PAGE_SHIFT) - 1; @@ -371,13 +371,6 @@ NV_STATUS nv_alloc_contig_pages( if (os_is_xen_dom0() || at->flags.unencrypted) return nv_alloc_coherent_pages(nv, at); - - - - - - - at->order = get_order(at->num_pages * PAGE_SIZE); gfp_mask = nv_compute_gfp_mask(nv, at); diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index b8ce6d5a9..9bc64fc10 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -37,11 +37,9 @@ #include "nv-vgpu-vfio-interface.h" #endif - #include "nvlink_proto.h" #include "nvlink_caps.h" - #include "nv-frontend.h" #include "nv-hypervisor.h" #include "nv-ibmnpu.h" @@ -141,11 +139,6 @@ static NvTristate nv_chipset_is_io_coherent = NV_TRISTATE_INDETERMINATE; // True if all the successfully probed devices support ATS // Assigned at device probe (module init) time NvBool nv_ats_supported = NVCPU_IS_PPC64LE - - - - - ; // allow an easy way to convert all debug printfs related to events @@ -416,16 +409,13 @@ nv_module_resources_init(nv_stack_t **sp) return rc; } - static void nvlink_drivers_exit(void) { - #if NVCPU_IS_64_BITS nvswitch_exit(); #endif - #if defined(NVCPU_PPC64LE) ibmnpu_exit(); #endif @@ -433,8 +423,6 @@ nvlink_drivers_exit(void) nvlink_core_exit(); } - - static int __init nvlink_drivers_init(void) { @@ -457,7 +445,6 @@ nvlink_drivers_init(void) } #endif - #if NVCPU_IS_64_BITS rc = nvswitch_init(); if (rc < 0) @@ -470,11 +457,9 @@ nvlink_drivers_init(void) } #endif - return rc; } - static void nv_module_state_exit(nv_stack_t *sp) { @@ -600,9 +585,6 @@ nv_report_applied_patches(void) static void nv_drivers_exit(void) { - - - nv_pci_unregister_driver(); nvidia_unregister_module(&nv_fops); @@ -629,16 +611,6 @@ nv_drivers_init(void) goto exit; } - - - - - - - - - - exit: if (rc < 0) { @@ -656,10 +628,8 @@ nv_module_exit(nv_stack_t *sp) rm_shutdown_rm(sp); nv_destroy_rsync_info(); - nvlink_drivers_exit(); - nv_cap_drv_exit(); nv_module_resources_exit(sp); @@ -683,14 +653,12 @@ nv_module_init(nv_stack_t **sp) goto cap_drv_exit; } - rc = nvlink_drivers_init(); if (rc < 0) { goto cap_drv_exit; } - nv_init_rsync_info(); nv_sev_init(); @@ -714,10 +682,8 @@ nv_module_init(nv_stack_t **sp) nvlink_exit: nv_destroy_rsync_info(); - nvlink_drivers_exit(); - cap_drv_exit: nv_cap_drv_exit(); nv_module_resources_exit(*sp); @@ -1266,7 +1232,8 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) #endif if (((!(nv->flags & NV_FLAG_USES_MSI)) && (!(nv->flags & NV_FLAG_USES_MSIX))) - && (nv->interrupt_line == 0) && !(nv->flags & NV_FLAG_SOC_DISPLAY)) + && (nv->interrupt_line == 0) && !(nv->flags & NV_FLAG_SOC_DISPLAY) + && !(nv->flags & NV_FLAG_SOC_IGPU)) { NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "No interrupts of any type are available. Cannot use this GPU.\n"); @@ -1279,9 +1246,6 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) { if (nv->flags & NV_FLAG_SOC_DISPLAY) { - - - } else if (!(nv->flags & NV_FLAG_USES_MSIX)) { @@ -1331,15 +1295,13 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) if (!rm_init_adapter(sp, nv)) { if (!(nv->flags & NV_FLAG_USES_MSIX) && - !(nv->flags & NV_FLAG_SOC_DISPLAY)) + !(nv->flags & NV_FLAG_SOC_DISPLAY) && + !(nv->flags & NV_FLAG_SOC_IGPU)) { free_irq(nv->interrupt_line, (void *) nvl); } else if (nv->flags & NV_FLAG_SOC_DISPLAY) { - - - } #if defined(NV_LINUX_PCIE_MSI_SUPPORTED) else @@ -1467,10 +1429,8 @@ static int nv_open_device(nv_state_t *nv, nvidia_stack_t *sp) return -ENODEV; } - - - - + if (unlikely(NV_ATOMIC_READ(nvl->usage_count) >= NV_S32_MAX)) + return -EMFILE; if ( ! (nv->flags & NV_FLAG_OPEN)) { @@ -1674,7 +1634,8 @@ void nv_shutdown_adapter(nvidia_stack_t *sp, } if (!(nv->flags & NV_FLAG_USES_MSIX) && - !(nv->flags & NV_FLAG_SOC_DISPLAY)) + !(nv->flags & NV_FLAG_SOC_DISPLAY) && + !(nv->flags & NV_FLAG_SOC_IGPU)) { free_irq(nv->interrupt_line, (void *)nvl); if (nv->flags & NV_FLAG_USES_MSI) @@ -1686,9 +1647,6 @@ void nv_shutdown_adapter(nvidia_stack_t *sp, } else if (nv->flags & NV_FLAG_SOC_DISPLAY) { - - - } #if defined(NV_LINUX_PCIE_MSI_SUPPORTED) else @@ -3838,9 +3796,6 @@ nvos_count_devices(void) count = nv_pci_count_devices(); - - - return count; } @@ -4901,7 +4856,6 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( NvU64 *compr_addr_sys_phys, NvU64 *addr_guest_phys, NvU32 *addr_width, - NvU32 *granularity, NvS32 *node_id ) { @@ -4940,43 +4894,9 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( *addr_width = nv_volta_dma_addr_size - nv_volta_addr_space_width; } - if (granularity != NULL) - { - *granularity = nv_volta_addr_space_width; - } - status = NV_OK; #endif - - - - - - - - - - - - - - - - - - - - - - - - - - - - - return status; } @@ -5188,7 +5108,6 @@ NvU32 NV_API_CALL nv_get_dev_minor(nv_state_t *nv) NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap(int fd, int *duped_fd) { - *duped_fd = nvlink_cap_acquire(fd, NVLINK_CAP_FABRIC_MANAGEMENT); if (*duped_fd < 0) { @@ -5196,9 +5115,6 @@ NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap(int fd, int *duped_fd) } return NV_OK; - - - } /* @@ -5419,7 +5335,6 @@ NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *nv) #endif } - NvBool NV_API_CALL nv_platform_supports_s0ix(void) { #if defined(CONFIG_ACPI) @@ -5483,7 +5398,6 @@ NvBool NV_API_CALL nv_s2idle_pm_configured(void) return (memcmp(buf, "[s2idle]", 8) == 0); } - /* * Function query system chassis info, to figure out if the platform is * Laptop or Notebook. @@ -5554,7 +5468,6 @@ void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_vir #if NVCPU_IS_PPC64LE return nv_ibmnpu_cache_flush_range(nv, cpu_virtual, size); #elif NVCPU_IS_AARCH64 - NvU64 va, cbsize; NvU64 end_cpu_virtual = cpu_virtual + size; @@ -5574,7 +5487,6 @@ void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_vir cond_resched(); } asm volatile("dsb sy" : : : "memory"); - #endif } diff --git a/kernel-open/nvidia/nv_gpu_ops.h b/kernel-open/nvidia/nv_gpu_ops.h index 6c09dda74..63ea73afe 100644 --- a/kernel-open/nvidia/nv_gpu_ops.h +++ b/kernel-open/nvidia/nv_gpu_ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -126,6 +126,7 @@ NV_STATUS nvGpuOpsQueryCesCaps(struct gpuDevice *device, NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace, NvU64 srcAddress, struct gpuAddressSpace *dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress); NV_STATUS nvGpuOpsDupMemory(struct gpuDevice *device, @@ -275,27 +276,4 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, char *methodStream, NvU32 methodStreamSize); - - - - - - - - - - - - - - - - - - - - - - - #endif /* _NV_GPU_OPS_H_*/ diff --git a/kernel-open/nvidia/nv_uvm_interface.c b/kernel-open/nvidia/nv_uvm_interface.c index 7e895a959..abb459750 100644 --- a/kernel-open/nvidia/nv_uvm_interface.c +++ b/kernel-open/nvidia/nv_uvm_interface.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -196,9 +196,7 @@ NV_STATUS nvUvmInterfaceSessionCreate(uvmGpuSessionHandle *session, memset(platformInfo, 0, sizeof(*platformInfo)); platformInfo->atsSupported = nv_ats_supported; - - - + platformInfo->sevEnabled = os_sev_enabled; status = rm_gpu_ops_create_session(sp, (gpuSessionHandle *)session); @@ -700,6 +698,7 @@ EXPORT_SYMBOL(nvUvmInterfaceUnsetPageDirectory); NV_STATUS nvUvmInterfaceDupAllocation(uvmGpuAddressSpaceHandle srcVaSpace, NvU64 srcAddress, uvmGpuAddressSpaceHandle dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress) { nvidia_stack_t *sp = NULL; @@ -714,6 +713,7 @@ NV_STATUS nvUvmInterfaceDupAllocation(uvmGpuAddressSpaceHandle srcVaSpace, (gpuAddressSpaceHandle)srcVaSpace, srcAddress, (gpuAddressSpaceHandle)dstVaSpace, + dstVaAlignment, dstAddress); nv_kmem_cache_free_stack(sp); @@ -1420,115 +1420,6 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe } EXPORT_SYMBOL(nvUvmInterfacePagingChannelPushStream); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #else // NV_UVM_ENABLE NV_STATUS nv_uvm_suspend(void) diff --git a/kernel-open/nvidia/nvlink_common.h b/kernel-open/nvidia/nvlink_common.h index 8cf88b490..d70f44028 100644 --- a/kernel-open/nvidia/nvlink_common.h +++ b/kernel-open/nvidia/nvlink_common.h @@ -69,9 +69,7 @@ struct nvlink_detailed_device_info NvU64 deviceType; NvU8 *devUuid; NvBool bInitialized; - - - + NvBool bEnableALI; void *dev_info; // Endpoint driver device info opaque // to core lib. Passed from end point // driver to core diff --git a/kernel-open/nvidia/nvlink_inband_drv_header.h b/kernel-open/nvidia/nvlink_inband_drv_header.h new file mode 100644 index 000000000..1521c479b --- /dev/null +++ b/kernel-open/nvidia/nvlink_inband_drv_header.h @@ -0,0 +1,66 @@ +/******************************************************************************* + Copyright (c) 2022 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ + +#ifndef NVLINK_INBAND_DRV_HDR_H +#define NVLINK_INBAND_DRV_HDR_H + +/* + * This header file defines the header that should be used by RM and NVSwitch + * driver to sync minions on both the sides before an actual inband message + * transfer is initiated. + * + * Modifying the existing header structure is not allowed. A versioning + * policy must be enforced if such changes are needed in the future. + * + * - Avoid use of enums or bit fields. Always use fixed types. + * - Avoid conditional fields in the structs + * - Avoid nested and complex structs. Keep them simple and flat for ease of + * encoding and decoding. + * - Avoid embedded pointers. Flexible arrays at the end of the struct are allowed. + * - Always use the packed struct to typecast inband messages. More details: + * - Always have reserved flags or fields to CYA given the stable ABI conditions. + */ + +/* Align to byte boundaries */ +#pragma pack(push, 1) + +#include "nvtypes.h" + +#define NVLINK_INBAND_MAX_XFER_SIZE 0x100 +#define NVLINK_INBAND_MAX_XFER_AT_ONCE 4 + +#define NVLINK_INBAND_DRV_HDR_TYPE_START NVBIT(0) +#define NVLINK_INBAND_DRV_HDR_TYPE_MID NVBIT(1) +#define NVLINK_INBAND_DRV_HDR_TYPE_END NVBIT(2) + +/* Rest of the bits are reserved for future use and must be always set zero. */ + +typedef struct +{ + NvU8 data; +} nvlink_inband_drv_hdr_t; + +#pragma pack(pop) + +/* Don't add any code after this line */ + +#endif diff --git a/kernel-open/nvidia/nvlink_inband_msg.h b/kernel-open/nvidia/nvlink_inband_msg.h new file mode 100644 index 000000000..2618cefdb --- /dev/null +++ b/kernel-open/nvidia/nvlink_inband_msg.h @@ -0,0 +1,166 @@ +/******************************************************************************* + Copyright (c) 2022 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ + +#ifndef NVLINK_INBAND_MSG_HDR_H +#define NVLINK_INBAND_MSG_HDR_H + +/* + * Messages do not have individual versioning, instead a strict ABI is maintained. When a change is + * required on existing message, instead of modifying corresponding message structure, a completely + * new message type (like INBAND_MSG_TYPE_XXX_V1, INBAND_MSG_TYPE_XXX_V2) and corresponding message + * definition structure needs to be added. Do not modify existing structs in any way. + * + * Messages may contain fields which are debug only and must be used for logging purpose. Such + * fields shouldn't be trusted. + * + * - Avoid use of enums or bitfields. Always use fixed types. + * - Avoid conditional fields in the structs. + * - Avoid nested and complex structs. Keep them simple and flat for ease of encoding and decoding. + * - Avoid embedded pointers. Flexible arrays at the end of the struct are allowed. + * - Always use the packed struct to typecast inband messages. More details: + * - Always have reserved flags or fields to CYA given the stable ABI conditions. + */ + +/* Align to byte boundaries */ +#pragma pack(push, 1) + +#include "nvtypes.h" +#include "nvmisc.h" +#include "nvCpuUuid.h" +#include "nvstatus.h" +#include "nvstatuscodes.h" + +#define NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NVLINK_INBAND_MSG_MAGIC_ID_FM 0xadbc + +/* Nvlink Inband messages types */ +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ 0 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP 1 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4 + +/* Nvlink Inband message packet header */ +typedef struct +{ + NvU16 magicId; /* Identifier to represent in-band msg, will be NVLINK_INBAND_MSG_MAGIC_ID */ + NvU64 requestId; /* Unique Id for a request and response will carry same id */ + NV_STATUS status; /* High level status of the message/request */ + NvU16 type; /* Type of encoded message. One of NVLINK_INBAND_MSG_TYPE_xxx */ + NvU32 length; /* Length of encoded message */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ +} nvlink_inband_msg_header_t; + +#define NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED NVBIT(0) + +/* Add more caps as need in the future */ + +typedef struct +{ + NvU32 pciInfo; /* Encoded as Bus:Device:Function.(debug only) */ + NvU8 moduleId; /* GPIO based physical/module ID of the GPU. (debug only) */ + NvUuid uuid; /* UUID of the GPU. (debug only) */ + NvU64 discoveredLinkMask; /* GPU's discovered NVLink mask info. (debug only) */ + NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */ + + NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */ + NvU8 reserved[16]; /* For future use. Must be initialized to zero */ +} nvlink_inband_gpu_probe_req_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_gpu_probe_req_t probeReq; +} nvlink_inband_gpu_probe_req_msg_t; + +#define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1 NVBIT64(0) +#define NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1 NVBIT64(1) + +typedef struct +{ + NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */ + NvU32 gfId; /* GFID which supports NVLink */ + NvU64 fmCaps; /* Capability of FM e.g. what features FM support. */ + NvU16 nodeId; /* Node ID of the system where this GPU belongs */ + NvU16 fabricPartitionId; /* Partition ID if the GPU belongs to a fabric partition */ + NvU16 clusterId; /* Cluster ID to which this node belongs */ + NvU64 gpaAddress; /* GPA starting address for the GPU */ + NvU64 gpaAddressRange; /* GPU GPA address range */ + NvU64 flaAddress; /* FLA starting address for the GPU */ + NvU64 flaAddressRange; /* GPU FLA address range */ + NvU8 reserved[32]; /* For future use. Must be initialized to zero */ +} nvlink_inband_gpu_probe_rsp_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_gpu_probe_rsp_t probeRsp; +} nvlink_inband_gpu_probe_rsp_msg_t; + +typedef struct +{ + NvU64 mcAllocSize; /* Multicast allocation size requested */ + NvU32 flags; /* For future use. Must be initialized to zero */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ + NvU16 numGpuHandles; /* Number of GPUs in this team */ + NvU64 gpuHandles[]; /* Array of probed handles, should be last */ +} nvlink_inband_mc_team_setup_req_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_mc_team_setup_req_t mcTeamSetupReq; +} nvlink_inband_mc_team_setup_req_msg_t; + +typedef struct +{ + NvU64 mcTeamHandle; /* Unique handle assigned for this Multicast team */ + NvU32 flags; /* For future use. Must be initialized to zero */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ + NvU64 mcAddressBase; /* FLA starting address assigned for the Multicast slot */ + NvU64 mcAddressSize; /* Size of FLA assigned to the Multicast slot */ +} nvlink_inband_mc_team_setup_rsp_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_mc_team_setup_rsp_t mcTeamSetupRsp; +} nvlink_inband_mc_team_setup_rsp_msg_t; + +typedef struct +{ + NvU64 mcTeamHandle; /* Unique handle assigned for the Multicast team */ + NvU32 flags; /* For future use. Must be initialized to zero */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ +} nvlink_inband_mc_team_release_req_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_mc_team_release_req_t mcTeamReleaseReq; +} nvlink_inband_mc_team_release_req_msg_t; + +#pragma pack(pop) + +/* Don't add any code after this line */ + +#endif diff --git a/kernel-open/nvidia/nvlink_linux.c b/kernel-open/nvidia/nvlink_linux.c index af8a048d0..8e7b36715 100644 --- a/kernel-open/nvidia/nvlink_linux.c +++ b/kernel-open/nvidia/nvlink_linux.c @@ -207,11 +207,6 @@ static int nvlink_fops_release(struct inode *inode, struct file *filp) nvlink_print(NVLINK_DBG_INFO, "nvlink driver close\n"); - - - - - mutex_lock(&nvlink_drvctx.lock); if (private->capability_fds.fabric_mgmt > 0) diff --git a/kernel-open/nvidia/nvlink_proto.h b/kernel-open/nvidia/nvlink_proto.h index b161ba92b..356001e4d 100644 --- a/kernel-open/nvidia/nvlink_proto.h +++ b/kernel-open/nvidia/nvlink_proto.h @@ -33,14 +33,12 @@ int nvlink_core_init (void); void nvlink_core_exit (void); - /* * Functions defined in nvswitch_linux.c */ int nvswitch_init (void); void nvswitch_exit (void); - #if defined(NVCPU_AARCH64) /* * Functions defined in tegrashim_linux.c (Tegra only) diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index c9ff6f8da..916eb1e11 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -28,14 +28,6 @@ #include "nv-time.h" - - - - - - - - extern char *NVreg_TemporaryFilePath; #define MAX_ERROR_STRING 512 @@ -52,16 +44,12 @@ NvU8 os_page_shift = PAGE_SHIFT; NvU32 os_sev_status = 0; NvBool os_sev_enabled = 0; - #if defined(CONFIG_DMA_SHARED_BUFFER) NvBool os_dma_buf_enabled = NV_TRUE; #else NvBool os_dma_buf_enabled = NV_FALSE; #endif // CONFIG_DMA_SHARED_BUFFER - - - void NV_API_CALL os_disable_console_access(void) { console_lock(); @@ -974,6 +962,11 @@ void NV_API_CALL os_dbg_set_level(NvU32 new_debuglevel) cur_debuglevel = new_debuglevel; } +NvU64 NV_API_CALL os_get_max_user_va(void) +{ + return TASK_SIZE; +} + NV_STATUS NV_API_CALL os_schedule(void) { if (NV_MAY_SLEEP()) @@ -1964,52 +1957,6 @@ void NV_API_CALL os_wake_up complete_all(&wq->q); } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - nv_cap_t* NV_API_CALL os_nv_cap_init ( const char *path @@ -2063,101 +2010,3 @@ void NV_API_CALL os_nv_cap_close_fd nv_cap_close_fd(fd); } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/kernel-open/nvidia/os-pci.c b/kernel-open/nvidia/os-pci.c index 3fdf487f5..2c0e9c927 100644 --- a/kernel-open/nvidia/os-pci.c +++ b/kernel-open/nvidia/os-pci.c @@ -158,49 +158,47 @@ void NV_API_CALL os_pci_remove( #endif } +NV_STATUS NV_API_CALL +os_enable_pci_req_atomics( + void *handle, + enum os_pci_req_atomics_type type +) +{ +#ifdef NV_PCI_ENABLE_ATOMIC_OPS_TO_ROOT_PRESENT + int ret; + u16 val; + switch (type) + { + case OS_INTF_PCIE_REQ_ATOMICS_32BIT: + ret = pci_enable_atomic_ops_to_root(handle, + PCI_EXP_DEVCAP2_ATOMIC_COMP32); + break; + case OS_INTF_PCIE_REQ_ATOMICS_64BIT: + ret = pci_enable_atomic_ops_to_root(handle, + PCI_EXP_DEVCAP2_ATOMIC_COMP64); + break; + case OS_INTF_PCIE_REQ_ATOMICS_128BIT: + ret = pci_enable_atomic_ops_to_root(handle, + PCI_EXP_DEVCAP2_ATOMIC_COMP128); + break; + default: + ret = -1; + break; + } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + if (ret == 0) + { + /* + * GPUs that don't support Requester Atomics have its + * PCI_EXP_DEVCTL2_ATOMIC_REQ always set to 0 even after SW enables it. + */ + if ((pcie_capability_read_word(handle, PCI_EXP_DEVCTL2, &val) == 0) && + (val & PCI_EXP_DEVCTL2_ATOMIC_REQ)) + { + return NV_OK; + } + } +#endif + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index 24dff412c..831bd7283 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -260,6 +260,9 @@ namespace DisplayPort virtual bool isMSAOverMSTCapable() = 0; virtual bool isFakedMuxDevice() = 0; + virtual bool setPanelReplayConfig(panelReplayConfig prcfg) = 0; + virtual bool isPanelReplaySupported() = 0; + protected: virtual ~Device() {} diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 0504a551e..8cd1e877f 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -315,14 +315,6 @@ namespace DisplayPort // bool bDscMstCapBug3143315; - // - // Enable DSC Pass through support in driver based on regkey. - // - bool bDscMstEnablePassThrough; - - // Reduce number of 2H1OR LTs which fixes bug 3534707 - bool bDscOptimizeLTBug3534707; - // // Synaptics branch device doesn't support Virtual Peer Devices so DSC // capability of downstream device should be decided based on device's own diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index a24ac928d..0faaf0ffa 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -173,6 +173,8 @@ namespace DisplayPort bool bIsFakedMuxDevice; bool bIsPreviouslyFakedMuxDevice; bool bisMarkedForDeletion; + bool bIgnoreMsaCap; + bool bIgnoreMsaCapCached; // // Device doing the DSC decompression for this device. This could be device itself @@ -194,6 +196,7 @@ namespace DisplayPort TriState bSdpExtCapable; bool bMSAOverMSTCapable; + bool bDscPassThroughColorFormatWar; DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent); ~DeviceImpl(); @@ -349,15 +352,9 @@ namespace DisplayPort return true; } - bool getIgnoreMSACap() - { - return hal->getMsaTimingparIgnored(); - } + bool getIgnoreMSACap(); - AuxRetry::status setIgnoreMSAEnable(bool msaTimingParamIgnoreEn) - { - return hal->setIgnoreMSATimingParamters(msaTimingParamIgnoreEn); - } + AuxRetry::status setIgnoreMSAEnable(bool msaTimingParamIgnoreEn); bool isVirtualPeerDevice() { diff --git a/src/common/displayport/inc/dp_edid.h b/src/common/displayport/inc/dp_edid.h index 149f76839..95eb53f2b 100644 --- a/src/common/displayport/inc/dp_edid.h +++ b/src/common/displayport/inc/dp_edid.h @@ -308,7 +308,9 @@ namespace DisplayPort static const NvU8 ddcAddrList[] = {EDID_DDC_ADR0, EDID_DDC_ADR1, EDID_DDC_ADR2}; const NvU8 ddcAddrListSize = sizeof(ddcAddrList)/sizeof(NvU8); - const NvU8 EDID_READ_MAX_RETRY_COUNT = 6; + + // HDMI 1.4 Section 8.5: HDMI Sink can have up to 100ms to get EDID ready. + const NvU8 EDID_READ_RETRY_TIMEOUT_MS = 100; const NvU8 EDID_MAX_AUX_RETRIES = 10; const NvU8 EDID_AUX_WAIT_TIME = 1; NvU8 getEDIDBlockChecksum(const Buffer &); diff --git a/src/common/displayport/inc/dp_groupimpl.h b/src/common/displayport/inc/dp_groupimpl.h index aa9b021b4..d421e7dd2 100644 --- a/src/common/displayport/inc/dp_groupimpl.h +++ b/src/common/displayport/inc/dp_groupimpl.h @@ -68,8 +68,6 @@ namespace DisplayPort Watermark watermarks; // Cached watermark calculations } timeslot; - bool bIsCurrentModesetGroup; // Group that is getting attached - GroupImpl(ConnectorImpl * parent, bool isFirmwareGroup = false) : parent(parent), streamValidationDone(true), @@ -82,7 +80,6 @@ namespace DisplayPort dscModeActive(DSC_MODE_NONE), singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY), singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE), - bIsCurrentModesetGroup(false), headAttached(false) { timeslot.count = 0; diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index ae29499ef..311b054a7 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -145,6 +145,7 @@ namespace DisplayPort EDP_3_24GHZ = 324000000, EDP_4_32GHZ = 432000000, HBR2 = 540000000, + EDP_6_75GHZ = 675000000, HBR3 = 810000000 }; diff --git a/src/common/displayport/inc/dp_messages.h b/src/common/displayport/inc/dp_messages.h index baf4d3bde..681695ad2 100644 --- a/src/common/displayport/inc/dp_messages.h +++ b/src/common/displayport/inc/dp_messages.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 0f6e37077..03e251f8a 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,12 +65,6 @@ // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" -// Enable DSC Pass through support in MST mode. -#define NV_DP_DSC_MST_ENABLE_PASS_THROUGH "DP_DSC_MST_ENABLE_PASS_THROUGH" - -// Regkey to reduce number of 2H1OR LTs which fixes bug 3534707 -#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707 "DP_DSC_OPTIMIZE_LT_BUG_3534707" - #define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING" #define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING "DP_DPCD_PROBING_FOR_BUSY_WAITING" @@ -106,8 +100,6 @@ struct DP_REGKEY_DATABASE bool bOptLinkKeptAliveSst; bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; - bool bDscMstEnablePassThrough; - bool bDscOptimizeLTBug3534707; bool bNoReplyTimerForBusyWaiting; bool bDpcdProbingForBusyWaiting; }; diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index b9f2fd8c0..db6d7b79e 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -188,8 +188,6 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab this->bDisableSSC = dpRegkeyDatabase.bSscDisabled; this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; - this->bDscMstEnablePassThrough = dpRegkeyDatabase.bDscMstEnablePassThrough; - this->bDscOptimizeLTBug3534707 = dpRegkeyDatabase.bDscOptimizeLTBug3534707; } void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled) @@ -633,27 +631,56 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device, newDev->queryGUID2(); } - // Read panel DSC support only if GPU supports DSC - bool bGpuDscSupported; - main->getDscCaps(&bGpuDscSupported); - if (bGpuDscSupported) + if (!linkAwaitingTransition) { - if (newDev->getDSCSupport()) - { - // Read and parse DSC caps only if panel supports DSC - newDev->readAndParseDSCCaps(); - - // Read and Parse Branch Specific DSC Caps - if (!newDev->isVideoSink() && !newDev->isAudioSink()) + // + // When link is awaiting SST<->MST transition, DSC caps read from downstream + // DSC branch device might be wrong. DSC Caps exposed by DSC MST branch depends + // on the current link state. If it is in SST mode ie MST_EN (0x111[bit 0]) is 0 and + // panel connected behind it supports DSC, then branch will expose the DSC caps + // of the panel connected down stream rather than it's own. This is because source + // will have no other way to read the caps of the downstream panel. In fact when + // MST_EN = 0 and UP_REQ_EN (0x111 [bit 1]) = 1 source can read the caps of the + // downstream panel using REMOTE_DPCD_READ but branch device's behavior depends + // only on MST_EN bit. Similarly in SST, if the panel connected downstream to branch + // does not support DSC, DSC MST branch will expose it's own DSC caps. + // During boot since VBIOS drives display in SST mode and when driver takes over, + // linkAwaitingTransition will be true. DpLib does link assessment and topology + // discovery by setting UP_REQ_EN to true while still keeping MST_EN to false. + // This is to ensure we detach the head and active modeset groups that are in SST mode + // before switching the link to MST mode. When processNewDevice is called at this + // point to create new devices we should not read DSC caps due to above mentioned reason. + // As long as linkIsAwaitingTransition is true, Dplib will not report new Devices to + // to client since isPendingNewDevice() will be false even though DPlib discovered + // new devices. After Dplib completes topology discovery, DD initiates notifyDetachBegin/End + // to remove active groups from the link and notifyDetachEnd calls assessLink + // where we toggle the link state. Only after this we should read DSC caps in this case. + // Following this assesslink calls fireEvents() which will report + // the new devies to clients and client will have the correct DSC caps. + // + bool bGpuDscSupported; + + // Check GPU DSC Support + main->getDscCaps(&bGpuDscSupported); + if (bGpuDscSupported) + { + if (newDev->getDSCSupport()) { - newDev->readAndParseBranchSpecificDSCCaps(); + // Read and parse DSC caps only if panel supports DSC + newDev->readAndParseDSCCaps(); + + // Read and Parse Branch Specific DSC Caps + if (!newDev->isVideoSink() && !newDev->isAudioSink()) + { + newDev->readAndParseBranchSpecificDSCCaps(); + } } - } - if (!processedEdid.WARFlags.bIgnoreDscCap) - { - // Check if DSC is possible for the device and if so, set DSC Decompression device. - newDev->setDscDecompressionDevice(this->bDscCapBasedOnParent); + if (!processedEdid.WARFlags.bIgnoreDscCap) + { + // Check if DSC is possible for the device and if so, set DSC Decompression device. + newDev->setDscDecompressionDevice(this->bDscCapBasedOnParent); + } } } @@ -675,6 +702,8 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device, newDev->bMSAOverMSTCapable = false; } + newDev->applyOUIOverrides(); + fireEvents(); } @@ -1194,6 +1223,40 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, DP_LOG(("Current version is 1.1")); } + if ((dev->devDoingDscDecompression == dev) && dev->parent) + { + if (dev->parent->bDscPassThroughColorFormatWar) + { + // + // Bug 3692417 + // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. + // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color + // format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode + // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify + // the WAR to be applied only before the firmware version that fixes it. + // + if ((modesetParams.colorFormat == dpColorFormat_RGB && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) || + (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || + (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422)) + { + if (pDscParams->forceDsc == DSC_FORCE_ENABLE) + { + // If DSC is force enabled then return failure here + compoundQueryResult = false; + pDscParams->bEnableDsc = false; + return false; + } + else + { + // We should check if mode is possible without DSC. + pDscParams->bEnableDsc = false; + lc.enableFEC(false); + goto nonDscDpIMP; + } + } + } + } + availableBandwidthBitsPerSecond = lc.minRate * 8 * lc.lanes; warData.dpData.linkRateHz = lc.peakRate; @@ -2550,7 +2613,6 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr } GroupImpl* targetImpl = (GroupImpl*)target; - targetImpl->bIsCurrentModesetGroup = true; if (bEnableDsc) { @@ -2667,7 +2729,6 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN_STATUS, bLinkTrainingStatus); bFromResumeToNAB = false; - targetImpl->bIsCurrentModesetGroup = false; return bLinkTrainingStatus; } @@ -3283,6 +3344,7 @@ bool ConnectorImpl::trainSingleHeadMultipleSSTLinkNotAlive(GroupImpl *pGroupAtta void ConnectorImpl::assessLink(LinkTrainingType trainType) { this->bSkipLt = false; // Assesslink should never skip LT, so let's reset it in case it was set. + bool bLinkStateToggle = false; if (bSkipAssessLinkForPCon) { @@ -3409,6 +3471,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) linkState = hal->getSupportsMultistream() ? DP_TRANSPORT_MODE_MULTI_STREAM : DP_TRANSPORT_MODE_SINGLE_STREAM; linkAwaitingTransition = false; + bLinkStateToggle = true; } else { @@ -3517,6 +3580,30 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) { disableFlush(); } + + if (bLinkStateToggle) + { + DP_LOG(("DP> Link state toggled, reading DSC caps now")); + // Read panel DSC support only if GPU supports DSC + bool bGpuDscSupported; + main->getDscCaps(&bGpuDscSupported); + if (bGpuDscSupported) + { + for (Device * i = enumDevices(0); i; i=enumDevices(i)) + { + DeviceImpl * dev = (DeviceImpl *)i; + if(dev->getDSCSupport()) + { + // Read and parse DSC caps only if panel and GPU supports DSC + dev->readAndParseDSCCaps(); + } + if (!(dev->processedEdid.WARFlags.bIgnoreDscCap)) + { + dev->setDscDecompressionDevice(this->bDscCapBasedOnParent); + } + } + } + } } bool ConnectorImpl::handleCPIRQ() @@ -3902,36 +3989,21 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) GroupImpl * groupAttached = 0; for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next) { - DP_ASSERT(bIsUefiSystem); + DP_ASSERT(bIsUefiSystem || linkUseMultistream() || (!groupAttached && "Multiple attached heads")); groupAttached = (GroupImpl * )e; - if (bDscOptimizeLTBug3534707) + if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL)) { - if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL)) - { - // - // If current modeset group requires 2Head1OR and - // - group is not active yet (first modeset on the group) - // - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR) - // then re-train the link - // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after - // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang. - // - bTwoHeadOneOrLinkRetrain = true; - break; - } - } - else - { - if (groupAttached->lastModesetInfo.mode == DSC_DUAL && groupAttached->bIsCurrentModesetGroup) - { - // - // If current modeset group requires 2Head1OR mode, we should retrain link. - // For SST, there will be only one group per connector. - // For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL. - bTwoHeadOneOrLinkRetrain = true; - break; - } + // + // If current modeset group requires 2Head1OR and + // - group is not active yet (first modeset on the group) + // - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR) + // then re-train the link + // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after + // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang. + // + bTwoHeadOneOrLinkRetrain = true; + break; } } @@ -4018,9 +4090,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) // // Check if we are already trained to the desired link config? // Make sure requested FEC state matches with the current FEC state of link. - // If 2Head1OR mode is requested, retrain if group is not active or - // last modeset on active group was not in 2Head1OR mode. - // bTwoHeadOneOrLinkRetrain tracks this requirement. + // If 2Head1OR mode is requested, retrain if group is not active or + // last modeset on active group was not in 2Head1OR mode. + // bTwoHeadOneOrLinkRetrain tracks this requirement. // // @@ -4033,8 +4105,7 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) if ((activeLinkConfig == lowestSelected) && (!isLinkInD3()) && (!isLinkLost()) && - ((!bDscOptimizeLTBug3534707 && !this->bFECEnable) || - (bDscOptimizeLTBug3534707 && (this->bFECEnable == activeLinkConfig.bEnableFEC))) && + (this->bFECEnable == activeLinkConfig.bEnableFEC) && !bTwoHeadOneOrLinkRetrain) { if (bSkipRedundantLt || main->isInternalPanelDynamicMuxCapable()) @@ -4151,8 +4222,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) // // Make sure link is physically active and healthy, otherwise re-train. // Make sure requested FEC state matches with the current FEC state of link. - // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group - // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. + // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group + // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. // bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) || isLinkLost() || @@ -6143,6 +6214,13 @@ void ConnectorImpl::notifyShortPulse() } } + // If DPCD access is not available, skip trying to restore link configuration. + hal->updateDPCDOffline(); + if (hal->isDpcdOffline()) + { + return; + } + DP_LOG(("DP> Link not alive, Try to restore link configuration")); if (trainSingleHeadMultipleSSTLinkNotAlive(getActiveGroupForSST())) diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 0427ef138..39ce07f87 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -91,7 +91,10 @@ DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * pa bIsFakedMuxDevice(false), bIsPreviouslyFakedMuxDevice(false), bisMarkedForDeletion(false), - bSdpExtCapable(Indeterminate) + bIgnoreMsaCap(false), + bIgnoreMsaCapCached(false), + bSdpExtCapable(Indeterminate), + bDscPassThroughColorFormatWar(false) { bandwidth.enum_path.dataValid = false; shadow.plugged = false; @@ -921,6 +924,7 @@ void DeviceImpl::applyOUIOverrides() (buffer[8] == 0x31 || buffer[8] == 0x20)) { this->bSdpExtCapable = False; + this->bDscPassThroughColorFormatWar = true; // // Check firmware version @@ -1026,7 +1030,7 @@ bool DeviceImpl::getSDPExtnForColorimetrySupported() _YES, byte) ? True : False; } } - this->applyOUIOverrides(); + if (parentDevice && (this->bSdpExtCapable == True)) { // @@ -1458,11 +1462,6 @@ NvBool DeviceImpl::getDSCSupport() { dscCaps.bDSCSupported = true; } - - if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte)) - { - dscCaps.bDSCPassThroughSupported = true; - } } else @@ -1572,6 +1571,11 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize) return false; } + if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, buffer[0x0])) + { + dscCaps.bDSCPassThroughSupported = true; + } + dscCaps.versionMajor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MAJOR, buffer[0x1]); dscCaps.versionMinor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MINOR, buffer[0x1]); @@ -1758,6 +1762,21 @@ bool DeviceImpl::readAndParseDSCCaps() return parseDscCaps(&rawDscCaps[0], sizeof(rawDscCaps)); } +bool DeviceImpl::readAndParseBranchSpecificDSCCaps() +{ + unsigned sizeCompleted = 0; + unsigned nakReason = NakUndefined; + NvU8 rawBranchSpecificDscCaps[3]; + + if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, + &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason)) + { + return false; + } + + return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps)); +} + void DeviceImpl::queryGUID2() { unsigned sizeCompleted = 0; @@ -1779,21 +1798,6 @@ void DeviceImpl::queryGUID2() } } -bool DeviceImpl::readAndParseBranchSpecificDSCCaps() -{ - unsigned sizeCompleted = 0; - unsigned nakReason = NakUndefined; - NvU8 rawBranchSpecificDscCaps[3]; - - if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, - &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason)) - { - return false; - } - - return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps)); -} - bool DeviceImpl::getDscEnable(bool *pEnable) { AuxBus::status status = AuxBus::success; @@ -1928,7 +1932,8 @@ bool DeviceImpl::setDscEnable(bool enable) unsigned nakReason = NakUndefined; bool bCurrDscEnable = false; bool bDscPassThrough = false; - bool bDscPassThroughUpdated = true; + AuxBus::status dscEnableStatus = AuxBus::success; + AuxBus::status dscPassThroughStatus = AuxBus::success; Address::StringBuffer buffer; DP_USED(buffer); @@ -1938,7 +1943,7 @@ bool DeviceImpl::setDscEnable(bool enable) return false; } - if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL && this->connector->bDscMstEnablePassThrough) + if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL) { // // If the device has a parent, that means the sink is on a MST link and @@ -1948,20 +1953,18 @@ bool DeviceImpl::setDscEnable(bool enable) // bDscPassThrough = true; } - else + + // + // Get Current DSC Enable State + // Ideally we don't need to check the current state but Synaptics DSC device, + // which was used for inital DSC code developement did not follow spec and so + // we have added this code. Overwriting the same value should not have any + // impact as per the spec. Will remove this check once all DSC devices follow spec. + // + if (!getDscEnable(&bCurrDscEnable)) { - // - // Get Current DSC Enable State - // Ideally we don't need to check the current state but Synaptics DSC device, - // which was used for inital DSC code developement did not follow spec and so - // we have added this code. Overwriting the same value should not have any - // impact as per the spec. Will remove this check once all DSC devices follow spec. - // - if (!getDscEnable(&bCurrDscEnable)) - { - DP_LOG(("DP-DEV> Not able to get DSC Enable State!")); - return false; - } + DP_LOG(("DP-DEV> Not able to get DSC Enable State!")); + return false; } if(enable) @@ -1970,7 +1973,7 @@ bool DeviceImpl::setDscEnable(bool enable) { dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscPassthroughByte); DP_LOG(("DP-DEV> Enabling DSC Pass through on branch device - %s", - this->parent->getTopologyAddress().toString(buffer))); + this->parent->getTopologyAddress().toString(buffer))); } if (!bCurrDscEnable) @@ -1983,7 +1986,6 @@ bool DeviceImpl::setDscEnable(bool enable) { DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); - return true; } } else @@ -2005,22 +2007,40 @@ bool DeviceImpl::setDscEnable(bool enable) { DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); - return true; } } if (bDscPassThrough) { - if(this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH, - &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason)) + dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH, + &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason); + if (dscPassThroughStatus != AuxBus::success) + { + DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", + this->parent->getTopologyAddress().toString(buffer))); + } + } + + if (enable != bCurrDscEnable) + { + dscEnableStatus = this->devDoingDscDecompression->setDpcdData(NV_DPCD14_DSC_ENABLE, + &dscEnableByte, sizeof dscEnableByte, &size, &nakReason); + if (dscEnableStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Passthrough state on parent branch failed")); - bDscPassThroughUpdated = false; + DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", + this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); + } } - return (!this->devDoingDscDecompression->setDpcdData(NV_DPCD14_DSC_ENABLE, - &dscEnableByte, sizeof dscEnableByte, &size, &nakReason)) && bDscPassThroughUpdated; + if ((dscPassThroughStatus != AuxBus::success) || (dscEnableStatus != AuxBus::success)) + { + return false; + } + else + { + return true; + } } unsigned DeviceImpl::getDscVersionMajor() @@ -2236,6 +2256,124 @@ bool DeviceImpl::getPCONCaps(PCONCaps *pPCONCaps) return true; } +bool DeviceImpl::getIgnoreMSACap() +{ + NvU8 byte = 0; + unsigned size = 0; + unsigned nakReason = NakUndefined; + AuxBus::status status; + + if (bIgnoreMsaCapCached) + { + return bIgnoreMsaCap; + } + + if (this->isMultistream()) + { + status = this->getDpcdData(NV_DPCD_DOWN_STREAM_PORT, + &byte, sizeof byte, &size, &nakReason); + if (status == AuxBus::success) + { + if(FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _YES, byte)) + { + if (this->parent && this->parent->isVirtualPeerDevice()) + { + byte = 0; + size = 0; + nakReason = NakUndefined; + + status = this->parent->getDpcdData(NV_DPCD_DOWN_STREAM_PORT, + &byte, sizeof byte, &size, &nakReason); + if (status == AuxBus::success) + { + if(FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _YES, byte)) + { + bIgnoreMsaCap = true; + } + else + { + bIgnoreMsaCap = false; + } + bIgnoreMsaCapCached = true; + } + else + { + DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!")); + return false; + } + } + else + { + bIgnoreMsaCap = true; + bIgnoreMsaCapCached = true; + } + } + else + { + bIgnoreMsaCap = false; + bIgnoreMsaCapCached = true; + } + } + else + { + DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!")); + return false; + } + } + else + { + bIgnoreMsaCap = hal->getMsaTimingparIgnored(); + bIgnoreMsaCapCached = true; + } + + return bIgnoreMsaCap; +} + +AuxRetry::status DeviceImpl::setIgnoreMSAEnable(bool msaTimingParamIgnoreEn) +{ + NvU8 byte = 0; + unsigned size = 0; + unsigned nakReason = NakUndefined; + AuxBus::status status; + + if (this->isMultistream()) + { + status = this->getDpcdData(NV_DPCD_DOWNSPREAD_CTRL, + &byte, sizeof byte, &size, &nakReason); + if (status == AuxBus::success) + { + if (msaTimingParamIgnoreEn) + { + byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL, _MSA_TIMING_PAR_IGNORED, _TRUE, byte); + } + else + { + byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL, _MSA_TIMING_PAR_IGNORED, _FALSE, byte); + } + + status = this->setDpcdData(NV_DPCD_DOWNSPREAD_CTRL, + &byte, sizeof byte, &size, &nakReason); + if (status == AuxBus::success) + { + return AuxRetry::ack; + } + else + { + DP_LOG(("DP-DEV> Aux Write to DPCD offset 0x107 failed!")); + return AuxRetry::nack; + } + } + else + { + DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!")); + return AuxRetry::nack; + } + } + else + { + return hal->setIgnoreMSATimingParamters(msaTimingParamIgnoreEn); + } +} void DeviceHDCPDetection::start() diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index c100cf148..c69e4698a 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,8 +94,6 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL}, - {NV_DP_DSC_OPTIMIZE_LT_BUG_3534707, &dpRegkeyDatabase.bDscOptimizeLTBug3534707, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING, &dpRegkeyDatabase.bDpcdProbingForBusyWaiting, DP_REG_VAL_BOOL} }; @@ -1048,6 +1046,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, case EDP_3_24GHZ: case EDP_4_32GHZ: case HBR2: + case EDP_6_75GHZ: case HBR3: linkBw = linkrate / DP_LINK_BW_FREQ_MULTI_MBPS; dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW, @@ -1797,6 +1796,7 @@ bool EvoMainLink::configureLinkRateTable case linkBW_3_24Gbps: case linkBW_4_32Gbps: case linkBW_5_40Gbps: + case linkBW_6_75Gbps: case linkBW_8_10Gbps: pLinkRates->import(params.linkBwTbl[i]); break; diff --git a/src/common/displayport/src/dp_groupimpl.cpp b/src/common/displayport/src/dp_groupimpl.cpp index 80a182d19..35944b7de 100644 --- a/src/common/displayport/src/dp_groupimpl.cpp +++ b/src/common/displayport/src/dp_groupimpl.cpp @@ -177,12 +177,59 @@ void GroupImpl::remove(Device * dev) void GroupImpl::destroy() { + ConnectorImpl* parent = NULL; for (Device * i = enumDevices(0); i; i = enumDevices(i)) remove(i); // Cancel any queue the auth callback. cancelHdcpCallbacks(); + parent = this->parent; + + if (parent) + { + if (!parent->activeGroups.isEmpty()) + { + for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next) + { + GroupImpl * group = (GroupImpl *)i; + if (group == this) + { + parent->activeGroups.remove(this); + DP_LOG(("DP-GRP> Deleted group 0x%x from active group!", this)); + break; + } + } + } + + + if (!parent->inactiveGroups.isEmpty()) + { + for (ListElement * i = parent->inactiveGroups.begin(); i != parent->inactiveGroups.end(); i = i->next) + { + GroupImpl * group = (GroupImpl *)i; + if (group == this) + { + parent->inactiveGroups.remove(this); + DP_LOG(("DP-GRP> Deleted group 0x%x from inactive group!", this)); + break; + } + } + } + + if (parent->intransitionGroups.contains(this)) + { + parent->intransitionGroups.remove(this); + DP_LOG(("DP-GRP> Deleted group 0x%x from intransition group!", this)); + } + + if (parent->addStreamMSTIntransitionGroups.contains(this)) + { + parent->addStreamMSTIntransitionGroups.remove(this); + DP_LOG(("DP-GRP> Deleted group 0x%x from addStreamMSTIntransitionGroups group!", this)); + } + } + delete this; } diff --git a/src/common/displayport/src/dp_messages.cpp b/src/common/displayport/src/dp_messages.cpp index b063a8fc1..961baebc4 100644 --- a/src/common/displayport/src/dp_messages.cpp +++ b/src/common/displayport/src/dp_messages.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/displayport/src/dp_sst_edid.cpp b/src/common/displayport/src/dp_sst_edid.cpp index 3985dba15..76ff92a51 100644 --- a/src/common/displayport/src/dp_sst_edid.cpp +++ b/src/common/displayport/src/dp_sst_edid.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -240,10 +240,13 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer, Edid previousEdid; Buffer *buffer; bool status; - + bool firstTrial = true; + NvU64 startTime, elapsedTime; for (unsigned i = 0; i < ddcAddrListSize; i++) { - for (unsigned j = 0; j < EDID_READ_MAX_RETRY_COUNT; j++) + startTime = timer->getTimeUs(); + elapsedTime = 0; + do { // // Client asks to use RM control code to fetch EDID. @@ -312,9 +315,10 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer, } else { - if (j == 0) // first failure? + if (firstTrial) // first failure? { previousEdid.swap(edid); + firstTrial = false; } else { @@ -327,7 +331,9 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer, } } } - } + elapsedTime = timer->getTimeUs() - startTime; + timer->sleep(1); + } while (elapsedTime < (EDID_READ_RETRY_TIMEOUT_MS * 1000)); } DP_LOG(("EDID> Failed to ping sst DDC addresses")); diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index de37a1cd9..7fcd9aed2 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -104,6 +104,7 @@ typedef enum linkBW_3_24Gbps = 0x0C, linkBW_4_32Gbps = 0x10, linkBW_5_40Gbps = 0x14, + linkBW_6_75Gbps = 0x19, linkBW_8_10Gbps = 0x1E, linkBW_Supported } DP_LINK_BANDWIDTH; @@ -118,6 +119,7 @@ typedef enum linkSpeedId_2_43Gbps = 0x05, linkSpeedId_3_24Gbps = 0x06, linkSpeedId_4_32Gbps = 0x07, + linkSpeedId_6_75Gbps = 0x08, linkSpeedId_Supported } DP_LINK_SPEED_INDEX; @@ -535,7 +537,8 @@ typedef struct PanelReplayConfig #define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \ ((NvU32)(val)==linkBW_2_43Gbps) || \ ((NvU32)(val)==linkBW_3_24Gbps) || \ - ((NvU32)(val)==linkBW_4_32Gbps)) + ((NvU32)(val)==linkBW_4_32Gbps) || \ + ((NvU32)(val)==linkBW_6_75Gbps)) #define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \ IS_INTERMEDIATE_LINKBW(val)) diff --git a/src/common/inc/displayport/dpcd.h b/src/common/inc/displayport/dpcd.h index 0e3909535..50bd544a7 100644 --- a/src/common/inc/displayport/dpcd.h +++ b/src/common/inc/displayport/dpcd.h @@ -1364,12 +1364,10 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_1_STATUS_IN_SYNC_YES (0x00000001) /* R-XUV */ // 0x00002010-0x0002025: RESERVED. Read all 0s - #define NV_DPCD_OVERDRIVE_STATUS (0x00002026) /* R-XUR */ #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS 0:0 /* R-XUF */ #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_NOT_ACTIVE (0x00000000) /* R-XUV */ #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_ACTIVE (0x00000001) /* R-XUV */ - // 0x00002027-0x00067FF: RESERVED. Read all 0s #define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000) /* R-XUR */ diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index 1d3e31e51..2c523a02e 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -47,7 +47,7 @@ #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) -/// BRANCH SPECIFIC DSC CAPS +// BRANCH SPECIFIC DSC CAPS #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 @@ -55,5 +55,4 @@ #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 #define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 - +#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 \ No newline at end of file diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 3db404ab5..374e29e89 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r515_00 + #define NV_BUILD_BRANCH r521_82 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r515_00 + #define NV_PUBLIC_BRANCH r521_82 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_00-409" -#define NV_BUILD_CHANGELIST_NUM (31799928) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r520/r521_82-338" +#define NV_BUILD_CHANGELIST_NUM (31864828) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_00-409" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31799928) +#define NV_BUILD_NAME "rel/gpu_drv/r520/r521_82-338" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31864828) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r515_00-323" -#define NV_BUILD_CHANGELIST_NUM (31799928) +#define NV_BUILD_BRANCH_VERSION "r521_82-4" +#define NV_BUILD_CHANGELIST_NUM (31858738) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "517.40" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31799928) -#define NV_BUILD_BRANCH_BASE_VERSION R515 +#define NV_BUILD_NAME "522.06" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31858738) +#define NV_BUILD_BRANCH_BASE_VERSION R520 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index d4eba52cc..05c53fa3b 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "515.76" +#define NV_VERSION_STRING "520.61.05" #else diff --git a/src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h b/src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h index af02ce8f5..241378979 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h @@ -28,15 +28,11 @@ #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */ #define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */ #define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */ #define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */ diff --git a/src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h b/src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h index 70e3aa252..5bfa1c1b2 100644 --- a/src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h +++ b/src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h @@ -28,15 +28,11 @@ #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */ #define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */ #define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */ #define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */ diff --git a/src/common/inc/swref/published/disp/v04_00/dev_disp.h b/src/common/inc/swref/published/disp/v04_00/dev_disp.h index 1b03f75c9..68e068d59 100644 --- a/src/common/inc/swref/published/disp/v04_00/dev_disp.h +++ b/src/common/inc/swref/published/disp/v04_00/dev_disp.h @@ -29,6 +29,10 @@ #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R---V */ #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */ #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(i) (0x00611C00+(i)*4) /* R--4A */ +#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA 1:1 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */ #define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_ce.h b/src/common/inc/swref/published/hopper/gh100/dev_ce.h new file mode 100644 index 000000000..6c3f3f6fc --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_ce.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_ce_h__ +#define __gh100_dev_ce_h__ +#define NV_CE_PCE2LCE_CONFIG__SIZE_1 16 +#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */ +#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */ +#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */ +#endif // __gh100_dev_ce_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h b/src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h new file mode 100644 index 000000000..78f372bb1 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_falcon_v4_h__ +#define __gh100_dev_falcon_v4_h__ + +#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */ +#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */ +#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ + +#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */ +#define NV_PFALCON_FALCON_OS__DEVICE_MAP 0x00000013 /* */ +#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ + +#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */ +#define NV_PFALCON_FALCON_HWCFG2_SHA 0:0 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_VHR 7:7 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_HS 8:8 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR 15:15 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SCP 16:16 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_SCP_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SCP_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_GDMA 17:17 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_GDMA_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_GDMA_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SE_LITE 18:18 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG2_SE_LITE_ENABLE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_SE_LITE_DISABLE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_HWCFG2_PRGN_RSVD_FUSE 31:24 /* R-IVF */ +#define NV_PFALCON_FALCON_HWCFG2_PRGN_RSVD_FUSE_DEFAULT 0x00000000 /* R-I-V */ + +#endif // __gh100_dev_falcon_v4_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fault.h b/src/common/inc/swref/published/hopper/gh100/dev_fault.h new file mode 100644 index 000000000..a85faa6e8 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fault.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fault_h__ +#define __gh100_dev_fault_h__ + +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */ + +#endif // __gh100_dev_fault_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fb.h b/src/common/inc/swref/published/hopper/gh100/dev_fb.h new file mode 100644 index 000000000..8bcb21316 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fb.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fb_h +#define __gh100_dev_fb_h_ +#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */ +#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */ +#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */ +#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */ +#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ +#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */ +#endif // __gh100_dev_fb_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h new file mode 100644 index 000000000..137fbe6ac --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fsp_addendum_h__ +#define __gh100_dev_fsp_addendum_h__ + +// +// RM uses channel 0 for FSP EMEM on GH100. +// +#define FSP_EMEM_CHANNEL_RM 0x0 + +// +// PMU/SOE use channel 4 for FSP EMEM on GH100. +// +#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 +#define FSP_EMEM_CHANNEL_MAX 0x8 + +// EMEM channel 0 (RM) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_RM_SIZE 1024 + +// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 +#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 + +// +// MCTP (Management Component Transport Protocol) overlayed on NVDM (NVIDIA Data +// Model) is the mechanism used between FSP management partition and CPU-RM. +// + +#define MCTP_HEADER_RSVD 7:4 +#define MCTP_HEADER_VERSION 3:0 + +#define MCTP_HEADER_DEID 15:8 + +#define MCTP_HEADER_SEID 23:16 + +#define MCTP_HEADER_SOM 31:31 +#define MCTP_HEADER_EOM 30:30 +#define MCTP_HEADER_SEQ 29:28 +#define MCTP_HEADER_TO 27:27 +#define MCTP_HEADER_TAG 26:24 + +#define MCTP_MSG_HEADER_IC 7:7 +#define MCTP_MSG_HEADER_TYPE 6:0 +#define MCTP_MSG_HEADER_VENDOR_ID 23:8 +#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 + +#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e +#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de + +#define NVDM_TYPE_HULK 0x11 +#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 +#define NVDM_TYPE_COT 0x14 +#define NVDM_TYPE_FSP_RESPONSE 0x15 +#define NVDM_TYPE_INFOROM 0x17 +#define NVDM_TYPE_SMBPBI 0x18 + +#endif // __gh100_dev_fsp_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h b/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h new file mode 100644 index 000000000..6debb1627 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_fsp_pri_h__ +#define __gh100_dev_fsp_pri_h__ + +#define NV_PFSP_EMEMC(i) (0x008F2ac0+(i)*8) /* RW-4A */ +#define NV_PFSP_EMEMC__SIZE_1 8 /* */ +#define NV_PFSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PFSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PFSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PFSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PFSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PFSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PFSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PFSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PFSP_EMEMD(i) (0x008F2ac4+(i)*8) /* RW-4A */ +#define NV_PFSP_EMEMD__SIZE_1 8 /* */ +#define NV_PFSP_EMEMD_DATA 31:0 /* RWXVF */ + +#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */ +#define NV_PFSP_MSGQ_HEAD__SIZE_1 8 /* */ +#define NV_PFSP_MSGQ_HEAD_VAL 31:0 /* RWIUF */ +#define NV_PFSP_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */ +#define NV_PFSP_MSGQ_TAIL__SIZE_1 8 /* */ +#define NV_PFSP_MSGQ_TAIL_VAL 31:0 /* RWIUF */ +#define NV_PFSP_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */ + +#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */ +#define NV_PFSP_QUEUE_HEAD__SIZE_1 8 /* */ +#define NV_PFSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ +#define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */ +#define NV_PFSP_QUEUE_TAIL__SIZE_1 8 /* */ +#define NV_PFSP_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */ +#define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */ + +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ + +#endif // __gh100_dev_fsp_pri_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h new file mode 100644 index 000000000..fec06073b --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_gc6_island_h__ +#define __gh100_dev_gc6_island_h__ + +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0 0x00118df4 /* RW-4R */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE 0:0 /* RWEVF */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE 0x00000000 /* R-E-V */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_TRIGGER 0x00000001 /* -W--T */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_NSEC 31:5 /* RWEUF */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_NSEC_ZERO 0x00000000 /* RWE-V */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1 0x00118df8 /* RW-4R */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC 28:0 /* RWEUF */ +#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO 0x00000000 /* RWE-V */ + +#endif // __gh100_dev_gc6_island_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h new file mode 100644 index 000000000..524252495 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_gc6_island_addendum_h__ +#define __gh100_dev_gc6_island_addendum_h__ + +#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100 + +#endif // __gh100_dev_gc6_island_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h new file mode 100644 index 000000000..0e9125ccc --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_gsp_h__ +#define __gh100_dev_gsp_h__ +#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */ +#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWEVF */ +#define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT 0 /* */ +#define NV_PGSP_FALCON_ENGINE_RESET_ASSERT 1 /* */ +#define NV_PGSP_FALCON_ENGINE_RESET_STATUS 10:8 /* R-EVF */ +#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */ +#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */ +#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */ +#endif // __gh100_dev_gsp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_mmu.h b/src/common/inc/swref/published/hopper/gh100/dev_mmu.h new file mode 100644 index 000000000..72c01164d --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_mmu.h @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_mmu_h__ +#define __gh100_dev_mmu_h__ + + +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_KIND (1*32+7):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */ +#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */ +#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */ + +#define NV_MMU_VER3_PDE /* ----G */ +#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PDE__SIZE 8 + +#define NV_MMU_VER3_DUAL_PDE /* ----G */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER3_DUAL_PDE__SIZE 16 + +#define NV_MMU_VER3_PTE /* ----G */ +#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */ +#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE 0x0000000A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE 0x0000000B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE 0x0000000E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000F /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD 0x00000013 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD 0x00000014 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD 0x00000015 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD 0x00000016 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD 0x00000017 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD 0x0000001A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD 0x0000001B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD 0x0000001E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */ +#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PTE__SIZE 8 + + +#endif // __gh100_dev_mmu_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h new file mode 100644 index 000000000..34571d6c0 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_nv_xal_addendum_h__ +#define __gh100_dev_nv_xal_addendum_h__ + +#define NV_XAL_EP_MEMOP_TOKEN_SIZE 31 +#define NV_XAL_EP_MEMOP_TOKEN_MAX_ISSUED 4 +#define NV_XAL_EP_MEMOP_MAX_OUTSTANDING 140 + +#endif // __gh100_dev_nv_xal_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_pmc.h b/src/common/inc/swref/published/hopper/gh100/dev_pmc.h new file mode 100644 index 000000000..aeade578d --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_pmc.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_pmc_h__ +#define __gh100_dev_pmc_h__ +#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ +#endif // __gh100_dev_pmc_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_ram.h b/src/common/inc/swref/published/hopper/gh100/dev_ram.h new file mode 100644 index 000000000..edd0b2c3d --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_ram.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_ram_h__ +#define __gh100_dev_ram_h__ +#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ +#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (19+1*32):(0+1*32) /* RWXUF */ +#endif // __gh100_dev_ram_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_riscv_pri.h b/src/common/inc/swref/published/hopper/gh100/dev_riscv_pri.h new file mode 100644 index 000000000..a1d32e033 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_riscv_pri.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_riscv_pri_h__ +#define __gh100_dev_riscv_pri_h__ + +#define NV_PRISCV_RISCV_BCR_DMACFG 0x0000066c /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET 1:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_LOCAL_FB 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* RW--V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_IO 0x00000003 /* RW--V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING 28:28 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING_FALSE 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING_TRUE 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK 31:31 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_LOCKED 0x00000001 /* RW--V */ + +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO 0x00000670 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL 31:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI 0x00000674 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL 11:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO 0x00000678 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL 31:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI 0x0000067c /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL 11:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO 0x00000680 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL 31:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI 0x00000684 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL 11:0 /* RWIVF */ +#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT 0x00000000 /* RWI-V */ + +#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */ +#define NV_PRISCV_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */ +#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */ +#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ +#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */ +#define NV_PRISCV_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */ +#define NV_PRISCV_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ +#define NV_PRISCV_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ +#define NV_PRISCV_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */ +#define NV_PRISCV_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */ +#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */ + +#endif // __gh100_dev_riscv_pri_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_therm.h b/src/common/inc/swref/published/hopper/gh100/dev_therm.h new file mode 100644 index 000000000..330e43aa0 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_therm.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_therm_h__ +#define __gh100_dev_therm_h__ + +#define NV_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */ +#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */ +#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */ + +#endif // __gh100_dev_therm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_therm_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_therm_addendum.h new file mode 100644 index 000000000..6d712f4f0 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_therm_addendum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_dev_therm_addendum_h__ +#define __gh100_dev_therm_addendum_h__ + +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0 +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000 + +#endif // __gh100_dev_therm_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_timer.h b/src/common/inc/swref/published/hopper/gh100/dev_timer.h new file mode 100644 index 000000000..095eaf860 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_timer.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_timer_h__ +#define __gh100_dev_timer_h__ + +#define NV_PTIMER_TIME_PRIV_LEVEL_MASK 0x00009430 /* RW-4R */ +#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ +#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 +#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 +#define NV_PTIMER_TIME_0_NSEC 31:5 /* R-XUF */ + +#endif // __gh100_dev_timer_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm.h b/src/common/inc/swref/published/hopper/gh100/dev_vm.h new file mode 100644 index 000000000..c30650123 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_vm_h__ +#define __gh100_dev_vm_h__ +#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */ +#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE 0x00000F10 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED 0x00000F14 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE 0x00000F18 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED 0x00000F1C /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 16 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 16 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */ + +#endif // __gh100_dev_vm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h new file mode 100644 index 000000000..edb6dbe5e --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_vm_addendum_h__ +#define __gh100_dev_vm_addendum_h__ + +// +// Compile time asserts in the source code files will ensure that +// these don't end up exceeding the range of the top level registers. +// + +// Subtrees at CPU_INTR top level for UVM owned interrupts +#define NV_CPU_INTR_UVM_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1) +#define NV_CPU_INTR_UVM_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1) + +#define NV_CPU_INTR_UVM_SHARED_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2) +#define NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2) + +// +// Subtrees at CPU_INTR top level for all stall interrupts from host-driven +// engines +// +#define NV_CPU_INTR_STALL_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3) +#define NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(4) +#define NV_CPU_INTR_STALL_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5) + +// +// CPU doorbell can be anything on GH100+! Define them the same as +// pre-GH100 for compatibility +// +#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 0x00000081 + +#endif // __gh100_dev_vm_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h new file mode 100644 index 000000000..bd968a72f --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__ +#define __gh100_dev_xtl_ep_pcfg_gpu_h__ +#define NV_EP_PCFG_GPU_ID 0x00000000 /* R--4R */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */ +#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */ +#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */ +#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */ +#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */ +#define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */ +#define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */ +#define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES 0x00000064 /* R--4R */ +#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED 5:5 /* R-IVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS 0x00000068 /* RW-4R */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_EP_PCFG_GPU_LINK_CAPABILITIES 0x0000006C /* R--4R */ +#define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS 0x00000070 /* RW-4R */ +#define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS_CURRENT_LINK_SPEED 19:16 /* R-EVF */ +#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER 0x000000B0 /* RW-4R */ +#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE 31:31 /* RWIVF */ +#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE_ENABLED 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS 0x000001BC /* RW-4R */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_DL_PROTOCOL_ERROR 4:4 /* RWCVF */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RCVD 12:12 /* RWCVF */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT 14:14 /* RWCVF */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION 16:16 /* RWCVF */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP 18:18 /* RWCVF */ +#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR 20:20 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS 0x000001C8 /* RW-4R */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR 0:0 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_TLP 6:6 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_DLLP 7:7 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER 8:8 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT 12:12 /* RWCVF */ +#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR 13:13 /* RWCVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_POD 0:0 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_SCPM 1:1 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_SCPM 2:2 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_SCPM 3:3 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_DCLS 4:4 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_DCLS 5:5 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_GSP_DCLS 6:6 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PMU_DCLS 7:7 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEQ_TOO_BIG 8:8 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRE_IFF_CRC 9:9 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_POST_IFF_CRC 10:10 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ECC 11:11 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_CMD 12:12 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRI 13:13 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG 14:14 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */ +#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */ +#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h new file mode 100644 index 000000000..db96d0b6e --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_xtl_ep_pri_h__ +#define __gh100_dev_xtl_ep_pri_h__ +#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */ +#endif // __gh100_dev_xtl_ep_pri_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/hwproject.h b/src/common/inc/swref/published/hopper/gh100/hwproject.h new file mode 100644 index 000000000..4fda40527 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/hwproject.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52 diff --git a/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h new file mode 100644 index 000000000..ff1576dbe --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_pri_nv_xal_ep_h__ +#define __gh100_pri_nv_xal_ep_h__ +#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010 +#define NV_XAL_EP_BAR0_WINDOW_BASE 21:0 +#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY 0x0010f810 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN 30:0 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED 0x0010f814 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31 +#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1 +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0010f80c +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0 +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31 +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1 +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808 +#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0 +#define NV_XAL_EP_INTR_0 0x0010f100 +#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5 +#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1 +#define NV_XAL_EP_INTR_0_PRI_FECSERR 1:1 +#define NV_XAL_EP_INTR_0_PRI_FECSERR_PENDING 0x1 +#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT 2:2 +#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT_PENDING 0x1 +#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3 +#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1 +#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200 +#endif // __gh100_pri_nv_xal_ep_h__ + diff --git a/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h new file mode 100644 index 000000000..b3a5ffd9f --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __gh100_pri_nv_xal_ep_p2p_h__ +#define __gh100_pri_nv_xal_ep_p2p_h__ +#define NV_XAL_EP_P2P 0x00827fff:0x00826000 +#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR 22:1 +#define NV_XAL_EP_P2P_WREQMB_L(i) (0x00826200+(i)*64) /* R--4A */ +#define NV_XAL_EP_P2P_WREQMB_L__SIZE_1 8 /* */ +#define NV_XAL_EP_P2P_WREQMB_L__PRIV_LEVEL_MASK 0x00826900 /* */ +#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR 21:0 /* R-IUF */ +#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR_INIT 0x000000 /* R-I-V */ +#define NV_XAL_EP_P2P_WREQMB_H(i) (0x00826204+(i)*64) /* R--4A */ +#define NV_XAL_EP_P2P_WREQMB_H__SIZE_1 8 /* */ +#define NV_XAL_EP_P2P_WREQMB_H__PRIV_LEVEL_MASK 0x00826900 /* */ +#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR 31:0 /* R-IUF */ +#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT 0x00000000 /* R-I-V */ +#endif // __gh100_pri_nv_xal_ep_p2p_h__ diff --git a/src/common/inc/swref/published/nv_arch.h b/src/common/inc/swref/published/nv_arch.h index 99db0eee6..507ce6f1d 100644 --- a/src/common/inc/swref/published/nv_arch.h +++ b/src/common/inc/swref/published/nv_arch.h @@ -24,6 +24,8 @@ #ifndef NV_ARCH_PUBLISHED_H #define NV_ARCH_PUBLISHED_H +#include "nvcfg_sdk.h" + // high byte indicates GPU-SERIES, as defined in Gpus.pm. #define NVGPU_ARCHITECTURE_SERIES 31:24 #define NVGPU_ARCHITECTURE_SERIES_CLASSIC 0x00 @@ -44,6 +46,9 @@ #define GPU_ARCHITECTURE_VOLTA2 GPU_ARCHITECTURE(_CLASSIC, 0x0150) #define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160) #define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170) +#define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180) + +#define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190) #define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040) #define GPU_ARCHITECTURE_T13X GPU_ARCHITECTURE(_TEGRA, 0x0013) @@ -89,6 +94,15 @@ #define GPU_IMPLEMENTATION_GA107 0x07 #define GPU_IMPLEMENTATION_GA102F 0x0F +#define GPU_IMPLEMENTATION_GH100 0x00 + + +#define GPU_IMPLEMENTATION_AD102 0x02 + +#define GPU_IMPLEMENTATION_AD103 0x03 + +#define GPU_IMPLEMENTATION_AD104 0x04 + #define GPU_IMPLEMENTATION_T124 0x00 #define GPU_IMPLEMENTATION_T132 0x00 #define GPU_IMPLEMENTATION_T210 0x00 diff --git a/src/common/inc/swref/published/nv_ref.h b/src/common/inc/swref/published/nv_ref.h index cf05badc3..1ca011257 100644 --- a/src/common/inc/swref/published/nv_ref.h +++ b/src/common/inc/swref/published/nv_ref.h @@ -127,6 +127,8 @@ #define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */ #define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */ #define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GH100 0x00000018 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_AD100 0x00000019 /* R---V */ #define NV_PMC_BOOT_1 0x00000004 /* R--4R */ #define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */ diff --git a/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h b/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h index 4543f22c8..58cfd6fc3 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h +++ b/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h @@ -28,15 +28,11 @@ #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ -#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */ #define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-XVF */ #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-XVF */ #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-XVF */ -#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */ #define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */ #define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */ diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.c b/src/common/modeset/hdmipacket/nvhdmipkt.c index 0a843bbde..f544d0790 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt.c @@ -25,6 +25,7 @@ * Purpose: Provide initialization functions for HDMI library */ +#include #include "nvlimits.h" #include "nvhdmipkt_common.h" #include "nvhdmipkt_class.h" @@ -46,6 +47,7 @@ #include "class/clc57d.h" #include "class/clc670.h" #include "class/clc67d.h" +#include "class/clc770.h" // Class hierarchy structure typedef struct tagNVHDMIPKT_CLASS_HIERARCHY @@ -167,6 +169,16 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NVC670_DISPLAY, // displayClass NVC67D_CORE_CHANNEL_DMA // coreDmaClass }, + {// Index 8==NVHDMIPKT_C771_CLASS + NVHDMIPKT_C771_CLASS, // classId + NVHDMIPKT_C671_CLASS, // parentClassId + NV_FALSE, // isRootClass + initializeHdmiPktInterfaceC771, // initInterface + hdmiConstructorC771, // constructor + hdmiDestructorC771, // destructor + NVC770_DISPLAY, // displayClass + NVC67D_CORE_CHANNEL_DMA // coreDmaClass + }, }; #if defined(DSC_CALLBACK_MODIFIED) @@ -234,6 +246,11 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle, return NVHDMIPKT_LIBRARY_INIT_FAIL; } + if ((pPacket == NULL) || (packetLen == 0)) + { + return NVHDMIPKT_INVALID_ARG; + } + return pClass->hdmiPacketWrite(pClass, subDevice, displayId, diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.h b/src/common/modeset/hdmipacket/nvhdmipkt.h index 35b2fbdc3..aff0311ba 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt.h @@ -70,6 +70,12 @@ typedef enum _NVHDMIPKT_TYPE NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME = 4, // VSI NVHDMIPKT_TYPE_AUDIO_INFOFRAME = 5, // Audio InfoFrame NVHDMIPKT_TYPE_EXTENDED_METADATA_PACKET = 6, // Extended Metadata Packet (HDMI 2.1) + NVHDMIPKT_TYPE_SHARED_GENERIC1 = 7, // ADA+ Specifc shared generic infoframe 1~6 + NVHDMIPKT_TYPE_SHARED_GENERIC2 = 8, + NVHDMIPKT_TYPE_SHARED_GENERIC3 = 9, + NVHDMIPKT_TYPE_SHARED_GENERIC4 = 10, + NVHDMIPKT_TYPE_SHARED_GENERIC5 = 11, + NVHDMIPKT_TYPE_SHARED_GENERIC6 = 12, NVHDMIPKT_INVALID_PKT_TYPE = 13 } NVHDMIPKT_TYPE; @@ -99,6 +105,11 @@ typedef enum _NVHDMIPKT_TYPE #define NV_HDMI_PKT_TRANSMIT_CTRL_VIDEO_FMT_SW_CTRL 0x00000000 #define NV_HDMI_PKT_TRANSMIT_CTRL_VIDEO_FMT_HW_CTRL 0x00000001 +#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC 7:6 +#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_VBLANK 0x00000000 +#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_VSYNC 0x00000001 +#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_LOADV 0x00000002 + // NVHDMIPKT_TC: HDMI Packet Transmit Control // NOTE: Client should use these defines below for transmit control, and avoid using the ones // above. Use only if client knows and wants fine control. And in that case the value @@ -132,6 +143,29 @@ typedef enum _NVHDMIPKT_TC NVHDMIPKT_TRANSMIT_CONTROL_VIDEO_FMT_HW_CTRL = (DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _VIDEO_FMT, _HW_CTRL)), + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_LOADV= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV)), + + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_LOADV= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV)), + + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_VSYNC= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC)), + + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_VSYNC= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC)), + + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_VBLANK= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK)), + + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_VBLANK= + (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK)), } NVHDMIPKT_TC; // RM client handles. Used when client chooses that hdmi library make RM calls. diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c index 0e1bae8b4..a5baf8bf2 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c @@ -109,6 +109,12 @@ hdmiPacketWrite0073(NVHDMIPKT_CLASS* pThis, NvU8 const *const pPacket) { NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; + + if (packetLen > NV0073_CTRL_SET_OD_MAX_PACKET_SIZE) + { + return NVHDMIPKT_INVALID_ARG; + } + NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = {0}; NVMISC_MEMSET(¶ms, 0, sizeof(params)); diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c index eb7d399b2..3c96934f9 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c @@ -282,12 +282,9 @@ hdmiWriteVendorPacket9171(NVHDMIPKT_CLASS* pThis, NvU32* pBaseReg, NvU32 head, NvU32 packetLen, - NvU8 const *const pPacketIn) + NvU8 const *const pPacket) { NvU32 data = 0; - NvU8 pPacket[31] = {0}; - - NVMISC_MEMCPY(pPacket, pPacketIn, packetLen); data = REG_RD32(pBaseReg, NV9171_SF_HDMI_VSI_HEADER(head)); data = FLD_SET_DRF_NUM(9171, _SF_HDMI_VSI_HEADER, _HB0, pPacket[0], data); @@ -515,6 +512,41 @@ checkPacketStatus(NVHDMIPKT_CLASS* pThis, return result; } +static NVHDMIPKT_RESULT +validateInputPacketLength(NvU32 pktType9171, + NvU32 packetLen, + NvU8 const *const pPacketIn) +{ + NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; + HDMI_PACKET_TYPE infoframeType = pPacketIn[0]; + + // Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent, + // check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need + // additional checksum byte (library clients take care of adding checksum byte if needed) + if (((infoframeType == hdmi_pktType_GeneralControl) && (packetLen < 6)) || + ((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) || + ((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))|| + ((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) || + ((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) || + ((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) || + ((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME)))) + // Unused: hdmi_pktType_AudioClkRegeneration + // Unused: hdmi_pktType_MpegSrcInfoFrame + { + result = NVHDMIPKT_INVALID_ARG; + } + + // Upper bound check. Check against number of bytes possible on the hw infoframe unit + if (((pktType9171 == NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME) && (packetLen > 17)) || // 3 bytes header + 14 bytes data + ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME) && (packetLen > 31)) || // 3 bytes header + 28 bytes data + ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_VSI) && (packetLen > 31))) // 3 bytes header + 28 bytes data + { + result = NVHDMIPKT_INVALID_ARG; + } + + return result; +} + /* * hdmiPacketWrite9171 */ @@ -526,7 +558,7 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, NVHDMIPKT_TYPE packetType, NVHDMIPKT_TC transmitControl, NvU32 packetLen, - NvU8 const *const pPacket) + NvU8 const *const pPacketIn) { NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase; @@ -534,13 +566,26 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, NvU32 tc = pThis->translateTransmitControl(pThis, transmitControl); NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS params = {0}; - if (pBaseReg == 0 || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 || - packetLen == 0 || pPacket == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE) + // packetIn can be of varying size. Use a fixed max size buffer for programing hw units to prevent out of bounds access + NvU8 pPacket[31] = {0}; + + if (pBaseReg == 0 || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 || + packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE) { result = NVHDMIPKT_INVALID_ARG; goto hdmiPacketWrite9171_exit; } + if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS) + { + NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect"); + NvHdmiPkt_Assert(0); + goto hdmiPacketWrite9171_exit; + } + + // input packet looks ok to use, copy over the bytes + NVMISC_MEMCPY(pPacket, pPacketIn, packetLen); + // acquire mutex pThis->callback.acquireMutex(pThis->cbHandle); diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_C771.c b/src/common/modeset/hdmipacket/nvhdmipkt_C771.c new file mode 100644 index 000000000..34064caa5 --- /dev/null +++ b/src/common/modeset/hdmipacket/nvhdmipkt_C771.c @@ -0,0 +1,306 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * File: nvhdmipkt_C771.c + * + * Purpose: Provides packet write functions for HDMI library for ADA+ chips + */ + +#include "nvhdmipkt_common.h" +#include "nvhdmipkt_class.h" + +#include "nvhdmipkt_internal.h" + +#include "class/clc771.h" + +extern NVHDMIPKT_RESULT hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, + NvU32 subDevice, + NvU32 displayId, + NvU32 head, + NVHDMIPKT_TYPE packetType, + NVHDMIPKT_TC transmitControl, + NvU32 packetLen, + NvU8 const *const pPacket); + +extern NVHDMIPKT_RESULT hdmiPacketCtrl9171(NVHDMIPKT_CLASS* pThis, + NvU32 subDevice, + NvU32 displayId, + NvU32 head, + NVHDMIPKT_TYPE packetType, + NVHDMIPKT_TC transmitControl); + +static NvU32 +translateTransmitControlC771(NVHDMIPKT_CLASS* pThis, + NVHDMIPKT_TC transmitControl) +{ + NvU32 tc = 0; + + if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _ENABLE, _YES, tc); + } + + if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _EN, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _SINGLE, _YES, tc); + } + + if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _EN, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _CHECKSUM_HW, _YES, tc); + } + + if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _VBLANK, tc); + } + else if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _VSYNC, tc); + } + else if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV, transmitControl)) + { + tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _LOADV, tc); + } + + return tc; +} + +static NVHDMIPKT_RESULT +hdmiWritePacketCtrlC771(NVHDMIPKT_CLASS* pThis, + NvU32* pBaseReg, + NvU32 head, + NvU32 pktTypeC771, + NvU32 transmitControl, + NvBool bDisable) +{ + NvU32 regOffset = 0; + NvU32 hdmiCtrl = 0; + NvU32 sharedGenericIdx = pktTypeC771; + + // This function only handles shared generic infoframe ctrl. + if (pBaseReg == 0 || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 || + sharedGenericIdx >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2) + { + return NVHDMIPKT_INVALID_ARG; + } + + regOffset = NVC771_SF_SHARED_GENERIC_CTRL(head, sharedGenericIdx); + hdmiCtrl = REG_RD32(pBaseReg, regOffset); + hdmiCtrl = (bDisable == NV_TRUE) ? + (FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _ENABLE, _NO, hdmiCtrl)) : + (transmitControl); + REG_WR32(pBaseReg, regOffset, hdmiCtrl); + + return NVHDMIPKT_SUCCESS; +} + +static NVHDMIPKT_RESULT +hdmiPacketCtrlC771(NVHDMIPKT_CLASS* pThis, + NvU32 subDevice, + NvU32 displayId, + NvU32 head, + NVHDMIPKT_TYPE packetType, + NVHDMIPKT_TC transmitControl) +{ + NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; + NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase; + + if (pBaseReg == 0 || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 + || packetType >= NVHDMIPKT_INVALID_PKT_TYPE) + { + return NVHDMIPKT_INVALID_ARG; + } + + NvU32 tc = 0; + switch (packetType) + { + case NVHDMIPKT_TYPE_SHARED_GENERIC1: + case NVHDMIPKT_TYPE_SHARED_GENERIC2: + case NVHDMIPKT_TYPE_SHARED_GENERIC3: + case NVHDMIPKT_TYPE_SHARED_GENERIC4: + case NVHDMIPKT_TYPE_SHARED_GENERIC5: + case NVHDMIPKT_TYPE_SHARED_GENERIC6: + tc = translateTransmitControlC771(pThis, transmitControl); + result = hdmiWritePacketCtrlC771(pThis, pBaseReg, head, packetType - NVHDMIPKT_TYPE_SHARED_GENERIC1, tc, NV_FALSE); + break; + default: + result = hdmiPacketCtrl9171(pThis, subDevice, displayId, head, packetType, transmitControl); + break; + } + return result; +} + +static NVHDMIPKT_RESULT +hdmiWriteSharedGenericPacketC771(NVHDMIPKT_CLASS* pThis, + NvU32 subDevice, + NvU32 displayId, + NvU32 head, + NvU32 pktTypeC771, + NVHDMIPKT_TC transmitControl, + NvU32 packetLen, + NvU8 const *const pPacketIn) +{ + NvU32 sharedGenericIdx = pktTypeC771; + NvU32 data = 0; + NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase; + NvU32 tc = translateTransmitControlC771(pThis, transmitControl); + NvU8 pPacket[36] = {0}; + + if (pBaseReg == 0 || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 || + packetLen == 0 || (packetLen > 36) || pPacketIn == 0 || sharedGenericIdx >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2) + { + return NVHDMIPKT_INVALID_ARG; + } + + // In case client doesn't guarantee input pkt length to be 9 DWORDs, create a local buffer to avoid out of bound access of input + NVMISC_MEMCPY(pPacket, pPacketIn, packetLen); + + // Disable this packet type. + hdmiWritePacketCtrlC771(pThis, pBaseReg, head, sharedGenericIdx, tc, NV_TRUE); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB0, pPacket[0], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB1, pPacket[1], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB2, pPacket[2], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB3, pPacket[3], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB0, pPacket[4], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB1, pPacket[5], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB2, pPacket[6], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB3, pPacket[7], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB4, pPacket[8], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB5, pPacket[9], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB6, pPacket[10], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB7, pPacket[11], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB8, pPacket[12], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB9, pPacket[13], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB10, pPacket[14], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB11, pPacket[15], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB12, pPacket[16], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB13, pPacket[17], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB14, pPacket[18], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB15, pPacket[19], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB16, pPacket[20], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB17, pPacket[21], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB18, pPacket[22], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB19, pPacket[23], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB20, pPacket[24], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB21, pPacket[25], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB22, pPacket[26], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB23, pPacket[27], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB24, pPacket[28], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB25, pPacket[29], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB26, pPacket[30], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB27, pPacket[31], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(head, sharedGenericIdx), data); + + data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(head, sharedGenericIdx)); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB28, pPacket[32], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB29, pPacket[33], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB30, pPacket[34], data); + data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB31, pPacket[35], data); + REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(head, sharedGenericIdx), data); + + // Enable this infoframe. + hdmiWritePacketCtrlC771(pThis, pBaseReg, head, sharedGenericIdx, tc, NV_FALSE); + + return NVHDMIPKT_SUCCESS; +} + +static NVHDMIPKT_RESULT +hdmiPacketWriteC771(NVHDMIPKT_CLASS* pThis, + NvU32 subDevice, + NvU32 displayId, + NvU32 head, + NVHDMIPKT_TYPE packetType, + NVHDMIPKT_TC transmitControl, + NvU32 packetLen, + NvU8 const *const pPacketIn) +{ + NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; + + if (head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 || + packetLen == 0 || + pPacketIn == 0 || + packetType >= NVHDMIPKT_INVALID_PKT_TYPE) + { + return NVHDMIPKT_INVALID_ARG; + } + + if (packetType >= NVHDMIPKT_TYPE_SHARED_GENERIC1 && packetType <= NVHDMIPKT_TYPE_SHARED_GENERIC6) + { + result = hdmiWriteSharedGenericPacketC771(pThis, subDevice, displayId, head, packetType - NVHDMIPKT_TYPE_SHARED_GENERIC1, transmitControl, packetLen, pPacketIn); + } + else + { + result = hdmiPacketWrite9171(pThis, subDevice, displayId, head, packetType, transmitControl, packetLen, pPacketIn); + } + + return result; +} + +// non-HW - class utility/maintenance functions +NvBool +hdmiConstructorC771(NVHDMIPKT_CLASS* pThis) +{ + NvBool result = NV_TRUE; + + return result; +} + +void +hdmiDestructorC771(NVHDMIPKT_CLASS* pThis) +{ + return; +} + +void +initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS* pClass) +{ + // Update SF_USER data + pClass->dispSfUserClassId = NVC771_DISP_SF_USER; + pClass->dispSfUserSize = sizeof(NvC771DispSfUserMap); + + pClass->hdmiPacketCtrl = hdmiPacketCtrlC771; + pClass->hdmiPacketWrite = hdmiPacketWriteC771; +} diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_class.h b/src/common/modeset/hdmipacket/nvhdmipkt_class.h index 2889753ef..3ff4c0e1c 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_class.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt_class.h @@ -47,6 +47,7 @@ typedef enum NVHDMIPKT_C371_CLASS = 5, // GV100 NVHDMIPKT_C571_CLASS = 6, // TU102 NVHDMIPKT_C671_CLASS = 7, // GA102, T234D + NVHDMIPKT_C771_CLASS = 8, // AD10X NVHDMIPKT_INVALID_CLASS // Not to be used by client, and always the last entry here. } NVHDMIPKT_CLASS_ID; diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_internal.h b/src/common/modeset/hdmipacket/nvhdmipkt_internal.h index 42487f0af..68942a8d4 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_internal.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt_internal.h @@ -41,6 +41,7 @@ extern void initializeHdmiPktInterface9471(NVHDMIPKT_CLASS*); extern void initializeHdmiPktInterface9571(NVHDMIPKT_CLASS*); extern void initializeHdmiPktInterfaceC371(NVHDMIPKT_CLASS*); extern void initializeHdmiPktInterfaceC671(NVHDMIPKT_CLASS*); +extern void initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS*); extern NvBool hdmiConstructor0073(NVHDMIPKT_CLASS*); extern void hdmiDestructor0073 (NVHDMIPKT_CLASS*); @@ -56,5 +57,7 @@ extern NvBool hdmiConstructorC371(NVHDMIPKT_CLASS*); extern void hdmiDestructorC371 (NVHDMIPKT_CLASS*); extern NvBool hdmiConstructorC671(NVHDMIPKT_CLASS*); extern void hdmiDestructorC671 (NVHDMIPKT_CLASS*); +extern NvBool hdmiConstructorC771(NVHDMIPKT_CLASS*); +extern void hdmiDestructorC771 (NVHDMIPKT_CLASS*); #endif //_NVHDMIPKT_INTERNAL_H_ diff --git a/src/common/modeset/timing/nvt_cvt.c b/src/common/modeset/timing/nvt_cvt.c index 0222ceb7a..af00dce2c 100644 --- a/src/common/modeset/timing/nvt_cvt.c +++ b/src/common/modeset/timing/nvt_cvt.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -38,19 +38,19 @@ CONS_SEGMENT(PAGE_CONS) const NvU32 NVT_MAX_NVU32= (NvU32)(-1); -const NvU32 NVT_CVT_CELL_GRAN=8; -const NvU32 NVT_CVT_MIN_VSYNCBP=11; // in 550us (!!) [1000000:550 = 20000:11] -const NvU32 NVT_CVT_V_PORCH=3; // in pixels -const NvU32 NVT_CVT_C_PRIME=30; // value of (C' * 10) -const NvU32 NVT_CVT_M_PRIME_D_20=15; // value of (M' / 100) -const NvU32 NVT_CVT_CLOCK_STEP=25; // Pclk step, in 10kHz -const NvU32 NVT_CVT_H_SYNC_PER=8; // HSYNC percentage (8%) +const NvU32 NVT_CVT_CELL_GRAN = 8; // Character cell width. +const NvU32 NVT_CVT_MIN_VSYNCBP = 11; // in 550us (!!) [1000000:550 = 20000:11] +const NvU32 NVT_CVT_V_PORCH = 3; // in pixels +const NvU32 NVT_CVT_C_PRIME = 30; // value of (C' * 10) +const NvU32 NVT_CVT_M_PRIME_D_20 = 15; // value of (M' / 100) +const NvU32 NVT_CVT_CLOCK_STEP = 25; // Pclk step, in 10kHz +const NvU32 NVT_CVT_H_SYNC_PER = 8; // HSYNC percentage (8%) -const NvU32 NVT_CVT_RB_HBLANK_CELLS=20; // 160 fixed hblank for RB -const NvU32 NVT_CVT_RB_HFPORCH_CELLS=6; // 48 fixed hfporch for RB -const NvU32 NVT_CVT_RB_HSYNCW_CELLS=4; // 32 fixed hsyncwidth for RB -const NvU32 NVT_CVT_RB_MIN_VBLANK=23; // 460 lines (or 460 us?) [1000000:460 = 50000:23] -const NvU32 NVT_CVT_MIN_V_BPORCH=6; +const NvU32 NVT_CVT_RB_HBLANK_CELLS = 20; // 160 fixed hblank for RB +const NvU32 NVT_CVT_RB_HFPORCH_CELLS = 6; // 48 fixed hfporch for RB +const NvU32 NVT_CVT_RB_HSYNCW_CELLS = 4; // 32 fixed hsyncwidth for RB +const NvU32 NVT_CVT_RB_MIN_VBLANK = 23; // 460 lines (or 460 us?) [1000000:460 = 50000:23] +const NvU32 NVT_CVT_MIN_V_BPORCH = 6; // Minimum vertical back porch. // VESA CVT spec ver1.2: @@ -60,13 +60,12 @@ const NvU32 NVT_CVT_MIN_V_BPORCH=6; #define NVT_CVT_RB2_H_BLANK_PIXELS 80 #define NVT_CVT_RB2_H_SYNC_PIXELS 32 #define NVT_CVT_RB2_MIN_VBLANK_MICROSEC 460 -#define NVT_CVT_RB2_V_FPORCH_MIN 1 -#define NVT_CVT_RB2_V_BPORCH 6 +#define NVT_CVT_RB2_MIN_V_FPORCH 1 +#define NVT_CVT_RB2_MIN_V_BPORCH 6 // Page 16 : Table 3-2 : Vertical Sync Duration #define NVT_CVT_RB2_V_SYNC_WIDTH 8 // Page 22: RB_MIN_VBI = RB_V_FPORCH + V_SYNC_RND + MIN_V_BPORCH -#define NVT_CVT_RB2_MIN_VBI NVT_CVT_RB2_V_SYNC_WIDTH + NVT_CVT_RB2_V_FPORCH_MIN + NVT_CVT_RB2_V_BPORCH - +#define NVT_CVT_RB2_MIN_VBI NVT_CVT_RB2_V_SYNC_WIDTH + NVT_CVT_RB2_MIN_V_FPORCH + NVT_CVT_RB2_MIN_V_BPORCH // Page 15 : The Horizontal Sync Pulse duration will in all cases be 32 pixel clocks in duration, with the position // set so that the trailing edge of the Horizontal Sync Pulse is located in the center of the Horizontal // Blanking period.This implies that for a fixed blank of 80 pixel clocks, the Horizontal Back Porch is @@ -74,6 +73,21 @@ const NvU32 NVT_CVT_MIN_V_BPORCH=6; #define NVT_CVT_RB2_H_FPORCH 8 #define NVT_CVT_RB2_H_BPORCH 40 +// VESA CVT spec ver2.0: +// +// Page 15 : Table 3-2 Constants +#define NVT_CVT_RB3_CLOCK_STEP_KHZ 1000 +#define NVT_CVT_RB3_H_BLANK_PIXELS NVT_CVT_RB2_H_BLANK_PIXELS +#define NVT_CVT_RB3_H_SYNC_PIXELS NVT_CVT_RB2_H_SYNC_PIXELS +#define NVT_CVT_RB3_H_FPORCH NVT_CVT_RB2_H_FPORCH +#define NVT_CVT_RB3_MIN_VBLANK_MICROSEC NVT_CVT_RB2_MIN_VBLANK_MICROSEC +#define NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ 350 +#define NVT_CVT_RB3_V_SYNC_WIDTH NVT_CVT_RB2_V_SYNC_WIDTH +#define NVT_CVT_RB3_MIN_V_FPORCH NVT_CVT_RB2_MIN_V_FPORCH +#define NVT_CVT_RB3_MIN_V_BPROCH NVT_CVT_RB2_MIN_V_BPORCH + +#define NVT_CVT_RB3_MIN_VBI NVT_CVT_RB2_MIN_VBI + CODE_SEGMENT(PAGE_DD_CODE) static NvU16 getCVTVSync(NvU32 XRes, NvU32 YRes) { @@ -136,10 +150,12 @@ NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING)); - pT->etc.status = NVT_STATUS_CVT; + pT->etc.status = NVT_STATUS_CVT; + + // H_PIXELS_RND = ROUNDDOWN(H_PIXELS / CELL_GRAN_RND,0) * CELL_GRAN_RND if ((width % NVT_CVT_CELL_GRAN)!=0) { - width = (width + NVT_CVT_CELL_GRAN / 2) / NVT_CVT_CELL_GRAN * NVT_CVT_CELL_GRAN; + width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN; NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT); } @@ -245,11 +261,12 @@ NVT_STATUS NvTiming_CalcCVT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, return NVT_STATUS_ERR;//NVT_STATUS_ERR_BACKOFF | NVT_STATUS_ERR_OUTOFRANGE; NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING)); - pT->etc.status = NVT_STATUS_CVT_RB; + + // H_PIXELS_RND = ROUNDDOWN(H_PIXELS / CELL_GRAN_RND,0) * CELL_GRAN_RND if ((width % NVT_CVT_CELL_GRAN)!=0) { - width = (width + NVT_CVT_CELL_GRAN / 2) / NVT_CVT_CELL_GRAN * NVT_CVT_CELL_GRAN; + width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN; NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT); } @@ -371,7 +388,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10 // 15. Find Actual Field Rate(Hz) : // ACT_FIELD_RATE = 1000 * ACT_H_FREQ / TOTAL_V_LINES // 16. Find actual Vertical Refresh Rate(Hz) : - // ACT_FRAME_RATE = IF(INT_RQD ? = "y", ACT_FIELD_RATE / 2, ACT_FI + // ACT_FRAME_RATE = IF(INT_RQD ? = "y", ACT_FIELD_RATE / 2, ACT_FIELD_RATE // fill in the essential timing info for output pT->HVisible = (NvU16)width; @@ -381,7 +398,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10 pT->VVisible = (NvU16)height; pT->VTotal = (NvU16)total_v_lines; pT->VSyncWidth = NVT_CVT_RB2_V_SYNC_WIDTH; - pT->VFrontPorch = (NvU16)(act_vbi_lines - NVT_CVT_RB2_V_SYNC_WIDTH - NVT_CVT_RB2_V_BPORCH); + pT->VFrontPorch = (NvU16)(act_vbi_lines - NVT_CVT_RB2_V_SYNC_WIDTH - NVT_CVT_RB2_MIN_V_BPORCH); pT->pclk = (act_pixel_freq_khz + 5) / 10; //convert to 10Khz pT->HSyncPol = NVT_H_SYNC_POSITIVE; pT->VSyncPol = NVT_V_SYNC_NEGATIVE; @@ -391,7 +408,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10 // fill in the extra timing info pT->etc.flag = 0; pT->etc.rr = (NvU16)rr; - pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000 * (NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal); + pT->etc.rrx1k = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal); pT->etc.aspect = 0; pT->etc.rep = 0x1; NVT_SNPRINTF((char *)pT->etc.name, 40, "CVT-RB2:%dx%dx%dHz", width, height, rr); @@ -400,27 +417,206 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10 return NVT_STATUS_SUCCESS; } + +// CVT-RB3 timing calculation +// This is intended to work in conjunction with VESA Adaptive-Sync operation (or other similar VRR methodology) +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT) +{ + NvU32 vbi, act_v_blank_time, act_v_blank_lines, v_back_porch, total_v_lines, total_pixels, adj_rr_x1M, act_pixel_freq_khz; + NvU64 act_pixel_freq_hz = 0xFFFFFFFFFFFFFFFFULL; + + // parameter check + if (pT == NULL) + return NVT_STATUS_ERR; + + if (width == 0 || height == 0 || rr == 0) + return NVT_STATUS_ERR; + + // Check for valid input parameter + if ( (height % 8 != 0) || (deltaHBlank % 8 != 0) || deltaHBlank > 120 || vBlankMicroSec > 245) + return NVT_STATUS_INVALID_PARAMETER; + + NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING)); + pT->etc.status = NVT_STATUS_CVT_RB_3; + + // 1 Calculate the required field refresh rate (Hz): + // V_FIELD_RATE_RQD = I_IP_FREQ_RQD * (1 + C_V_FIELD_RATE_PPM_ADJ / 1000000) + + // Parameters mapping: + // - V_FIELD_RATE_RQD == "adj_rr_x1M" + // - I_IP_FREQ_RQD == "rr" + // - C_V_FIELD_RATE_PPM_ADJ == "NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ" + adj_rr_x1M = rr * (1000000 + NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ); + + // 2 Round the desired number of horizontal pixels down to the nearest character cell boundary: + // TOTAL_ACTIVE_PIXELS = ROUNDDOWN(I_H_PIXELS / C_CELL_GRAN_RND, 0) * C_CELL_GRAN_RND + + // Parameters mapping: + // - TOTAL_ACTIVE_PIXELS and I_H_PIXELS == "width" + // - C_CELL_GRAN_RND == "NVT_CVT_CELL_GRAN" + if ((width % NVT_CVT_CELL_GRAN) != 0) + { + // ROUNDDOWN + width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN; + NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT); + } + + // 3 Round the number of vertical lines down to the nearest integer: + // V_LINES_RND = ROUNDDOWN(I_V_LINES, 0) + + // Parameters mapping: + // - V_LINES_RND == "height" + + // 4 Calculate the estimated Horizontal Period (kHz): + // H_PERIOD_EST = ((1000000 / (V_FIELD_RATE_RQD)) - C_RB_MIN_V_BLANK) / V_LINES_RND + + // Parameters mapping: + // - H_PERIOD_EST == "h_period_est" + // - C_RB_MIN_V_BLANK == "NVT_CVT_RB3_MIN_VBLANK_MICROSEC" + // h_period_est = ((1000000000000 / adj_rr_x1M) - NVT_CVT_RB3_MIN_VBLANK_MICROSEC) / height + + // 5 Calculate the total VBlank time: + // ACT_V_BLANK_TIME = IF(I_VBLANK < C_RB_MIN_V_BLANK, C_RB_MIN_V_BLANK, I_VBLANK) + + // Parameters mapping: + // - ACT_V_BLANK_TIME == "act_v_blank_time" + // - I_VBLANK == "vBlankMicroSec" + act_v_blank_time = MAX(vBlankMicroSec + 460, NVT_CVT_RB3_MIN_VBLANK_MICROSEC); + + // 6 Calculate the number of idealized lines in the VBlank interval: + // VBI_LINES = ROUNDUP(ACT_V_BLANK_TIME / H_PERIOD_EST, 0) + + // Parameters mapping: + // - VBI_LINES == vbi" + // below formula are combining step 4, 5, 6 togerther. i.e. both numerator and denominator multiple by height and addj_rr_x1M. + vbi = (NvU32)(((NvU64)height * (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) / ((NvU64)1000000000000 - (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M)); + // ROUNDUP + if (((NvU64)height * (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) % ((NvU64)1000000000000 - (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) !=0) + vbi += 1; + + // 7 Determine whether idealized VBlank is sufficient and calculate the actual number of lines in the VBlank period: + // RB_MIN_VBI = C_RB_V_FPORCH + C_V_SYNC_RND + C_MIN_V_BPORCH + // V_BLANK = IF(VBI_LINES < RB_MIN_VBI, RB_MIN_VBI, VBI_LINES) + + // Paameters mapping: + // - C_RB_V_FPORCH == 1 + // - C_V_SYNC_RND == 8 + // - C_MIN_V_BPORCH == 6 + // - V_BLANK == "act_v_blank_lines" + // NVT_CVT_RB3_MIN_VBI == 1 + 8 + 6 = 15 + act_v_blank_lines = MAX(vbi, NVT_CVT_RB3_MIN_VBI); + + // 8 Calculate the total number of vertical lines: + // TOTAL_V_LINES = V_BLANK + V_LINES_RND + total_v_lines = act_v_blank_lines + height; + + // 9 Calculate the vertical back porch: + // V_BACK_PORCH = IF(AND(I_RED_BLANK_VER=3, I_EARLY_VSYNC_RQD?="Y"), ROUNDDOWN(VBI_LINES / 2, 0), C_MIN_V_BPORCH) + + // Paameters mapping: + // - V_BACK_PORCH == "v_back_porch" + // - I_RED_BLANK_VER == "3" this is for RB3 function so the value is 3 + // - I_EARLY_VSYNC_RQD == "isEarlyVSync" + // - C_MIN_V_BPORCH == 6 + if (isEarlyVSync) + v_back_porch = vbi / 2; + // v_back_porch = act_v_blank_lines /2 ; + else + v_back_porch = NVT_CVT_RB3_MIN_V_BPROCH; + + // 10 Calculate the vertical front porch: + // V_FRONT_PORCH = V_BLANK – V_BACK_PORCH – C_V_SYNC_RND + // we directly use this to assign as pT->VFrontPorch value in NVT_TIMING + + // 11 Calculate the total number of pixels per line: + // TOTAL_PIXELS = TOTAL_ACTIVE_PIXELS + C_RB_H_BLANK + IF(I_RED_BLANK_VER=3, I_ADDITIONAL_HBLANK, 0) + + // Parameters mapping: + // - C_RB_H_BLANK == 80 + // - I_ADDITIONAL_HBLANK == deltaHBlank scopes are defined in the TypeX in displayId2.1 + // 80 <= HBlank <=200 is a valid scope + total_pixels = width + deltaHBlank + 80; + + // 12 Calculate the horizontal back porch: + // H_BACK_PORCH = C_RB_H_BLANK + IF(I_RED_BLANK_VER=3, I_ADDITIONAL_HBLANK, 0) – C_H_FRONT_PORCH – C_RB_H_SYNC + // NVT_TIMING did not need to store H_BACK_PORCH + + // sanity check just in case of bad edid where the timing value could exceed the limit of NVT_TIMING structure which unfortunately is defined in NvU16 + if (total_pixels > (NvU16)-1 || total_v_lines > (NvU16)-1) + return NVT_STATUS_INVALID_PARAMETER; + + // 13 Calculate the pixel clock frequency to the nearest C_CLOCK_STEP (MHz): + // ACT_PIXEL_FREQ = C_CLOCK_STEP * ROUNDUP((V_FIELD_RATE_RQD * TOTAL_V_LINES * TOTAL_PIXELS / 1000000 * 1) / C_CLOCK_STEP, 0)) + + // Parameters mapping: + // - ACT_PIXEL_FREQ == "act_pixel_freq_hz" + // - C_CLOCK_STEP == "NVT_CVT_RB3_CLOCK_STEP_KHZ" == 1000 + act_pixel_freq_hz = ((NvU64)adj_rr_x1M * (NvU64)total_v_lines * (NvU64)total_pixels / (NvU64)1000000); + + // Here we need to divide extra 1000 because adj_rr_x1M extends to Million, i.e 1Mhz / 1000 = 1kHz + act_pixel_freq_khz = (NvU32)(act_pixel_freq_hz / NVT_CVT_RB3_CLOCK_STEP_KHZ); + + // kHz ROUNDUP + if ((act_pixel_freq_hz % 1000) != 0) + act_pixel_freq_khz += 1; + + pT->HVisible = (NvU16)width; + pT->HTotal = (NvU16)total_pixels; + pT->HFrontPorch = NVT_CVT_RB3_H_FPORCH; + pT->HSyncWidth = NVT_CVT_RB3_H_SYNC_PIXELS; + pT->VVisible = (NvU16)height; + pT->VTotal = (NvU16)total_v_lines; + pT->VSyncWidth = NVT_CVT_RB3_V_SYNC_WIDTH; + pT->VFrontPorch = (NvU16)(act_v_blank_lines - NVT_CVT_RB2_V_SYNC_WIDTH - v_back_porch); + pT->pclk = ((NvU32)act_pixel_freq_khz + 5) / 10; //convert to 10Khz + pT->HSyncPol = NVT_H_SYNC_POSITIVE; + pT->VSyncPol = NVT_V_SYNC_NEGATIVE; + pT->HBorder = pT->VBorder = 0; // not supported + pT->interlaced = 0; // not supported yet + + // fill in the extra timing info + pT->etc.flag = 0; + pT->etc.rr = (NvU16)rr; + pT->etc.rrx1k = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal); + pT->etc.aspect = 0; + pT->etc.rep = 0x1; + NVT_SNPRINTF((char *)pT->etc.name, 40, "CVT-RB3:%dx%dx%dHz", width, height, rr); + pT->etc.name[39] = '\0'; + + return NVT_STATUS_SUCCESS; +} + CODE_SEGMENT(PAGE_DD_CODE) NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming) { // Check from the Timing Type NvU32 reducedType = 0; + NvU32 hblank = 0; reducedType = NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status); - if (reducedType == NVT_TYPE_CVT_RB || reducedType == NVT_TYPE_CVT_RB_2) + if (reducedType == NVT_TYPE_CVT_RB || reducedType == NVT_TYPE_CVT_RB_2 || reducedType == NVT_TYPE_CVT_RB_3) { return NV_TRUE; } + hblank = pTiming->HTotal - pTiming->HVisible; + // Manually Check for RB 1 and 2 // RB1 - HBlank = 160, and HSync = 32, HFrontPorch = 48, HBackPorch = 80 - if (((pTiming->HTotal - pTiming->HVisible) == 160) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 48)) + if ((hblank == 160) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 48)) { return NV_TRUE; } // RB2 - HBlank = 80, HSync = 32, HFrontPorch = 8, HBackPorch = 40 - if (((pTiming->HTotal - pTiming->HVisible) == 80) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8)) + if ((hblank == 80) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8)) + { + return NV_TRUE; + } + + // RB3 - HBlank is any integer multiple of 8 [80-200], HSync = 32, HFrontPorch = 8 + if (((hblank > 80) && (hblank <= 200) && (hblank % 8 == 0)) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8)) { return NV_TRUE; } diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index b0cbaa634..ec725b314 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -283,6 +283,114 @@ static const NvU8 maxqp444_12b[15][61]={ ,{23,23,22,22,21,21,21,21,20,20,19,19,19,19,18,18,18,17,17,17,16,16,16,16,15,15,14,14,14,14,14,13,13,12,12,12,12,12,11,11,10,10,10,10,10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4} }; +static const NvU8 minqp422_8b[15][21] = { + {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0} + ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0} + ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0} + ,{3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0} + ,{3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1} + ,{3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1} + ,{5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1} + ,{5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1} + ,{5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1} + ,{8 ,8 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2} + ,{12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3} +}; + +static const NvU8 maxqp422_8b[15][21] = { + {4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{4 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{5 ,5 ,5 ,5 ,5 ,4 ,3 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0} + ,{6 ,6 ,6 ,6 ,6 ,5 ,4 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0} + ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1} + ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1} + ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1} + ,{8 ,8 ,8 ,8 ,8 ,7 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1} + ,{9 ,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2} + ,{10,10,9 ,9 ,9 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2} + ,{10,10,10,9 ,9 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2} + ,{11,11,10,10,9 ,9 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2} + ,{11,11,11,10,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2} + ,{12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,3} + ,{13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4} +}; + +static const NvU8 minqp422_10b[15][29] = { + {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{4 ,4 ,4 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{5 ,5 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{6 ,6 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{6 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0} + ,{6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0} + ,{6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0} + ,{7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1} + ,{7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1} + ,{8 ,8 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1} + ,{9 ,9 ,9 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1} + ,{9 ,9 ,9 ,9 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1} + ,{9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1} + ,{12,12,11,11,11,11,11,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1} + ,{16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3} +}; + +static const NvU8 maxqp422_10b[15][29] = { + {8 ,8 ,7 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{8 ,8 ,8 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{9 ,9 ,9 ,8 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0} + ,{10,10,10,10,9 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1} + ,{11,11,11,11,10,9 ,8 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1} + ,{11,11,11,11,11,10,9 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1} + ,{11,11,11,11,11,10,9 ,8 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1} + ,{12,12,12,12,12,11,10,9 ,8 ,8 ,8 ,7 ,7 ,7 ,7 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2} + ,{13,13,13,12,12,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2} + ,{14,14,13,13,13,12,11,10,9 ,9 ,9 ,9 ,8 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2} + ,{14,14,14,13,13,12,11,11,10,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2} + ,{15,15,14,14,13,13,12,11,11,11,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2} + ,{15,15,15,14,13,13,12,12,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2} + ,{16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2} + ,{17,17,16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4} +}; + +static const NvU8 minqp422_12b[15][37] = { + {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{9 ,9 ,9 ,8 ,7 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{10,10,10,10,8 ,8 ,8 ,7 ,6 ,6 ,6 ,6 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{11,11,11,11,10,9 ,9 ,8 ,7 ,7 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{11,11,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0} + ,{11,11,11,11,11,10,10,10,9 ,9 ,9 ,9 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0} + ,{11,11,11,11,11,11,10,10,10,10,10,9 ,8 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0} + ,{11,11,11,11,11,11,11,11,11,11,11,10,9 ,8 ,8 ,8 ,7 ,6 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,0 ,0 ,0} + ,{11,11,11,11,11,11,11,11,11,11,11,11,9 ,9 ,9 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,0 ,0} + ,{13,13,13,13,13,12,12,12,12,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,8 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1} + ,{13,13,13,13,13,13,13,13,13,13,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1} + ,{13,13,13,13,13,13,13,13,13,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1} + ,{16,16,15,15,15,15,15,15,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2} + ,{20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,12,12,12,11,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4} +}; + +static const NvU8 maxqp422_12b[15][37] = { + {12,12,11,9 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{12,12,12,10,9 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{13,13,13,12,10,9 ,8 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0} + ,{14,14,14,14,12,11,10,9 ,8 ,8 ,8 ,8 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0} + ,{15,15,15,15,14,13,12,10,9 ,9 ,9 ,9 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0} + ,{15,15,15,15,15,14,13,12,11,10,10,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1} + ,{15,15,15,15,15,14,13,12,11,11,11,11,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1} + ,{16,16,16,16,16,15,14,13,12,12,12,11,10,10,10,9 ,8 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1} + ,{17,17,17,16,16,15,14,14,13,13,13,12,11,10,10,10,9 ,8 ,8 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,1 ,1 ,1} + ,{18,18,17,17,17,16,15,14,13,13,13,13,11,11,11,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1} + ,{18,18,18,17,17,16,15,15,14,14,14,13,13,12,12,12,11,11,10,10,10,8 ,8 ,7 ,7 ,7 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2} + ,{19,19,18,18,17,17,16,15,15,15,14,14,13,13,12,12,12,11,11,10,10,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2} + ,{19,19,19,18,17,17,16,16,15,15,15,14,14,13,13,12,12,11,11,10,10,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2} + ,{20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3} + ,{21,21,20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,13,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5} +}; + static const NvU32 rcBufThresh[] = { 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 7744, 7872, 8000, 8064 }; /* ------------------------ Static Variables ------------------------------- */ @@ -369,7 +477,7 @@ DSC_PpsCalcExtraBits DSC_OUTPUT_PARAMS *out ) { - NvU32 numSsps = 3; + NvU32 numSsps = out->native_422 ? 4 : 3; NvU32 sliceBits; NvU32 extra_bits; NvU32 bitsPerComponent = out->bits_per_component; @@ -418,6 +526,7 @@ DSC_PpsCalcRcInitValue ) { NvU32 bitsPerPixel = out->bits_per_pixel; + NvU32 xmit_delay; out->rc_model_size = 8192; if (out->native_422) @@ -427,7 +536,7 @@ DSC_PpsCalcRcInitValue out->initial_offset = 2048; else if (bitsPerPixel >= 14 * BPP_UNIT) out->initial_offset = 5632 - ((bitsPerPixel - 14 * BPP_UNIT) * 1792 + BPP_UNIT / 2) / BPP_UNIT; - else if (bitsPerPixel >= 12 * BPP_UNIT) + else out->initial_offset = 5632; } else @@ -450,12 +559,52 @@ DSC_PpsCalcRcInitValue } RANGE_CHECK("initial_scale_value", out->initial_scale_value, 0, 63); - out->initial_xmit_delay = (4096*BPP_UNIT + bitsPerPixel / 2) / bitsPerPixel; - //RANGE_CHECK("initial_xmit_delay", out->initial_xmit_delay, 0, 1023); + xmit_delay = (4096*BPP_UNIT + bitsPerPixel/2) / bitsPerPixel; + + if (out->native_420 || out->native_422) + { + NvU32 slicew = (out->native_420 || out->native_422) ? out->slice_width / 2 : out->slice_width; + NvU32 padding_pixels = ((slicew % 3) ? (3 - (slicew % 3)) : 0) * (xmit_delay / slicew); + if (3 * bitsPerPixel >= ((xmit_delay + 2) / 3) * (out->native_422 ? 4 : 3) * BPP_UNIT && + (((xmit_delay + padding_pixels) % 3) == 1)) + { + xmit_delay++; + } + } + out->initial_xmit_delay = xmit_delay; + RANGE_CHECK("initial_xmit_delay", out->initial_xmit_delay, 0, 1023); return NVT_STATUS_SUCCESS; } +static NvU32 DSC_PpsCalcComputeOffset(DSC_OUTPUT_PARAMS *out, NvU32 grpcnt) +{ + NvU32 offset = 0; + NvU32 groupsPerLine = out->groups_per_line; + NvU32 grpcnt_id = (out->initial_xmit_delay + PIXELS_PER_GROUP - 1) / PIXELS_PER_GROUP; + + if(grpcnt <= grpcnt_id) + offset = (grpcnt * PIXELS_PER_GROUP * out->bits_per_pixel + BPP_UNIT - 1) / BPP_UNIT; + else + offset = (grpcnt_id * PIXELS_PER_GROUP * out->bits_per_pixel + BPP_UNIT - 1) / BPP_UNIT - (((grpcnt-grpcnt_id) * out->slice_bpg_offset)>>OFFSET_FRACTIONAL_BITS); + + if(grpcnt <= groupsPerLine) + offset += grpcnt * out->first_line_bpg_offset; + else + offset += groupsPerLine * out->first_line_bpg_offset - (((grpcnt - groupsPerLine) * out->nfl_bpg_offset)>>OFFSET_FRACTIONAL_BITS); + + if(out->native_420) + { + if(grpcnt <= groupsPerLine) + offset -= (grpcnt * out->nsl_bpg_offset) >> OFFSET_FRACTIONAL_BITS; + else if(grpcnt <= 2*groupsPerLine) + offset += (grpcnt - groupsPerLine) * out->second_line_bpg_offset - ((groupsPerLine * out->nsl_bpg_offset)>>OFFSET_FRACTIONAL_BITS); + else + offset += (grpcnt - groupsPerLine) * out->second_line_bpg_offset - (((grpcnt - groupsPerLine) * out->nsl_bpg_offset)>>OFFSET_FRACTIONAL_BITS); + } + return(offset); +} + /* * @brief Calculate bpg value except slice_bpg_offset * @@ -477,6 +626,7 @@ NvU32 DSC_PpsCalcBpg NvU32 bitsPerPixel; NvU32 rbsMin; NvU32 hrdDelay; + NvU32 groups_total; if (out->native_422) uncompressedBpgRate = PIXELS_PER_GROUP * out->bits_per_component * 4; @@ -515,9 +665,35 @@ NvU32 DSC_PpsCalcBpg out->second_line_offset_adj = out->native_420 ? 512 : 0; bitsPerPixel = out->bits_per_pixel; - rbsMin = out->rc_model_size - out->initial_offset + groups_total = out->groups_per_line * out->slice_height; + out->slice_bpg_offset = (((out->rc_model_size - out->initial_offset + out->num_extra_mux_bits) << OFFSET_FRACTIONAL_BITS) + + groups_total - 1) / groups_total; + RANGE_CHECK("slice_bpg_offset", out->slice_bpg_offset, 0, 65535); + + if((PIXELS_PER_GROUP * bitsPerPixel << OFFSET_FRACTIONAL_BITS) - (out->slice_bpg_offset + out->nfl_bpg_offset) * BPP_UNIT + < (1+5*PIXELS_PER_GROUP)*BPP_UNIT <dsc_version_major > 1) || (out->dsc_version_major == 1 && out->dsc_version_minor >= 2)) && + (out->native_420 || out->native_422)) + { + // OPTIMIZED computation of rbsMin: + // Compute max by sampling offset at points of inflection + // *MODEL NOTE* MN_RBS_MIN + NvU32 maxOffset; + maxOffset = DSC_PpsCalcComputeOffset(out, (out->initial_xmit_delay+PIXELS_PER_GROUP-1)/PIXELS_PER_GROUP ); // After initial delay + maxOffset = MAX(maxOffset, DSC_PpsCalcComputeOffset(out, out->groups_per_line)); // After first line + maxOffset = MAX(maxOffset, DSC_PpsCalcComputeOffset(out, 2*out->groups_per_line)); + rbsMin = out->rc_model_size - out->initial_offset + maxOffset; + } + else + { // DSC 1.1 method + rbsMin = out->rc_model_size - out->initial_offset + (out->initial_xmit_delay * bitsPerPixel + BPP_UNIT - 1) / BPP_UNIT + out->groups_per_line * out->first_line_bpg_offset; + } hrdDelay = (rbsMin * BPP_UNIT + bitsPerPixel - 1) / bitsPerPixel; out->initial_dec_delay = hrdDelay - out->initial_xmit_delay; RANGE_CHECK("initial_dec_delay", out->initial_dec_delay, 0, 65535); @@ -526,7 +702,7 @@ NvU32 DSC_PpsCalcBpg } /* - * @brief Calculate slice_bpg_offset, final_offset and scale_increment_interval, + * @brief Calculate final_offset and scale_increment_interval, * scale_decrement_interval * * @param[in/out] out DSC output parameter @@ -541,22 +717,9 @@ DSC_PpsCalcScaleInterval ) { NvU32 final_scale; - NvU32 groups_total; - NvU32 bitsPerPixel = out->bits_per_pixel; - - groups_total = out->groups_per_line * out->slice_height; - out->slice_bpg_offset = (((out->rc_model_size - out->initial_offset + out->num_extra_mux_bits) << OFFSET_FRACTIONAL_BITS) - + groups_total - 1) / groups_total; - RANGE_CHECK("slice_bpg_offset", out->slice_bpg_offset, 0, 65535); - - if ((PIXELS_PER_GROUP * bitsPerPixel << OFFSET_FRACTIONAL_BITS) - (out->slice_bpg_offset + out->nfl_bpg_offset) * BPP_UNIT - < (1 + 5 * PIXELS_PER_GROUP) * BPP_UNIT << OFFSET_FRACTIONAL_BITS) - { - DSC_Print("The bits/pixel allocation for non-first lines is too low (<5.33bpp)."); - DSC_Print("Consider decreasing FIRST_LINE_BPG_OFFSET."); - } - out->final_offset = out->rc_model_size - (out->initial_xmit_delay * bitsPerPixel + 8)/BPP_UNIT + out->num_extra_mux_bits; + out->final_offset = (out->rc_model_size - (out->initial_xmit_delay * out->bits_per_pixel + 8) / + BPP_UNIT + out->num_extra_mux_bits); RANGE_CHECK("final_offset", out->final_offset, 0, out->rc_model_size-1); //try increase initial_xmit_delay final_scale = 8 * out->rc_model_size / (out->rc_model_size - out->final_offset); @@ -571,7 +734,8 @@ DSC_PpsCalcScaleInterval // for that configuration. // out->scale_increment_interval = (out->final_offset << OFFSET_FRACTIONAL_BITS) / - ((final_scale - 9) * (out->nfl_bpg_offset + out->slice_bpg_offset + out->nsl_bpg_offset)); + ((final_scale - 9) * (out->nfl_bpg_offset + + out->slice_bpg_offset + out->nsl_bpg_offset)); RANGE_CHECK("scale_increment_interval", out->scale_increment_interval, 0, 65535); } else @@ -607,6 +771,9 @@ DSC_PpsCalcRcParam NvU32 bpcm8 = out->bits_per_component - 8; NvU32 yuv_modifier = out->convert_rgb == 0 && out->dsc_version_minor == 1; NvU32 qp_bpc_modifier = bpcm8 * 2 - yuv_modifier; + const int ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; + const int ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + const int ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; out->flatness_min_qp = 3 + qp_bpc_modifier; out->flatness_max_qp = 12 + qp_bpc_modifier; @@ -620,102 +787,167 @@ DSC_PpsCalcRcParam for (i = 0; i < NUM_BUF_RANGES - 1; i++) out->rc_buf_thresh[i] = rcBufThresh[i] & (0xFF << 6); - //if (out->native_420) - // idx = bitsPerPixel/BPP_UNIT - 8; - //else if(out->native_422) - // idx = bitsPerPixel/BPP_UNIT - 12; - //else - idx = (2 * (bitsPerPixel - 6 * BPP_UNIT) ) / BPP_UNIT; - - if (bpcm8 == 0) + if (out->native_422) { - for (i = 0; i < NUM_BUF_RANGES; i++) + idx = bitsPerPixel/BPP_UNIT - 12; + if (bpcm8 == 0) { - const NvU32 min = minqp444_8b[i][idx]; - const NvU32 max = maxqp444_8b[i][idx]; - - out->range_min_qp[i] = MAX(0, min - yuv_modifier); - out->range_max_qp[i] = MAX(0, max - yuv_modifier); + for (i = 0; i < NUM_BUF_RANGES; ++i) + { + out->range_min_qp[i] = minqp422_8b[i][idx]; + out->range_max_qp[i] = maxqp422_8b[i][idx]; + } } - } - else if (bpcm8 == 2) - { - for (i = 0; i < NUM_BUF_RANGES; i++) + else if (bpcm8 == 2) { - const NvU32 min = minqp444_10b[i][idx]; - const NvU32 max = maxqp444_10b[i][idx]; + for (i=0; i < NUM_BUF_RANGES; i++) + { + out->range_min_qp[i] = minqp422_10b[i][idx]; + out->range_max_qp[i] = maxqp422_10b[i][idx]; + } + } + else + { + for (i=0; irange_min_qp[i] = minqp422_12b[i][idx]; + out->range_max_qp[i] = maxqp422_12b[i][idx]; + } + } - out->range_min_qp[i] = MAX(0, min - yuv_modifier); - out->range_max_qp[i] = MAX(0, max - yuv_modifier); + for (i = 0; i < NUM_BUF_RANGES; ++i) + { + if (bitsPerPixel <= 12*BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und6[i]; + } + else if (bitsPerPixel <= 14*BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 12*BPP_UNIT) * + (ofs_und7[i] - ofs_und6[i]) + BPP_UNIT) / (2*BPP_UNIT); + } + else if (bitsPerPixel <= 16*BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und7[i]; + } + else if (bitsPerPixel <= 20*BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und7[i] + ((bitsPerPixel - 16*BPP_UNIT) * + (ofs_und10[i] - ofs_und7[i]) + 2*BPP_UNIT) / (4*BPP_UNIT); + } + else + { + out->range_bpg_offset[i] = ofs_und10[i]; + } } } else { - for (i = 0; i < NUM_BUF_RANGES; i++) + idx = (2 * (bitsPerPixel - 6 * BPP_UNIT) ) / BPP_UNIT; + + if (bpcm8 == 0) { - const NvU32 min = minqp444_12b[i][idx]; - const NvU32 max = maxqp444_12b[i][idx]; + for (i = 0; i < NUM_BUF_RANGES; i++) + { + const NvU32 min = minqp444_8b[i][idx]; + const NvU32 max = maxqp444_8b[i][idx]; - out->range_min_qp[i] = MAX(0, min - yuv_modifier); - out->range_max_qp[i] = MAX(0, max - yuv_modifier); + out->range_min_qp[i] = MAX(0, min - yuv_modifier); + out->range_max_qp[i] = MAX(0, max - yuv_modifier); + } } - } + else if (bpcm8 == 2) + { + for (i = 0; i < NUM_BUF_RANGES; i++) + { + const NvU32 min = minqp444_10b[i][idx]; + const NvU32 max = maxqp444_10b[i][idx]; - for (i = 0; i < NUM_BUF_RANGES; ++i) - { - //if (out->native_420) - //{ - // NvU32 ofs_und4[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; - // NvU32 ofs_und5[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; - // NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; - // NvU32 ofs_und8[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; - // out->range_min_qp[i] = minqp_420[bpcm8 / 2][i][idx]; - // out->range_max_qp[i] = maxqp_420[bpcm8 / 2][i][idx]; - // if (bitsPerPixel <= 8*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und4[i]; - // else if (bitsPerPixel <= 10*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und4[i] + (NvU32)(0.5 * (bitsPerPixel - 8.0) * (ofs_und5[i] - ofs_und4[i]) + 0.5); - // else if (bitsPerPixel <= 12*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und5[i] + (NvU32)(0.5 * (bitsPerPixel - 10.0) * (ofs_und6[i] - ofs_und5[i]) + 0.5); - // else if (bitsPerPixel <= 16*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)(0.25 * (bitsPerPixel - 12.0) * (ofs_und8[i] - ofs_und6[i]) + 0.5); - // else - // out->range_bpg_offset[i] = ofs_und8[i]; - //} - //else if (out->native_422) - //{ - // NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; - // NvU32 ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; - // NvU32 ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; - // out->range_min_qp[i] = minqp_422[bpcm8 / 2][i][idx]; - // out->range_max_qp[i] = maxqp_422[bpcm8 / 2][i][idx]; - // if (bitsPerPixel <= 12*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und6[i]; - // else if(bitsPerPixel <= 14*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)((bitsPerPixel - 12.0) * (ofs_und7[i] - ofs_und6[i]) / 2.0 + 0.5); - // else if(bitsPerPixel <= 16*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und7[i]; - // else if(bitsPerPixel <= 20*BPP_UNIT) - // out->range_bpg_offset[i] = ofs_und7[i] + (NvU32)((bitsPerPixel - 16.0) * (ofs_und10[i] - ofs_und7[i]) / 4.0 + 0.5); - // else - // out->range_bpg_offset[i] = ofs_und10[i]; - //} - //else + out->range_min_qp[i] = MAX(0, min - yuv_modifier); + out->range_max_qp[i] = MAX(0, max - yuv_modifier); + } + } + else { - const NvU32 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; - const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; - const NvU32 ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; - const NvU32 ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; - if (bitsPerPixel <= 6 * BPP_UNIT) - out->range_bpg_offset[i] = ofs_und6[i]; - else if (bitsPerPixel <= 8 * BPP_UNIT) - out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 6 * BPP_UNIT) * (ofs_und8[i] - ofs_und6[i]) + BPP_UNIT) / (2 * BPP_UNIT); - else if (bitsPerPixel <= 12 * BPP_UNIT) - out->range_bpg_offset[i] = ofs_und8[i]; - else if (bitsPerPixel <= 15 * BPP_UNIT) - out->range_bpg_offset[i] = ofs_und12[i] + ((bitsPerPixel - 12 * BPP_UNIT) * (ofs_und15[i] - ofs_und12[i]) + 3 * BPP_UNIT / 2) / (3 * BPP_UNIT); - else - out->range_bpg_offset[i] = ofs_und15[i]; + for (i = 0; i < NUM_BUF_RANGES; i++) + { + const NvU32 min = minqp444_12b[i][idx]; + const NvU32 max = maxqp444_12b[i][idx]; + + out->range_min_qp[i] = MAX(0, min - yuv_modifier); + out->range_max_qp[i] = MAX(0, max - yuv_modifier); + } + } + + for (i = 0; i < NUM_BUF_RANGES; ++i) + { + //if (out->native_420) + //{ + // NvU32 ofs_und4[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; + // NvU32 ofs_und5[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + // NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + // NvU32 ofs_und8[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; + // out->range_min_qp[i] = minqp_420[bpcm8 / 2][i][idx]; + // out->range_max_qp[i] = maxqp_420[bpcm8 / 2][i][idx]; + // if (bitsPerPixel <= 8*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und4[i]; + // else if (bitsPerPixel <= 10*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und4[i] + (NvU32)(0.5 * (bitsPerPixel - 8.0) * (ofs_und5[i] - ofs_und4[i]) + 0.5); + // else if (bitsPerPixel <= 12*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und5[i] + (NvU32)(0.5 * (bitsPerPixel - 10.0) * (ofs_und6[i] - ofs_und5[i]) + 0.5); + // else if (bitsPerPixel <= 16*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)(0.25 * (bitsPerPixel - 12.0) * (ofs_und8[i] - ofs_und6[i]) + 0.5); + // else + // out->range_bpg_offset[i] = ofs_und8[i]; + //} + //else if (out->native_422) + //{ + // NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; + // NvU32 ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + // NvU32 ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; + // out->range_min_qp[i] = minqp_422[bpcm8 / 2][i][idx]; + // out->range_max_qp[i] = maxqp_422[bpcm8 / 2][i][idx]; + // if (bitsPerPixel <= 12*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und6[i]; + // else if(bitsPerPixel <= 14*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)((bitsPerPixel - 12.0) * (ofs_und7[i] - ofs_und6[i]) / 2.0 + 0.5); + // else if(bitsPerPixel <= 16*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und7[i]; + // else if(bitsPerPixel <= 20*BPP_UNIT) + // out->range_bpg_offset[i] = ofs_und7[i] + (NvU32)((bitsPerPixel - 16.0) * (ofs_und10[i] - ofs_und7[i]) / 4.0 + 0.5); + // else + // out->range_bpg_offset[i] = ofs_und10[i]; + //} + //else + { + const NvU32 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; + const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + const NvU32 ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + const NvU32 ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; + + if (bitsPerPixel <= 6 * BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und6[i]; + } + else if (bitsPerPixel <= 8 * BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 6 * BPP_UNIT) * + (ofs_und8[i] - ofs_und6[i]) + BPP_UNIT) / (2 * BPP_UNIT); + } + else if (bitsPerPixel <= 12 * BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und8[i]; + } + else if (bitsPerPixel <= 15 * BPP_UNIT) + { + out->range_bpg_offset[i] = ofs_und12[i] + ((bitsPerPixel - 12 * BPP_UNIT) * + (ofs_und15[i] - ofs_und12[i]) + 3 * BPP_UNIT / 2) / (3 * BPP_UNIT); + } + else + { + out->range_bpg_offset[i] = ofs_und15[i]; + } + } } } return NVT_STATUS_SUCCESS; @@ -1155,6 +1387,11 @@ DSC_PpsCalcSliceParams out->slice_width = (out->pic_width + out->slice_num - 1) / out->slice_num; + if (out->native_420 || out->native_422) + { + out->slice_width = (out->slice_width+1)/2 * 2 ; + } + if (out->slice_width > max_slice_width) { DSC_Print("Slice width corresponding to the requested slice count is not supported\n"); @@ -1934,13 +2171,7 @@ DSC_GeneratePPS if (*pBitsPerPixelX16 != 0) { *pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision); - - // The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth, - // which is applicable to DP alone and not to HDMI FRL. - // Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec - // to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone. - if ((pWARData && (pWARData->connectorType == DSC_DP)) && - (*pBitsPerPixelX16 > in->bits_per_pixel)) + if (*pBitsPerPixelX16 > in->bits_per_pixel) { DSC_Print("ERROR - Invalid bits per pixel value specified."); ret = NVT_STATUS_INVALID_PARAMETER; @@ -2009,6 +2240,36 @@ DSC_GeneratePPS in->slice_count_mask = pDscInfo->sinkCaps.sliceCountSupportedMask; in->peak_throughput_mode0 = pDscInfo->sinkCaps.peakThroughputMode0; in->peak_throughput_mode1 = pDscInfo->sinkCaps.peakThroughputMode1; + + if (in->native_422) + { + if (in->dsc_version_minor == 1) + { + DSC_Print("Error! DSC1.1 can't support native422!\n"); + ret = NVT_STATUS_INVALID_PARAMETER; + goto done; + } + //the bpp in native 422 mode is doubled. + if((((NvS32)(in->bits_per_pixel)) < (NvS32)(2*6*BPP_UNIT)) || + (((NvS32)(in->bits_per_pixel)) > (NvS32)(2*32*BPP_UNIT-1))) + { + DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", + in->bits_per_pixel, 2*6*BPP_UNIT, 2*32*BPP_UNIT-1); + ret = NVT_STATUS_INVALID_PARAMETER; + goto done; + } + } + else + { + if ((((NvS32)(in->bits_per_pixel)) < (NvS32)(8*BPP_UNIT)) || + (((NvS32)(in->bits_per_pixel)) > (NvS32)(32*BPP_UNIT))) + { + DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", + in->bits_per_pixel, 8*BPP_UNIT, 32*BPP_UNIT); + ret = NVT_STATUS_INVALID_PARAMETER; + goto done; + } + } ret = DSC_PpsDataGen(in, pps); diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index 67df6eaf1..4dd5b859f 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -2871,6 +2871,7 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) pHdmiInfo->cnmvrr = pHdmiForum->CNMVRR; pHdmiInfo->cinemaVrr = pHdmiForum->CinemaVRR; pHdmiInfo->m_delta = pHdmiForum->M_delta; + pHdmiInfo->fapa_end_extended = pHdmiForum->FAPA_End_Extended; // sixth byte if (!remainingSize--) diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index 047d7af93..cf96ebdde 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -304,6 +304,7 @@ typedef enum NVT_TIMING_TYPE NVT_TYPE_DISPLAYID_8, // DisplayID 2.0 enumerated timing - Type VIII NVT_TYPE_DISPLAYID_9, // DisplayID 2.0 formula-based timing - Type IX NVT_TYPE_DISPLAYID_10, // DisplayID 2.0 formula-based timing - Type X + NVT_TYPE_CVT_RB_3, // CVT timing with reduced blanking V3 }NVT_TIMING_TYPE; // // 5. the timing sequence number like the TV format and EIA861B predefined timing format @@ -357,6 +358,7 @@ typedef enum NVT_TV_FORMAT #define NVT_STATUS_CVT NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT, 0) // CVT timing with regular blanking #define NVT_STATUS_CVT_RB NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB, 0) // CVT_RB timing #define NVT_STATUS_CVT_RB_2 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_2, 0) // CVT_RB timing V2 +#define NVT_STATUS_CVT_RB_3 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_3, 0) // CVT_RB timing V3 #define NVT_STATUS_CUST NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST, 0) // Customized timing #define NVT_STATUS_EDID_DTD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_DTD, 0) #define NVT_STATUS_EDID_STD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_STD, 0) @@ -2081,6 +2083,7 @@ typedef struct tagNVT_HDMI_LLC_INFO typedef struct tagNVT_HDMI_FORUM_INFO { NvU8 max_TMDS_char_rate; + NvU8 threeD_Osd_Disparity : 1; NvU8 dual_view : 1; NvU8 independent_View : 1; @@ -2089,29 +2092,40 @@ typedef struct tagNVT_HDMI_FORUM_INFO NvU8 cable_status : 1; NvU8 rr_capable : 1; NvU8 scdc_present : 1; + NvU8 dc_30bit_420 : 1; NvU8 dc_36bit_420 : 1; NvU8 dc_48bit_420 : 1; NvU8 uhd_vic : 1; NvU8 max_FRL_Rate : 4; + NvU8 fapa_start_location : 1; NvU8 allm : 1; NvU8 fva : 1; NvU8 cnmvrr : 1; NvU8 cinemaVrr : 1; NvU8 m_delta : 1; - NvU8 vrr_min : 6; + NvU8 fapa_end_extended : 1; + NvU8 rsvd : 1; + + NvU16 vrr_min : 6; NvU16 vrr_max : 10; + + NvU16 dsc_MaxSlices : 6; + NvU16 dsc_MaxPclkPerSliceMHz : 10; + NvU8 dsc_10bpc : 1; NvU8 dsc_12bpc : 1; NvU8 dsc_16bpc : 1; NvU8 dsc_All_bpp : 1; + NvU8 dsc_Max_FRL_Rate : 4; + NvU8 dsc_Native_420 : 1; NvU8 dsc_1p2 : 1; - NvU8 dsc_MaxSlices : 6; - NvU16 dsc_MaxPclkPerSliceMHz : 10; - NvU8 dsc_Max_FRL_Rate : 4; + NvU8 rsvd_2 : 6; + NvU8 dsc_totalChunkKBytes : 7; // = 1 + EDID reported DSC_TotalChunkKBytes + NvU8 rsvd_3 : 1; } NVT_HDMI_FORUM_INFO; @@ -2785,10 +2799,6 @@ typedef struct tagNVT_SPD_INFOFRAME_PAYLOAD NvU8 productBytes[16]; NvU8 sourceInformation; - - // Since HDMI Library doesn't clear the rest of the bytes and checksum is calculated for all the 32 bytes : Temporary WAR - NvU8 paddingBytes[3]; - } NVT_SPD_INFOFRAME_PAYLOAD; @@ -3720,7 +3730,9 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD NvU8 CNMVRR : 1; NvU8 CinemaVRR : 1; NvU8 M_delta : 1; - NvU8 Rsvd_2 : 2; + NvU8 Rsvd_2 : 1; + NvU8 FAPA_End_Extended : 1; + // sixth byte NvU8 VRR_min : 6; NvU8 VRR_max_high : 2; @@ -5253,6 +5265,7 @@ NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcCVT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is1000div1001, NVT_TIMING *pT); +NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT); NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming); // CEA/EIA/Psf timing diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 5244f936b..8dd71eab5 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2014-2022 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ // // nvlink.h @@ -72,6 +71,7 @@ extern "C" { #define NVLINK_TRANSITION_OFF_TIMEOUT 1 #define NVLINK_TRANSITION_SAFE_TIMEOUT 300 #define NVLINK_TRANSITION_HS_TIMEOUT 8000 +#define NVLINK_TRANSITION_ACTIVE_PENDING 2000 #define NVLINK_TRANSITION_POST_HS_TIMEOUT 70 // Link training seed values @@ -109,9 +109,17 @@ struct nvlink_device NvU64 type; NvBool initialized; + // Training type: ALI or Non-ALI + NvBool enableALI; + // fabric node id NvU16 nodeId; + // per Ioctrl data + NvU32 numIoctrls; + NvU32 numLinksPerIoctrl; + NvU32 numActiveLinksPerIoctrl; + // Client private information void *pDevInfo; }; @@ -249,6 +257,7 @@ struct nvlink_link_handlers NV_API_CALL NvlStatus (*read_discovery_token) (struct nvlink_link *link, NvU64 *token); NV_API_CALL void (*training_complete) (struct nvlink_link *link); NV_API_CALL void (*get_uphy_load) (struct nvlink_link *link, NvBool* bUnlocked); + NV_API_CALL NvlStatus (*ali_training) (struct nvlink_link *link); }; // @@ -318,11 +327,15 @@ typedef struct nvlink_inband_data nvlink_inband_data; #define NVLINK_LINKSTATE_DISABLE_HEARTBEAT 0x18 // Disables the heartbeat errors #define NVLINK_LINKSTATE_CONTAIN 0x19 // TL is in contain mode #define NVLINK_LINKSTATE_INITTL 0x1A // INITTL +#define NVLINK_LINKSTATE_INITPHASE5 0x1B // INITPHASE5 +#define NVLINK_LINKSTATE_ALI 0x1C // ALI +#define NVLINK_LINKSTATE_ACTIVE_PENDING 0x1D // Intermediate state for a link going to active #define NVLINK_LINKSTATE_INVALID 0xFF // Invalid state // NVLINK TX SUBLINK states #define NVLINK_SUBLINK_STATE_TX_HS 0x0 // TX High Speed #define NVLINK_SUBLINK_STATE_TX_SINGLE_LANE 0x4 // TX Single Lane (1/8th or 1/4th) Mode (Deprecated) +#define NVLINK_SUBLINK_STATE_TX_LOW_POWER 0x4 // TX Single Lane Mode / L1 #define NVLINK_SUBLINK_STATE_TX_TRAIN 0x5 // TX training #define NVLINK_SUBLINK_STATE_TX_SAFE 0x6 // TX Safe Mode #define NVLINK_SUBLINK_STATE_TX_OFF 0x7 // TX OFF @@ -336,6 +349,7 @@ typedef struct nvlink_inband_data nvlink_inband_data; // NVLINK RX SUBLINK states #define NVLINK_SUBLINK_STATE_RX_HS 0x0 // RX High Speed #define NVLINK_SUBLINK_STATE_RX_SINGLE_LANE 0x4 // RX Single Lane (1/8th or 1/4th) Mode (Deprecated) +#define NVLINK_SUBLINK_STATE_RX_LOW_POWER 0x4 // RX Single Lane Mode / L1 #define NVLINK_SUBLINK_STATE_RX_TRAIN 0x5 // RX training #define NVLINK_SUBLINK_STATE_RX_SAFE 0x6 // RX Safe Mode #define NVLINK_SUBLINK_STATE_RX_OFF 0x7 // RX OFF @@ -426,6 +440,15 @@ NvlStatus nvlink_lib_set_link_master(nvlink_link *link); */ NvlStatus nvlink_lib_get_link_master(nvlink_link *link, nvlink_link **master); +/* + * Set the training state for the given link as non-ALI or ALI + */ +NvlStatus nvlink_lib_is_link_using_ALI(nvlink_link *link, NvBool *usingALI); + +/* + * Set the training state for the given link as non-ALI or ALI + */ +NvlStatus nvlink_lib_link_set_training_mode(nvlink_link *link, NvBool enableALI); /************************************************************************************************/ /*************************** NVLink topology discovery functions ********************************/ /************************************************************************************************/ @@ -508,6 +531,7 @@ void nvlink_lib_restore_training_seeds(nvlink_link * link, NvlStatus nvlink_lib_check_training_complete(nvlink_link **links, NvU32 linkCount); + /************************************************************************************************/ /********************************** NVLink shutdown functions ***********************************/ /************************************************************************************************/ @@ -542,21 +566,26 @@ NvlStatus nvlink_lib_reset_links(nvlink_link **links, NvU32 numLinks, NvU32 flags); +/* + * Floorsweep the necessary links and set buffer ready on the active links + */ +NvlStatus nvlink_lib_powerdown_floorswept_links_to_off(nvlink_device *pDevice); + /* * Nvlink core library structure iterators */ -#define FOR_EACH_DEVICE_REGISTERED(dev, head, node) \ +#define FOR_EACH_DEVICE_REGISTERED(dev, head, node) \ nvListForEachEntry(dev, &head.node, node) -#define FOR_EACH_LINK_REGISTERED(link, dev, node) \ +#define FOR_EACH_LINK_REGISTERED(link, dev, node) \ nvListForEachEntry(link, &dev->link_list, node) #define FOR_EACH_LINK_REGISTERED_SAFE(link, next, dev, node) \ nvListForEachEntry_safe(link, next, &dev->link_list, node) -#define FOR_EACH_CONNECTION(conn, head, node) \ +#define FOR_EACH_CONNECTION(conn, head, node) \ nvListForEachEntry(conn, &head.node, node) #ifdef __cplusplus diff --git a/src/common/nvlink/interface/nvlink_common.h b/src/common/nvlink/interface/nvlink_common.h index 5a671768c..d70f44028 100644 --- a/src/common/nvlink/interface/nvlink_common.h +++ b/src/common/nvlink/interface/nvlink_common.h @@ -69,6 +69,7 @@ struct nvlink_detailed_device_info NvU64 deviceType; NvU8 *devUuid; NvBool bInitialized; + NvBool bEnableALI; void *dev_info; // Endpoint driver device info opaque // to core lib. Passed from end point // driver to core diff --git a/src/common/nvlink/interface/nvlink_lib_ctrl.h b/src/common/nvlink/interface/nvlink_lib_ctrl.h index 19bb0168e..1a481c69d 100644 --- a/src/common/nvlink/interface/nvlink_lib_ctrl.h +++ b/src/common/nvlink/interface/nvlink_lib_ctrl.h @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2016-2022 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #ifndef _NVLINK_LIB_CTRL_H_ #define _NVLINK_LIB_CTRL_H_ @@ -30,7 +29,7 @@ /* List of supported capability type */ #define NVLINK_CAP_FABRIC_MANAGEMENT 0 -/* +/* * Max supported capabilities count * */ @@ -62,7 +61,7 @@ /* * Total number of nvlink endpoints core library can have - * This is mapped to NVLINK_MAX_SYSTEM_LINK_NUM in drivers/nvlink/interface/nvlink.h + * This is mapped to NVLINK_MAX_SYSTEM_LINK_NUM in drivers/nvlink/interface/nvlink.h */ #define NVLINK_MAX_NVLINK_ENDPOINTS 624 @@ -90,7 +89,7 @@ typedef struct typedef struct { NvU16 nodeId; - NvU32 linkIndex; + NvU16 linkIndex; nvlink_pci_dev_info pciInfo; } nvlink_endpoint; @@ -110,13 +109,15 @@ typedef struct NvU16 numLinks; NvU32 devType; NV_DECLARE_ALIGNED(NvU64 enabledLinkMask, 8); + NvBool bEnableAli; + /* See struct definition modification guidelines at the top of this file */ } nvlink_detailed_dev_info; /* detailed information about a remote nvlink connection endpoint */ typedef struct { NvU16 nodeId; - NvU32 linkIndex; + NvU16 linkIndex; nvlink_pci_dev_info pciInfo; NvU8 devUuid[NVLINK_UUID_LEN]; NvU32 devType; @@ -188,9 +189,9 @@ typedef enum /* link and sublink state of an nvlink endpoint */ typedef struct { - NvU32 linkMode; - NvU32 txSubLinkMode; - NvU32 rxSubLinkMode; + NvU8 linkMode; + NvU8 txSubLinkMode; + NvU8 rxSubLinkMode; } nvlink_link_state; /* @@ -353,7 +354,7 @@ typedef struct */ typedef struct { - NvU32 linkIndex; + NvU16 linkIndex; NvBool initStatus; } nvlink_link_init_status; @@ -502,7 +503,7 @@ typedef struct */ typedef struct { - NvU32 linkIndex; + NvU16 linkIndex; NV_DECLARE_ALIGNED(NvU64 tokenValue, 8); } nvlink_token_info; @@ -586,6 +587,7 @@ typedef enum nvlink_train_conn_to_off, nvlink_train_conn_active_to_swcfg, nvlink_train_conn_swcfg_to_off, + /* See enum modification guidelines at the top of this file */ } nvlink_conn_train_type; typedef struct @@ -1075,7 +1077,7 @@ typedef struct } nvlink_initphase5; /* - * CTRL_NVLINK_GET_DEVICE_LINKS_STATE + * CTRL_NVLINK_GET_DEVICE_LINK_STATES * * Returns the link state of all enabled links on a given device. * @@ -1109,6 +1111,11 @@ typedef struct NvU32 endStatesCount; } nvlink_get_device_link_states; +/* + * Note: Verify that new parameter structs for IOCTLs satisfy + * sizing restrictions for all OSs they could be used in. + */ + #define CTRL_NVLINK_CHECK_VERSION 0x01 #define CTRL_NVLINK_SET_NODE_ID 0x02 #define CTRL_NVLINK_SET_TX_COMMON_MODE 0x03 diff --git a/src/common/nvlink/interface/nvlink_lock.h b/src/common/nvlink/interface/nvlink_lock.h index df707ddaa..0b1a2bd92 100644 --- a/src/common/nvlink/interface/nvlink_lock.h +++ b/src/common/nvlink/interface/nvlink_lock.h @@ -1,25 +1,21 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020 NVidia Corporation + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #ifndef _NVLINK_LOCK_H_ diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c index ee483fb2a..1698296d4 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -392,7 +391,9 @@ nvlink_core_check_intranode_conn_state if ((nvlink_core_check_link_state(conn->end0, NVLINK_LINKSTATE_HS)) && (nvlink_core_check_link_state(conn->end1, NVLINK_LINKSTATE_HS))) { - if (!((nvlink_core_check_tx_sublink_state(conn->end0, + // In NVLINK4.0, corelib doesn't control sublink state transitions + if (conn->end0->version < NVLINK_DEVICE_VERSION_40 && + !((nvlink_core_check_tx_sublink_state(conn->end0, NVLINK_SUBLINK_STATE_TX_HS)) && (nvlink_core_check_tx_sublink_state(conn->end1, NVLINK_SUBLINK_STATE_TX_HS)) && @@ -455,6 +456,16 @@ nvlink_core_check_intranode_conn_state return NVL_ERR_GENERIC; } + case NVLINK_LINKSTATE_ACTIVE_PENDING: + { + // Check if both ends of connection are already in ACTIVE_PENDING + if ((nvlink_core_check_link_state(conn->end0, NVLINK_LINKSTATE_ACTIVE_PENDING)) && + (nvlink_core_check_link_state(conn->end1, NVLINK_LINKSTATE_ACTIVE_PENDING))) + { + return NVL_SUCCESS; + } + break; + } } return NVL_SUCCESS; diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c index d39264a78..2cd2c2a64 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -85,6 +84,15 @@ nvlink_core_discover_and_get_remote_end pLinks[linkCount++] = link; } } + + if (pLinks[0]->version >= NVLINK_DEVICE_VERSION_40) + { + if (!pLinks[0]->dev->enableALI) + { + nvlink_core_init_links_from_off_to_swcfg_non_ALI(pLinks, linkCount, flags); + } + } + else { nvlink_core_init_links_from_off_to_swcfg(pLinks, linkCount, flags); } @@ -216,11 +224,12 @@ _nvlink_core_discover_topology(void) isTokenFound = NV_TRUE; // - // If R4 tokens were used for NVLink3.0+, then mark initnegotiate - // passed, since ALT training won't get kicked off without it. + // If a token is found mark bInitnegotiateConfigGood as + // True since we can only finish off discovery if + // INITNEGOTIATE has finished in order to get topology info from + // MINION // - if ((end0->version >= NVLINK_DEVICE_VERSION_30) && - ((end0->localSid == 0) || (end0->remoteSid == 0))) + if ((end0->version >= NVLINK_DEVICE_VERSION_30)) { end0->bInitnegotiateConfigGood = NV_TRUE; end1->bInitnegotiateConfigGood = NV_TRUE; diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c index 7d47bf59a..f2d50b4eb 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2021 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -255,6 +254,294 @@ nvlink_core_init_links_from_off_to_swcfg nvlink_core_initnegotiate(pLinks, numLinks, flags); } +/** + * Initialize all the endpoints from OFF to SWCFG state + * Used for NvLink 4.0+ + * + * @param[in] links Array of link endpoints to initialize + * @param[in] numLinks Number of links in the array + * @param[in] flags Flags to determine whether init is sync/async + */ +void +nvlink_core_init_links_from_off_to_swcfg_non_ALI +( + nvlink_link **pLinks, + NvU32 numLinks, + NvU32 flags +) +{ + NvlStatus status = NVL_SUCCESS; + NvU64 linkMode; + NvU32 i; + + // Sanity check the links array + nvlink_assert(pLinks != NULL); + + // Return early if there are no links to initialize + if (numLinks == 0) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: No links to initialize\n", + __FUNCTION__)); + return; + } + + // Step 1: Perform INITPHASE1 on all endpoints + nvlink_core_initphase1(pLinks, numLinks, flags); + + // Get state on all links. This ensures NVLINK_LINKSTATE_INITPHASE1 completes + if (flags == NVLINK_STATE_CHANGE_ASYNC) + { + for (i = 0; i < numLinks; i++) + { + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); + if ((status != NVL_SUCCESS) || + (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Link %s:%s is in bad state\n", + __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + } + } + } + + // Step 2 RECEIVER DETECT :Perform receiver detect on all the endpoints + nvlink_core_set_rx_detect(pLinks, numLinks, flags); + + // Get state on all links. This ensures receiver detect command completes + if (flags == NVLINK_STATE_CHANGE_ASYNC) + { + for (i = 0; i < numLinks; i++) + { + // In NVLink3.0 and 3.1, RXDET must be called serially - done above (Bug 2546220) + if (!((pLinks[i]->version == NVLINK_DEVICE_VERSION_30) || + (pLinks[i]->version == NVLINK_DEVICE_VERSION_31))) + { + // If receiver detect has passed for the link, move to next link + if (pLinks[i]->bRxDetected) + continue; + + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); + if ((status != NVL_SUCCESS) || + (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Link %s:%s is in bad state\n", + __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + } + } + } + } + + // Step 2.1 RECEIVER DETECT :Poll for output of receiver detect on all the endpoints + nvlink_core_get_rx_detect(pLinks, numLinks, flags); + + + /***************** Receiver Detect is completed at this point ****************/ + /***************** Proceed with the link initialization steps ****************/ + + // Step 3: Enable Common mode on all Tx's + nvlink_core_enable_common_mode(pLinks, numLinks, flags); + + // Get state on all links. This ensures NVLINK_SUBLINK_STATE_TX_COMMON_MODE completes + if (flags == NVLINK_STATE_CHANGE_ASYNC) + { + for (i = 0; i < numLinks; i++) + { + // If receiver detect failed for the link, move to next link + if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail) + continue; + + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); + if ((status != NVL_SUCCESS) || + (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Link %s:%s is in bad state\n", + __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + } + } + } + + // Step 4: call INITPHASE5 + nvlink_core_initphase5(pLinks, numLinks, flags); + + // Get state on all links. This ensures NVLINK_SUBLINK_STATE_TX_DATA_READY completes + if (flags == NVLINK_STATE_CHANGE_ASYNC) + { + for (i = 0; i < numLinks; i++) + { + // If receiver detect failed for the link, move to next link + if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails) + continue; + + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); + if ((status != NVL_SUCCESS) || + (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Link %s:%s is in bad state\n", + __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + } + } + } + + // Step 5: Put the links in SAFE mode + for (i = 0; i < numLinks; i++) + { + // If receiver detect failed for the link, move to next link + if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails) + continue; + + linkMode = 0; + if (pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get link mode for %s:%s", + __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + } + + if ((linkMode != NVLINK_LINKSTATE_SAFE) && (linkMode != NVLINK_LINKSTATE_HS)) + { + // Check if the link has reached failed state + if (pLinks[i]->state == NVLINK_LINKSTATE_FAIL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "%s:%s marked as failed.\n", + pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + continue; + } + + // + // Check if number of attempts to put the link into + // safe state has already exceeded the maximum number + // of retries. If yes, mark the link as failed + // + // On NVLink3.0, we don't support retraining in the driver. + // However MODS test 252 (on NVL3+ specifically) will train + // HS->OFF->HS many times. This check causes RM to stop + // training after NVLINK_MAX_NUM_SAFE_RETRIES times + // + if ((pLinks[i]->safe_retries > NVLINK_MAX_NUM_SAFE_RETRIES) && + (pLinks[i]->version < NVLINK_DEVICE_VERSION_30)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "Max safe mode retries reached for %s:%s. Marking it as failed.\n", + + pLinks[i]->dev->deviceName, pLinks[i]->linkName)); + pLinks[i]->state = NVLINK_LINKSTATE_FAIL; + continue; + } + + // Put the link in safe state and increment the retry count + pLinks[i]->link_handlers->set_dl_link_mode(pLinks[i], NVLINK_LINKSTATE_SAFE, flags); + pLinks[i]->safe_retries++; + } + } + + // Poll for links to enter SAFE mode + for (i = 0; i < numLinks; i++) + { + status = nvlink_core_wait_for_link_init(pLinks[i]); + if (status == NVL_SUCCESS) + { + pLinks[i]->powerStateTransitionStatus = nvlink_power_state_in_L0; + } + } + + // Send INITNEGOTIATE to all the links + nvlink_core_initnegotiate(pLinks, numLinks, flags); +} + +/** + * Kick-off INITPHASE5 on the given array of links + * + * @param[in] links Array of nvlink_link pointers + * @param[in] numLinks Number of links in the array + * @param[in] flags Flags - Async/Sync + * + * return NvlStatus + */ +NvlStatus +nvlink_core_initphase5 +( + nvlink_link **links, + NvU32 numLinks, + NvU32 flags +) +{ + NvU32 i; + + // Sanity check the links array + nvlink_assert(links != NULL); + + // Return early if link array is empty + if (numLinks == 0) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "%s: Link array is empty\n", + __FUNCTION__)); + return NVL_SUCCESS; + } + + for (i = 0; i < numLinks; i++) + { + NvlStatus status = NVL_SUCCESS; + NvU64 dlLinkMode = 0; + + // INITPHASE5 is supported only for NVLINK version >= 4.0 + if (links[i]->version < NVLINK_DEVICE_VERSION_40) + continue; + + // If receiver detect failed for the link, move to next link + if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail) + continue; + + if (links[i]->link_handlers->get_dl_link_mode(links[i], &dlLinkMode)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get link mode for %s:%s", + __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName)); + } + + // Check if the link has reached failed state + if (links[i]->state == NVLINK_LINKSTATE_FAIL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "%s: %s:%s marked as failed.\n", + __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName)); + continue; + } + + // Skip this step if link is in HS/SAFE + if (dlLinkMode == NVLINK_LINKSTATE_HS || + dlLinkMode == NVLINK_LINKSTATE_SAFE) + { + continue; + } + + status = links[i]->link_handlers->set_dl_link_mode(links[i], + NVLINK_LINKSTATE_INITPHASE5, + flags); + + // Although it fails we need to continue with the next link + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Initphase5 failed on Device:Link %s:%s\n", + __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName)); + links[i]->bInitphase5Fails = NV_TRUE; + } + } + + // + // We could have links which are faulty and cannot be initialized. But proceeding + // the initialization sequence allows us to use other non-faulty links. Therefore + // return success always. + // + return NVL_SUCCESS; +} + /** * Kick-off INITPHASE1 on the given array of links * @@ -295,11 +582,16 @@ nvlink_core_initphase1 NvU32 txSubMode = 0; NvU64 rxMode = 0; NvU32 rxSubMode = 0; + NvBool bPhyUnlocked = NV_FALSE; // INITPHASE1 is supported only for NVLINK version >= 3.0 if (links[i]->version < NVLINK_DEVICE_VERSION_30) continue; + if (links[i]->version >= NVLINK_DEVICE_VERSION_40) + links[i]->link_handlers->get_uphy_load(links[i], &bPhyUnlocked); + + if (!bPhyUnlocked) { if (links[i]->link_handlers->get_tl_link_mode(links[i], &tlLinkMode)) { @@ -343,6 +635,7 @@ nvlink_core_initphase1 // if ((tlLinkMode == NVLINK_LINKSTATE_SLEEP) || (dlLinkMode == NVLINK_LINKSTATE_RESET) || + (bPhyUnlocked) || ((txMode == NVLINK_SUBLINK_STATE_TX_OFF) && (rxMode == NVLINK_SUBLINK_STATE_RX_OFF))) { diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c index a0c0880b7..cfbc5707f 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2017-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvVer.h" @@ -443,6 +442,8 @@ nvlink_core_copy_device_info devInfo->numLinks = nvListCount(&tmpDev->link_list); devInfo->devType = _nvlink_core_map_device_type(tmpDev->type); devInfo->enabledLinkMask = _nvlink_core_get_enabled_link_mask(tmpDev); + devInfo->bEnableAli = tmpDev->enableALI; + // copy device uuid information if available if (tmpDev->uuid != NULL) { diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c index 717cd3eb1..c0f4f94b9 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -68,7 +67,36 @@ nvlink_core_check_link_state } break; } + case NVLINK_LINKSTATE_ALI: + { + status = link->link_handlers->get_tl_link_mode(link, &crntTlLinkMode); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get TL link mode for %s:%s\n", + __FUNCTION__, link->dev->deviceName, link->linkName)); + return NV_FALSE; + } + + status = link->link_handlers->get_dl_link_mode(link, &crntDlLinkMode); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get DL link mode for %s:%s\n", + __FUNCTION__, link->dev->deviceName, link->linkName)); + return NV_FALSE; + } + + if (crntTlLinkMode == NVLINK_LINKSTATE_HS && + (crntDlLinkMode == NVLINK_LINKSTATE_HS || + crntDlLinkMode == NVLINK_LINKSTATE_SLEEP)) + { + return NV_TRUE; + } + break; + } case NVLINK_LINKSTATE_SLEEP: + case NVLINK_LINKSTATE_ACTIVE_PENDING: { status = link->link_handlers->get_tl_link_mode(link, &crntTlLinkMode); if (status != NVL_SUCCESS) @@ -85,7 +113,6 @@ nvlink_core_check_link_state } break; } - } // return false for default case or the states are not matching diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c index f087c9656..52cb95b65 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index ca601a5b0..e30cda60b 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -431,7 +430,7 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // to track Failure conns[i]->end0->inSWCFG = NV_FALSE; - } + } else { conns[i]->end0->inSWCFG = NV_TRUE; @@ -449,14 +448,14 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // to track Failure conns[i]->end1->inSWCFG = NV_FALSE; - } + } else { conns[i]->end1->inSWCFG = NV_TRUE; } // Change each sublink state to SAFE - if(conns[i]->end0->inSWCFG == NV_TRUE) + if(conns[i]->end0->inSWCFG == NV_TRUE) { conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, @@ -843,3 +842,148 @@ _nvlink_core_clear_link_state link->tx_sublink_state = NVLINK_SUBLINK_STATE_TX_OFF; link->rx_sublink_state = NVLINK_SUBLINK_STATE_RX_OFF; } + +static NvBool +_nvlink_core_check_if_conn_in_array +( + nvlink_intranode_conn **connArray, + NvU32 connArrayLength, + nvlink_intranode_conn *conn +) +{ + NvU32 i; + + for (i = 0; i < connArrayLength; ++i) + { + if (conn == connArray[i]) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +NvlStatus +nvlink_core_powerdown_floorswept_conns_to_off +( + nvlink_link **links, + NvU32 linkCount, + NvU32 numIoctrls, + NvU32 numLinksPerIoctrl, + NvU32 numActiveLinksPerIoctrl +) +{ + NvU32 i,j; + nvlink_intranode_conn **connsToShutdown; + nvlink_intranode_conn **visitedConns; + nvlink_intranode_conn *conn; + NvU32 connCount; + NvU32 numConnsToShutdown; + + if (linkCount == 0 || numIoctrls == 0 || numLinksPerIoctrl == 0 || + numActiveLinksPerIoctrl == 0) + { + return NVL_BAD_ARGS; + } + + connsToShutdown = (nvlink_intranode_conn **)nvlink_malloc( + sizeof(nvlink_intranode_conn *) * NVLINK_MAX_SYSTEM_LINK_NUM); + + if (connsToShutdown == NULL) + { + return NVL_NO_MEM; + } + + visitedConns = (nvlink_intranode_conn **)nvlink_malloc( + sizeof(nvlink_intranode_conn *) * NVLINK_MAX_SYSTEM_LINK_NUM); + + if (visitedConns == NULL) + { + return NVL_NO_MEM; + } + + + // + // For each IOCTRL find the total # of connections and shutdown + // any connections over the number of active links per IOCTRL + // + for (i=0; ilinkNumber >= numLinksPerIoctrl*i && + links[j]->linkNumber < numLinksPerIoctrl*(i+1)) + { + nvlink_core_get_intranode_conn(links[j], &(conn)); + if (conn == NULL || + _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || + (conn->end0 == NULL || conn->end1 == NULL)) + { + continue; + } + else if(nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_OFF) == + NVL_SUCCESS) + { + continue; + } + else if ((nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_HS) != NVL_SUCCESS && + nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_SAFE) != NVL_SUCCESS) && + (!_nvlink_core_check_if_conn_in_array(connsToShutdown, numConnsToShutdown, conn))) + { + // If link is not in SAFE or HS and not currently in our connsToShutdown array then add it + connsToShutdown[numConnsToShutdown++] = conn; + } + else + { + visitedConns[connCount++] = conn; + if (connCount > numActiveLinksPerIoctrl && + !_nvlink_core_check_if_conn_in_array(connsToShutdown, numConnsToShutdown, conn)) + { + connsToShutdown[numConnsToShutdown++] = conn; + } + } + + // + // If the #of conns found == #of links per IOCTRl then + // bail early since we know none of the other links can be + // part of this IOCTRL + // + if (connCount == numLinksPerIoctrl) + { + connCount = 0; + break; + } + } + } + + // + // If the number of shutdown is non-zero then shutdown the connections + // and remove the connection from the corelib since all endpoints + // will query the corelib for topology and this connection should no longer + // be reported + // + if (numConnsToShutdown != 0) + { + nvlink_core_powerdown_intranode_conns_from_active_to_off(connsToShutdown, numConnsToShutdown, 0); + + for (j = 0; j < numConnsToShutdown; ++j) + { + nvlink_core_remove_intranode_conn(connsToShutdown[j]); + } + } + } + + return NVL_SUCCESS; +} diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c index 6bf16f70f..d2d0a2d9d 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -31,6 +30,31 @@ static void _nvlink_core_set_sublink_pre_hs_settings(nvlink_link *, NvU32); static void _nvlink_core_set_link_pre_active_settings(nvlink_link *, NvU32); static void _nvlink_core_set_link_post_active_settings(nvlink_link *, NvU32); +NvlStatus +nvlink_core_train_check_link_ready_ALI +( + nvlink_link **links, + NvU32 linkCount +) +{ + NvU32 i = 0; + NvlStatus status = NVL_SUCCESS; + + for (i = 0; i < linkCount; i++) + { + if (!nvlink_core_check_link_state(links[i], NVLINK_LINKSTATE_ALI)) + { + // If link is not in active, update status to be error and continue + status = NVL_ERR_GENERIC; + continue; + } + + links[i]->link_handlers->training_complete(links[i]); + } + + return status; +} + /** * Link training * Train the internode connection link from SWCFG to ACTIVE @@ -671,6 +695,157 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active return status; } +/** + * Train intranode connections associated with a list of links to HS + * using non-ALI sequence + * + * @param[in] conns Array of connections to train + * @param[in] connCount Number of connections in the array + * @param[in] flags Flags to track if training is sync/async + * + * return NVL_SUCCESS if the connections train successfully + */ +NvlStatus +nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI +( + nvlink_intranode_conn **conns, + NvU32 connCount, + NvU32 flags +) +{ + NvlStatus status = NVL_SUCCESS; + NvlStatus pollStatus = NVL_SUCCESS; + NvU32 i; + + if ((conns == NULL) || (connCount == 0)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: No connections to train to ACTIVE\n", + __FUNCTION__)); + + return NVL_ERR_GENERIC; + } + + // Trigger INITOPTIMIZE on both ends of the connection + for (i = 0; i < connCount; i++) + { + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, + NVLINK_LINKSTATE_INITOPTIMIZE, + flags); + + // On loopback, only send INITOPTIMIZE to one side. + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1, + NVLINK_LINKSTATE_INITOPTIMIZE, + flags); + } + } + + // Trigger POST_INITOPTIMIZE (Checks INITOPTIMIZE was successful) on both ends of the connection + for (i = 0; i < connCount; i++) + { + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, + NVLINK_LINKSTATE_POST_INITOPTIMIZE, + flags); + + // On loopback, only send POST_INITOPTIMIZE to one side. + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1, + NVLINK_LINKSTATE_POST_INITOPTIMIZE, + flags); + } + } + + // Set link modes to ACTIVE + for (i = 0; i < connCount; i++) + { + // Some settings required before moving to ACTIVE + _nvlink_core_set_link_pre_active_settings(conns[i]->end0, flags); + _nvlink_core_set_link_pre_active_settings(conns[i]->end1, flags); + + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, + NVLINK_LINKSTATE_HS, + flags); + + // If not in loopback send the dl link mode + if (conns[i]->end0 != conns[i]->end1) + { + + conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1, + NVLINK_LINKSTATE_HS, + flags); + } + + } + + // Verify link mode HS on the endpoints + for (i = 0; i < connCount; i++) + { + + pollStatus = nvlink_core_poll_link_state(conns[i]->end0, + NVLINK_LINKSTATE_HS, + NVLINK_TRANSITION_HS_TIMEOUT); + if (pollStatus != NVL_SUCCESS) + { + status = pollStatus; + } + + pollStatus = nvlink_core_poll_link_state(conns[i]->end1, + NVLINK_LINKSTATE_HS, + NVLINK_TRANSITION_HS_TIMEOUT); + if (pollStatus != NVL_SUCCESS) + { + status = pollStatus; + } + + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, + NVLINK_LINKSTATE_INITTL, + flags); + + // On loopback, only send once + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1, + NVLINK_LINKSTATE_INITTL, + flags); + } + + conns[i]->end0->link_handlers->training_complete(conns[i]->end0); + + // On loopback, only send once + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->training_complete(conns[i]->end1); + } + + conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, + NVLINK_SUBLINK_STATE_TX_POST_HS, + flags); + // On loopback, only send once + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->set_tx_mode(conns[i]->end1, + NVLINK_SUBLINK_STATE_TX_POST_HS, + flags); + } + + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, + NVLINK_LINKSTATE_TRAFFIC_SETUP, + flags); + // On loopback, only send once + if (conns[i]->end0 != conns[i]->end1) + { + conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1, + NVLINK_LINKSTATE_TRAFFIC_SETUP, + flags); + } + } + + return status; +} + /** * Train intranode connections associated with a list of links to HS * using ALT sequence diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c index a0a07853e..807158355 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2017-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvVer.h" @@ -708,6 +707,12 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + if (links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_initphase1(links, numLinks, NVLINK_STATE_CHANGE_SYNC); break; @@ -727,6 +732,16 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + // + // If the current nvlink device does not support the command + // skip using the command and return success for FM to continue on. + // + if (links[0]->version >= NVLINK_DEVICE_VERSION_40) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_rx_init_term(links, numLinks, NVLINK_STATE_CHANGE_ASYNC); break; @@ -746,6 +761,12 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + if (links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_set_rx_detect(links, numLinks, NVLINK_STATE_CHANGE_ASYNC); break; @@ -765,6 +786,12 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + if (links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_get_rx_detect(links, numLinks, NVLINK_STATE_CHANGE_ASYNC); break; @@ -784,6 +811,12 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + if (links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + if (iocReq->commMode) { iocReq->status = nvlink_core_enable_common_mode(links, numLinks, @@ -816,6 +849,16 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + // + // If the current nvlink device does not support the command + // skip using the command and return success for FM to continue on. + // + if (links[0]->version >= NVLINK_DEVICE_VERSION_40) + { + iocReq->status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_calibrate_links(links, numLinks, NVLINK_STATE_CHANGE_SYNC); break; @@ -834,6 +877,16 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + // + // If the current nvlink device does not support the command + // skip using the command and return success for FM to continue on. + // + if (links[0]->version >= NVLINK_DEVICE_VERSION_40) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_enable_data(links, numLinks, NVLINK_STATE_CHANGE_SYNC); break; @@ -871,10 +924,17 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + if (links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_initnegotiate(links, numLinks, NVLINK_STATE_CHANGE_ASYNC); break; } + case CTRL_NVLINK_INITPHASE5: { nvlink_initphase5 *iocReq; @@ -889,6 +949,18 @@ nvlink_lib_ctrl_all_links // default initialize status to NVL_SUCCESS iocReq->status = NVL_SUCCESS; + // + // If the current nvlink device does not support the command + // skip using the command and return success for FM to continue on. + // + if (links[0]->version < NVLINK_DEVICE_VERSION_40 || + links[0]->dev->enableALI) + { + status = NVL_SUCCESS; + goto nvlink_lib_ctrl_all_links_end; + } + iocReq->status = nvlink_core_initphase5(links, numLinks, + NVLINK_STATE_CHANGE_ASYNC); break; } @@ -2043,6 +2115,16 @@ nvlink_lib_ctrl_train_intranode_conn { case nvlink_train_conn_off_to_swcfg: { + if (srcLink->version >= NVLINK_DEVICE_VERSION_40) + { + // non-ALI training for NVLink4.0+ + if (!srcLink->dev->enableALI) + { + nvlink_core_init_links_from_off_to_swcfg_non_ALI( + initLinks, count, NVLINK_STATE_CHANGE_SYNC); + } + } + else { // ALT training for NVLink3.0+ nvlink_core_init_links_from_off_to_swcfg( @@ -2052,8 +2134,16 @@ nvlink_lib_ctrl_train_intranode_conn } case nvlink_train_conn_swcfg_to_active: { - if (srcLink->version >= NVLINK_DEVICE_VERSION_30) - + if (srcLink->version >= NVLINK_DEVICE_VERSION_40) + { + // non-ALI training for NVLink4.0+ + if (!srcLink->dev->enableALI) + { + status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI( + &conn, 1, NVLINK_STATE_CHANGE_SYNC); + } + } + else if (srcLink->version >= NVLINK_DEVICE_VERSION_30) { // ALT training for NVLink3.0+ status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT( @@ -2333,6 +2423,16 @@ nvlink_lib_ctrl_train_intranode_conns_parallel { case nvlink_train_conn_off_to_swcfg: { + if (srcLink->version >= NVLINK_DEVICE_VERSION_40) + { + // non-ALI training for NVLink4.0+ + if (!srcLink->dev->enableALI) + { + nvlink_core_init_links_from_off_to_swcfg_non_ALI( + initLinks, count, NVLINK_STATE_CHANGE_SYNC); + } + } + else { // ALT training for NVLink3.0+ nvlink_core_init_links_from_off_to_swcfg( @@ -2342,6 +2442,16 @@ nvlink_lib_ctrl_train_intranode_conns_parallel } case nvlink_train_conn_swcfg_to_active: { + if (srcLink->version >= NVLINK_DEVICE_VERSION_40) + { + // non-ALI training for NVLink4.0+ + if (!srcLink->dev->enableALI) + { + status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI( + conns, numConns, NVLINK_STATE_CHANGE_SYNC); + } + } + else { // ALT training for NVLink3.0+ status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT( @@ -3418,8 +3528,6 @@ nvlink_lib_ctrl_get_device_link_states { nvlink_link *endpoint = NULL; nvlink_device *dev = NULL; - nvlink_device *devIter = NULL; - nvlink_link *remoteLink = NULL; NvlStatus status = NVL_SUCCESS; NvU32 numLinks = 0; NvU32 i = 0; @@ -3463,14 +3571,12 @@ nvlink_lib_ctrl_get_device_link_states // Top-level lock is now acquired. Proceed to traversing the list // of devices and list of links to lock all links // - FOR_EACH_DEVICE_REGISTERED(devIter, nvlinkLibCtx.nv_devicelist_head, node) + FOR_EACH_LINK_REGISTERED(endpoint, dev, node) { - FOR_EACH_LINK_REGISTERED(endpoint, devIter, node) - { - if (numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM) + if (numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM", + "%s: numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS", __FUNCTION__)); nvlink_assert(0); @@ -3483,7 +3589,6 @@ nvlink_lib_ctrl_get_device_link_states links[numLinks] = endpoint; numLinks++; } - } // Acquire the per-link locks status = nvlink_lib_link_locks_acquire(links, numLinks); @@ -3519,31 +3624,6 @@ nvlink_lib_ctrl_get_device_link_states "%s: link 0x%x -- rxDet status 0x%x, linkMode 0x%x,\n", __FUNCTION__, i, links[i]->bRxDetected, params->endStates[i].linkMode)); - // - // If the link succeeds rxDet then go through and find its peer link. What is important - // is not actually finding the link, but making sure the corelib goes through the discovery - // process and has endpoints cache the remote information in the corelib such that - // FM or endpoints can query the corelib for the topology of the system. - // - if (links[i]->bRxDetected) - { - remoteLink = NULL; - nvlink_core_discover_and_get_remote_end(links[i], &remoteLink, 0); - - if (remoteLink == NULL) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: link 0x%x: couldn't find link pair\n", - __FUNCTION__, i)); - continue; - } - - // If the link is in active, issue postActive settings - if (params->endStates[i].linkMode == nvlink_link_mode_active) - { - links[i]->link_handlers->training_complete(links[i]); - } - } } params->endStatesCount = numLinks; diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c index afbcb1717..4542e45e0 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c index 63474fcb5..f34f33a1d 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -108,6 +107,16 @@ nvlink_lib_reinit_link_from_off_to_swcfg // Release the top level-lock // nvlink_lib_top_lock_release(); + + if (conn->end0->version >= NVLINK_DEVICE_VERSION_40 || + conn->end1->version >= NVLINK_DEVICE_VERSION_40) + { + if (!conn->end0->dev->enableALI) + { + nvlink_core_init_links_from_off_to_swcfg_non_ALI(links, 2, flags); + } + } + else { nvlink_core_init_links_from_off_to_swcfg(links, 2, flags); } diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c index 1dc7733ec..261f6399a 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -320,4 +319,135 @@ nvlink_lib_get_link_master return status; } +/** + * Set whether the link is using ALI for training. + * + * @param[in] link NVLink Link pointer + * @param[in] enableALI Boolean for whether the link is using + * ALI to train the link + * + * return NvlSuccess if setting the variable was successful. + */ +NvlStatus +nvlink_lib_link_set_training_mode +( + nvlink_link *link, + NvBool enableALI +) +{ + NvlStatus status = NVL_SUCCESS; + if (link == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Bad link pointer specified.\n", + __FUNCTION__)); + return NVL_ERR_GENERIC; + } + + // Acquire the top-level lock + status = nvlink_lib_top_lock_acquire(); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + + return status; + } + + + // Acquire the per-link lock + status = nvlink_lib_link_locks_acquire(&link, 1); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire per-link locks\n", + __FUNCTION__)); + + // Release the top-level lock + nvlink_lib_top_lock_release(); + + return status; + } + + // + // All the required per-link locks are successfully acquired + // The connection list traversal is also complete now + // Release the top level-lock + // + nvlink_lib_top_lock_release(); + + // TODO: Add Setter for per-link enableALI state variable + + // Release the per-link lock + nvlink_lib_link_locks_release(&link, 1); + + return status; +} + +/** + * Get whether the link is using ALI for training. + * + * @param[in] link NVLink Link pointer + * @param[out] usingAli Boolean on whether ALI training is being used + * + * return NVL_SUCCESS if getting the variable is successful + */ +NvlStatus +nvlink_lib_is_link_using_ALI +( + nvlink_link *link, + NvBool *usingALI +) +{ + NvlStatus status = NVL_SUCCESS; + usingALI = NV_FALSE; + + if (link == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Bad link pointer specified.\n", + __FUNCTION__)); + return NVL_ERR_GENERIC; + } + + // Acquire the top-level lock + status = nvlink_lib_top_lock_acquire(); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + + return status; + } + + // Acquire the per-link lock + status = nvlink_lib_link_locks_acquire(&link, 1); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire per-link locks\n", + __FUNCTION__)); + + // Release the top-level lock + nvlink_lib_top_lock_release(); + + return status; + } + + // + // All the required per-link locks are successfully acquired + // The connection list traversal is also complete now + // Release the top level-lock + // + nvlink_lib_top_lock_release(); + + // TODO: Add Getter for per-link enableALI state variable + + // Release the per-link lock + nvlink_lib_link_locks_release(&link, 1); + + return status; +} diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c index 29345c796..db2b3efd4 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c index 760e5c917..5604870cf 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -304,10 +303,10 @@ nvlink_lib_powerdown_links_from_active_to_off nvlink_intranode_conn **conns = NULL; nvlink_intranode_conn *conn = NULL; NvU32 numConns = 0; - NvU32 i; + NvU32 i,j; NvU32 lockLinkCount = 0; nvlink_link **lockLinks = NULL; - + NvBool bIsAlreadyPresent = NV_FALSE; if ((links == NULL) || (numLinks == 0)) { @@ -424,8 +423,51 @@ nvlink_lib_powerdown_links_from_active_to_off continue; } - conns[numConns] = conn; - numConns++; + // + // If device is using ALI based link training, it is possible + // for links to be still transitioning to active when a request to shutdown + // is made. Ensure that all connections transiton successfully to HS or fault + // before continuining to shutdown + // + if(links[0]->dev->enableALI) + { + + status = nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_ACTIVE_PENDING); + + if (status == NVL_SUCCESS) + { + status = nvlink_core_poll_link_state(conn->end0, + NVLINK_LINKSTATE_HS, + NVLINK_TRANSITION_ACTIVE_PENDING); + + if (status != NVL_SUCCESS && + nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_FAULT) != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Connection between %s: %s and %s: %s is not ready for shutdown (link state is no in HS or FAULT). Soldiering on...\n", + __FUNCTION__, conn->end0->dev->deviceName, conn->end0->linkName, + conn->end1->dev->deviceName, conn->end1->linkName)); + } + } + } + + bIsAlreadyPresent = NV_FALSE; + // Check if the the connection is already included in the list + for (j = 0; j < numConns; j++) + { + if (conns[j] == conn) + { + bIsAlreadyPresent = NV_TRUE; + break; + } + } + + // If this is a new connection, add it to the list + if (!bIsAlreadyPresent) + { + conns[numConns] = conn; + numConns++; + } } // @@ -775,3 +817,109 @@ nvlink_lib_reset_links return status; } + + +NvlStatus +nvlink_lib_powerdown_floorswept_links_to_off +( + nvlink_device *dev +) +{ + NvlStatus status = NVL_SUCCESS; + nvlink_link *link = NULL; + nvlink_link **lockLinks = NULL; + NvU32 lockLinkCount = 0; + + if (dev == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Bad device pointer specified.\n", + __FUNCTION__)); + + return NVL_ERR_GENERIC; + } + + lockLinks = (nvlink_link **)nvlink_malloc( + sizeof(nvlink_link *) * NVLINK_MAX_SYSTEM_LINK_NUM); + if (lockLinks == NULL) + { + return NVL_NO_MEM; + } + + // Acquire the top-level lock + status = nvlink_lib_top_lock_acquire(); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + goto nvlink_core_powerdown_floorswept_conns_to_off_end; + } + + // + // If the device has less than or equal links in the IP then + // can be active, then skip floorsweeping + // + if (dev->numActiveLinksPerIoctrl >= dev->numLinksPerIoctrl) + { + nvlink_lib_top_lock_release(); + goto nvlink_core_powerdown_floorswept_conns_to_off_end; + } + + // + // Top-level lock is now acquired. Proceed to traversing the device + // and link lists and connection lists + // + + // Get the array of link endpoints whose lock needs to be acquired + FOR_EACH_LINK_REGISTERED(link, dev, node) + { + if(link == NULL) + { + continue; + } + + lockLinks[lockLinkCount] = link; + lockLinkCount++; + } + + // Acquire the per-link locks for all links captured + status = nvlink_lib_link_locks_acquire(lockLinks, lockLinkCount); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire per-link locks\n", + __FUNCTION__)); + + // Release the top-level lock + nvlink_lib_top_lock_release(); + + goto nvlink_core_powerdown_floorswept_conns_to_off_end; + } + + // + // All the required per-link locks are successfully acquired + // The connection list traversal is also complete now + // Release the top level-lock + // + nvlink_lib_top_lock_release(); + + status = nvlink_core_powerdown_floorswept_conns_to_off(lockLinks, lockLinkCount, dev->numIoctrls, + dev->numLinksPerIoctrl, dev->numActiveLinksPerIoctrl); + + if (status == NVL_BAD_ARGS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "%s: Bad args passed in for floorsweeping. Chip might not support the feature\n", + __FUNCTION__)); + } + +nvlink_core_powerdown_floorswept_conns_to_off_end: + if (lockLinks != NULL) + { + nvlink_free((void *)lockLinks); + } + + return status; +} + diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c index 201860a1d..7f2e32814 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" @@ -116,6 +115,24 @@ nvlink_lib_check_training_complete nvlink_lib_top_lock_release(); + // Only run the check if ALI is enabled + if(links[0]->dev->enableALI) + { + // + // This will be the returned back to the caller, the core function + // will return early with an error status if a link is not Active + // + status = nvlink_core_train_check_link_ready_ALI(lockLinks, lockLinkCount); + } + else + { + // If ALI is not enabled, return error + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: ALI is not enabled! Cannot check training status, please use non-ALI or ALT training to get links to active\n", + __FUNCTION__)); + status = NVL_ERR_GENERIC; + } + // Release the per-link locks nvlink_lib_link_locks_release(lockLinks, lockLinkCount); nvlink_lib_check_training_complete_end: @@ -297,7 +314,18 @@ nvlink_lib_train_links_from_swcfg_to_active if (connCount > 0) { - if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) || + if ((conn->end0->version >= NVLINK_DEVICE_VERSION_40) || + (conn->end1->version >= NVLINK_DEVICE_VERSION_40)) + { + if (!conn->end0->dev->enableALI) + { + status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(conns, + connCount, + flags); + } + } + // For NVLink3+, use ALT sequence + else if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) || (conn->end1->version >= NVLINK_DEVICE_VERSION_30)) { status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(conns, @@ -685,9 +713,23 @@ nvlink_lib_retrain_link_from_swcfg_to_active return status; } - if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) || + + if ((conn->end0->version >= NVLINK_DEVICE_VERSION_40) || + (conn->end1->version >= NVLINK_DEVICE_VERSION_40)) + { + if (!conn->end0->bInitnegotiateConfigGood || + !conn->end1->bInitnegotiateConfigGood) + { + status = NVL_ERR_GENERIC; + } + else if (!conn->end0->dev->enableALI) + { + // ALI training for NVLink4.0+ + status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(conns, 0x1, flags); + } + } + else if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) || (conn->end1->version >= NVLINK_DEVICE_VERSION_30)) - { if (!conn->end0->bInitnegotiateConfigGood || !conn->end1->bInitnegotiateConfigGood) diff --git a/src/common/nvlink/kernel/nvlink/nvlink_ctx.h b/src/common/nvlink/kernel/nvlink/nvlink_ctx.h index 39554daac..0c3ab607f 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_ctx.h +++ b/src/common/nvlink/kernel/nvlink/nvlink_ctx.h @@ -1,25 +1,25 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2014-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2014-2017 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ + #ifndef _NVLINK_CTX_H_ #define _NVLINK_CTX_H_ diff --git a/src/common/nvlink/kernel/nvlink/nvlink_helper.h b/src/common/nvlink/kernel/nvlink/nvlink_helper.h index 40f6b810d..3d0a14aab 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_helper.h +++ b/src/common/nvlink/kernel/nvlink/nvlink_helper.h @@ -1,30 +1,28 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2017-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #ifndef _NVLINK_HELPER_H_ #define _NVLINK_HELPER_H_ - // // fabric node id will be used as MSB 16 bits of the link token value to // generate a unique token for discovering connections @@ -67,6 +65,11 @@ void nvlink_core_copy_device_info(nvlink_device *tmpDev, nvlink_detailed_dev_inf /****************************** NVLink initialization functions *********************************/ /************************************************************************************************/ +/** + * Kick-off INITPHASE5 on the given array of links + */ +NvlStatus nvlink_core_initphase5(nvlink_link **links, NvU32 numLinks, NvU32 flags); + /** * Kick-off INITPHASE1 on the given array of links */ @@ -124,12 +127,18 @@ void nvlink_core_init_links_from_off_to_swcfg(nvlink_link **pLinks, NvU32 numLinks, NvU32 flags); +/* + * Initialize all the endpoints from OFF to SWCFG state for Non-ALI sequence + * Used for nvlink 4.0+ + */ +void nvlink_core_init_links_from_off_to_swcfg_non_ALI(nvlink_link **pLinks, + NvU32 numLinks, + NvU32 flags); /** * Send INITNEGOTIATE command on the given array of links */ NvlStatus nvlink_core_initnegotiate(nvlink_link **links, NvU32 numLinks, NvU32 flags); - /************************************************************************************************/ /*************************** NVLink topology discovery functions ********************************/ /************************************************************************************************/ @@ -195,6 +204,7 @@ NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(nvlink_intr NvU32 flags); + /** * Train a single intranode connection associated with a list of links to HS using legacy * pre-Ampere sequence @@ -203,6 +213,21 @@ NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy(nvlink_i NvU32 connCount, NvU32 flags); +/** + * Train intranode connections associated with a list of links to HS using non-ALI sequence + * for nvlink 4.0+ + */ +NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(nvlink_intranode_conn **conns, + NvU32 connCount, + NvU32 flags); + +/** + * Check to make sure that links are in active and ready for ALI training for nvlink 4.0+ + */ +NvlStatus nvlink_core_train_check_link_ready_ALI(nvlink_link **links, + NvU32 linkCount); + + /************************************************************************************************/ /********************************** NVLink shutdown functions ***********************************/ /************************************************************************************************/ @@ -239,6 +264,15 @@ NvlStatus nvlink_core_reset_intranode_conns(nvlink_intranode_conn **conns, NvU32 connCount, NvU32 flags); +/** + * Check to make sure that links are in active and ready for ALI training for nvlink 4.0+ + */ +NvlStatus nvlink_core_powerdown_floorswept_conns_to_off(nvlink_link **links, + NvU32 numLinks, + NvU32 numIoctrls, + NvU32 numLinksPerIoctrl, + NvU32 numActiveLinksPerIoctrl); + /************************************************************************************************/ /**************************** NVLink connection management functions ****************************/ diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c index 988fe6f32..d3517f945 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c @@ -1,25 +1,24 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2019-2020 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lock.c b/src/common/nvlink/kernel/nvlink/nvlink_lock.c index c16a8df9a..f23b85d66 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lock.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lock.c @@ -1,25 +1,21 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020 NVidia Corporation + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ #include "nvlink.h" #include "nvtypes.h" diff --git a/src/common/nvswitch/common/inc/soe/soebif.h b/src/common/nvswitch/common/inc/soe/soebif.h index 5c79c99de..5c802675a 100644 --- a/src/common/nvswitch/common/inc/soe/soebif.h +++ b/src/common/nvswitch/common/inc/soe/soebif.h @@ -57,16 +57,6 @@ enum * Get UPHY EOM(Eye Opening Measurement) status. */ RM_SOE_BIF_CMD_GET_EOM_STATUS, - - /*! - * Signal Lane Margining - */ - RM_SOE_BIF_CMD_SIGNAL_LANE_MARGINING, - - /*! - * Handle Margining interrupt - */ - RM_SOE_BIF_CMD_SERVICE_MARGINING_INTERRUPTS, }; /*! @@ -99,12 +89,6 @@ typedef struct NvU32 laneSelectMask; } RM_SOE_BIF_CMD_UPHY_DLN_CFG_SPACE; -typedef struct -{ - NvU8 cmdType; - NvU8 laneNum; -} RM_SOE_BIF_CMD_LANE_MARGINING; - #define RM_SOE_BIF_LINK_SPEED_INVALID (0x00) #define RM_SOE_BIF_LINK_SPEED_GEN1PCIE (0x01) #define RM_SOE_BIF_LINK_SPEED_GEN2PCIE (0x02) @@ -141,7 +125,7 @@ typedef union RM_SOE_BIF_CMD_UPHY_DLN_CFG_SPACE cfgctl; RM_SOE_BIF_CMD_PCIE_LINK_SPEED speedctl; RM_SOE_BIF_CMD_EOM_STATUS eomStatus; - RM_SOE_BIF_CMD_LANE_MARGINING laneMargining; } RM_SOE_BIF_CMD; #endif // _SOEBIF_H_ + diff --git a/src/common/nvswitch/common/inc/soe/soeifsoe.h b/src/common/nvswitch/common/inc/soe/soeifsoe.h index ef9e660e1..d441c5769 100644 --- a/src/common/nvswitch/common/inc/soe/soeifsoe.h +++ b/src/common/nvswitch/common/inc/soe/soeifsoe.h @@ -42,6 +42,22 @@ enum RM_SOE_INIT_MSG_ID_SOE_INIT = 0, }; +/* + * CMDQ and MSGQ lengths used in INIT-MSG on LS10 + * + * These values are hard-coded in soe-riscv. + * They need to be same in SOE and driver and + * are protected by compile time checks in SOE. + * + */ +#define SOE_CMD_QUEUE_LENGTH (0x80ul) +#define SOE_MSG_QUEUE_LENGTH (0x80ul) + +/*! + * Define SOE CMDQ and MSGQ EMEM offsets + */ +#define SOE_EMEM_CHANNEL_CMDQ_OFFSET 0x1000080 +#define SOE_EMEM_CHANNEL_MSGQ_OFFSET 0x1000000 /*! * Defines the logical queue IDs that must be used when submitting commands diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index a962bb485..12ffd208f 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -85,10 +85,11 @@ typedef enum nvswitch_get_info_index NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_63_32, NVSWITCH_GET_INFO_INDEX_NUM_VCS, NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE, - NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE, - NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE, NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE, NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE, + NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE, + NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE, + NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE, NVSWITCH_GET_INFO_INDEX_FREQ_KHZ = 0x200, NVSWITCH_GET_INFO_INDEX_VCOFREQ_KHZ, @@ -105,6 +106,9 @@ typedef enum nvswitch_get_info_index #define NVSWITCH_GET_INFO_INDEX_ARCH_LR10 0x02 #define NVSWITCH_GET_INFO_INDEX_IMPL_LR10 0x01 +#define NVSWITCH_GET_INFO_INDEX_ARCH_LS10 0x03 +#define NVSWITCH_GET_INFO_INDEX_IMPL_LS10 0x01 + #define NVSWITCH_GET_INFO_INDEX_PLATFORM_UNKNOWN 0x00 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_RTLSIM 0x01 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_FMODEL 0x02 @@ -352,7 +356,8 @@ typedef enum nvswitch_table_select_remap NVSWITCH_TABLE_SELECT_REMAP_PRIMARY = 0, NVSWITCH_TABLE_SELECT_REMAP_EXTA, NVSWITCH_TABLE_SELECT_REMAP_EXTB, - NVSWITCH_TABLE_SELECT_REMAP_MULTICAST + NVSWITCH_TABLE_SELECT_REMAP_MULTICAST, + NVSWITCH_TABLE_SELECT_REMAP_MAX } NVSWITCH_TABLE_SELECT_REMAP; typedef struct nvswitch_set_remap_policy @@ -826,6 +831,29 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR = 11022, NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR = 11023, NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRTYPEERR = 11024, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR = 11025, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR = 11026, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR = 11027, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR = 11028, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR = 11029, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR = 11030, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR = 11031, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR = 11032, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR = 11033, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL = 11034, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL = 11035, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL = 11036, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR = 11037, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR = 11038, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR = 11039, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR = 11040, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR = 11041, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR = 11042, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCCMDTOUCADDRERR = 11043, + NVSWITCH_ERR_HW_NPORT_INGRESS_READMCREFLECTMEMERR = 11044, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR = 11045, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR = 11046, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR = 11047, NVSWITCH_ERR_HW_NPORT_INGRESS_LAST, /* NOTE: Must be last */ /* NPORT: Egress errors */ @@ -863,9 +891,24 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR = 12031, NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR = 12032, NVSWITCH_ERR_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR = 12033, - NVSWITCH_ERR_HW_NPORT_EGRESS_TIMESTAMP_LOG = 12034, - NVSWITCH_ERR_HW_NPORT_EGRESS_MISC_LOG = 12035, - NVSWITCH_ERR_HW_NPORT_EGRESS_HEADER_LOG = 12036, + NVSWITCH_ERR_HW_NPORT_EGRESS_INVALIDVCSET_ERR = 12034, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR = 12035, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR = 12036, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR = 12037, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR = 12038, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR = 12039, + NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR = 12040, + NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR = 12041, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR = 12042, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR = 12043, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR = 12044, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR = 12045, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR = 12046, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR = 12047, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR = 12048, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR = 12049, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_CNT_ERR = 12050, + NVSWITCH_ERR_HW_NPORT_EGRESS_RBRSP_CNT_ERR = 12051, NVSWITCH_ERR_HW_NPORT_EGRESS_LAST, /* NOTE: Must be last */ /* NPORT: Fstate errors */ @@ -917,7 +960,7 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR = 15011, NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR = 15012, NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR = 15013, - NVSWITCH_ERR_HW_NPORT_ROUTE_LAST, /* NOTE: Must be last */ + NVSWITCH_ERR_HW_NPORT_ROUTE_LAST = 15021, /* NOTE: Must be last */ /* NPORT: Nport errors */ NVSWITCH_ERR_HW_NPORT = 16000, @@ -1153,6 +1196,9 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR = 24005, NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR = 24006, NVSWITCH_ERR_HW_NPORT_SOURCETRACK_SOURCETRACK_TIME_OUT_ERR = 24007, + NVSWITCH_ERR_HW_NPORT_SOURCETRACK_DUP_CREQ_TCEN0_TAG_ERR = 24008, + NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN0_RSP_ERR = 24009, + NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN1_RSP_ERR = 24010, NVSWITCH_ERR_HW_NPORT_SOURCETRACK_LAST, /* NOTE: Must be last */ /* NVLIPT_LNK errors */ @@ -1300,6 +1346,8 @@ typedef struct nvswitch_set_latency_bins * Set true, if the port is AC coupled. * enableVC1 [IN] * Set true, if VC1 should be enabled for the port. + * trunkSrcMask [IN] + * Mask of source trunk ports. */ typedef enum nvswitch_connection_type @@ -1328,6 +1376,7 @@ typedef struct nvswitch_set_switch_port_config NvU32 count; NvBool acCoupled; NvBool enableVC1; + NvU64 trunkSrcMask; } NVSWITCH_SET_SWITCH_PORT_CONFIG; @@ -1652,6 +1701,7 @@ typedef struct #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004) #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005) #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006) +#define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007) #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000) #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001) @@ -1659,6 +1709,7 @@ typedef struct #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004) #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005) #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006) +#define NVSWITCH_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007) /* @@ -1769,6 +1820,9 @@ typedef struct // LR10+ only NvU32 laneRxdetStatusMask; + // LS10+ only + NvBool bIsRepeaterMode; + NVSWITCH_NVLINK_DEVICE_INFO remoteDeviceInfo; NVSWITCH_NVLINK_DEVICE_INFO localDeviceInfo; } NVSWITCH_NVLINK_LINK_STATUS_INFO; @@ -1926,6 +1980,24 @@ typedef struct #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE_OFFSET 0x03 #define NVSWITCH_NUM_CHANNELS_LR10 4 +/* + * Laguna Seca thermal channels + */ +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_MAX 0x00 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_OFFSET_MAX 0x01 +#define NVSWITCH_THERM_CHANNEL_LS10_TDIODE 0x02 +#define NVSWITCH_THERM_CHANNEL_LS10_TDIODE_OFFSET 0x03 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_0 0x04 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_1 0x05 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_2 0x06 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_3 0x07 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_4 0x08 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_5 0x09 +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_6 0x0A +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_7 0x0B +#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_8 0x0C +#define NVSWITCH_NUM_CHANNELS_LS10 13 + /* * CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS * @@ -2094,7 +2166,8 @@ typedef struct nvswitch_set_training_error_info #define NVSWITCH_DEVICE_EVENT_NONFATAL 1 #define NVSWITCH_DEVICE_EVENT_PORT_UP 2 #define NVSWITCH_DEVICE_EVENT_PORT_DOWN 3 -#define NVSWITCH_DEVICE_EVENT_COUNT 4 +#define NVSWITCH_DEVICE_EVENT_INBAND_DATA 4 +#define NVSWITCH_DEVICE_EVENT_COUNT 5 #define NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS (500) /* @@ -2784,6 +2857,140 @@ typedef struct nvswitch_get_rd_stall_busy NVSWITCH_STALL_BUSY vc1; } NVSWITCH_GET_RB_STALL_BUSY; +/* + * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR + * + * Control for querying multicast ID error vector + * + * Parameters: + * [in] link + * Link number on which the error vector is requested + * + * [out] error_vector[] + * Bit vector of multicast IDs that are in error. + */ + +#define NVSWITCH_MC_ID_ERROR_VECTOR_COUNT 128 + +typedef struct nvswitch_get_multicast_id_error_vector +{ + NvU32 link; + NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)]; +} NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR; + +/* + * CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR + * + * Control for clearing multicast ID error vector + * + * Parameters: + * [in] link + * Link number on which the error vector clear is requested + * + * [in] error_vector[] + * Bit vector of multicast IDs to clear error. + */ + +typedef struct nvswitch_clear_multicast_id_error_vector +{ + NvU32 link; + NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)]; +} NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR; + +#define NVSWITCH_INBAND_DATA_SIZE 4096 + +/* + * CTRL_NVSWITCH_INBAND_SEND_DATA + * + * Control call used for sending data over inband. + * + * Parameters: + * + * dataSize[IN] + * Valid data in the buffer + * + * linkId[IN] + * Link number on which the data needs to be sent + * + * buffer[IN] + * Data which needs to be sent on the other side + * + * dataSent [OUT] + * Bytes of data which were sent to the other side + */ +typedef struct nvswitch_inband_send_data_params +{ + /* input parameters */ + NvU32 dataSize; + NvU32 linkId; + NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; + + /* output parameters */ + NvU32 dataSent; +} NVSWITCH_INBAND_SEND_DATA_PARAMS; + +/* + * CTRL_NVSWITCH_INBAND_READ_DATA + * + * Control call used for reading data received over inband + * + * Parameters: + * + * linkId[IN] + * Link number on which the data needs to be read. + * + * dataSize[OUT] + * Valid data in the buffer + * + * buffer[OUT] + * Data which needs to be read from the other side + */ +typedef struct nvswitch_inband_read_data_params +{ + /* input parameters */ + NvU32 linkId; + + /* output parameters */ + NvU32 dataSize; + NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; +} NVSWITCH_INBAND_READ_DATA_PARAMS; + +/* + * CTRL_NVSWITCH_INBAND_FLUSH_DATA + * + * Flushing all the pending data for the corresponding link. + * Messages would be stored in a queue. If flush is send all the + * pending messages which are there for that linkId will be deleted. + * + * Parameters: + * + * linkMask[IN] + * Mask of Links on which the data needs to be flushed. + */ +typedef struct nvswitch_inband_flush_data_params +{ + /* input parameters */ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + + /* output parameters */ +} NVSWITCH_INBAND_FLUSH_DATA_PARAMS; + +/* + * CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS + * + * Control call to check which links have pending data + * + * Parameters: + * + * linkMask[OUT] + * Mask of the links which has data on it. + */ +typedef struct nvswitch_inband_pending_data_stats_params +{ + /* output parameters */ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); +} NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS; + #define NVSWITCH_GET_SW_INFO_COUNT_MAX 32 typedef enum nvswitch_get_sw_info_index @@ -3106,6 +3313,12 @@ typedef struct #define CTRL_NVSWITCH_RESERVED_3 0x3A #define CTRL_NVSWITCH_RESERVED_4 0x3B #define CTRL_NVSWITCH_RESERVED_5 0x3C +#define CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 0x3D +#define CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 0x3E +#define CTRL_NVSWITCH_INBAND_SEND_DATA 0x43 +#define CTRL_NVSWITCH_INBAND_READ_DATA 0x44 +#define CTRL_NVSWITCH_INBAND_FLUSH_DATA 0x45 +#define CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS 0x46 #define CTRL_NVSWITCH_GET_SW_INFO 0x47 #define CTRL_NVSWITCH_RESERVED_6 0x48 #define CTRL_NVSWITCH_RESERVED_7 0x49 diff --git a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c index 73aeee313..3b41b0544 100644 --- a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1405,29 +1405,14 @@ _flcnQueueCmdPostNonBlocking_IMPL } // Falcon must be in a ready state before commands may be submitted. - if (!pFlcn->bOSReady) + status = soeWaitForInitAck_HAL(device, (PSOE)pFlcn->pFlcnable); + if (status != NV_OK) { - if (pFlcn->engineTag != ENG_TAG_SOE) { - NVSWITCH_PRINT(device, ERROR, - "%s: FLCN not ready for command processing\n", - __FUNCTION__); - return NV_ERR_INVALID_STATE; - } - else - { - SOE *pSoe = (PSOE)pFlcn->pFlcnable; - - status = soeWaitForInitAck(device, pSoe); - - if (status != NV_OK || !pFlcn->bOSReady) - { - NVSWITCH_PRINT(device, ERROR, - "%s: SOE not ready for command processing\n", - __FUNCTION__); - NVSWITCH_ASSERT(0); - return status; - } - } + NVSWITCH_PRINT(device, ERROR, + "%s: SOE not ready for command processing\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return status; } // Sanity check the command input. diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index c5d53322c..a4271eba1 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -389,6 +389,9 @@ struct nvswitch_device // List of client events NVListRec client_events_list; + + // To be removed once newer vbios is on TOT. + NvBool bIsNvlinkVbiosTableVersion2; }; #define NVSWITCH_IS_DEVICE_VALID(device) \ @@ -485,6 +488,7 @@ typedef struct NVSWITCH_TIMEOUT #define NVSWITCH_INTERVAL_1MSEC_IN_NS 1000000LL #define NVSWITCH_INTERVAL_5MSEC_IN_NS 5000000LL #define NVSWITCH_INTERVAL_1SEC_IN_NS 1000000000LL +#define NVSWITCH_INTERVAL_4SEC_IN_NS 4000000000LL #define NVSWITCH_HEARTBEAT_INTERVAL_NS NVSWITCH_INTERVAL_1SEC_IN_NS @@ -505,6 +509,7 @@ do \ #define NVSWITCH_SET_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) |= (0?cap##field)) NvBool nvswitch_is_lr10_device_id(NvU32 device_id); +NvBool nvswitch_is_ls10_device_id(NvU32 device_id); NvU32 nvswitch_reg_read_32(nvswitch_device *device, NvU32 offset); void nvswitch_reg_write_32(nvswitch_device *device, NvU32 offset, NvU32 data); @@ -529,6 +534,10 @@ void nvswitch_setup_link_loopback_mode(nvswitch_device *device, NvU32 linkN void nvswitch_reset_persistent_link_hw_state(nvswitch_device *device, NvU32 linkNumber); void nvswitch_store_topology_information(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_launch_ALI(nvswitch_device *device); +NvlStatus nvswitch_launch_ALI_link_training(nvswitch_device *device, nvlink_link *link, NvBool bSync); +NvlStatus nvswitch_inband_read_data(nvswitch_device *device, NvU8 *dest, NvU32 linkId, NvU32 *dataSize); +void nvswitch_filter_messages(nvswitch_device *device, NvU32 linkId); NvlStatus nvswitch_set_training_mode(nvswitch_device *device); NvBool nvswitch_is_link_in_reset(nvswitch_device *device, nvlink_link *link); void nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *link); diff --git a/src/common/nvswitch/kernel/inc/error_nvswitch.h b/src/common/nvswitch/kernel/inc/error_nvswitch.h index fec751bcc..1cefd94e9 100644 --- a/src/common/nvswitch/kernel/inc/error_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/error_nvswitch.h @@ -61,9 +61,27 @@ typedef struct NvU32 data[4]; // record of interrupt specific data } NVSWITCH_INTERRUPT_LOG_TYPE; +#define NVSWITCH_RAW_ERROR_LOG_DATA_SIZE 16 + +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME BIT(0) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC BIT(1) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR BIT(2) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME BIT(3) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC BIT(4) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR BIT(5) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME BIT(6) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC BIT(7) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR BIT(8) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME BIT(9) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC BIT(10) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR BIT(11) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME BIT(12) +#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME BIT(13) + typedef struct { - NvU32 data[16]; + NvU32 flags; + NvU32 data[NVSWITCH_RAW_ERROR_LOG_DATA_SIZE]; } NVSWITCH_RAW_ERROR_LOG_TYPE; #define NVSWITCH_ERROR_NEXT_LOCAL_NUMBER(log) (log->error_total) diff --git a/src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h b/src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h index b1a81de8b..c23c55402 100644 --- a/src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h @@ -97,6 +97,7 @@ void flcnQueueSetupHal(struct FLCN *pFlcn); void flcnRtosSetupHal(struct FLCN *pFlcn); void flcnQueueRdSetupHal(struct FLCN *pFlcn); +void flcnSetupHal_LS10(struct FLCN *pFlcn); void flcnSetupHal_LR10(struct FLCN *pFlcn); void flcnSetupHal_v03_00(struct FLCN *pFlcn); diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index d7cf072aa..d42ab5e22 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -79,6 +79,8 @@ _op(NvlStatus, nvswitch_ctrl_get_ingress_response_table, (nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_ingress_response_table, (nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_ganged_link_table, (nvswitch_device *device, NVSWITCH_SET_GANGED_LINK_TABLE *p), _arch) \ + _op(void, nvswitch_init_npg_multicast, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_init_warm_reset, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_remap_policy, (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_remap_policy, (nvswitch_device *device, NVSWITCH_GET_REMAP_POLICY_PARAMS *params), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_remap_policy_valid, (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY_VALID *p), _arch) \ @@ -114,15 +116,15 @@ _op(NvlStatus, nvswitch_ctrl_get_fom_values, (nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \ - _op(NvlStatus, nvswitch_soe_set_ucode_core, (nvswitch_device *device, NvBool bFalcon), _arch) \ _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ - _op(NvlStatus, nvswitch_soe_prepare_for_reset, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \ _op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_setup_link_system_registers, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_read_vbios_link_entries, (nvswitch_device *device, NvU32 tblPtr,NvU32 expected_link_entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_link_entriesCount), _arch) \ + _op(NvlStatus, nvswitch_vbios_read_structure, (nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format), _arch) \ _op(NvlStatus, nvswitch_get_nvlink_ecc_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_inforom_ecc_log_error_event, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *error_event), _arch) \ _op(void, nvswitch_oms_set_device_disable, (INFOROM_OMS_STATE *pOmsState, NvBool bForceDeviceDisable), _arch) \ @@ -184,7 +186,6 @@ _op(NvlStatus, nvswitch_init_nxbar, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_clear_nport_rams, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_pri_ring_init, (nvswitch_device *device), _arch) \ - _op(NvlStatus, nvswitch_get_soe_ucode_binaries, (nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header), _arch) \ _op(NvlStatus, nvswitch_get_remap_table_selector, (nvswitch_device *device, NVSWITCH_TABLE_SELECT_REMAP table_selector, NvU32 *remap_ram_sel), _arch) \ _op(NvU32, nvswitch_get_ingress_ram_size, (nvswitch_device *device, NvU32 ingress_ram_selector), _arch) \ _op(NvlStatus, nvswitch_minion_get_dl_status, (nvswitch_device *device, NvU32 linkId, NvU32 statusIdx, NvU32 statusArgs, NvU32 *statusData), _arch) \ @@ -202,14 +203,22 @@ _op(NvBool, nvswitch_is_link_in_reset, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(void, nvswitch_init_buffer_ready, (nvswitch_device *device, nvlink_link * link, NvBool bNportBufferReady), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_nvlink_lp_counters, (nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *p), _arch) \ - _op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \ - _op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \ _op(void, nvswitch_apply_recal_settings, (nvswitch_device *device, nvlink_link *), _arch) \ _op(NvlStatus, nvswitch_service_nvldl_fatal_link, (nvswitch_device *device, NvU32 nvliptInstance, NvU32 link), _arch) \ - _op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \ _op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) +#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ + _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link, NvBool bSync), _arch) \ + _op(NvlStatus, nvswitch_ctrl_inband_send_data, (nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_inband_read_data, (nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_clear_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p), _arch) \ + // // Declare HAL function pointer table // @@ -226,6 +235,7 @@ typedef struct nvswitch_hal_functions { NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_FUNCTIONS, HAL) + NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_FUNCTIONS, HAL) } nvswitch_hal; @@ -243,6 +253,9 @@ typedef struct nvswitch_hal_functions #define NVSWITCH_INIT_HAL(device, arch) \ NVSWITCH_HAL_FUNCTION_LIST(CREATE_HAL_FUNCTIONS, arch) \ +#define NVSWITCH_INIT_HAL_LS10(device, arch) \ + NVSWITCH_HAL_FUNCTION_LIST_LS10(CREATE_HAL_FUNCTIONS, arch) \ + // // Declare HAL function dispatch functions // @@ -255,8 +268,10 @@ typedef struct nvswitch_hal_functions _return _function _params; NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_DISPATCHERS, unused_argument) +NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_DISPATCHERS, unused_argument) // HAL functions void nvswitch_setup_hal_lr10(nvswitch_device *device); +void nvswitch_setup_hal_ls10(nvswitch_device *device); #endif //_HALDEF_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/io_nvswitch.h b/src/common/nvswitch/kernel/inc/io_nvswitch.h index 7cfc04f9a..b3fc071b1 100644 --- a/src/common/nvswitch/kernel/inc/io_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/io_nvswitch.h @@ -24,6 +24,9 @@ #ifndef _IO_NVSWITCH_H_ #define _IO_NVSWITCH_H_ +#include "nv_list.h" +#include "ctrl_dev_nvswitch.h" + // NVSWITCH_REG_* MMIO wrappers are to be used for absolute symbolic BAR0 offset // register references like SMC, CLOCK, BUS, and PRIV_MASTER. // @@ -92,11 +95,7 @@ typedef struct engine_descriptor // NVSWITCH_REG_RD/WR IO wrappers. // -#define NVSWITCH_LIST_ALL_ENGINES(_op) \ - _op(XVE) \ - _op(SAW) \ - _op(SOE) \ - _op(SMR) \ +#define NVSWITCH_LIST_LS10_ONLY_ENGINES(_op) \ _op(GIN) \ _op(XAL) \ _op(XAL_FUNC) \ @@ -124,6 +123,15 @@ typedef struct engine_descriptor _op(SYSB_PRI_RS_CTRL) \ _op(PRI_MASTER_RS) \ _op(PTIMER) \ + _op(CPR) \ + _op(TILEOUT) \ + _op(TILEOUT_PERFMON) \ + +#define NVSWITCH_LIST_ALL_ENGINES(_op) \ + _op(XVE) \ + _op(SAW) \ + _op(SOE) \ + _op(SMR) \ \ _op(NPG) \ _op(NPORT) \ @@ -134,11 +142,9 @@ typedef struct engine_descriptor _op(NVLIPT_LNK) \ _op(NVLTLC) \ _op(NVLDL) \ - _op(CPR) \ \ _op(NXBAR) \ _op(TILE) \ - _op(TILEOUT) \ \ _op(NPG_PERFMON) \ _op(NPORT_PERFMON) \ @@ -149,7 +155,6 @@ typedef struct engine_descriptor \ _op(NXBAR_PERFMON) \ _op(TILE_PERFMON) \ - _op(TILEOUT_PERFMON) \ #define ENGINE_ID_LIST(_eng) \ NVSWITCH_ENGINE_ID_##_eng, @@ -164,6 +169,7 @@ typedef struct engine_descriptor typedef enum nvswitch_engine_id { NVSWITCH_LIST_ALL_ENGINES(ENGINE_ID_LIST) + NVSWITCH_LIST_LS10_ONLY_ENGINES(ENGINE_ID_LIST) NVSWITCH_ENGINE_ID_SIZE, } NVSWITCH_ENGINE_ID; @@ -312,30 +318,30 @@ typedef enum nvswitch_engine_id #define NVSWITCH_MAX_SEED_BUFFER_SIZE NVSWITCH_MAX_SEED_NUM + 1 -#define NVSWITCH_MAX_INBAND_BUFFER_SIZE 256*8 -#define NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE 32 -#define NVSWITCH_MAX_INBAND_BUFFER_ENTRIES NVSWITCH_MAX_INBAND_BUFFER_SIZE/NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE - // -// Inband data structure +// Storing list entries for sending to FM // -struct nvswitch_inband_data +typedef struct { - // Inband bufer at sender Minion - NvU32 sendBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES]; - - // Inband buffer at receiver Minion - NvU32 receiveBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES]; + NVListRec entry; + NvU8 data[NVSWITCH_INBAND_DATA_SIZE]; + NvU32 dataSize; +} nvswitch_inband_data_list; - // Is the current Minion a sender or receiver of Inband Data? - NvBool bIsSenderMinion; +typedef struct +{ + // Temp entry being received + nvswitch_inband_data_list *message; - // Bool to say fail or not - NvBool bTransferFail; + // + // Persistent messages are stored even if the listener (e.g. FM) is + // not present. + // + NVListRec persistent_list; - // # of transmisions done - count - // NvU32 txCount; -}; + // Stores messages if and only if the listener is present. + NVListRec nonpersistent_list; +} nvswitch_inband_receive_data; typedef struct { @@ -347,14 +353,21 @@ typedef struct NvBool egress_packet_latched; NvBool nea; // Near end analog - NvBool ned; // Near end digital + NvBool nedr; // Near end digital + NvBool nedw; NvU32 lane_rxdet_status_mask; NvBool bIsRepeaterMode; + // Check if BUFFER_COMPLETE is seen + volatile NvBool isBufferComplete; + + // Check if BUFFER_FAIL is seen + volatile NvBool isBufferFail; + // Minion Inband Data structure - struct nvswitch_inband_data inBandData; + nvswitch_inband_receive_data inbandData; } NVSWITCH_LINK_TYPE; diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index e0421f308..36f73296f 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -352,7 +352,7 @@ typedef NVSWITCH_LINK_TYPE NVSWITCH_LINK_TYPE_LR10; // // -// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. +// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. // But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used as PowerPC ATS support is not a POR for LR10 HW. // #define NVSWITCH_NUM_VCS_LR10 8 @@ -436,7 +436,7 @@ typedef struct // In order to collect all the useful unit information into a single container, // we need to pick where to find each piece within the parsed discovery table. // Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes, -// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP +// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP // wrapper to broadcast to all the sub-units in all the IP wrappers. // So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point // to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside @@ -627,11 +627,11 @@ NvlStatus nvswitch_get_link_public_id_lr10(nvswitch_device *device, NvU32 linkId NvlStatus nvswitch_get_link_local_idx_lr10(nvswitch_device *device, NvU32 linkId, NvU32 *localLinkIdx); NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams); +NvlStatus nvswitch_read_vbios_link_entries_lr10(nvswitch_device *device, NvU32 tblPtr,NvU32 entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_entriesCount); NvlStatus nvswitch_ctrl_get_fatal_error_scope_lr10(nvswitch_device *device, NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS *pParams); void nvswitch_init_scratch_lr10(nvswitch_device *device); void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link); NvlStatus nvswitch_init_nport_lr10(nvswitch_device *device); -NvlStatus nvswitch_get_soe_ucode_binaries_lr10(nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header); NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link); void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber); void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber); @@ -646,8 +646,13 @@ void nvswitch_corelib_get_uphy_load_lr10(nvlink_link *link, NvBool *bUnlocked); void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params); NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); +NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); +NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); +NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync); NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance); void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); +NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device); + #endif //_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/minion_lr10.h b/src/common/nvswitch/kernel/inc/lr10/minion_lr10.h index 11fd79b41..5052603e7 100644 --- a/src/common/nvswitch/kernel/inc/lr10/minion_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/minion_lr10.h @@ -92,4 +92,5 @@ NvU32 nvswitch_minion_get_data_rate_KiBps_lr10(nvswitch_device *device, NvU3 NvlStatus nvswitch_set_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion, NvBool initialized); NvBool nvswitch_is_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion); NvlStatus nvswitch_minion_clear_dl_error_counters_lr10(nvswitch_device *device, NvU32 linkId); + #endif //_MINION_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h b/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h index a10370692..4e9ccab4a 100644 --- a/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h @@ -58,10 +58,8 @@ typedef const struct // Internal function declarations // NvlStatus nvswitch_init_soe_lr10(nvswitch_device *device); -NvlStatus nvswitch_soe_prepare_for_reset_lr10(nvswitch_device *device); void nvswitch_soe_unregister_events_lr10(nvswitch_device *device); void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg, void *pParams, NvU32 seqDesc, NV_STATUS status); -NvlStatus nvswitch_soe_set_ucode_core_lr10(nvswitch_device *device, NvBool bFalcon); NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device); #endif //_SOE_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h index a98ab85cb..10a1067c2 100644 --- a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h @@ -229,15 +229,6 @@ #define NV_SWITCH_REGKEY_SOE_DISABLE_NO 0x0 #define NV_SWITCH_REGKEY_SOE_DISABLE_YES 0x1 -/* - * NV_SWITCH_REGKEY_SOE_BOOT_CORE - Selects SOE core - * - * Public: Available in release drivers - */ -#define NV_SWITCH_REGKEY_SOE_BOOT_CORE "SoeBootCore" -#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_FALCON 0x0 -#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_DEFAULT 0x2 - /* * NV_SWITCH_REGKEY_ENABLE_PM * @@ -409,11 +400,18 @@ * * When the regkey is set to FALCON, the Nvswitch driver will run MINION on Falcon core. * + * If set to RISCV, the MINION will run on RISCV core in Non-Manifest Mode. + * If set to RISCV_MANIFEST, the MINION will run on RISCV core in Manifest Mode. + * + * In the default option, RISCV_BCR_CTRL register will be used to get the default core. + * * Private: Debug use only */ #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET "MinionSetUcodeTarget" #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_DEFAULT 0x0 #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_FALCON 0x1 +#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV 0x2 +#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV_MANIFEST 0x3 /* * NV_SWITCH_REGKEY_MINION_SET_SIMMODE - Selects simmode settings to send to MINION @@ -500,13 +498,14 @@ /* * NV_SWITCH_REGKEY_LINK_TRAINING_SELECT - Select the Link training to be done * - * This regkey will + * For LS10, links can be trained via non-ALI or ALI training. This regkey will * allow for overriding System Defaults and can force either training method * when desired. */ - #define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT "LinkTrainingMode" #define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_DEFAULT 0x0 +#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_NON_ALI 0x1 +#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI 0x2 /* * NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL - Enable access to all I2C Ports/Devices * diff --git a/src/common/nvswitch/kernel/inc/rom_nvswitch.h b/src/common/nvswitch/kernel/inc/rom_nvswitch.h index 4f5e3288d..9b8a5aaba 100644 --- a/src/common/nvswitch/kernel/inc/rom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/rom_nvswitch.h @@ -547,6 +547,9 @@ nvswitch_read_rom_tables #define NVLINK_CONFIG_DATA_HEADER_20_SIZE 8 #define NVLINK_CONFIG_DATA_HEADER_20_FMT "6b1w" +#define NVLINK_CONFIG_DATA_HEADER_VER_30 0x3 +#define NVLINK_CONFIG_DATA_HEADER_30_SIZE 8 + typedef struct _PCI_DATA_STRUCT { bios_U032 sig; // 00h: Signature, the string "PCIR" or NVIDIA's alternate "NPDS" @@ -747,7 +750,9 @@ typedef struct _nvlink_Config_Data_Header_20 #define NV_NVLINK_VBIOS_PARAM6_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT 7:4 #define NVLINK_CONFIG_DATA_BASEENTRY_FMT "1b" -#define NVLINK_CONFIG_DATA_LINKENTRY_FMT "7b" +#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_20 "7b" +#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_30 "10b" + // Version 2.0 Link Entry and Base Entry typedef struct _nvlink_config_data_baseentry_20 { @@ -764,9 +769,11 @@ typedef struct _nvlink_config_data_linkentry_20 NvU8 nvLinkparam4; NvU8 nvLinkparam5; NvU8 nvLinkparam6; + NvU8 nvLinkparam7; + NvU8 nvLinkparam8; + NvU8 nvLinkparam9; } NVLINK_CONFIG_DATA_LINKENTRY; - // Union of different VBIOS configuration table formats typedef union __nvlink_Config_Data_Header { @@ -788,7 +795,22 @@ typedef struct _nvlink_vbios_config_data_linkentry_20 bios_U008 nvLinkparam4; bios_U008 nvLinkparam5; bios_U008 nvLinkparam6; -} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY; +} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20; + +typedef struct _nvlink_vbios_config_data_linkentry_30 +{ + // VBIOS configuration Data + bios_U008 nvLinkparam0; + bios_U008 nvLinkparam1; + bios_U008 nvLinkparam2; + bios_U008 nvLinkparam3; + bios_U008 nvLinkparam4; + bios_U008 nvLinkparam5; + bios_U008 nvLinkparam6; + bios_U008 nvLinkparam7; + bios_U008 nvLinkparam8; + bios_U008 nvLinkparam9; +} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30; // // NVSwitch driver structures diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index d9bc115c1..feccf9404 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -33,9 +33,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0xb4890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x64890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002fe189, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002d8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -72,57 +72,57 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000fc0, - 0x8900f89a, 0xbf000fb4, 0x8900f89a, 0xbf000fc4, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fc889, - 0xa9a099bf, 0x000fc089, 0xa9b599bf, 0x0f00f801, 0x0fcc8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000fc8, 0xa609bf9f, 0x110bf4f9, 0x000fc089, 0x09989fbf, 0xf4f9a601, 0xc08d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fc88929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000fc48f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fd4, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001074, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0fd489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0xc489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e001078, 0x89000bee, 0xbf000fb4, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000fb482, 0xb0b229bf, 0x000fc081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x108c890b, 0x067d3e00, 0x10908900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0fc489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fcc, - 0x08453e9f, 0x0fb48900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x748064bd, 0xbc870010, 0xb884000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fd48e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f70, + 0x8900f89a, 0xbf000f64, 0x8900f89a, 0xbf000f74, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000f7889, + 0xa9a099bf, 0x000f7089, 0xa9b599bf, 0x0f00f801, 0x0f7c8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000f78, 0xa609bf9f, 0x110bf4f9, 0x000f7089, 0x09989fbf, 0xf4f9a601, 0x708d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0f788929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f748f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000f84, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001038, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0f8489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0x7489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e00103c, 0x89000bee, 0xbf000f64, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f6482, 0xb0b229bf, 0x000f7081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1050890b, 0x067d3e00, 0x10548900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f7489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000f7c, + 0x08453e9f, 0x0f648900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x388064bd, 0x6c870010, 0x6884000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000f848e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fd4, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000f84, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xd48e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0x848e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fdc, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000fd4, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fd4, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000f8c, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000f84, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000f84, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fd48f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001074, - 0x0ad07e96, 0x0485fb00, 0xc48922f9, 0x99bf000f, 0xcd009db3, 0x10a88900, 0x899fbf00, 0xbf000fc0, - 0x0099b999, 0x0bf4f9a6, 0x0fb4890f, 0x0b9abf00, 0x0a957eec, 0x0fc08e00, 0x8fe9bf00, 0x900010a8, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10908f1f, 0x108c8e00, 0xbffcbf00, 0x0fc88de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010908f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000f848f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001038, + 0x0ad07e96, 0x0485fb00, 0x748922f9, 0x99bf000f, 0xcd009db3, 0x106c8900, 0x899fbf00, 0xbf000f70, + 0x0099b999, 0x0bf4f9a6, 0x0f64890f, 0x0b9abf00, 0x0a957eec, 0x0f708e00, 0x8fe9bf00, 0x9000106c, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10548f1f, 0x10508e00, 0xbffcbf00, 0x0f788de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010548f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000fc082, 0x00109081, 0xb3100a90, 0x89bf0004, 0xbf0010ac, 0x0094b399, 0x09283e17, 0x10ac8f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000fc481, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf0010b0, 0x0099b399, 0x788f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0xb48314bd, 0x7882000f, 0xaa3e0010, 0x517e0009, + 0x000f7082, 0x00105481, 0xb3100a90, 0x89bf0004, 0xbf001070, 0x0094b399, 0x09283e17, 0x10708f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f7481, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf001074, 0x0099b399, 0x3c8f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x648314bd, 0x3c82000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10ac8fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xcc890e01, 0x99bf000f, 0x160194b3, - 0xcc89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0xc48932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000fc081, 0x000fb482, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x8c890b18, 0x423e0010, 0x9089000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10708fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0x7c890e01, 0x99bf000f, 0x160194b3, + 0x7c89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x748932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f7081, 0x000f6482, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x50890b18, 0x423e0010, 0x5489000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0xa08f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf0005a0, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf000554, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0041407e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xdc800099, 0x0fbf0010, + 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xa0800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, 0x407e000a, 0x01fb0041, 0x0041557e, 0x00185a7e, 0x0800a0b3, 0x00068a7e, 0x0041407e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, @@ -144,8 +144,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, 0x7e170003, 0x3300195a, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10e08f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, - 0x000a9b7e, 0x747e00f8, 0xe08e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0x10a48f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, + 0x000a9b7e, 0x747e00f8, 0xa48e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, @@ -156,37 +156,37 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, 0x0142fe01, 0x90271190, 0x1ab22622, 0xf77e2bb2, 0x020a0040, 0x117eab32, 0x0abf0041, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf004111, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010e4, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e4, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2fd88900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010a8, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010a8, 0xf8000e6b, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2d808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002fc0, - 0xc91bf4fd, 0x002fd889, 0x9b7e9abf, 0x11fb0000, 0x108b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf001110, 0x11148990, 0x899fbf00, 0x18001100, 0x9e35180e, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002d68, + 0xc91bf4fd, 0x002d8089, 0x9b7e9abf, 0x11fb0000, 0xd48b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf0010d4, 0x10d88990, 0x899fbf00, 0x180010c4, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111489, 0x01fb90a0, 0x89ffa4f0, - 0x8c003231, 0xbc003224, 0xacbcd0a9, 0x3fdf3fa0, 0x32318cae, 0xffe9c400, 0x20909cbc, 0x3224899f, - 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x32318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001118, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, - 0x00323189, 0x91209f3f, 0x00322489, 0x3d0009bc, 0x20092094, 0x3224892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x11188f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x0010d889, 0x01fb90a0, 0x89ffa4f0, + 0x8c003031, 0xbc003024, 0xacbcd0a9, 0x3fdf3fa0, 0x30318cae, 0xffe9c400, 0x20909cbc, 0x3024899f, + 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x30318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f0010dc, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x00303189, 0x91209f3f, 0x00302489, 0x3d0009bc, 0x20092094, 0x3024892f, 0xfff4f000, 0x20f0f9bc, + 0xf921fbf1, 0x10dc8f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, - 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0d1800bf, 0x0014331d, 0x4f02f806, - 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xdf320b0c, 0x9f3ee43d, 0x02f80011, 0xdf32e43d, 0x00119f3e, - 0xc401ff12, 0x09bcfff9, 0x20991890, 0x1bf49126, 0x3ea43d09, 0x330011c9, 0x32080094, 0x33010efd, - 0x33e100f4, 0xc41100e0, 0x09bcffd9, 0x20913590, 0x0011b63e, 0x49fe02f8, 0x08999001, 0x010a9fbf, + 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, + 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, + 0xc401ee12, 0x09bcffe9, 0x20991890, 0x1bf49126, 0x3ea43d09, 0x330011c9, 0x32080094, 0x33010fed, + 0x33e100e4, 0xc41100f0, 0x09bcffd9, 0x20913590, 0x0011b63e, 0x49fe02f8, 0x08999001, 0x010a9fbf, 0xfd19f918, 0xf935059a, 0x0415fb19, 0x0011417e, 0x0600a433, 0x00f802f8, 0xf9fc30f4, 0x32a0b212, 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, - 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x32008fff, - 0x32188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x0005a488, 0x8120597c, 0x3e001118, + 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x30008fff, + 0x30188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e0010dc, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, - 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0032248f, 0x18909fbc, 0x19180190, - 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0032188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0032, + 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0030248f, 0x18909fbc, 0x19180190, + 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0030188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0030, 0xf0102098, 0x1975fff4, 0xf09f7c01, 0x58021f75, 0x9b520219, 0xffb9e401, 0x021b75ff, 0xfe0894b6, 0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033, - 0x00320080, 0x80e80f7c, 0x3c003218, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, + 0x00300080, 0x80e80f7c, 0x3c003018, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, 0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2, 0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e, 0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012, @@ -208,266 +208,266 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x000005a0, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0xb4d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, - 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3650daf2, 0x50db0000, 0x7e000034, - 0x7e0015f6, 0xf7000b68, 0xb4d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, - 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003650, 0x003450db, 0x15f67e00, - 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000034, 0x00003250, 0x0015f67e, 0x000b207e, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x00289880, 0x64d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3450daf2, 0x50db0000, 0x7e000032, + 0x7e0015f6, 0xf7000b68, 0x64d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003450, 0x003250db, 0x15f67e00, + 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000032, 0x00003050, 0x0015f67e, 0x000b207e, 0x0016473e, 0xf91832f4, 0x0188fef2, 0x3b7e80f9, 0x80fc0040, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x2cdf00f8, 0xf4000006, 0x62f9fc30, - 0xffbffebf, 0x900149fe, 0x9ea01c99, 0x000630d9, 0xbd9fa000, 0x010089f4, 0x009ff601, 0xb87fff4f, + 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0xdcdf00f8, 0xf4000005, 0x62f9fc30, + 0xffbffebf, 0x900149fe, 0x9ea01c99, 0x0005e0d9, 0xbd9fa000, 0x010089f4, 0x009ff601, 0xb87fff4f, 0x003f0099, 0xdf009ff6, 0x03ff0000, 0x010099b8, 0x009ff600, 0x00ff808f, 0x0a0099b8, 0x009ff600, - 0xb810004f, 0x024a0099, 0xd6009ff6, 0x40000000, 0x011c0085, 0x000640d0, 0x02008400, 0x00008301, + 0xb810004f, 0x024a0099, 0xd6009ff6, 0x40000000, 0x011c0085, 0x0005f0d0, 0x02008400, 0x00008301, 0xaaa0d210, 0xfd01beef, 0x227e080a, 0xa6fd001c, 0x280bf504, 0x0049cf00, 0xf50493fd, 0xde001e0b, - 0x00000640, 0xf2fff4bd, 0x90e9a095, 0xee9001ff, 0x04f4b304, 0x17f03ef5, 0x0059cf00, 0xf40194f0, + 0x000005f0, 0xf2fff4bd, 0x90e9a095, 0xee9001ff, 0x04f4b304, 0x17f03ef5, 0x0059cf00, 0xf40194f0, 0x3cf4fa1b, 0xf009b21f, 0x99fa0593, 0xf503f806, 0xf590043c, 0xf590033c, 0xf5ac543c, 0xf5c4043c, 0xb2d0333c, 0x0393f009, 0xf80599fa, 0x003cf403, 0xe9920ebf, 0xf491a601, 0x0e98250d, 0x01e99201, - 0x0df491a6, 0x020e981a, 0xa601e992, 0x0f0df491, 0x92030e98, 0x91a601e9, 0xff700cf5, 0x000640df, - 0xd094bd00, 0x0000062c, 0xa003f9b5, 0x01f9b5f9, 0xa002f9b5, 0x589a7e0e, 0x0630d900, 0x99bf0000, + 0x0df491a6, 0x020e981a, 0xa601e992, 0x0f0df491, 0x92030e98, 0x91a601e9, 0xff700cf5, 0x0005f0df, + 0xd094bd00, 0x000005dc, 0xa003f9b5, 0x01f9b5f9, 0xa002f9b5, 0x589a7e0e, 0x05e0d900, 0x99bf0000, 0x09a0a4bd, 0x900149fe, 0x9fbf1c99, 0xf9a609bf, 0x7e070bf4, 0xfb0042e9, 0x30f40465, 0xd112f9fc, - 0x0000062c, 0x40fe19bf, 0x08009001, 0xcf7e09a0, 0x0fbf0019, 0xa4f019bf, 0xf4f9a6ff, 0xe97e070b, - 0x15fb0042, 0x062cdf04, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0xf40031f4, 0x49fe0028, 0xd99fbf01, - 0x0000062c, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4efbf00, 0x49fefc30, - 0xf89fa001, 0xbf9fbf02, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x00062cd1, + 0x000005dc, 0x40fe19bf, 0x08009001, 0xcf7e09a0, 0x0fbf0019, 0xa4f019bf, 0xf4f9a6ff, 0xe97e070b, + 0x15fb0042, 0x05dcdf04, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0xf40031f4, 0x49fe0028, 0xd99fbf01, + 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4efbf00, 0x49fefc30, + 0xf89fa001, 0xbf9fbf02, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf001a81, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, - 0x00001438, 0xf9fc30f4, 0x062cd112, 0x9b180000, 0x0c9a180d, 0x40fe19bf, 0x08009001, 0xe67e09a0, - 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x0000062c, 0x40fe19bf, + 0x00001334, 0xf9fc30f4, 0x05dcd112, 0x9b180000, 0x0c9a180d, 0x40fe19bf, 0x08009001, 0xe67e09a0, + 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x000005dc, 0x40fe19bf, 0x08009001, 0xe67e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, - 0x0000062c, 0x40fe19bf, 0x08009001, 0x517e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, - 0x2cdf0415, 0xbf000006, 0xfc30f4ff, 0xa00149fe, 0x1400899f, 0x0099cf02, 0xf40194f0, 0x1f7e180b, - 0x008f0047, 0xf9ce0213, 0x0195f000, 0x3e00f9f7, 0xf80019b5, 0x0149fe02, 0x2cd99fbf, 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0x1d98021c, 0x02099803, 0xdb040a98, - 0x000001cc, 0x91b0010e, 0x23037e00, 0xb309bf00, 0x98350494, 0x1d98041c, 0x040a9805, 0xdb020998, - 0x000001dc, 0x91b0010e, 0x23037e00, 0x081c9800, 0x98091d98, 0x21b0040a, 0x01dcdb00, 0xe43d0000, - 0x0023037e, 0x94b309bf, 0x1c981b05, 0x071d9806, 0xb0040a98, 0xdcdb0021, 0x3d000001, 0x23037ee4, - 0xb309bf00, 0x98351594, 0x1d980c1c, 0x040a980d, 0xdb020998, 0x000001ec, 0x91b0010e, 0x23037e00, - 0x0a1c9800, 0x980b1d98, 0x21b0040a, 0x01ecdb00, 0xe43d0000, 0x0023037e, 0x94b309bf, 0x1c981b16, - 0x0f1d980e, 0xb0040a98, 0xecdb0021, 0x3d000001, 0x23037ee4, 0x20009000, 0x1bf507a6, 0x0109ff33, - 0x4d940920, 0x145cd902, 0x4cdf0000, 0xbc000014, 0xff0ad0d9, 0x002a4cde, 0xa6f9bf00, 0x2f1bf469, - 0xa601f998, 0x271bf459, 0x3308f918, 0xb3210194, 0xb0140130, 0x08f40136, 0xb3ff0a0d, 0x3e110234, + 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xa699bf00, + 0x070bf4f9, 0x0042e97e, 0xf42c85fb, 0xdcd9fc30, 0xf9000005, 0xf499bf62, 0x24d0fc30, 0xfe000028, + 0xff90014f, 0x3ff9a020, 0xb2a5b209, 0xb2c2b2b4, 0x009d33d3, 0xb4bd0111, 0xda14e44c, 0x00001344, + 0x000b947e, 0x06b294bd, 0x8a0091b0, 0xdb02c000, 0x000001fc, 0x00020cdc, 0x3d1a0d00, 0x1344d0e4, + 0x037e0000, 0x14bd0023, 0x94b309bf, 0x09981f13, 0x040a9802, 0x0001ccdb, 0x0344dc00, 0x91b00000, + 0x0e080d00, 0x23037e01, 0xb30dbf00, 0x983504d4, 0x0998040a, 0x01dcdb02, 0xa4dc0000, 0x0e000003, + 0x0091b001, 0x0023037e, 0xb0040a98, 0xdcdb0011, 0xdc000001, 0x000003d4, 0xe43d090d, 0x0023037e, + 0x94b309bf, 0x0a981c05, 0x0011b004, 0x0001dcdb, 0x0440dc00, 0x020d0000, 0x037ee43d, 0x09bf0023, + 0x371594b3, 0x98040a98, 0xecdb0209, 0xdc000001, 0x00000458, 0x010e040d, 0x7e0091b0, 0x98002303, + 0x11b0040a, 0x01ecdb00, 0x88dc0000, 0x0d000004, 0x7ee43d04, 0xbf002303, 0x1694b309, 0x040a981c, + 0xdb0011b0, 0x000001ec, 0x0004b8dc, 0x3d020d00, 0x23037ee4, 0x20009000, 0x1bf506a6, 0x0109ff2e, + 0x3d940920, 0x1358d902, 0x48df0000, 0xbc000013, 0xff0ad0d9, 0x002828de, 0xa6f9bf00, 0x2f1bf459, + 0xa601f998, 0x271bf449, 0x3308f918, 0xb3210194, 0xb0140120, 0x08f40126, 0xb3ff0a0d, 0x3e110224, 0x980025ea, 0xec3e03fa, 0xdabf0025, 0x9020ff90, 0xfea620dd, 0x09c51bf4, 0xf4a9a6ff, 0x190f0d1b, - 0xf7110049, 0x02f8009f, 0x900149fe, 0x9fbf2499, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xfb0430f4, 0x30f40475, 0xd112f9f4, 0x0000062c, 0x40fe19bf, 0x10009001, 0x09a0caa0, 0xcbb594bd, - 0x02c9b501, 0x00140cd9, 0xfe9fbf00, 0x99900149, 0x019bb508, 0xb5b69aa0, 0xd8fab811, 0xb17e0002, - 0x0fbf001c, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40c15, 0xd252f9e8, 0x0000062c, 0x40fe29bf, + 0xf7110049, 0x02f8009f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, + 0xfb0430f4, 0x30f40465, 0xd112f9f4, 0x000005dc, 0x40fe19bf, 0x10009001, 0x09a0caa0, 0xcbb594bd, + 0x02c9b501, 0x00130cd9, 0xfe9fbf00, 0x99900149, 0x019bb508, 0xb5b69aa0, 0xd8fab811, 0xb17e0002, + 0x0fbf001c, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40c15, 0xd252f9e8, 0x000005dc, 0x40fe29bf, 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0xae320031, 0x0c00a433, 0xbc7e0ab2, 0xae320030, 0x900149fe, - 0x9fbf0499, 0x00062cd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x05fb0042, 0xf430f404, 0x00062cd9, + 0x9fbf0499, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x05fb0042, 0xf430f404, 0x0005dcd9, 0xbf12f900, 0x014ffe99, 0x4b10ff90, 0xf9a003e8, 0x0016fc7e, 0x4afea0b2, 0x08aa9001, 0x817ea1b2, 0xa08a0015, 0x227e00e5, 0xa6b0001c, 0x1c1ff400, 0x9c7e1ab2, 0xa0a60015, 0x0a090df4, 0x334b3e04, - 0x000e7e00, 0x33223e00, 0xfea43d00, 0x99900149, 0xd99fbf10, 0x0000062c, 0xf9a699bf, 0x7e070bf4, - 0xfb0042e9, 0x30f40c15, 0x062cdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0b0b2, 0x3f01ad58, + 0x000e7e00, 0x33223e00, 0xfea43d00, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, + 0xfb0042e9, 0x30f40c15, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0b0b2, 0x3f01ad58, 0x02a958af, 0x000000de, 0xffdce480, 0x03f4f0ff, 0xb60093f0, 0x9cbc12f4, 0x05fefd90, 0xf0019992, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, 0x001cb17e, 0xf97e0ab2, 0x49fe0032, 0x04999001, - 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xf830f404, 0x00062cdf, 0xbf52f900, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xf830f404, 0x0005dcdf, 0xbf52f900, 0x0149feff, 0xb21c9990, 0x729fa0a3, 0x71020ab1, 0xf40100b6, 0x44fe450c, 0xe4a08201, 0x18449000, 0x723e54bd, 0x45a00034, 0x16701072, 0x050df404, 0x3bb20400, 0xffff0ce4, 0x7e7e4ab2, 0x4bbf000b, 0x107b2ab2, 0x04229002, 0x7e0003f0, 0xbc001cb1, 0x14733030, 0xa43dd400, 0x900149fe, 0x9fbf1c99, - 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, 0x2cd9fc30, 0xf9000006, 0xfe99bf32, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, 0xdcd9fc30, 0xf9000005, 0xfe99bf32, 0xff90014f, 0xa0b2b210, 0x58c3b2f9, 0xbb5802b9, 0x00a0b301, 0x0093f056, 0x9990fc0f, 0xffb0e403, 0x149fffff, 0xb30b1bf4, 0x3e0c0004, 0xb3003507, 0xb20e0000, 0x34157eda, 0x00a43300, 0x8b2ab230, 0x7e07a120, 0x33003366, 0xb32200a4, 0xb01e0010, 0xccf00006, 0x01c6f00b, 0x1b723ab2, 0x7e05c436, - 0x3e003054, 0x0a003509, 0x0149fe35, 0xbf109990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, - 0x0435fb00, 0xdff830f4, 0x0000062c, 0xffbf12f9, 0x900149fe, 0x40fe0c99, 0x909fa001, 0xb1b20800, + 0x3e003054, 0x0a003509, 0x0149fe35, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, + 0x0435fb00, 0xdff830f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0x40fe0c99, 0x909fa001, 0xb1b20800, 0xe87e0cb2, 0x0fbf0050, 0x9802f958, 0x93f003ff, 0x0c94b600, 0x0035653e, 0x0bf491a6, 0x06ff9815, 0x100099b8, 0x00f4b300, 0x3e350af3, 0x98003584, 0xf99802fe, 0xbcffbf05, 0x9ea6909f, 0xf0089cf0, - 0x9a320196, 0x900149fe, 0x9fbf0c99, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40815fb, - 0x2cdfe030, 0xf9000006, 0xb0ffbf82, 0x49fe09b1, 0x40999001, 0xa00140fe, 0x3c00909f, 0x0cb2a4b2, + 0x9a320196, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40815fb, + 0xdcdfe030, 0xf9000005, 0xb0ffbf82, 0x49fe09b1, 0x40999001, 0xa00140fe, 0x3c00909f, 0x0cb2a4b2, 0x0050e87e, 0x395803bf, 0x03319802, 0xb60093f0, 0xe63e0c94, 0xe0b40035, 0xf49ea609, 0x1198130b, 0x0099b806, 0x14b30010, 0xb83ef000, 0x19980037, 0x031f9805, 0xb6041e98, 0x9fbc0395, 0xf42ea620, 0x43fe4f0c, 0x904ab201, 0x2bb23833, 0x3db2010c, 0x0031aa7e, 0xad33a032, 0xbf01a400, 0xff004f39, 0x90014efe, 0x99bc34ee, 0x059ffd90, 0x2cb24ab2, 0xe9a0ebb2, 0x4a7e040d, 0xa032004b, 0x7e00ad33, - 0x05199801, 0xb5019990, 0xba3e0519, 0xd4d90037, 0x9800002a, 0x49fe049e, 0x3c999001, 0x9ea09fb2, + 0x05199801, 0xb5019990, 0xba3e0519, 0x7cd90037, 0x98000028, 0x49fe049e, 0x3c999001, 0x9ea09fb2, 0x0036703e, 0x33091918, 0x98130090, 0xf1a00411, 0x14b3f1bf, 0xd43ef200, 0x39350037, 0x36a83e08, 0x08b91800, 0x13009033, 0xa004bb98, 0xb31bbf1b, 0x3ef200b4, 0xbf0037b8, 0x7e4ab2bb, 0x32004a98, 0x00ad33a0, 0x11bf0119, 0xbf011f98, 0x0142fe3b, 0x3fb54ab2, 0x04195801, 0x0c302290, 0x752db204, @@ -479,21 +479,21 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb24ab201, 0x7e040d7b, 0x33004b4a, 0xa07500a4, 0x031b9823, 0x040c4ab2, 0xbb928db2, 0x31aa7e04, 0x00a43300, 0x032c985f, 0x8bb24ab2, 0xcc92040d, 0x4b4a7e04, 0x00a43300, 0x021f984b, 0x29b594bd, 0x0066b805, 0x2fb50010, 0x06229802, 0xb3061198, 0xff6f001d, 0x0037ba3e, 0x49fe3500, 0x40999001, - 0x2cd99fbf, 0xbf000006, 0xa60a3299, 0x1d0bf4f9, 0x0037e63e, 0xa00141fe, 0x3c1190fe, 0x00368d3e, - 0xba3ea032, 0xe97e0037, 0x85fb0042, 0xfc30f420, 0x00062cdf, 0xbf02f900, 0x0149feff, 0xb2049990, - 0xb39fa0a0, 0x985100a0, 0x90b306a9, 0x0cd94a00, 0xbf000014, 0xe0aab89a, 0x227e0004, 0xa9e4001c, + 0xdcd99fbf, 0xbf000005, 0xa60a3299, 0x1d0bf4f9, 0x0037e63e, 0xa00141fe, 0x3c1190fe, 0x00368d3e, + 0xba3ea032, 0xe97e0037, 0x85fb0042, 0xfc30f420, 0x0005dcdf, 0xbf02f900, 0x0149feff, 0xb2049990, + 0xb39fa0a0, 0x985100a0, 0x90b306a9, 0x0cd94a00, 0xbf000013, 0xe0aab89a, 0x227e0004, 0xa9e4001c, 0x9ab30fff, 0xb3380fff, 0xe7330090, 0xb3016caa, 0x2b0fffaa, 0x2600a0b3, 0xb6060e98, 0xaf940c94, 0xa0a43d0c, 0x060e98e9, 0xf9bce9bf, 0x01efb5f0, 0x00385c3e, 0x5c3e350a, 0x2e0a0038, 0x900149fe, - 0x9fbf0499, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0x2cdfd830, 0xf9000006, + 0x9fbf0499, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0xdcdfd830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0a6b248, 0x00a0b39f, 0x06a09821, 0x0bbffd09, 0xa601bf92, 0x110cf4f9, 0x09010f98, 0xf4f9a6ff, 0xf4b3070b, 0x02f81100, 0x6db30205, 0x3e027d00, 0x92003b3c, 0x100c10bb, - 0x002ad4dd, 0x31aa7e00, 0x33a53200, 0x026400ad, 0x002ad4da, 0x0068db00, 0x080c0000, 0x000ba87e, + 0x00287cdd, 0x31aa7e00, 0x33a53200, 0x026400ad, 0x00287cda, 0x0068db00, 0x080c0000, 0x000ba87e, 0x7e00adb3, 0x01099802, 0xf9a60fbf, 0x027818f5, 0x0ffffee4, 0x02701bf5, 0xfe066f98, 0x99900149, 0xbf843d44, 0x0af1b0ff, 0x94bd9ea0, 0x3e0b91b0, 0x3d003b19, 0x7e140ba4, 0xb20040e5, 0x00a4b3a3, 0x0502f80c, 0x3b2f3e05, 0x0ae0b400, 0xb6ff89c4, 0x9ebc0c94, 0xa094bdb0, 0x04a9b5ab, 0x0fffb9e4, 0x02241bf5, 0xb2014dfe, 0x90040c6a, 0xaa7e44dd, 0xa0330031, 0xa5320a00, 0x003b2b3e, 0xf11190b4, 0x750fff94, 0x90b40239, 0x6c99e711, 0x03397501, 0xb61190b4, 0x39351f95, 0x11f0b408, 0x0ffff9e4, - 0x0fff9ab3, 0x6cf9e713, 0xff9ab301, 0x01090a0f, 0xbf093935, 0x0099b339, 0xd4df0090, 0x1800002a, + 0x0fff9ab3, 0x6cf9e713, 0xff9ab301, 0x01090a0f, 0xbf093935, 0x0099b339, 0x7cdf0090, 0x18000028, 0x99900dfb, 0x0ffc4a04, 0xf00991b0, 0xbb7effb4, 0x94bd0016, 0x91b0743d, 0xfffc090d, 0x91b094a9, 0x3af13e0c, 0x0ba43d00, 0x40e57e1c, 0xb3a1b200, 0xf80c00a4, 0x3e050002, 0xb4003b58, 0x7ac40cb0, 0x16fc7eff, 0xb5e4bd00, 0xb0b4061e, 0xfe040c09, 0xdd90014d, 0xb0babc40, 0x1bb56ab2, 0x31aa7e01, @@ -504,58 +504,58 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x2b906ab2, 0x904cb204, 0x857e38dd, 0xad330051, 0xbf00c800, 0x0ef0b419, 0xa0909fbc, 0x3aca3e19, 0x07f4b300, 0xffffde29, 0x9efd00ff, 0x042b9004, 0xb50219b5, 0x1bb50414, 0xb24cb203, 0x141d906a, 0x0051857e, 0xd23ea032, 0x2290003a, 0xf424a604, 0x0d338d0d, 0x98008600, 0x94b30339, 0x31b50b00, - 0x3aeb3e03, 0x0df0b400, 0x1006f1b5, 0x11b00177, 0x2ad4de0d, 0xe9180000, 0xf579260d, 0x98feca08, - 0x94b304e9, 0xe3b50b00, 0x3b133e04, 0x0bf0b400, 0x1004f3b5, 0x31b00188, 0x2ad4de0b, 0xe9180000, + 0x3aeb3e03, 0x0df0b400, 0x1006f1b5, 0x11b00177, 0x287cde0d, 0xe9180000, 0xf579260d, 0x98feca08, + 0x94b304e9, 0xe3b50b00, 0x3b133e04, 0x0bf0b400, 0x1004f3b5, 0x31b00188, 0x287cde0b, 0xe9180000, 0xf589260c, 0x3efdf008, 0x33003b3c, 0x98110050, 0xff0f0669, 0x69989fa0, 0x019fb506, 0x900149fe, - 0x9fbf4899, 0x00062cd9, 0x3299bf00, 0xf4f9a65a, 0x6a3e1f0b, 0xa032003b, 0x2b3e0532, 0x3505003b, - 0x003b2f3e, 0x2f3e0205, 0xe97e003b, 0x85fb0042, 0xf430f428, 0x00062cdf, 0xbf22f900, 0x0149feff, - 0xfe149990, 0x9fa00142, 0x229094bd, 0x7e29a00c, 0x33004863, 0x0b5600a0, 0x2a9cda04, 0xbcb20000, + 0x9fbf4899, 0x0005dcd9, 0x3299bf00, 0xf4f9a65a, 0x6a3e1f0b, 0xa032003b, 0x2b3e0532, 0x3505003b, + 0x003b2f3e, 0x2f3e0205, 0xe97e003b, 0x85fb0042, 0xf430f428, 0x0005dcdf, 0xbf22f900, 0x0149feff, + 0xfe149990, 0x9fa00142, 0x229094bd, 0x7e29a00c, 0x33004863, 0x0b5600a0, 0x2844da04, 0xbcb20000, 0x397e2db2, 0xa032004e, 0x4300a433, 0x900141fe, 0x1ab21011, 0x003c087e, 0xa433a032, 0x1cbf3100, - 0xa4bd2bbf, 0x001428d1, 0xd1797e00, 0xb31aa000, 0x3d1a00a0, 0xd2117eb4, 0x00a0b300, 0x001abf12, - 0xd74b7eff, 0x3beb3e00, 0xfeff0000, 0x99900149, 0xd99fbf14, 0x0000062c, 0x0a3299bf, 0x0bf4f9a6, - 0x42e97e07, 0x0c25fb00, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x09f9a001, 0xbfa9a00e, 0x3de9bfff, - 0xf4f9a6a4, 0xe97e070b, 0x30f40042, 0xf400f804, 0x2cdfd830, 0xf9000006, 0xf4ffbf62, 0x49fef430, + 0xa4bd2bbf, 0x001324d1, 0xd1477e00, 0xb31aa000, 0x3d1a00a0, 0xd1df7eb4, 0x00a0b300, 0x001abf12, + 0xd7197eff, 0x3beb3e00, 0xfeff0000, 0x99900149, 0xd99fbf14, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x42e97e07, 0x0c25fb00, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x09f9a001, 0xbfa9a00e, 0x3de9bfff, + 0xf4f9a6a4, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdfd830, 0xf9000005, 0xf4ffbf62, 0x49fef430, 0x4c999001, 0xa93f9fa0, 0xa398a6b2, 0x01903301, 0x489d330d, 0x3c3e0360, 0x3018003e, 0x010d3304, - 0x3298011b, 0x04319803, 0xdc4ba43d, 0x01004c10, 0x000680d5, 0x40cb7e00, 0xb35aa000, 0xf80c00a4, - 0x3e050102, 0xfe003fb3, 0x99900149, 0x2af4d428, 0x1cb20000, 0xb50741b5, 0x2bb20191, 0xb5154035, + 0x3298011b, 0x04319803, 0xdc4ba43d, 0x01004c10, 0x000630d5, 0x40cb7e00, 0xb35aa000, 0xf80c00a4, + 0x3e050102, 0xfe003fb3, 0x99900149, 0x289cd428, 0x1cb20000, 0xb50741b5, 0x2bb20191, 0xb5154035, 0x92a00642, 0xdc4ed4bd, 0x26727e10, 0x33a13200, 0x015900ad, 0x993f59bf, 0x0d009033, 0xf0014998, - 0x49b50895, 0x0680d901, 0x99bf0000, 0x33699918, 0xdf130090, 0x00002af4, 0xf101f998, 0xb5400095, - 0xf4da01f9, 0x7e00002a, 0x9800b9ce, 0x027e0230, 0xebd90001, 0xb20000a6, 0x0091b0ac, 0xb4bd0db2, - 0xc8da04bd, 0xb000002f, 0x01300101, 0x7e010e08, 0xd90013c8, 0x00002af4, 0x000000df, 0x5090351e, - 0x900149fe, 0x42fe3499, 0x909fa001, 0x010a3822, 0xcd7e2bb2, 0xa43300b1, 0x2bbf1b1f, 0xf401b9c4, - 0xb5f0141b, 0xa0010a01, 0xb20f7e2b, 0x1fa03300, 0xbd09f806, 0x7e020ab4, 0xda00b20f, 0x00002af4, - 0x00b85d7e, 0xbd014afe, 0x0dc4bdb4, 0x34aa9001, 0x0090537e, 0x003e0d3e, 0x32020433, 0x000680d9, - 0xb39abf00, 0xd97f00a0, 0x00002b0c, 0xbf019c98, 0xd9f43d9b, 0x00002af4, 0x9f35d4bd, 0x10dc4e15, - 0x0026727e, 0x083ea132, 0x0d33003e, 0x7e020703, 0x1800010e, 0x90330839, 0x3e982400, 0x2b94d903, - 0x9cdf0000, 0xa000002b, 0x043e989e, 0x98019eb5, 0xf9a00539, 0xb5063e98, 0x391801fe, 0x0090331c, - 0x2af4df21, 0x39980000, 0x2dfe9808, 0xfd2efd98, 0xf9b5059e, 0x0939982d, 0xb5059dfd, 0x087e2ef9, + 0x49b50895, 0x0630d901, 0x99bf0000, 0x33699918, 0xdf130090, 0x0000289c, 0xf101f998, 0xb5400095, + 0x9cda01f9, 0x7e000028, 0x9800b99c, 0x027e0230, 0xb9d90001, 0xb20000a6, 0x0091b0ac, 0xb4bd0db2, + 0x70da04bd, 0xb000002d, 0x01300101, 0x7e010e08, 0xd90013c8, 0x0000289c, 0x000000df, 0x5090351e, + 0x900149fe, 0x42fe3499, 0x909fa001, 0x010a3822, 0x9b7e2bb2, 0xa43300b1, 0x2bbf1b1f, 0xf401b9c4, + 0xb5f0141b, 0xa0010a01, 0xb1dd7e2b, 0x1fa03300, 0xbd09f806, 0x7e020ab4, 0xda00b1dd, 0x0000289c, + 0x00b82b7e, 0xbd014afe, 0x0dc4bdb4, 0x34aa9001, 0x0090217e, 0x003e0d3e, 0x32020433, 0x000630d9, + 0xb39abf00, 0xd97f00a0, 0x000028b4, 0xbf019c98, 0xd9f43d9b, 0x0000289c, 0x9f35d4bd, 0x10dc4e15, + 0x0026727e, 0x083ea132, 0x0d33003e, 0x7e020703, 0x1800010e, 0x90330839, 0x3e982400, 0x293cd903, + 0x44df0000, 0xa0000029, 0x043e989e, 0x98019eb5, 0xf9a00539, 0xb5063e98, 0x391801fe, 0x0090331c, + 0x289cdf21, 0x39980000, 0x2dfe9808, 0xfd2efd98, 0xf9b5059e, 0x0939982d, 0xb5059dfd, 0x087e2ef9, 0x143d0001, 0x003e0d3e, 0xab001d33, 0x016b1801, 0x817e3ab2, 0x0209000f, 0x90014ffe, 0xf92048ff, 0xf935943d, 0x03331802, 0xb4bd0409, 0xf335fab2, 0x01f93503, 0x000f717e, 0x003fb33e, 0xfe0140fe, - 0x00900141, 0x40119044, 0xb20142fe, 0x3c22900a, 0x2cb21bb2, 0x537ed43d, 0x39980090, 0x0a0fbf02, - 0xf4f9a601, 0x70de3c1b, 0x3f000005, 0x009033e9, 0x0a943d0e, 0x3ee9201e, 0xd9003e9f, 0x200000ff, - 0xb394f9ff, 0xb2121c94, 0xb21bb20a, 0xb6647e2c, 0x3e9f3e00, 0xb20ab200, 0x7e2cb21b, 0xfe00a9ff, + 0x00900141, 0x40119044, 0xb20142fe, 0x3c22900a, 0x2cb21bb2, 0x217ed43d, 0x39980090, 0x0a0fbf02, + 0xf4f9a601, 0x24de3c1b, 0x3f000005, 0x009033e9, 0x0a943d0e, 0x3ee9201e, 0xd9003e9f, 0x200000ff, + 0xb394f9ff, 0xb2121c94, 0xb21bb20a, 0xb6327e2c, 0x3e9f3e00, 0xb20ab200, 0x7e2cb21b, 0xfe00a9cd, 0xbb90014b, 0xc4bebf44, 0xffdf1fa9, 0xb6e0ffff, 0xeffd1894, 0xe59eff04, 0x00d9bea0, 0xff400000, 0x0bf494e9, 0x1fa4336b, 0x0149fe68, 0xbf409990, 0x0499929d, 0xe4339cbf, 0x03df421e, 0x89ff0000, 0xff3fffff, 0xd9fff4ef, 0x0294b694, 0xb3e5f9ff, 0xc50b00c0, 0x093e03e9, 0xfd09003f, 0xfd16df95, 0xf0b304e9, 0xe9c50d00, 0x3eb9a001, 0x09003f2d, 0x94e9fffe, 0x003f093e, 0x000000df, 0xffffd9ff, 0xefff00ff, 0x94d9fff4, 0xa005f9fd, 0x0149febf, 0x90014ffe, 0xff904099, 0xbf9ebf44, 0x049992ff, - 0x99929dbf, 0x929fa004, 0x9ea00499, 0xa0049992, 0x0a747e9d, 0x2af4d900, 0x99180000, 0x00943348, + 0x99929dbf, 0x929fa004, 0x9ea00499, 0xa0049992, 0x0a747e9d, 0x289cd900, 0x99180000, 0x00943348, 0x3e02f80a, 0x33003f6b, 0xfe1e0190, 0xee90014e, 0xdfe9bf38, 0xe0ffffff, 0xdf049ffd, 0x01000000, - 0xa0059ffd, 0xd9f43de9, 0x00002af4, 0x9f35010d, 0x014bfe48, 0x90014cfe, 0xcc9034bb, 0x014afe30, - 0x7e38aa90, 0x7e009053, 0x3d000a9b, 0x3fb33e14, 0xfee40100, 0x99900149, 0xd99fbf4c, 0x0000062c, + 0xa0059ffd, 0xd9f43de9, 0x0000289c, 0x9f35010d, 0x014bfe48, 0x90014cfe, 0xcc9034bb, 0x014afe30, + 0x7e38aa90, 0x7e009021, 0x3d000a9b, 0x3fb33e14, 0xfee40100, 0x99900149, 0xd99fbf4c, 0x000005dc, 0x1a3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0c30f400, 0x922865fb, 0x9ba004a9, 0xb548ae92, 0x008906ec, - 0xe9a03000, 0x94bdafb2, 0xb24cff92, 0xf8f9a0fa, 0x7e02f900, 0xb300715d, 0xbd0a00a4, 0x40373e04, + 0xe9a03000, 0x94bdafb2, 0xb24cff92, 0xf8f9a0fa, 0x7e02f900, 0xb300714f, 0xbd0a00a4, 0x40373e04, 0x16898900, 0x0093fe00, 0x00163389, 0x890090fe, 0xfe001671, 0xa4bd0091, 0x897eb4bd, 0xa0b2000a, 0xf400a6b0, 0xa4bd0c1f, 0x7efe0b4b, 0x7e000a95, 0x3e004140, 0xb200162b, 0x7e01fb0a, 0xf8000ad6, 0x8f22f900, 0xb200ffff, 0xf4bfa6c0, 0xc0b3720c, 0xc9926f00, 0x049cfd01, 0xa6651bf4, 0x600cf4cf, - 0x0903bf90, 0x14f9fffc, 0x7e550bf4, 0x82000a74, 0x7f003244, 0x3240892d, 0x899abf00, 0xc2003246, + 0x0903bf90, 0x14f9fffc, 0x7e550bf4, 0x82000a74, 0x7f003044, 0x3040892d, 0x899abf00, 0xc2003046, 0x9b7f0f0f, 0x5201ff79, 0x907c01d9, 0xc4f9ff90, 0x08f4cd66, 0xd0c17c21, 0xffffd9e4, 0x08f491a6, 0xf4db6615, 0xc9e4100c, 0x2d60ffff, 0x3e009abc, 0xbd0040b5, 0x0a9b7e04, 0x40bf3e00, 0xb204bd00, 0x0c21fb0a, 0x40417e04, 0xf900f800, 0x7eb1b212, 0xb2004041, 0x00a0b3a0, 0xbd1cb20c, 0x0b947eb4, - 0xfb0ab200, 0x7e040c11, 0xf80040cb, 0x3dabb200, 0x40e57ea4, 0x8f00f800, 0xbf001110, 0x1b9918f9, - 0x20069536, 0x18f9bfa9, 0x99c71b99, 0xf8b92024, 0x11108c00, 0x14cdbf00, 0xbec406af, 0x04e43603, + 0xfb0ab200, 0x7e040c11, 0xf80040cb, 0x3dabb200, 0x40e57ea4, 0x8f00f800, 0xbf0010d4, 0x1b9918f9, + 0x20069536, 0x18f9bfa9, 0x99c71b99, 0xf8b92024, 0x10d48c00, 0x14cdbf00, 0xbec406af, 0x04e43603, 0xf01bd918, 0xf9fd3f94, 0x1bdf3505, 0xf918cfbf, 0xcf94f01b, 0x3505e9fd, 0x327e1bfe, 0x00f80019, - 0x00111089, 0x9a1899bf, 0x24abc71b, 0x7e06a536, 0xf8001932, 0x18ff7e00, 0xf400f800, 0x82f9e030, + 0x0010d489, 0x9a1899bf, 0x24abc71b, 0x7e06a536, 0xf8001932, 0x18ff7e00, 0xf400f800, 0x82f9e030, 0xffffc1e4, 0xb210c295, 0xffa0e4c5, 0x10a395ff, 0x48fea4b2, 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, 0x1ab28aa0, 0x0016fc7e, 0xa6b20bb2, 0xfc7e2ab2, 0x3bb20016, 0x1ab2a0b2, 0x0016fc7e, 0xa1b23bb2, 0xfc7e2ab2, 0x10bc0016, 0x10699500, 0x09bcadb2, 0xf410a600, 0x00890a0d, @@ -566,88 +566,88 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x9801afb5, 0xaabf01ab, 0xf81030f4, 0x014afe00, 0xbd019fb9, 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x483eaabf, 0x30f40042, 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, 0x0096b002, 0xbc211df4, 0x4efef4bc, 0x95a9bc01, 0xbc059ffd, 0xe9b5f4ac, 0x98efa001, 0xeabf01eb, 0xf81030f4, - 0x014efe00, 0xbd019fb9, 0xf4afbc94, 0xefb5e9a0, 0x98eabf01, 0x9c3e01eb, 0x2cde0042, 0xbf000006, - 0xfc30f4e9, 0xdd014ffe, 0x00000000, 0x34d9f9a0, 0xbf000014, 0xbf9da0ff, 0xa6a43de9, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, 0x00062cdf, 0xbf12f900, + 0x014efe00, 0xbd019fb9, 0xf4afbc94, 0xefb5e9a0, 0x98eabf01, 0x9c3e01eb, 0xdcde0042, 0xbf000005, + 0xfc30f4e9, 0xdd014ffe, 0x00000000, 0x30d9f9a0, 0xbf000013, 0xbf9da0ff, 0xa6a43de9, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001cb1, 0x3f80014a, 0xaa904c4b, 0x7ea1b208, 0x8a001581, 0x7e12004c, 0xf0001c22, 0x1bf43fa4, 0x3e010a09, 0xb2004346, 0x159c7e1a, 0xf4a0a600, - 0x02f8e40d, 0x49fea43d, 0x10999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x15fb0042, - 0xfc30f40c, 0x00062cdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb39fa0b1, 0xb02101a0, 0x08f401a6, + 0x02f8e40d, 0x49fea43d, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, + 0xfc30f40c, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb39fa0b1, 0xb02101a0, 0x08f401a6, 0xb3ff0e0e, 0x00be02ad, 0x0044113e, 0x0049020f, 0x009ff60a, 0x00441f3e, 0xcf0a0049, 0xfe0e009f, 0xf604fefd, 0xd033009f, 0x004f2d00, 0x00f9cf08, 0xf9f694bd, 0x09004000, 0x4b0009cf, 0xcab203e8, 0x0016fc7e, 0x0200aab8, 0x0aa5b600, 0x3e000af6, 0x400043f9, 0x09cf0800, 0x03e84b00, 0xfc7ecab2, - 0xaab80016, 0xb6000200, 0xaa920aa5, 0x000af601, 0xcf090049, 0x9af6009f, 0x2a4cd900, 0x004f0000, + 0xaab80016, 0xb6000200, 0xaa920aa5, 0x000af601, 0xcf090049, 0x9af6009f, 0x2828d900, 0x004f0000, 0x0191b50a, 0xf000f9cf, 0xf9f60195, 0x443f3e00, 0x0a004e00, 0x0f00e9cf, 0x049ffdfe, 0x4f00e9f6, - 0xf9cf0800, 0xf694bd00, 0x004f00f9, 0x00f9cf09, 0xf9f694bd, 0xd9f4bd00, 0x00002a4c, 0x3d019fb5, - 0x0149fee4, 0xbf089990, 0x062cd99f, 0x99bf0000, 0xf9a6ea32, 0x7e070bf4, 0xfb0042e9, 0x2cdf0415, - 0xbf000006, 0xfc30f4ff, 0xa00149fe, 0x2a4cd99f, 0x99980000, 0x0194b301, 0x7e797e0c, 0x44833e00, - 0xfe02f800, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, - 0x2cd122f9, 0xbf000006, 0xfea2b219, 0x148a0140, 0x009008d1, 0x7e09a00c, 0x3f001c22, 0xbf0ebf29, - 0x08aac71f, 0xa6ff94f0, 0x0bacf0a9, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xdffc30f4, 0x0000062c, + 0xf9cf0800, 0xf694bd00, 0x004f00f9, 0x00f9cf09, 0xf9f694bd, 0xd9f4bd00, 0x00002828, 0x3d019fb5, + 0x0149fee4, 0xbf089990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, + 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x2828d99f, 0x99980000, 0x0194b301, 0x7e6b7e0c, 0x44833e00, + 0xfe02f800, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, + 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x148a0140, 0x009008d1, 0x7e09a00c, 0x3f001c22, 0xbf0ebf29, + 0x08aac71f, 0xa6ff94f0, 0x0bacf0a9, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xdffc30f4, 0x000005dc, 0xffbf02f9, 0x900149fe, 0x9fa00499, 0x0189008f, 0xf000f9ce, 0xf9f78095, 0x43004e00, 0x0f00e9ce, - 0x049ffdfe, 0xd000e9f7, 0x0000140c, 0xaab80abf, 0x7e00034c, 0xbf001c22, 0x03abc509, 0x034c9ab8, - 0x1cb17e00, 0x0149fe00, 0xbf049990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, - 0xdffc30f4, 0x0000062c, 0xffbf12f9, 0xfef430f4, 0x99900149, 0x8f9fa014, 0xcf01c000, 0x99c700f9, + 0x049ffdfe, 0xd000e9f7, 0x0000130c, 0xaab80abf, 0x7e00034c, 0xbf001c22, 0x03abc509, 0x034c9ab8, + 0x1cb17e00, 0x0149fe00, 0xbf049990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, + 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0xfef430f4, 0x99900149, 0x8f9fa014, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30085, 0x02f8f501, 0x00455b3e, 0xc700f9cf, 0x90b34c99, 0x90b35f00, 0x02f8f601, 0x0045703e, 0x001b957e, 0x0bb204bd, 0xd4bdc4bd, 0x6b7e0b0a, 0xa1900024, 0x7e1ab268, 0xe4001c22, 0xb30e00ab, 0x0b0e00be, 0xb17e1ab2, 0x0090001c, 0x2404b301, 0xbd94bdd9, 0x089130b4, 0xb00091b0, - 0xc4bd0191, 0xe43dd4bd, 0x001414da, 0x13c87e00, 0x46073e00, 0xc2008900, 0x0099cf01, 0xf40194f0, + 0xc4bd0191, 0xe43dd4bd, 0x001310da, 0x13c87e00, 0x46073e00, 0xc2008900, 0x0099cf01, 0xf40194f0, 0x843e280b, 0x1c8f0045, 0x00890285, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, - 0x3e9fb200, 0xfe004570, 0x99900149, 0xd99fbf14, 0x0000062c, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, - 0x15fb0c30, 0xfc30f404, 0x2cd112f9, 0xbf000006, 0xf430f419, 0x1c8ab4bd, 0x40fe0285, 0x14009001, - 0xb17e09a0, 0x027e001c, 0x40d90001, 0xb0000045, 0x94bd0091, 0x9130acb2, 0x0191b008, 0x001414da, + 0x3e9fb200, 0xfe004570, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, + 0x15fb0c30, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0xf430f419, 0x1c8ab4bd, 0x40fe0285, 0x14009001, + 0xb17e09a0, 0x027e001c, 0x40d90001, 0xb0000045, 0x94bd0091, 0x9130acb2, 0x0191b008, 0x001310da, 0x4db4bd00, 0x010e2710, 0x0013c87e, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0c30f400, 0xf40415fb, - 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00280f, 0xa619bf0f, 0x070bf4f9, - 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0027d6, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, - 0x7e09a008, 0xbf00279d, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, + 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00280f, 0xa619bf0f, 0x070bf4f9, + 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0027d6, + 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, + 0x7e09a008, 0xbf00279d, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0028db, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, - 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00291c, 0xa619bf0f, 0x070bf4f9, - 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0065ad, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, 0x0000062c, 0x30f4ffbf, 0x0149fefc, 0x008f9fa0, + 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00291c, 0xa619bf0f, 0x070bf4f9, + 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00659f, + 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, 0x000005dc, 0x30f4ffbf, 0x0149fefc, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x823e02f8, 0xf9cf0047, 0x4c99c700, 0x330090b3, 0xf60190b3, 0x963e02f8, 0x00890047, 0x9af601c1, 0x0099b800, 0x9bf60001, 0x00f2df00, 0x99b88000, - 0xf6020200, 0x9fcf009f, 0x3e9fb200, 0xfe004796, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0x062cdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x01c0008f, 0xc700f9cf, + 0xf6020200, 0x9fcf009f, 0x3e9fb200, 0xfe004796, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x01c0008f, 0xc700f9cf, 0x90b34c99, 0x90b32200, 0x02f8f601, 0x0047fc3e, 0xc700f9cf, 0x90b34c99, 0x90b33300, 0x02f8f601, 0x0048103e, 0x01c10089, 0xb8009af6, 0x00010099, 0xdf009bf6, 0x800000f2, 0x020099b8, 0x009ff602, - 0xb2009fcf, 0x48103e9f, 0x0149fe00, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x1ed9f9a0, 0xbf000011, 0xbf9a3fff, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xf400f804, 0x42f9f030, 0x00062cd4, 0xb249bf00, 0xbd0601a2, 0xfe1cb2b4, + 0xb2009fcf, 0x48103e9f, 0x0149fe00, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, + 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0xe2d9f9a0, 0xbf000010, 0xbf9a3fff, 0xf4f9a6e9, + 0xe97e070b, 0x30f40042, 0xf400f804, 0x42f9f030, 0x0005dcd4, 0xb249bf00, 0xbd0601a2, 0xfe1cb2b4, 0x43fe0140, 0x16009001, 0xb2203390, 0x7e39a00a, 0xbd000b94, 0x014dfe94, 0xa01cdd90, 0x75d120d9, 0x29180209, 0xb22ab204, 0x20c4bd0b, 0x35180909, 0x01090109, 0x7e010975, 0xbf003493, 0xa649bf3f, - 0x070bf4f9, 0x0042e97e, 0xf41045fb, 0x2cdfec30, 0xf9000006, 0xfeffbf22, 0x99900149, 0xa0a1b21c, + 0x070bf4f9, 0x0042e97e, 0xf41045fb, 0xdcdfec30, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a1b21c, 0xb2060c9f, 0x0140feb2, 0x0090b4bd, 0x7e0ab20e, 0xbd000b94, 0x014ffe94, 0xa018ff90, 0x041e18f9, 0x41fe1ab2, 0x14119001, 0x010919a0, 0x75020975, 0x05090109, 0x1909f920, 0x0bb20e20, 0xb2010935, - 0x7e1cb2fd, 0x32003493, 0x00a433a0, 0xb21abf0c, 0x2f7e7e2b, 0x0149fe00, 0xbf1c9990, 0x062cd99f, - 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0x30f41425, 0x062cd9f0, 0x42f90000, 0x4ffe99bf, + 0x7e1cb2fd, 0x32003493, 0x00a433a0, 0xb21abf0c, 0x2f7e7e2b, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, + 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0x30f41425, 0x05dcd9f0, 0x42f90000, 0x4ffe99bf, 0x20ff9001, 0xf9a0a3b2, 0xe84bbab2, 0x16fc7e03, 0x0142fe00, 0x04bda1b2, 0x90014afe, 0xaa901c22, 0x7ea4b214, 0x3e001581, 0xb20049b7, 0x159c7e4a, 0x7ea0b200, 0xb200000e, 0x7e2bb23a, 0x330048eb, 0xbf1600a4, 0x0194f029, 0x0d009033, 0x08f401a6, 0x49e03edd, 0xf401a600, 0xa43d0918, 0x0049e23e, - 0x49fe040a, 0x20999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x45fb0042, 0xf030f410, - 0x00062cdf, 0xbf22f900, 0x0149feff, 0x32189990, 0xa0a2b2b0, 0x488b7e9f, 0x00a43300, 0x00043364, + 0x49fe040a, 0x20999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x45fb0042, 0xf030f410, + 0x0005dcdf, 0xbf22f900, 0x0149feff, 0x32189990, 0xa0a2b2b0, 0x488b7e9f, 0x00a43300, 0x00043364, 0x3e143d0a, 0x18004a30, 0x94f01129, 0x0291140f, 0x060cb4bd, 0x900140fe, 0x0ab20e00, 0x000b947e, 0x4ffe94bd, 0x14ff9001, 0xf135f9a0, 0x02097501, 0xb2042918, 0xb2fdb20b, 0x0909202a, 0x09f92001, 0x01093518, 0xc4bd0209, 0x7e010975, 0x33003493, 0xb20e00a4, 0x86a08b2a, 0x49727e01, 0x0149fe00, - 0xbf189990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x1025fb00, 0xd9f030f4, 0x0000062c, + 0xbf189990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x1025fb00, 0xd9f030f4, 0x000005dc, 0x99bf22f9, 0x90014ffe, 0xa1b218ff, 0xb2b2f9a0, 0xb4bd060c, 0x90014afe, 0x947e0eaa, 0x94bd000b, 0xb20140fe, 0x1400901a, 0x8b7e09a0, 0xa4330048, 0x19186100, 0x0499c711, 0x0a0094b3, 0xe43e2009, 0xd709004a, 0x19180920, 0x014efe04, 0xfe0eee90, 0xe920014f, 0x90102995, 0xf93514ff, 0x08299501, 0x0902f935, 0x01e93518, 0xe9750409, 0xb2947d01, 0x03f235eb, 0xe975fdb2, 0xbd1ab202, 0x34937ec4, - 0x00a43300, 0x8b1ab20e, 0x7e07a120, 0xfe004972, 0x99900149, 0xd99fbf18, 0x0000062c, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f41025, 0x062cdfec, 0x72f90000, 0x49feffbf, 0x30999001, 0x9fa0a1b2, + 0x00a43300, 0x8b1ab20e, 0x7e07a120, 0xfe004972, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, + 0x7e070bf4, 0xfb0042e9, 0x30f41025, 0x05dcdfec, 0x72f90000, 0x49feffbf, 0x30999001, 0x9fa0a1b2, 0xc3b2b7b2, 0xa9b3d672, 0x71009e00, 0xf50100d6, 0xbd00950c, 0x0cb4bd54, 0x0140fe06, 0x900142fe, 0x22902000, 0x7505a02c, 0x25a00205, 0x900144fe, 0x4ab22644, 0x000b947e, 0x8b7e1ab2, 0xa4330048, 0x23356800, 0x04191803, 0x05750bb2, 0x202db202, 0x20020909, 0x10399529, 0x95012935, 0x29350839, 0x35080902, 0x04090109, 0x09751ab2, 0x7ec4bd01, 0x33003493, 0x753300a4, 0x45750146, 0x04191802, 0x7db24bb2, 0x49201ab2, 0xc4bd1009, 0x7e014935, 0x33003493, 0xb21300a4, 0x32004b1a, 0x0049727e, - 0x004c063e, 0x49fe350a, 0x30999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x75fb0042, - 0xfc30f414, 0x00062cdf, 0xbf62f900, 0xfea3b2ff, 0x99900149, 0x989fa01c, 0xc4b205aa, 0xfd09d6b2, + 0x004c063e, 0x49fe350a, 0x30999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x75fb0042, + 0xfc30f414, 0x0005dcdf, 0xbf62f900, 0xfea3b2ff, 0x99900149, 0x989fa01c, 0xc4b205aa, 0xfd09d6b2, 0xbebcaebf, 0x01ef9220, 0x0cf4f9a6, 0x01af9823, 0xf9a6ff09, 0xb3190bf4, 0xa61600f0, 0x1008f42e, 0xa690c2bc, 0x0808f492, 0x0df49fa6, 0x1802f805, 0x010a1139, 0xb30599c7, 0xb2410094, 0x32aa7e3a, 0x33a53200, 0xbd3300a4, 0x4cb13e14, 0x0241bc00, 0x010006b1, 0x40060df4, 0x3ab20100, 0xb2b061bc, 0x7e0d722c, 0x33004b4a, 0xbc1100a4, 0x10bc2020, 0xf414a610, 0x5a32da08, 0x900149fe, 0x9fbf1c99, - 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40465fb, 0x2cd9fc30, 0xf9000006, 0xfe99bf72, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40465fb, 0xdcd9fc30, 0xf9000005, 0xfe99bf72, 0xff90014f, 0xa0a0b220, 0x05ae98f9, 0xfd02c5b2, 0xf992efbf, 0xf492a601, 0xee98260c, 0xa6ff0101, 0x1c0bf4e1, 0x1900e0b3, 0xa630bfbc, 0x1008f43f, 0xa690c3bc, 0x0808f493, 0x0df49ea6, 0x0e02f80b, 0x4dc33e35, 0x11a91800, 0x99c7010e, 0x009db305, 0xaa7e0096, 0xa4320032, 0x8900ad33, 0xb227b200, @@ -655,20 +655,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x01f99821, 0x0bf496a6, 0x0090b319, 0xb20ab216, 0x35247e1b, 0x00a03300, 0x3e030e0a, 0xb2004dc3, 0x7e1bb20a, 0x32004a98, 0x00a433ae, 0x060f983a, 0x9992f9bf, 0xf497a601, 0xf9981d0c, 0xf496a601, 0x90b3150b, 0x1bb21200, 0x9f7e0ab2, 0xae320035, 0x1300a433, 0x100022b8, 0x1023bc00, 0x08f425a6, - 0xfe4e3289, 0x99900149, 0xd99fbf20, 0x0000062c, 0xea3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0475fb00, - 0xd9fc30f4, 0x0000062c, 0x99bf02f9, 0x90014ffe, 0xb0b204ff, 0xb9bff9a0, 0xa6b0c9bc, 0x1708f4b9, + 0xfe4e3289, 0x99900149, 0xd99fbf20, 0x000005dc, 0xea3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0475fb00, + 0xd9fc30f4, 0x000005dc, 0x99bf02f9, 0x90014ffe, 0xb0b204ff, 0xb9bff9a0, 0xa6b0c9bc, 0x1708f4b9, 0xffffd9e4, 0xa6f09bbc, 0x0b08f4fb, 0xa6010998, 0x050df4f9, 0xdc7202f8, 0xaa7eedb2, 0x49fe0031, - 0x04999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0x2cd112f9, - 0xbf000006, 0x0140fe19, 0xb2080090, 0xb209a0cf, 0x05ab98b9, 0x9cb2deb2, 0xe07efd72, 0x0fbf004d, + 0x04999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, + 0xbf000005, 0x0140fe19, 0xb2080090, 0xb209a0cf, 0x05ab98b9, 0x9cb2deb2, 0xe07efd72, 0x0fbf004d, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0xf0fc0415, 0xf9fc30f4, 0xf430f4f0, 0x90b472f9, 0xfeb0b20d, - 0xbb90014b, 0x01b9b520, 0x00062cd9, 0xfe99bf00, 0xff90014f, 0xa0a5b228, 0xa009bff9, 0x0ce1b0be, + 0xbb90014b, 0x01b9b520, 0x0005dcd9, 0xfe99bf00, 0xff90014f, 0xa0a5b228, 0xa009bff9, 0x0ce1b0be, 0xc9bcd4b2, 0xf439a630, 0xd3bc1f08, 0xf4f3a6f0, 0x09981708, 0xf4f9a601, 0xb6b20f0c, 0x010024bd, 0x273efc07, 0x02f8004f, 0x2c3e0100, 0x42bc004f, 0x0096b192, 0x060df401, 0x90010049, 0xb4bd0399, - 0x4c1497ff, 0x00da0100, 0x7e000012, 0xb2000b94, 0x723bb25a, 0x1200dd1c, 0xaa7e0000, 0xa0320031, - 0x2c00a433, 0x6c986bbf, 0x1200da01, 0x2db20000, 0x7e01004e, 0x330026d8, 0xf80a00a0, 0x4f2c3e02, - 0x3031bc00, 0xa62021bc, 0xa508f424, 0x900149fe, 0x9fbf2899, 0x00062cd9, 0x3299bf00, 0xf4f9a60a, - 0xe97e070b, 0x70fb0042, 0xfc0c30f4, 0x0430f4f0, 0x30f4f4f9, 0x062cdfe4, 0x42f90000, 0x49feffbf, - 0x2c999001, 0x9fa0a1b2, 0x00111ed9, 0x33993f00, 0x3d0a0090, 0x50c13e04, 0xfef4bd00, 0x99900149, + 0x4c1497ff, 0x00da0100, 0x7e000011, 0xb2000b94, 0x723bb25a, 0x1100dd1c, 0xaa7e0000, 0xa0320031, + 0x2c00a433, 0x6c986bbf, 0x1100da01, 0x2db20000, 0x7e01004e, 0x330026d8, 0xf80a00a0, 0x4f2c3e02, + 0x3031bc00, 0xa62021bc, 0xa508f424, 0x900149fe, 0x9fbf2899, 0x0005dcd9, 0x3299bf00, 0xf4f9a60a, + 0xe97e070b, 0x70fb0042, 0xfc0c30f4, 0x0430f4f0, 0x30f4f4f9, 0x05dcdfe4, 0x42f90000, 0x49feffbf, + 0x2c999001, 0x9fa0a1b2, 0x0010e2d9, 0x33993f00, 0x3d0a0090, 0x50c13e04, 0xfef4bd00, 0x99900149, 0x929fa024, 0x9fa00499, 0x98049992, 0xa49805a2, 0x7e9fa006, 0x32002fb6, 0x00a033a0, 0x2ea43308, 0x982bbf6b, 0xb9a60129, 0x013318f5, 0x0fffb9e4, 0x012b1bf5, 0xb20143fe, 0x1c33901a, 0x3db2040c, 0x0031aa7e, 0xa433a032, 0x3fbf4200, 0x4ad93500, 0xa6534646, 0x331bf4f9, 0xed7e1ab2, 0xa4330037, @@ -678,26 +678,26 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0104fdb2, 0x9f090920, 0x1909f920, 0x09010935, 0x01047503, 0xfe020975, 0x1ab20142, 0xb2242290, 0x34937e2c, 0x33a03200, 0xbf5a00a4, 0x7e1ab22b, 0x32002f12, 0x00a433a0, 0x1112184c, 0xb30529c7, 0xfe390094, 0x1ab20143, 0xb2203390, 0x48eb7e3b, 0x00a43300, 0x943fbf15, 0x94f00229, 0x049ffd3c, - 0x35060bf4, 0x1ab22014, 0xfd7eb43d, 0xa0330049, 0xa0320a00, 0x0050c13e, 0x1ed9010f, 0x20000011, - 0x0149fe9f, 0xbf2c9990, 0x062cd99f, 0x99bf0000, 0xf9a60a32, 0x3e110bf4, 0x000050e1, 0x50083e02, - 0x42e97e00, 0x1c45fb00, 0x00062cdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0x982100a0, 0xfd0f06aa, + 0x35060bf4, 0x1ab22014, 0xfd7eb43d, 0xa0330049, 0xa0320a00, 0x0050c13e, 0xe2d9010f, 0x20000010, + 0x0149fe9f, 0xbf2c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x3e110bf4, 0x000050e1, 0x50083e02, + 0x42e97e00, 0x1c45fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0x982100a0, 0xfd0f06aa, 0x9992a9bf, 0xf49fa601, 0xaa98110c, 0xa6ff0901, 0x070bf4a9, 0x0c00a4b3, 0x020a02f8, 0x00516b3e, - 0x0fffb9e4, 0x1bf4020a, 0x2ad4d945, 0x9f980000, 0x51633e04, 0x08f91800, 0x28009033, 0x3309f918, + 0x0fffb9e4, 0x1bf4020a, 0x287cd945, 0x9f980000, 0x51633e04, 0x08f91800, 0x28009033, 0x3309f918, 0x58210090, 0xfe5802f9, 0x0093f003, 0xa60c94b6, 0x0f08f4b9, 0xffffe9e4, 0xa60c94b6, 0x0a0df4b9, - 0xb304ff98, 0xa0d200f4, 0xfe350acf, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xf80430f4, 0xf830f400, 0x00062cdf, 0xbf52f900, 0xfea4b2ff, 0x42fe0149, 0x1c999001, 0xc3b2b0b2, + 0xb304ff98, 0xa0d200f4, 0xfe350acf, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, + 0xf80430f4, 0xf830f400, 0x0005dcdf, 0xbf52f900, 0xfea4b2ff, 0x42fe0149, 0x1c999001, 0xc3b2b0b2, 0x9fa0d5b2, 0x350a14bd, 0x3e182290, 0xb200523c, 0x0c0bb24a, 0x7e2db204, 0x330031aa, 0x008900ad, 0x94b329bf, 0x11900e00, 0x04009020, 0x00523c3e, 0xfd019eb9, 0x008904e9, 0xe9ffff00, 0x0bfcf094, 0xd901f6f0, 0xff00ff00, 0xf094e9ff, 0xb6f00bbc, 0xf0f0d901, 0xe9fff0f0, 0x0bccf094, 0xd901c6f0, 0xcccccccc, 0xf094e9ff, 0xd6f00bdc, 0xaaaad901, 0xf4b6aaaa, 0x03b4b604, 0xb602c4b6, 0xe9fd01d4, 0x0b9cf004, 0xfd0196f0, 0xfbfd05f9, 0x05fcfd05, 0xa005fdfd, 0x101fbc2f, 0x0052423e, 0x0df503a6, - 0x51a0ff71, 0x900149fe, 0x9fbf1c99, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, - 0x2cdffc30, 0xf9000006, 0xb2ffbf42, 0xfec2b2a0, 0xe3b20149, 0xb2149990, 0xb29fa0b4, 0x3ec4bdea, + 0x51a0ff71, 0x900149fe, 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, + 0xdcdffc30, 0xf9000005, 0xb2ffbf42, 0xfec2b2a0, 0xe3b20149, 0xb2149990, 0xb29fa0b4, 0x3ec4bdea, 0xf00052de, 0xf99407e2, 0xf0ffbc03, 0xbcf0f9bc, 0xbe3ff0fe, 0x9030ff92, 0xbab201bb, 0x3030e912, 0x0df40996, 0x00f4b3e1, 0x33010f06, 0x312d64e0, 0xf40064e6, 0xe4330b1c, 0xca3e2862, 0xe0330052, 0xe4330c73, 0xd13e1c77, 0xcfbc0052, 0x52de3ec0, 0x90ffbc00, 0x0052db3e, 0xbc02f994, 0xae3fc0c9, 0x0d00e033, 0xbd01ab90, 0x529a3ef4, 0x20c6b000, 0xf8090df4, 0x54063e02, 0x00d0b300, 0xbfdca006, - 0x90c2bc0f, 0x9fa6ff01, 0x01000cf5, 0x002a9cda, 0x07a99800, 0xbf010098, 0xbc0db29b, 0xaa7eb02b, + 0x90c2bc0f, 0x9fa6ff01, 0x01000cf5, 0x002844da, 0x07a99800, 0xbf010098, 0xbc0db29b, 0xaa7eb02b, 0xa1320031, 0xe400ad33, 0xb242b200, 0xff00440a, 0x0053f73e, 0xc203c994, 0xccbc07be, 0xbcdb3ff0, 0xdd90f0f9, 0xf0febc01, 0xb230fc92, 0x30b912d3, 0xf4099630, 0xc4b3e10d, 0x010c0600, 0xf03e20b2, 0xb0330053, 0xb6315b64, 0x1cf40064, 0x62bd330c, 0x833e0099, 0xb0330053, 0xbd331973, 0x3e008c77, @@ -705,1104 +705,1104 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x53e63e05, 0x01a91800, 0xad90af3f, 0xff94f002, 0xb6fff4f0, 0x9fff0894, 0x53e63ef5, 0x03ad1800, 0x3f02af18, 0x01a918ae, 0xf018d4b6, 0xf4b6fff4, 0xffe4f010, 0xb6ff94f0, 0x9efd0894, 0x059ffd05, 0x90f59dff, 0x0fa004ad, 0x9001cc92, 0xdab20400, 0xcdb302b2, 0x3fff7000, 0x00b0333b, 0x013d900f, - 0x4b3ec4bd, 0xff010053, 0x900149fe, 0x9fbf1499, 0x00062cd9, 0x3299bf00, 0xf4f9a61a, 0xe97e070b, - 0x45fb0042, 0xf830f404, 0x2cd222f9, 0xbf000006, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, + 0x4b3ec4bd, 0xff010053, 0x900149fe, 0x9fbf1499, 0x0005dcd9, 0x3299bf00, 0xf4f9a61a, 0xe97e070b, + 0x45fb0042, 0xf830f404, 0xdcd222f9, 0xbf000005, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, 0xb2d4bd19, 0x0074de0b, 0x5f7e0000, 0x1fbf0052, 0x0a7f29bf, 0x0bf4f9a6, 0x42e97e07, 0x0825fb00, - 0xf9f830f4, 0x062cd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, + 0xf9f830f4, 0x05dcd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, 0x000076de, 0x525f7e00, 0xbf1fbf00, 0xa60abf29, 0x070bf4f9, 0x0042e97e, 0xf40825fb, 0x22f9f830, - 0x00062cd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, - 0x00525f7e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb0042e9, 0x30f40825, 0x062cdff0, 0x62f90000, - 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, 0x1c339000, 0x05242290, 0xbf040402, - 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2a9cda04, + 0x0005dcd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, + 0x00525f7e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb0042e9, 0x30f40825, 0x05dcdff0, 0x62f90000, + 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001304d6, 0x1c339000, 0x05242290, 0xbf040402, + 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2844da04, 0x94330000, 0x527e0a00, 0xa032004f, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, - 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40054ff, 0x2cdff430, 0xf9000006, 0xbdffbf22, - 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0xd4d21499, 0xa000002f, 0x7e01b29f, 0x3e008f2c, - 0x98005592, 0x993f0119, 0x0a099433, 0x2f7e0ab2, 0xc8da003c, 0x7e00002f, 0xb2001475, 0xb22abfad, - 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002fc8, 0x0014b57e, 0x0055923e, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, - 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, - 0x42e97e07, 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, - 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, - 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, - 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, - 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cde00f8, - 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, - 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, - 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, - 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, - 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, + 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40054ff, 0xdcdff430, 0xf9000005, 0xbdffbf22, + 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, 0xa000002d, 0x7e01b29f, 0x3e008efa, + 0x98005592, 0x993f0119, 0x0a099433, 0x2f7e0ab2, 0x70da003c, 0x7e00002d, 0xb2001475, 0xb22abfad, + 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002d70, 0x0014b57e, 0x0055923e, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, + 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, + 0x42e97e07, 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, + 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, + 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, + 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, + 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcde00f8, + 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, + 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, + 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, + 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, + 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, + 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, + 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, - 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, - 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, - 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, - 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x062cdffc, - 0x12f90000, 0x30f4ffbf, 0x0149fed4, 0xa0349990, 0x49ff0f9f, 0x9ff70500, 0x5c997e00, 0x71c67e00, - 0x42ba7e00, 0x5f737e00, 0x00a93300, 0x060f02d6, 0xf7110049, 0x837e009f, 0xed7e005e, 0xb57e005e, - 0xbf7e0061, 0x1f7e005b, 0xb17e0064, 0xe67e0064, 0x657e005c, 0x497e0065, 0x7e7e0066, 0xe27e0066, - 0x387e0066, 0x8e7e0067, 0xe47e0067, 0xc37e0067, 0xb77e0089, 0x847e0068, 0x797e006d, 0x617e0063, - 0x314c0068, 0x00c3f177, 0x01943d00, 0x28913002, 0x30009130, 0x91300891, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x300111b0, 0x10da0c11, 0xdb000006, 0x0000018c, 0x804e010d, 0x71d87e00, - 0x00ad3300, 0x08da023e, 0x0b000014, 0x7e010c04, 0x33006e05, 0x022c00ad, 0xf17ed24c, 0x000000c3, + 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, + 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, + 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, + 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, + 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, + 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x05dcdffc, + 0x12f90000, 0x30f4ffbf, 0x0149fed4, 0xa0349990, 0x49ff0f9f, 0x9ff70500, 0x5c997e00, 0x71b87e00, + 0x42ba7e00, 0x5f737e00, 0x00a93300, 0x060f02d6, 0xf7110049, 0x837e009f, 0xed7e005e, 0xb07e005e, + 0xbf7e0061, 0x1a7e005b, 0xac7e0064, 0xe67e0064, 0x577e005c, 0x3b7e0065, 0x707e0066, 0xd47e0066, + 0x2a7e0066, 0x807e0067, 0xd67e0067, 0x917e0067, 0xa97e0089, 0x767e0068, 0x747e006d, 0x537e0063, + 0x234c0068, 0x00c3f177, 0x01943d00, 0x28913002, 0x30009130, 0x91300891, 0x14913010, 0x30189130, + 0x91301c91, 0x24913020, 0x300111b0, 0xc0da0c11, 0xdb000005, 0x0000018c, 0x804e010d, 0x71ca7e00, + 0x00ad3300, 0x08da023e, 0x0b000013, 0x7e010c04, 0x33006df7, 0x022c00ad, 0xf17ec44c, 0x000000c3, 0x28a13001, 0x3000a130, 0xa13008a1, 0x10a1300c, 0x3014a130, 0xa13018a1, 0x24a13020, 0x000168db, - 0x0101b000, 0x0d1c0130, 0x00804e03, 0x000614da, 0x71d87e00, 0x1400da00, 0x040b0000, 0x057e080c, - 0xad33006e, 0x4c01dd00, 0xc3f18863, 0x44db0000, 0x30000001, 0xa13028a1, 0x10a13000, 0x3014a130, - 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x0618da00, 0xd87e0000, - 0x24da0071, 0x0b000014, 0x7e080c04, 0x33006e05, 0x019000ad, 0xf155534c, 0xdb0000c3, 0x00000120, + 0x0101b000, 0x0d1c0130, 0x00804e03, 0x0005c4da, 0x71ca7e00, 0x1300da00, 0x040b0000, 0xf77e080c, + 0xad33006d, 0x4c01dd00, 0xc3f18855, 0x44db0000, 0x30000001, 0xa13028a1, 0x10a13000, 0x3014a130, + 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05c8da00, 0xca7e0000, + 0x20da0071, 0x0b000013, 0x7e080c04, 0x33006df7, 0x019000ad, 0xf155534c, 0xdb0000c3, 0x00000120, 0x3028a130, 0xa13000a1, 0x14a13010, 0x3018a130, 0xa13020a1, 0x0101b024, 0x30081130, 0x01300c11, - 0x4e070d1c, 0x1cda0100, 0x7e000006, 0xda0071d8, 0x00002fd4, 0x080c1bb2, 0x006e057e, 0x4300ad33, + 0x4e070d1c, 0xccda0100, 0x7e000005, 0xda0071ca, 0x00002d7c, 0x080c1bb2, 0x006df77e, 0x4300ad33, 0x54d64c01, 0x0000c3f1, 0x0000fcdb, 0x28a13000, 0x3000a130, 0xa13010a1, 0x18a13014, 0x3020a130, - 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x00000620, 0x0071d87e, 0x001404da, - 0x0c040b00, 0x6e057e08, 0x00ad3300, 0xf64c00f6, 0x00c3f18a, 0x00d8db00, 0xa1300000, 0x00a13028, + 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x0071ca7e, 0x001304da, + 0x0c040b00, 0x6df77e08, 0x00ad3300, 0xc44c00f6, 0x00c3f18a, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x000624da, 0x71d87e00, 0x142cda00, 0x040b0000, 0x057e080c, 0xad33006e, 0x4c00a900, 0xc3f1dabf, + 0x0005d4da, 0x71ca7e00, 0x1328da00, 0x040b0000, 0xf77e080c, 0xad33006d, 0x4c00a900, 0xc3f1da8d, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, - 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x0628da00, 0xd87e0000, 0x20da0071, 0x0b000014, 0x7e080c04, - 0x33006e05, 0x7e5c00a4, 0x7e007165, 0x7e005c75, 0x7e006dff, 0x7e000a74, 0x7e004747, 0x7e00645a, - 0x7e005c17, 0x7e005d1b, 0x7e0063ae, 0x7e0063de, 0x7e0066b3, 0x7e006717, 0x7e00676d, 0x7e0067c3, - 0x7e006840, 0x7e006896, 0x7e006dc9, 0x7e008989, 0x7e0068ec, 0x7e005eb8, 0x33006e7c, 0xf80600a0, - 0x0149fe02, 0xbf349990, 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0x2d8eda9a, 0xf9980000, 0xbf95f90c, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, + 0x22f9fc30, 0x00130cd0, 0x05dcd200, 0x0abf0000, 0xff0b29bf, 0xb80141fe, 0x0008b8aa, 0xa00c1190, + 0x1cb17e19, 0x0b0abf00, 0xbcaab8ff, 0xb17e0008, 0x0abf001c, 0xaab8ff0b, 0x7e0008c0, 0xbf001cb1, + 0xb8ff0b0a, 0x0008c4aa, 0x001cb17e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001cb1, 0x0000db0a, + 0xaab80100, 0x7e0008a8, 0xbf001cb1, 0xffffdb0a, 0xaab80e03, 0x7e0008e0, 0xbf001cb1, 0x0000db0a, + 0xaab8ce00, 0x7e0008b4, 0xbf001cb1, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0x12f9fc30, + 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x2d8fda08, 0x09a00000, 0x001330d9, 0x9899bf00, 0x95f90799, + 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, + 0x90da0800, 0xa000002d, 0x1330d909, 0x99bf0000, 0xf9099998, 0xbf0fbf95, 0xf4f9a619, 0xe97e070b, + 0x15fb0042, 0x05dcde04, 0xe9bf0000, 0xfefc30f4, 0x38dd014f, 0xa0000028, 0xbffcbff9, 0xa0ff09ef, + 0xb50f09d9, 0xcfa601d9, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, + 0x900140fe, 0x91da0800, 0xa000002d, 0x1330d909, 0x99bf0000, 0xf90a9998, 0xbf0fbf95, 0xf4f9a619, + 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xfebf0000, 0xfefc30f4, 0x9ea00149, 0xf9bf9ebf, 0x0bf4e9a6, + 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, 0x000005dc, 0x40fe19bf, 0x08009001, 0x002d92da, + 0xd909a000, 0x00001330, 0x999899bf, 0xbf95f904, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, + 0x000005dc, 0x30f4febf, 0x0149fefc, 0x9ebf9ea0, 0xe9a6f9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, + 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, 0x93da0800, 0xa000002d, 0x1330d909, 0x99bf0000, + 0xf9039998, 0xbf0fbf95, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xfebf0000, 0xfefc30f4, + 0x9ea00149, 0xf9bf9ebf, 0x0bf4e9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, 0x000005dc, + 0x40fe19bf, 0x08009001, 0x002878da, 0xd909a000, 0x00001330, 0x999899bf, 0xdf95f90f, 0x00002870, + 0x1ebf0dbf, 0x002844d9, 0x069fb500, 0x002868df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, + 0xb5320f08, 0xdea6039f, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, 0xbf000005, 0xfc30f4fe, 0xa00149fe, + 0xbf9ebf9e, 0xf4e9a6f9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, + 0x00900140, 0x2d94da08, 0x09a00000, 0x001330d9, 0x9899bf00, 0x95f90699, 0x19bf0fbf, 0x0bf4f9a6, + 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4febf00, 0x49fefc30, 0xbf9ea001, 0xa6f9bf9e, 0x070bf4e9, + 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd112f9, 0xbf000005, 0x0140fe19, 0xda080090, 0x00002898, + 0x30d909a0, 0xbf000013, 0x01999899, 0x0fbf95f9, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f50415, + 0xdcdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001c22, 0x7e080aa0, + 0xd9001c22, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0x417e040c, + 0xa4b20040, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, 0x00002890, + 0x90014ffe, 0x44dae8ff, 0xb5000028, 0xb67e019f, 0xa232002f, 0x0900a033, 0x112ead33, 0x2844d903, + 0x99980000, 0x2890de07, 0x9fbf0000, 0xbb019998, 0xe9a0029f, 0x9b0099b3, 0x75499800, 0x8b009db3, + 0x0143fe00, 0x14bde5b2, 0xd6aa5547, 0x52494350, 0x3ea83390, 0xda0069fd, 0x00002890, 0x257e1bb2, + 0xa7660054, 0xda561bf4, 0x00002890, 0x7e181b90, 0xbf005425, 0x00a3f059, 0x9000a1bc, 0xf9a61c0f, + 0xda3a18f4, 0x00002890, 0x607e0bb2, 0xa6a60054, 0xb22a1bf4, 0x2890da0c, 0x3bb20000, 0x7aded4bd, + 0x7e000000, 0x3300525f, 0x982800a4, 0x9eb30139, 0xb50c10de, 0x073e7541, 0x1190006a, 0x9259bf01, + 0x19a63499, 0x989308f4, 0x99b37549, 0x33025f00, 0x025a002d, 0xb3744998, 0x0110009d, 0xb3754298, + 0x3e740024, 0xda006c69, 0x00002890, 0x257e2bb2, 0xa8660054, 0xda511bf4, 0x00002890, 0x7e022b90, + 0xa6005460, 0x401bf4a7, 0xda7442b5, 0x00002890, 0xbd082b90, 0x549b7e04, 0xc414bd00, 0x773effa3, + 0x02bc006a, 0x2890dab0, 0x00900000, 0x549b7e01, 0xffa4f000, 0xa6101abc, 0xe908f403, 0x09001033, + 0xa00156b5, 0x74499856, 0x240094b3, 0x3e012290, 0xd5006aa1, 0x00002890, 0x87b8ff48, 0xbd544942, + 0x9259bf64, 0x29a60399, 0xff7f08f5, 0xb3744c98, 0x027800cd, 0x006c693e, 0x98043b98, 0x30987449, + 0xff1ac403, 0x7e0009bc, 0xb20016fc, 0x000abc2b, 0x0cb2d4bd, 0x002890da, 0x0087de00, 0x5f7e0000, + 0xad330052, 0xbf018700, 0x754f9829, 0xb3032c98, 0xbc2a4994, 0x90dac0cf, 0xb2000028, 0xded4bd5b, + 0x0000008c, 0x00525f7e, 0x6100ad33, 0x0e5f9801, 0xbc754998, 0x49b5909f, 0x01111076, 0xc4053f98, + 0x9fa6ff19, 0x989408f4, 0x19b37641, 0xda013f00, 0x00002890, 0x9b7e1bb2, 0xad330054, 0xda012f02, + 0x00002890, 0x7e011b90, 0x3300549b, 0x011e08ad, 0xda0140fe, 0x00002890, 0xb27c0090, 0xbd0bb21c, + 0x0090ded4, 0x5f7e0000, 0xad330052, 0x9800ff00, 0x56b00505, 0x050df424, 0x49fe2405, 0x7c999001, + 0x98029e98, 0x40b2019f, 0x24bd94bd, 0xb5f01fbc, 0x41fe7049, 0x30febc01, 0x3e601190, 0xda006be8, + 0x00002890, 0x3cb21bb2, 0x95ded4bd, 0x7e000000, 0x3300525f, 0x3f3d00a4, 0x07339019, 0x20012290, + 0x04191809, 0x18010935, 0x09350819, 0x0c191802, 0x18030935, 0x09351019, 0x14191804, 0x18050935, + 0x09351819, 0x07009006, 0x08f425a6, 0x7042b5b5, 0xb0704198, 0x0cf42416, 0x3d24bd0b, 0x6c153e04, + 0x10004900, 0x0f0091f7, 0x1100490a, 0xf8009ff7, 0xbd043d02, 0x3e34bd24, 0x98006c5d, 0x9e94714f, + 0x02e9bb03, 0xb609f994, 0x9fbb06f4, 0xe0e9bc02, 0xb3904ebc, 0x3c270090, 0x94f0984e, 0x00903302, + 0xbd010a1d, 0xff0cc4b4, 0x0042667e, 0xff953bff, 0x9fb2a52a, 0xe2b2aeb2, 0x0010f3b2, 0xff09c401, + 0x08f491a6, 0x6c6d3eb9, 0xbd24bd00, 0x90008934, 0x0099ce00, 0xf50194f0, 0xbd00e10b, 0x3ef70544, + 0xc4006d1c, 0x0bf50129, 0xc4bd008d, 0x4bb2d4bd, 0x6b7e080a, 0xa0b20024, 0x0608a1b8, 0x7e1ab200, + 0xe5001c22, 0xb28000ab, 0x1cb17e1a, 0x2001b800, 0x1ab20006, 0x001c227e, 0xb204abc5, 0x1cb17e1a, + 0x0001b800, 0x1ab20006, 0x001c227e, 0x8000abe5, 0xb17e1ab2, 0x01b8001c, 0xb2000618, 0x1c227e1a, + 0xb4a5ff00, 0xb17e1ab2, 0x01b8001c, 0xb2000604, 0x1c227e1a, 0x00abe500, 0x7e1ab280, 0xb8001cb1, + 0x00061c00, 0x227e0ab2, 0xabc5001c, 0x7e0ab204, 0x90001cb1, 0x33950144, 0x01229d01, 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0x48fe5499, 0xfe9fa001, 0x99920144, + 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000013, + 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, + 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x18007f43, 0x0b98050a, 0x78e27e02, 0x3ea13200, + 0x18007fb1, 0x2b320801, 0x817e0ab2, 0x040f000f, 0x45354320, 0x024f3503, 0x0c001033, 0x7e011433, + 0x007f863e, 0xb2020998, 0xa07bb24a, 0x08099079, 0xb5019f98, 0x9f98017f, 0x027fb502, 0xb5039998, + 0xa43e0379, 0x0f98007f, 0x08099002, 0x6bb24ab2, 0x9f986fa0, 0x016fb501, 0xb5029f98, 0x9998026f, + 0x0369b503, 0x49351409, 0x0f617e01, 0x7efa3e00, 0x320ab200, 0x0f817e2b, 0x3d050f00, 0x358f2094, + 0x00180289, 0xb2040f03, 0x018f358a, 0xbd038035, 0x0f717eb4, 0x00193300, 0x02f8ff25, 0x007efa3e, + 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0xb02c02b0, 0x0cf402b6, 0x01b4b30b, 0x800f3e10, + 0x03b0b300, 0x04b0b32d, 0x3e020e3f, 0xbf008051, 0x8fe43da9, 0x3e0c0000, 0xbf00803d, 0xffff8fa9, + 0xfde43df3, 0x008f049f, 0x3d3e0800, 0xa9bf0080, 0xf3ffff8f, 0x9ffde43d, 0x00008f04, 0x059ffd04, + 0x00804f3e, 0xff8fa9bf, 0xe43df3ff, 0xa0049ffd, 0x0149fea9, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, + 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd252f9, 0xbf000005, 0xb2b3b229, 0xb2d5b2c4, + 0x0141fea0, 0x0880008a, 0xa0181190, 0x1c227e19, 0xb60a6000, 0x3a6010a5, 0x08802c8a, 0x001c227e, + 0xa5b64a60, 0xbf5a6010, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40455fb, 0x22f9fc30, 0x0005dcd1, + 0xb219bf00, 0x0140fea2, 0x08d5008a, 0xa00c0090, 0x1c227e09, 0xf00fbf00, 0x2aa000a3, 0xf9a619bf, + 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0xd122f9fc, 0x000005dc, 0xa2b219bf, 0x8a0140fe, 0x9008d540, + 0x09a00c00, 0x001c227e, 0xa3f00fbf, 0xbf2aa000, 0xf4f9a619, 0xe97e070b, 0x25fb0042, 0xfc30f404, + 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x808a0140, 0x009008d5, 0x7e09a00c, 0xbf001c22, 0x00a3f00f, + 0x19bf2aa0, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, + 0xd5808a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, + 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, 0xd6408a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, + 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, + 0x88548a01, 0x0c009008, 0x227e09a0, 0x0fbf001c, 0xa000a3f0, 0xa619bf2a, 0x070bf4f9, 0x0042e97e, + 0xf40425fb, 0x42f9fc30, 0x0005dcd1, 0xb219bf00, 0xb2b2b2a3, 0x0140fec4, 0x0884ac8a, 0xa0140090, + 0x1c227e09, 0xe8a9c700, 0xa9c729a0, 0xb639a0f0, 0x4aa018a5, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, + 0x0445fb00, 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0xa0b20899, 0xb1b29fa0, 0x0880888a, + 0x001c227e, 0xb370a9c7, 0xb01a0290, 0x0cf40296, 0x0194b30b, 0x82613e1d, 0x0390b300, 0x0494b308, + 0xc709a011, 0xa4b3b4aa, 0x9a3e1004, 0x94bd0082, 0xb43e09a0, 0xa6b00082, 0x0f0cf404, 0x1801a0b3, + 0x3002a4b3, 0x0082943e, 0x1808a0b3, 0x2410a4b3, 0x0082aa3e, 0xa43e1aa0, 0x03090082, 0x0082a23e, + 0x19a00409, 0xb63ea43d, 0x05090082, 0x0082a23e, 0x19a094bd, 0x49feff0a, 0x08999001, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, + 0xb2049990, 0x8a9fa0a0, 0x7e088088, 0xc7001c22, 0xa0b370aa, 0xa6b01a02, 0x0b0cf402, 0x1801a4b3, + 0x00830c3e, 0x0803a0b3, 0x0c04a4b3, 0xa43d0aa0, 0x00831a3e, 0xff0a94bd, 0x49fe09a0, 0x04999001, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, + 0x0140fe19, 0x08c0408a, 0xa0080090, 0x1c227e09, 0xbf0fbf00, 0x1fa4f019, 0xa60bacf0, 0x070bf4f9, + 0x0042e97e, 0xd90415fb, 0x000005dc, 0x30f499bf, 0x014ffefc, 0x357ef9a0, 0xa4330083, 0xa4bd0a00, + 0x00838f3e, 0x08d32c8a, 0x001c227e, 0xfe12aac7, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd222f9, 0xbf000005, 0xfea0b229, 0x008a0141, 0x119008d1, + 0x7e19a00c, 0x89001c22, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1cb17eb5, 0xbf1fbf00, + 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0xdcdff830, 0xf9000005, 0xfeffbf62, 0x99900149, + 0xb29c201f, 0x01999096, 0x9fa0a432, 0xb2c4d3b2, 0x7e080aff, 0xd9001c22, 0x40000000, 0x010504bd, + 0x3e14a9ff, 0xbc008451, 0x5abca002, 0x83a97ea4, 0x0014b300, 0x449dda1d, 0x6bb20000, 0xa97e3cb2, + 0xa4330015, 0x09f80c00, 0x583e040a, 0x00900084, 0xf4402601, 0xa43dd40c, 0x900149fe, 0x9fbf2099, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40865fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, + 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001cb1, 0x00008367, 0x00dcb4bd, 0x7e01312d, + 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x82d17e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, + 0x3e0e050b, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x15fb0042, + 0xfc30f408, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb29fa0b0, 0xd1008aa1, 0x1c227e08, + 0x00008900, 0xff04f1ff, 0xb4a9ffff, 0x08d1008a, 0x7eb50bff, 0x8a001cb1, 0xf108d170, 0xdb03ff14, + 0xc0000000, 0xff1014b6, 0xb17eb51b, 0x748a001c, 0x227e08d1, 0x0089001c, 0xa3f00201, 0x009af700, + 0x900149fe, 0x9fbf0899, 0x0005dcd9, 0x3d99bf00, 0xf4f9a6a4, 0xe97e070b, 0x15fb0042, 0xfc30f404, + 0xdcd232f9, 0xbf000005, 0x32c13229, 0xd1708ab0, 0x0000db08, 0x43fec229, 0x10339001, 0xb17e39a0, + 0x748a001c, 0x227e08d1, 0xa4f1001c, 0x02dbfff8, 0xffa22900, 0x708ab5ab, 0xb17e08d1, 0x04f0001c, + 0x0f14f0ff, 0x940c0994, 0x94f1081f, 0x708affff, 0x04b608d1, 0x0000db04, 0x04f0a22a, 0x0509fdff, + 0xfd0501fd, 0x0bff050f, 0x1cb17eb5, 0xbf3fbf00, 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40435fb, + 0x72f9d430, 0xfe15f0b4, 0x99900149, 0xb5a23220, 0xf0b4019f, 0x32b43214, 0xa0d632c5, 0x05dcdf9f, + 0xffbf0000, 0xb2289990, 0xb39fa0e3, 0x3d0a00e4, 0x872d3e24, 0x3dff0000, 0x32f4bd14, 0x953fbc0e, + 0xf40194f0, 0x0e260d0b, 0x32051bf4, 0x011110f0, 0xb301ff90, 0x30ea10f4, 0x0cf41016, 0xff1fc412, + 0xbcff09c4, 0x76b070f9, 0x0b0df410, 0x020209f8, 0x00872d3e, 0xa97e3ab2, 0x5c320083, 0x4b326d32, + 0x5d7e2a32, 0x3ab20085, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xffff7f49, 0x148ab4a9, 0xb17e08d1, + 0x1a32001c, 0xc43d0b32, 0xef7e640d, 0xa2320083, 0x9d00ad33, 0x7e3ab200, 0x8a0083a9, 0x7e08d114, + 0xe5001c22, 0x8a4080ab, 0x7e08d114, 0x32001cb1, 0x0c0b321a, 0x25a08d01, 0x83ef7e26, 0x33a23200, + 0xb26e00a4, 0x83a97e3a, 0xd1148a00, 0x1c227e08, 0xbf7f4900, 0xff0143fe, 0x0132b4a9, 0x08d1148a, + 0x7e283390, 0x04001cb1, 0x870a3e01, 0xa440bc00, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xb69000bc, + 0x39bc10a5, 0x01111090, 0x10c49a60, 0xf407a6ff, 0x49fede1e, 0x20999001, 0xbf019c98, 0xbd3ab29b, + 0x7e200ed4, 0x330026d8, 0xf80600a0, 0x0149fe02, 0xbf489990, 0x05dcd99f, 0x99bf0000, 0xf9a62a32, + 0x7e070bf4, 0xfb0042e9, 0x30f42c75, 0x05dcd9e8, 0x52f90000, 0x4ffe99bf, 0x2cff9001, 0xf9a0a2b2, + 0x08b8c08a, 0x001c227e, 0xc08aa5b2, 0x5bc508b8, 0x1cb17e04, 0x8335da00, 0xb4bd0000, 0x030d408c, + 0xa97e0400, 0xa9330015, 0x8a00a800, 0x7e08c040, 0xfe001c22, 0x2bb20141, 0xa0281190, 0x7e1ab21a, + 0x32007fe0, 0x00ad33a0, 0x19bf0089, 0x13b2f00f, 0xfd014afe, 0x95f0049f, 0x18aa9001, 0xa4b219a0, + 0xfaf07fd1, 0x15817e02, 0xb23abf00, 0x84737e2b, 0x33a03200, 0xb2213ea4, 0x159c7e4a, 0xf4a1a600, + 0x3abfea0d, 0x737e2bb2, 0xa4330084, 0x0400df3e, 0x0087f83e, 0x3a00a033, 0x900149fe, 0x99bf2899, + 0xfe0141fe, 0x11900142, 0x20229024, 0x2ab219a0, 0x0082d17e, 0x1a00a433, 0x1ab22bbf, 0x007fe07e, + 0x0e00a433, 0x408a1bbf, 0xb17e08c0, 0xc08a001c, 0x5bb208b8, 0x001cb17e, 0x900149fe, 0x9fbf2c99, + 0x0005dcd9, 0x3299bf00, 0xf4f9a60a, 0xe97e070b, 0x55fb0042, 0xdc30f418, 0x0005dcdf, 0xbf82f900, + 0xf830f4ff, 0x900149fe, 0x9fa04c99, 0x920140fe, 0xf4bd0c99, 0xfe2c0090, 0x93b20142, 0xa0019fb5, + 0x1320d89f, 0x22900000, 0x06020748, 0x0c059004, 0x3bb28abf, 0xff0d080c, 0x0000c17e, 0xf400a433, + 0x3f013198, 0x0a943319, 0x011998eb, 0x18041f18, 0x09a00134, 0x98041990, 0x0eb5019e, 0x029e9801, + 0x98020eb5, 0x0eb5039e, 0x04999803, 0x330409b5, 0x302a01f0, 0x08f401f6, 0x02f0330f, 0x03f4332e, + 0x89123eb3, 0x010a1800, 0x18030b18, 0x0d18020c, 0x855d7e04, 0x89303e00, 0x010a9800, 0x7e020b98, + 0x3e0084e1, 0x98008930, 0x4a7e010a, 0x303e0087, 0x59bf0089, 0x18010a18, 0x0c18030b, 0x040d1802, + 0xb0020e98, 0x59980091, 0x0191b001, 0x0085df7e, 0x6000ad33, 0x022a35ff, 0x1e182720, 0xb24b3203, + 0x0126351a, 0x7e032e35, 0xb2000f81, 0x7eb4bd2a, 0x3e000f71, 0xd9008890, 0x000005d4, 0xf9fc30f4, + 0x05dcd112, 0x9abf0000, 0x10db19bf, 0x0c000013, 0x0140fe01, 0xa0080090, 0x72e57e09, 0x89cc7e00, + 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0x0140fe19, + 0xda080090, 0x00002d8d, 0x30d909a0, 0xbf000013, 0x20943d9f, 0x02f998a9, 0x0fbf95f9, 0xa43d19bf, + 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, 0x09a00800, + 0x0046257e, 0x0044d87e, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xd9f430f4, 0x000005dc, + 0x99bf22f9, 0xfefc30f4, 0x4ffe0140, 0x10009001, 0xa018ff90, 0x010db50c, 0xb2b2a1b2, 0x637ef9a0, + 0xff0e0048, 0x1e00a033, 0xda010998, 0x00002844, 0x2db21cb2, 0xbf0091b0, 0x07ab980e, 0x004e6e7e, + 0x49feae32, 0x18999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x0042e97e, 0xfb0430f4, + 0xdcdf0c25, 0xbf000005, 0xf030f4ff, 0x900149fe, 0x9fa00c99, 0x002844d9, 0x079f9800, 0xa00149fe, + 0x019bb59a, 0xff98febf, 0x08999001, 0xd4bdbcb2, 0xb202febb, 0xb29fa0ab, 0x7e040e9a, 0x330026d8, + 0xf80800a0, 0xfe010a02, 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, + 0x00f81030, 0xd9c030f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0x46fe60ff, 0xbdf9a001, 0x2c669094, + 0xb01691b0, 0x44fe1591, 0x0148fe01, 0x90046990, 0x88904044, 0x0991b05c, 0x008c423e, 0x3f1650b4, + 0x0b9d3359, 0x5e980141, 0x045f1801, 0xa0045990, 0x55e0344e, 0x982be130, 0x4eb5019e, 0x029e9801, + 0x98024eb5, 0x4eb5039e, 0x04999803, 0x330449b5, 0x302d01f0, 0x08f401f6, 0x02fd330c, 0x7c3e0107, + 0x4998008b, 0x014a9802, 0xb40269b5, 0x6ab509e0, 0x01eb9801, 0x008a627e, 0x008c133e, 0x98024998, + 0x4b98014c, 0x034a9804, 0xb40269b5, 0x6cb509e0, 0x01ed9801, 0x0089f87e, 0x008c133e, 0x98014018, + 0x41980242, 0x07435801, 0xda0c4718, 0x00002e00, 0x004cb4bd, 0x0b947e02, 0x01043300, 0xff7bc431, + 0xffff3ce4, 0x002e00da, 0x0b947e00, 0xb51bb200, 0x61b50262, 0xe42cb201, 0xbdffff3e, 0x2e00dad4, + 0xd87e0000, 0x173e0026, 0x2cb2008c, 0xb50262b5, 0x1bb20161, 0xffff3ee4, 0x002e00da, 0x7ed4bd00, + 0xe4002672, 0xbdffff3c, 0x2e00def4, 0xfebc0000, 0xf4fca690, 0x993f0e18, 0x0bf49726, 0x8c403e0d, + 0x33993f00, 0x903d0094, 0xfeb301ff, 0x3edf0200, 0x33008c17, 0x092d00a4, 0x20e43d02, 0x028e3589, + 0x182bb034, 0x040e0359, 0x8e355ab2, 0x03893501, 0x000f817e, 0xb4bd8ab2, 0x000f717e, 0x008c423e, + 0x10da02f8, 0x7e000013, 0xd9001475, 0x00001328, 0x9abfadb2, 0x0c014bfe, 0x54bb9008, 0x0000c17e, + 0x9c00a933, 0x1310dafe, 0xb57e0000, 0x423e0014, 0x30f4008c, 0x05dcdffc, 0x22f90000, 0x00130cd1, + 0xbfffbf00, 0x0149fe1e, 0xb20c9990, 0xb89fa0a2, 0x0004e8ea, 0x001c227e, 0x1abfa0b2, 0xb80104f0, + 0x0004e0aa, 0x001c227e, 0x04b30109, 0xa9c70700, 0xfe292018, 0x99900149, 0xd99fbf0c, 0x000005dc, + 0xf9a699bf, 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0x130cd9fc, 0x22f90000, 0xa2b299bf, 0x0005dcd1, + 0x0140fe00, 0x05109ab8, 0x9019bf00, 0x09a00c00, 0x001c227e, 0xaac70fbf, 0xbf2aa0f3, 0xf4f9a619, + 0xe97e070b, 0x25fb0042, 0xfc30f404, 0x00130cd9, 0xbf42f900, 0xd1a2b299, 0x000005dc, 0x9ab8b3b2, + 0xbf000510, 0xfec4b219, 0x00900140, 0x7e09a014, 0xc7001c22, 0x296049a9, 0x6046a9c7, 0x81aac739, + 0x0fbf4a60, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40445, 0xd142f9ec, 0x0000130c, 0xa4b219bf, + 0x0005dcd3, 0x0142fe00, 0x05009ab8, 0x9039bf00, 0x40fe2422, 0x14009001, 0x227e29a0, 0x19bf001c, + 0x9ab80aa0, 0x7e000504, 0xbf001c22, 0x010ab519, 0x05089ab8, 0x1c227e00, 0xb519bf00, 0x9ab8020a, + 0x7e00050c, 0xb2001c22, 0x030ab50b, 0x4ab2100c, 0x000b7e7e, 0x39bf2fbf, 0x0bf4f9a6, 0x42e97e07, + 0x1445fb00, 0xdff030f4, 0x000005dc, 0x0cd022f9, 0xbf000013, 0xfe0ebfff, 0x99900149, 0xa0a2b218, + 0xf8eab89f, 0x227e0004, 0xa9b2001c, 0x9e950abf, 0x089d9418, 0xb6189f94, 0x94f10895, 0xfefdff00, + 0x05f9fd05, 0xff0000d9, 0x04d9fd00, 0xfe05fdfd, 0xaab80141, 0x900004fc, 0x40fe0c11, 0x901fa001, + 0x0fa01400, 0x001c227e, 0x1ab52eb2, 0xdbd4bd01, 0x000000a1, 0x0d3c2e01, 0x02e135f8, 0xdc01dd90, + 0x000000a1, 0xc70ff9c4, 0xb93c64ff, 0xf8bf3c98, 0x2001e935, 0x03ee90ef, 0xde04d4b3, 0x3c0fa9c4, + 0x293598c9, 0x64a9c70d, 0x3598c93c, 0x49fe0c29, 0x18999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0xe97e070b, 0x25fb0042, 0xfc30f410, 0xdcd222f9, 0xbf000005, 0x28ccdb29, 0xcedc0000, 0xdd000028, + 0x000028d0, 0x0028cada, 0x0141fe00, 0xa00c1190, 0x806d7e19, 0x289cd000, 0x09980000, 0x28bcda01, + 0x95f10000, 0x09b51e00, 0x8dc47e01, 0x01099800, 0x0028d2da, 0x0095f100, 0x0109b501, 0x008d527e, + 0xbf010998, 0xf12fbf1e, 0xb5200095, 0xefa60109, 0x7e070bf4, 0xfb0042e9, 0x9cde0425, 0xf4000028, + 0x12f9fc30, 0xbf04e998, 0x01ec98ed, 0xf002ef98, 0xe9b5c095, 0x0001d904, 0xd9fd3400, 0x0000d905, + 0xc9fd4c40, 0xd1e30905, 0x000005dc, 0xbf04f9fd, 0xf0fe091b, 0xf9fd04f5, 0x5000d904, 0xf9fd00c7, + 0x35050905, 0xff0914e9, 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0x9efd10f4, + 0x18d4b605, 0xfd05f9fd, 0x0bf505df, 0x0505045e, 0xf503d6b0, 0xb5045d0c, 0xd4b3013d, 0x00490e01, + 0x0239b550, 0x00d2b23e, 0x18080d18, 0x0f180909, 0x0b0e180a, 0xf0ffd4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xe4b6059d, 0x05f9fd18, 0xb505effd, 0x3ab2023e, 0x237e0bb2, 0x3a9800c6, 0xa6ff0902, + 0x091bf4a9, 0xc83e04bd, 0xa5b600d6, 0x303b9007, 0x7e033ab5, 0xb200d88f, 0x00adb3a5, 0x3b9803f5, + 0x90c00903, 0xbb90343a, 0x04b9fd3f, 0x7e03b5b6, 0xb200da25, 0x00adb3a5, 0x47fe03d9, 0x0148fe01, + 0xbd407790, 0x01799044, 0xb03c8890, 0x223e0991, 0xe4bd00d4, 0x44b38ea0, 0x3a980f00, 0x0cb4bd0c, + 0xd3453efe, 0xb23ab200, 0x7e7cb24b, 0xb200c4b8, 0x00adb3a5, 0x793f039d, 0xf40194f0, 0x3a98120b, + 0x0c4bb20c, 0xd7977eff, 0xd41f3e00, 0x7e7ab200, 0xb300c1c9, 0x980f00a0, 0x4bb20c3a, 0x453efd0c, + 0x793f00d3, 0xf40294f0, 0x3a980e1b, 0x0c4bb20c, 0xd4143efd, 0x09b0b400, 0x010c3ab2, 0x9d7e8db2, + 0xa0b300c6, 0x793f5d00, 0x24bd3fb2, 0x900299c7, 0x91b00199, 0x54f5980a, 0x390054b3, 0xbc09b0b4, + 0x030c0022, 0xb60002bc, 0x01b80304, 0xbc000140, 0x1ab21031, 0x00d9fd7e, 0xb80030bc, 0x00014309, + 0x02b59520, 0x0af0b453, 0xa0540fb5, 0xd3df3e81, 0x01229000, 0xb318ff90, 0x3ebe1424, 0xbf00d70c, + 0x58793f8e, 0x7d18027f, 0x03ee9807, 0xc70d3a98, 0xf3f00299, 0x70ffcc00, 0xb21f96cb, 0xd8e6cb4b, + 0xd6cb010c, 0xe0f6ebf0, 0xc0f27e01, 0x0c3a9800, 0x6cb24bb2, 0x00d7977e, 0xadb3a5b2, 0x9002b400, + 0x3b980144, 0xf54ba603, 0xbdfeeb08, 0xb0bbbc94, 0x8ab289a0, 0x00da597e, 0xadb3a5b2, 0xb2029400, + 0x9884bd37, 0x88bc547f, 0x9098bc90, 0xb80394b6, 0x00014099, 0xb09039bc, 0xf9b30b91, 0x98025300, + 0xa0b4033c, 0xbdb43d0f, 0xc0ccbc24, 0xd27e44bd, 0x60b400d9, 0xd53d3e0f, 0x0d3a9800, 0x41b02bb2, + 0xc1467e0c, 0x00a93300, 0x3a9800b5, 0x014cfe0c, 0xcc902bb2, 0xd7597e38, 0x00adb300, 0xe0b4020c, + 0x0e90b40b, 0xc703ef98, 0x9fa6d899, 0x008e1bf5, 0xb20d3a98, 0x7e010c2b, 0xfe00c11c, 0x3ab2014c, + 0xcc902bb2, 0xc4fc7e30, 0x06a4b300, 0x0c3a9813, 0xfd0c2bb2, 0x00d7977e, 0x00d53a3e, 0xcb00adb3, + 0x1c907401, 0xbc0093f0, 0x69bc9099, 0xe4017f00, 0xf4ffff19, 0x0260091b, 0x00d53a3e, 0xfe0c3a98, + 0x1be4014c, 0xcc90ffff, 0xd7597e34, 0x00adb300, 0xf0340198, 0x3690343a, 0x0df4f926, 0xe4026010, + 0x98ffff1b, 0x2f3e0c3a, 0x3a9800d5, 0x0c2bb20c, 0xd7977efd, 0x00adb300, 0x22900170, 0x033a9801, + 0x08f52aa6, 0x64b2ff37, 0xb43d6eb2, 0xf4bdd43d, 0x713ec4bd, 0xe97f00d5, 0x0a009473, 0x6b3e010d, + 0xd03300d5, 0x010b0600, 0x9001cc90, 0xee9001ff, 0xf4faa602, 0xc4b3e308, 0x7cb50b00, 0xd6ad3e54, + 0x00b93300, 0x399800a6, 0x0296b001, 0x09300cf4, 0xb56db203, 0xe4bd5479, 0xb03ef4bd, 0xd97f00d5, + 0x0a009073, 0x90f9697c, 0xee9001ff, 0x02dd9001, 0xa6033998, 0xe908f4e9, 0x00d6273e, 0xf10b94bd, + 0xbd5479b5, 0x3eb1b224, 0x7f00d601, 0xff09e440, 0x260bf4ff, 0xbfa6f10f, 0xe40b1bf4, 0x3effff0b, + 0x9800d5f9, 0x0ce40c3a, 0x977effff, 0xadb300d7, 0xe400b900, 0xb2ffff0b, 0x01229019, 0xb2024490, + 0x03399891, 0x08f429a6, 0xa6f109c5, 0xa00bf5b9, 0x0c3a9800, 0x7e0a3c98, 0xb300d797, 0x008c00ad, + 0x3e0a31b5, 0x7f00d6ad, 0x9294bd6f, 0x79b501c1, 0x00f3f051, 0x7fb504bd, 0xd6653e52, 0x584b7f00, + 0x3a98014c, 0x0100900c, 0xf000b3f0, 0x449000c3, 0xd7977e02, 0x00a4b300, 0x0be0b452, 0x9001e998, + 0xe9b57099, 0xf401a601, 0x607cd608, 0x0c3a9808, 0x0be4f00c, 0x977effff, 0xa4b300d7, 0x4cfe2d00, + 0xff0be401, 0x903ab2ff, 0xb87e40cc, 0xa4b300c4, 0x90341900, 0x517f9846, 0xbcff94f0, 0x7fb5f0f9, + 0xd6ad3e51, 0xb2030a00, 0xd6b83ea5, 0x01889000, 0xb3187790, 0xfd90148d, 0x900149fe, 0x9abf3c99, + 0x00d9067e, 0x00d6ce3e, 0xd03e0305, 0x04bd00d6, 0x3ab20bb2, 0x00c6237e, 0x1a0050b3, 0xbd0c3a98, + 0xd85e7e04, 0x0d3a9800, 0x7e0c30b5, 0xb500d906, 0x49fe0d30, 0x50999001, 0xdcd99fbf, 0xbf000005, + 0xa65ab299, 0x110bf4f9, 0x00d7123e, 0xce3e0105, 0xe97e00d6, 0x85fb0042, 0xfc30f430, 0xdcd222f9, + 0xbf000005, 0xfea0b229, 0x11900141, 0x7e19a00c, 0x9800c5b9, 0x5e7e0c0a, 0x0a9800d8, 0xd9067e0d, + 0x7e0ab200, 0xbf00d906, 0xbd29bf1f, 0xf4f9a6a4, 0xe97e070b, 0x25fb0042, 0x05dcd904, 0x99bf0000, + 0xfefc30f4, 0xaeb2014f, 0xa9bff9a0, 0xb9a6020a, 0x900d18f4, 0xe9bc01b9, 0xa0a4bd98, 0x0149fec9, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, + 0x014ffefc, 0xf9a0aeb2, 0x020aa9bf, 0x18f4b9a6, 0x01b9900b, 0xecbca4bd, 0x0149fe99, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, 0x014ffefc, + 0xb9bff9a0, 0x08f4c9a6, 0x3ef10c09, 0xb500d7f7, 0xaca002ab, 0xfe01acb5, 0x9fbf0149, 0x0005dcd9, + 0xb299bf00, 0xf4f9a6ca, 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, + 0x9fa0aebf, 0xbc02a998, 0xaba0b0be, 0xb9a699bf, 0xbc0808f4, 0xa9a092b9, 0xbf01a998, 0xf4a9a6aa, + 0xf10a051b, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcd900f8, + 0xbf000005, 0xfc30f499, 0xa0014ffe, 0x00a0b3f9, 0xd9067e08, 0x0149fe00, 0xdcd99fbf, 0xbf000005, + 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdff830, 0xf9000005, 0xfeffbf32, 0x99900149, + 0xa0a0b214, 0xb3b3b29f, 0x024200a0, 0xf4a2a6fd, 0xab903a0c, 0x0141fe01, 0x9002b4b6, 0x1ab21011, + 0x00da597e, 0x2700a4b3, 0x1db219bf, 0xe4bd2cb2, 0xdfbf90a0, 0xb201e990, 0x99fcbc9e, 0x08f490a6, + 0xa0ddbff4, 0xd8eb3e3d, 0xfe020a00, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4, + 0xfb0042e9, 0xdcdf0835, 0xbf000005, 0xfc30f4fe, 0xa00149fe, 0xbf9ebf9e, 0xf4e9a6f9, 0xe97e070b, + 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x44da0140, 0x90000028, 0x09a00800, + 0x004cd37e, 0x19bf0fbf, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, + 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0xda0140fe, 0x00002844, 0xa0080090, 0x4c217e09, 0xbf0fbf00, + 0x00a63019, 0xf00bacf0, 0xaab901a6, 0xf4f9a601, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, + 0xbf000005, 0x0140fe19, 0x002844da, 0x08009000, 0x397e09a0, 0x0fbf004e, 0xa63019bf, 0x0bacf000, + 0xb901a6f0, 0xf9a601aa, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x000005dc, 0xb4f019bf, + 0x0140feff, 0xa0080090, 0x0b947e09, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0xfc30f404, + 0xdcd112f9, 0xbf000005, 0x0140fe19, 0xa0080090, 0x0b7e7e09, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, + 0x15fb0042, 0xfc30f404, 0xdcd122f9, 0xbf000005, 0xfea2b219, 0xa43d0140, 0xa00c0090, 0x40e57e09, + 0xbf2aa000, 0xb019bf0f, 0xacf000a6, 0xf4f9a60b, 0xe97e070b, 0x25fb0042, 0xfc30f404, 0xdcd122f9, + 0xbf000005, 0xfea2b219, 0xa43d0140, 0xa00c0090, 0x40c37e09, 0xbf2aa000, 0xb019bf0f, 0xacf000a6, + 0xf4f9a60b, 0xe97e070b, 0x25fb0042, 0xe430f404, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0x900145fe, + 0x47fe3c99, 0x909fa001, 0x77902455, 0x131cd934, 0x9abf0000, 0x0c014bfe, 0x2cbb9008, 0xc17eff0d, + 0xa4330000, 0x30b4eb00, 0x33393f0c, 0x18e20c94, 0x10330431, 0x19330f00, 0x3d00b001, 0xdc333e04, + 0x023f9800, 0x00132cd9, 0x04319800, 0xa00a3458, 0x989f3f5f, 0x36900339, 0x0159b518, 0x79a0ff09, + 0x1800f433, 0x003b717e, 0xad33a032, 0x09012900, 0x132cdf01, 0xf9200000, 0x43f01272, 0x3e14bd00, + 0xbc00db73, 0x06b10241, 0x0df40100, 0x01004006, 0x000b947e, 0x001324d9, 0xe49abf00, 0xb2ffff2c, + 0xde0db26b, 0x00001200, 0x00cfec7e, 0xadb37aa0, 0xbf00d400, 0x015c985b, 0xb2041d90, 0x20207c0e, + 0xda1010bc, 0x00001200, 0x0026d87e, 0xad33a032, 0xbd00c500, 0x01004cb4, 0x001200da, 0xf414a600, + 0x223ea408, 0x3f9800dc, 0x132cd902, 0x34980000, 0x0a325804, 0x9f3f5fa0, 0x90033998, 0x59b51838, + 0xa0ff0901, 0x00f43379, 0x3b717e16, 0x33a03200, 0x008400ad, 0x00132cdf, 0xe4f12000, 0xbdffff26, + 0xdc133e24, 0x1262bc00, 0x010016b1, 0x41060df4, 0x947e0100, 0x5bbf000b, 0x90015c98, 0x1eb2042d, + 0x001200da, 0x26727e00, 0xff4ce400, 0x2021bcff, 0x8bb2a032, 0x00de1db2, 0x7c000012, 0xa4334041, + 0x24d93500, 0xbf000013, 0xcd167e9a, 0xb37aa000, 0xbd1300a4, 0x01004cb4, 0x001200da, 0xf426a600, + 0x5bbfa608, 0xb2015c98, 0x0ed4bd7a, 0x26d87e04, 0x34a03200, 0x3ab22db0, 0x000f817e, 0x71000d33, + 0x3a0130fe, 0xf130020f, 0x03331838, 0x4afe0409, 0x39913001, 0xbd3b3130, 0x38aa90b4, 0x000f717e, + 0x00daad3e, 0x002830d9, 0xfc30f400, 0x0005dcdf, 0xb202f900, 0xbfffbfa0, 0x0149fe9a, 0x0b049990, + 0x7e9fa064, 0x0e0000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, 0x8a009ff6, 0x4b02a600, + 0xc4bd1000, 0xbd27104d, 0x1b0f7ee4, 0x00a43300, 0x2830d915, 0x9abf0000, 0x00009b7e, 0xea3e040e, + 0x0ab200dc, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, 0x9af601aa, 0x01114f00, + 0x020099b8, 0x009ff600, 0x49fee43d, 0x04999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, + 0x0042e97e, 0x000405fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1825,9 +1825,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000021db, 0x00002222, 0x00002253, 0x00002292, 0x00001f4e, 0x00001f95, 0x00001fc6, 0x00002017, 0x00002088, 0x000020cf, 0x00002119, 0x0000216a, 0x00001e2a, - 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000024c, 0x0000001a, 0x00000384, 0x00000009, 0x000003f0, - 0x00000004, 0x00000420, 0x00000002, 0x00000438, 0x00000009, 0x000004a4, 0x00000004, 0x000004d4, - 0x00000004, 0x00000504, 0x00000002, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, + 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, 0x00000000, 0x00000013, 0x00000001, 0x00000001, 0x00000013, 0x00000001, 0x00000002, 0x00000013, 0x00000001, 0x00000003, 0x00000013, 0x00000001, 0x00000004, 0x00000013, 0x00000001, 0x00000005, 0x00000013, 0x00000001, 0x00000006, 0x00000013, 0x00000001, 0x00000007, 0x00000013, 0x00000001, @@ -1836,41 +1834,27 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000004, 0x00000002, 0x00000005, 0x00000004, 0x00000002, 0x00000006, 0x00000004, 0x00000002, 0x00000007, 0x00000004, 0x00000002, 0x00000008, 0x00000005, 0x00000003, 0x00000000, 0x00000015, 0x00000004, 0x00000000, 0x00000015, 0x00000004, 0x00000001, 0x00000015, 0x00000004, 0x00000002, - 0x00000015, 0x00000004, 0x00000003, 0x00000016, 0x00000005, 0x00000000, 0x0000000e, 0x00000012, + 0x00000015, 0x00000004, 0x00000003, 0x00000016, 0x00000005, 0x00000000, 0x0000000e, 0x00000011, 0x00000000, 0x00000006, 0x00000007, 0x00000000, 0x00000006, 0x00000007, 0x00000001, 0x00000006, 0x00000007, 0x00000002, 0x00000006, 0x00000007, 0x00000003, 0x0000001a, 0x00000008, 0x00000000, 0x0000001a, 0x00000008, 0x00000001, 0x0000001a, 0x00000008, 0x00000002, 0x0000001a, 0x00000008, - 0x00000003, 0x00000004, 0x00000015, 0x00000000, 0x00000002, 0x0000000b, 0x00000000, 0x00000002, - 0x0000000b, 0x00000001, 0x00000002, 0x0000000b, 0x00000002, 0x00000002, 0x0000000b, 0x00000003, - 0x00000003, 0x0000000c, 0x00000000, 0x00000001, 0x0000000a, 0x00000000, 0x00000001, 0x00000009, - 0x00000000, 0x00000001, 0x00000009, 0x00000001, 0x00000001, 0x00000009, 0x00000002, 0x00000001, - 0x00000009, 0x00000003, 0x00000001, 0x00000009, 0x00000004, 0x00000001, 0x00000009, 0x00000005, - 0x00000001, 0x00000009, 0x00000006, 0x00000001, 0x00000009, 0x00000007, 0x00000001, 0x00000009, - 0x00000008, 0x00000001, 0x0000000d, 0x00000000, 0x00000001, 0x0000000d, 0x00000001, 0x00000001, - 0x0000000d, 0x00000002, 0x00000001, 0x0000000d, 0x00000003, 0x00000002, 0x0000000f, 0x00000000, - 0x00000002, 0x0000000f, 0x00000001, 0x00000002, 0x0000000f, 0x00000002, 0x00000002, 0x0000000f, - 0x00000003, 0x00000003, 0x00000010, 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, - 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, - 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, - 0x12000000, 0x12400000, 0x12800000, 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, - 0x0000bd08, 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, - 0x0000ffff, 0x00004300, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, - 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, - 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000002, 0x0000000b, 0x00000000, 0x00000002, 0x0000000b, 0x00000001, 0x00000002, + 0x0000000b, 0x00000002, 0x00000002, 0x0000000b, 0x00000003, 0x00000001, 0x00000009, 0x00000000, + 0x00000001, 0x00000009, 0x00000001, 0x00000001, 0x00000009, 0x00000002, 0x00000001, 0x00000009, + 0x00000003, 0x00000001, 0x00000009, 0x00000004, 0x00000001, 0x00000009, 0x00000005, 0x00000001, + 0x00000009, 0x00000006, 0x00000001, 0x00000009, 0x00000007, 0x00000001, 0x00000009, 0x00000008, + 0x00000003, 0x0000000c, 0x00000000, 0x00000001, 0x0000000a, 0x00000000, 0x00000002, 0x0000000f, + 0x00000000, 0x00000002, 0x0000000f, 0x00000001, 0x00000002, 0x0000000f, 0x00000002, 0x00000002, + 0x0000000f, 0x00000003, 0x00000001, 0x0000000d, 0x00000000, 0x00000001, 0x0000000d, 0x00000001, + 0x00000001, 0x0000000d, 0x00000002, 0x00000001, 0x0000000d, 0x00000003, 0x00000003, 0x00000010, + 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, + 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, + 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, + 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, + 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00004300, 0x46020f1f, + 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, + 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, + 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2211,7 +2195,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00560000, 0x00420074, 0x007f0078, 0x008c0089, 0x004200c0, 0x00dc0042, 0x00051f00, 0x35040b08, 0x0200001d, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, - 0x00003650, 0xc8b00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00003450, 0xcab00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2492,7 +2476,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003300, 0x00000000, 0x0000de00, 0x00000000, + 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003100, 0x00000000, 0x0000de00, 0x00000000, 0xe4f7f5ef, 0xee6f0434, 0xa742283d, 0xb837517d, 0x49e4d804, 0xd8d4d342, 0xa7c8bf31, 0xe15c25cf, 0x3acb76c7, 0x6ca73cfc, 0xc5002b4d, 0x9dc59b12, 0x8f11945c, 0xe814622b, 0xc745df38, 0xc179824e, 0x50ed0464, 0x40f4b2de, 0x4ea86960, 0xacb935cf, 0xf1b2d5f8, 0xa4ba5e6f, 0x90a0a1eb, 0x69da0dfa, @@ -2557,8 +2541,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x3a16e326, 0xba6b6ea3, 0x87a41305, 0x8f25c7a1, 0x33c8446a, 0xc71830a5, 0xa6396ea5, 0xaca6ee44, - 0x58e60046, 0xb8c9d1da, 0x5b48c2ac, 0x7c81985b, 0xa3c7950d, 0x475262b8, 0xc32028c8, 0xcda615d9, + 0x7a9040dd, 0x0251d13c, 0x4450ac04, 0xc13389f9, 0x1f789ab9, 0x340dcaa2, 0xa6b485f7, 0xee512b70, + 0x59823fc0, 0xf12a3ca4, 0x45b67ae9, 0xd31002ea, 0x6d8e8937, 0x3b58b368, 0x0fce515f, 0x46a7c8f4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2630,26 +2614,26 @@ const NvU32 soe_ucode_header_lr10_dbg[] = { /* .appCodeImemOffset = */ 0, /* .appCodeIsSecure = */ 0, /* .appDataStartOffset = */ 56832, - /* .appDataSize = */ 13056, + /* .appDataSize = */ 12544, /* .appDataDmemOffset = */ 0, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 69888, + /* .appCodeStartOffset = */ 69376, /* .appCodeSize = */ 1024, /* .appCodeImemOffset = */ 56832, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 74240, + /* .appDataStartOffset = */ 73728, /* .appDataSize = */ 7424, /* .appDataDmemOffset = */ 56832, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 70912, + /* .appCodeStartOffset = */ 70400, /* .appCodeSize = */ 3328, /* .appCodeImemOffset = */ 57856, /* .appCodeIsSecure = */ 1, - /* .appDataStartOffset = */ 81664, + /* .appDataStartOffset = */ 81152, /* .appDataSize = */ 0, /* .appDataDmemOffset = */ 0, }; -const NvU32 soe_ucode_data_size_lr10_dbg = 20416; +const NvU32 soe_ucode_data_size_lr10_dbg = 20288; #endif //_SOE_UCODE_LR10_DBG_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 61377f5d1..0e1a99519 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -33,9 +33,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0xb4890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x64890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002fe189, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002d8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -72,57 +72,57 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000fc0, - 0x8900f89a, 0xbf000fb4, 0x8900f89a, 0xbf000fc4, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fc889, - 0xa9a099bf, 0x000fc089, 0xa9b599bf, 0x0f00f801, 0x0fcc8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000fc8, 0xa609bf9f, 0x110bf4f9, 0x000fc089, 0x09989fbf, 0xf4f9a601, 0xc08d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fc88929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000fc48f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fd4, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001074, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0fd489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0xc489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e001078, 0x89000bee, 0xbf000fb4, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000fb482, 0xb0b229bf, 0x000fc081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x108c890b, 0x067d3e00, 0x10908900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0fc489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fcc, - 0x08453e9f, 0x0fb48900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x748064bd, 0xbc870010, 0xb884000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fd48e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f70, + 0x8900f89a, 0xbf000f64, 0x8900f89a, 0xbf000f74, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000f7889, + 0xa9a099bf, 0x000f7089, 0xa9b599bf, 0x0f00f801, 0x0f7c8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000f78, 0xa609bf9f, 0x110bf4f9, 0x000f7089, 0x09989fbf, 0xf4f9a601, 0x708d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0f788929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f748f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000f84, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001038, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0f8489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0x7489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e00103c, 0x89000bee, 0xbf000f64, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f6482, 0xb0b229bf, 0x000f7081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1050890b, 0x067d3e00, 0x10548900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f7489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000f7c, + 0x08453e9f, 0x0f648900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x388064bd, 0x6c870010, 0x6884000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000f848e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fd4, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000f84, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xd48e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0x848e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fdc, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000fd4, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fd4, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000f8c, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000f84, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000f84, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fd48f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001074, - 0x0ad07e96, 0x0485fb00, 0xc48922f9, 0x99bf000f, 0xcd009db3, 0x10a88900, 0x899fbf00, 0xbf000fc0, - 0x0099b999, 0x0bf4f9a6, 0x0fb4890f, 0x0b9abf00, 0x0a957eec, 0x0fc08e00, 0x8fe9bf00, 0x900010a8, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10908f1f, 0x108c8e00, 0xbffcbf00, 0x0fc88de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010908f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000f848f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001038, + 0x0ad07e96, 0x0485fb00, 0x748922f9, 0x99bf000f, 0xcd009db3, 0x106c8900, 0x899fbf00, 0xbf000f70, + 0x0099b999, 0x0bf4f9a6, 0x0f64890f, 0x0b9abf00, 0x0a957eec, 0x0f708e00, 0x8fe9bf00, 0x9000106c, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10548f1f, 0x10508e00, 0xbffcbf00, 0x0f788de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010548f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000fc082, 0x00109081, 0xb3100a90, 0x89bf0004, 0xbf0010ac, 0x0094b399, 0x09283e17, 0x10ac8f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000fc481, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf0010b0, 0x0099b399, 0x788f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0xb48314bd, 0x7882000f, 0xaa3e0010, 0x517e0009, + 0x000f7082, 0x00105481, 0xb3100a90, 0x89bf0004, 0xbf001070, 0x0094b399, 0x09283e17, 0x10708f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f7481, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf001074, 0x0099b399, 0x3c8f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x648314bd, 0x3c82000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10ac8fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xcc890e01, 0x99bf000f, 0x160194b3, - 0xcc89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0xc48932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000fc081, 0x000fb482, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x8c890b18, 0x423e0010, 0x9089000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10708fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0x7c890e01, 0x99bf000f, 0x160194b3, + 0x7c89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x748932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f7081, 0x000f6482, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x50890b18, 0x423e0010, 0x5489000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0xa08f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf0005a0, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf000554, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0041407e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xdc800099, 0x0fbf0010, + 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xa0800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, 0x407e000a, 0x01fb0041, 0x0041557e, 0x00185a7e, 0x0800a0b3, 0x00068a7e, 0x0041407e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, @@ -144,8 +144,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, 0x7e170003, 0x3300195a, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10e08f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, - 0x000a9b7e, 0x747e00f8, 0xe08e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0x10a48f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, + 0x000a9b7e, 0x747e00f8, 0xa48e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, @@ -156,37 +156,37 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, 0x0142fe01, 0x90271190, 0x1ab22622, 0xf77e2bb2, 0x020a0040, 0x117eab32, 0x0abf0041, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf004111, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010e4, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e4, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2fd88900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010a8, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010a8, 0xf8000e6b, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2d808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002fc0, - 0xc91bf4fd, 0x002fd889, 0x9b7e9abf, 0x11fb0000, 0x108b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf001110, 0x11148990, 0x899fbf00, 0x18001100, 0x9e35180e, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002d68, + 0xc91bf4fd, 0x002d8089, 0x9b7e9abf, 0x11fb0000, 0xd48b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf0010d4, 0x10d88990, 0x899fbf00, 0x180010c4, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111489, 0x01fb90a0, 0x89ffa4f0, - 0x8c003231, 0xbc003224, 0xacbcd0a9, 0x3fdf3fa0, 0x32318cae, 0xffe9c400, 0x20909cbc, 0x3224899f, - 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x32318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001118, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, - 0x00323189, 0x91209f3f, 0x00322489, 0x3d0009bc, 0x20092094, 0x3224892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x11188f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x0010d889, 0x01fb90a0, 0x89ffa4f0, + 0x8c003031, 0xbc003024, 0xacbcd0a9, 0x3fdf3fa0, 0x30318cae, 0xffe9c400, 0x20909cbc, 0x3024899f, + 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x30318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f0010dc, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x00303189, 0x91209f3f, 0x00302489, 0x3d0009bc, 0x20092094, 0x3024892f, 0xfff4f000, 0x20f0f9bc, + 0xf921fbf1, 0x10dc8f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, - 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0d1800bf, 0x0014331d, 0x4f02f806, - 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xdf320b0c, 0x9f3ee43d, 0x02f80011, 0xdf32e43d, 0x00119f3e, - 0xc401ff12, 0x09bcfff9, 0x20991890, 0x1bf49126, 0x3ea43d09, 0x330011c9, 0x32080094, 0x33010efd, - 0x33e100f4, 0xc41100e0, 0x09bcffd9, 0x20913590, 0x0011b63e, 0x49fe02f8, 0x08999001, 0x010a9fbf, + 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, + 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, + 0xc401ee12, 0x09bcffe9, 0x20991890, 0x1bf49126, 0x3ea43d09, 0x330011c9, 0x32080094, 0x33010fed, + 0x33e100e4, 0xc41100f0, 0x09bcffd9, 0x20913590, 0x0011b63e, 0x49fe02f8, 0x08999001, 0x010a9fbf, 0xfd19f918, 0xf935059a, 0x0415fb19, 0x0011417e, 0x0600a433, 0x00f802f8, 0xf9fc30f4, 0x32a0b212, 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, - 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x32008fff, - 0x32188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x0005a488, 0x8120597c, 0x3e001118, + 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x30008fff, + 0x30188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e0010dc, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, - 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0032248f, 0x18909fbc, 0x19180190, - 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0032188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0032, + 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0030248f, 0x18909fbc, 0x19180190, + 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0030188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0030, 0xf0102098, 0x1975fff4, 0xf09f7c01, 0x58021f75, 0x9b520219, 0xffb9e401, 0x021b75ff, 0xfe0894b6, 0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033, - 0x00320080, 0x80e80f7c, 0x3c003218, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, + 0x00300080, 0x80e80f7c, 0x3c003018, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, 0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2, 0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e, 0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012, @@ -208,266 +208,266 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x000005a0, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0xb4d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, - 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3650daf2, 0x50db0000, 0x7e000034, - 0x7e0015f6, 0xf7000b68, 0xb4d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, - 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003650, 0x003450db, 0x15f67e00, - 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000034, 0x00003250, 0x0015f67e, 0x000b207e, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x00289880, 0x64d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3450daf2, 0x50db0000, 0x7e000032, + 0x7e0015f6, 0xf7000b68, 0x64d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003450, 0x003250db, 0x15f67e00, + 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000032, 0x00003050, 0x0015f67e, 0x000b207e, 0x0016473e, 0xf91832f4, 0x0188fef2, 0x3b7e80f9, 0x80fc0040, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x2cdf00f8, 0xf4000006, 0x62f9fc30, - 0xffbffebf, 0x900149fe, 0x9ea01c99, 0x000630d9, 0xbd9fa000, 0x010089f4, 0x009ff601, 0xb87fff4f, + 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0xdcdf00f8, 0xf4000005, 0x62f9fc30, + 0xffbffebf, 0x900149fe, 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0x7e070bf4, 0xfb0042e9, 0x0cd90415, 0xf4000013, 0x12f9fc30, + 0x0005dcd1, 0xbf9abf00, 0x0140fe19, 0x000000db, 0x08009040, 0x08c4aab8, 0x7e09a000, 0xbf009efa, + 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, 0x0000130c, 0xf9fc30f4, 0x05dcd112, 0x9abf0000, + 0x40fe19bf, 0x0000db01, 0x00908000, 0xc4aab808, 0x09a00008, 0x009efa7e, 0x19bf0fbf, 0x0bf4f9a6, + 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xd99fa001, 0x0000130c, 0x008f99bf, 0x9a9001c0, 0x00f9cf60, 0xb34c99c7, 0xb34a0090, 0xf8f60190, 0x28653e02, 0x00f9cf00, 0xb34c99c7, - 0xb30e0090, 0xf8f60190, 0x28793e02, 0xc2008b00, 0x00bbcf01, 0x040018d9, 0x05b9fd04, 0x009f2c7e, - 0xbf0149fe, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x28d23e28, 0xc1008900, 0x009af601, 0x0000f1df, + 0xb30e0090, 0xf8f60190, 0x28793e02, 0xc2008b00, 0x00bbcf01, 0x040018d9, 0x05b9fd04, 0x009efa7e, + 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x28d23e28, 0xc1008900, 0x009af601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0x793e9fb2, 0xe97e0028, 0x30f40042, 0xf400f804, 0x0cd9fc30, - 0xf9000014, 0xb299bf22, 0x062cd1a2, 0x40fe0000, 0xc89ab801, 0x19bf0008, 0xa00c0090, 0x1c227e09, + 0xf9000013, 0xb299bf22, 0x05dcd1a2, 0x40fe0000, 0xc89ab801, 0x19bf0008, 0xa00c0090, 0x1c227e09, 0xbf0ebf00, 0xbb01091f, 0xa9fd0492, 0x0bacf004, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xd9fc30f4, - 0x0000062c, 0x99bf02f9, 0x90014ffe, 0xf9a004ff, 0x00140cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, + 0x000005dc, 0x99bf02f9, 0x90014ffe, 0xf9a004ff, 0x00130cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b301d2, 0x02f8f501, 0x00293b3e, 0xc700f9cf, 0x99b34c99, 0xb301ae00, 0xf8f50190, 0x29503e02, 0x00f9cf00, 0xb34c99c7, 0x01770099, 0xf50190b3, 0x653e02f8, 0xf9cf0029, 0x4c99c700, - 0x480099b3, 0x0190b301, 0x3e02f8f5, 0x7e00297a, 0xd90090f2, 0x00800000, 0xf49409ff, 0x317e070b, - 0x0cd9002d, 0xbf000014, 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00f30099, 0xf50190b3, 0xad3e02f8, + 0x480099b3, 0x0190b301, 0x3e02f8f5, 0x7e00297a, 0xd90090c0, 0x00800000, 0xf49409ff, 0x317e070b, + 0x0cd9002d, 0xbf000013, 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00f30099, 0xf50190b3, 0xad3e02f8, 0xf9cf0029, 0x4c99c700, 0xcf0099b3, 0x0190b300, 0x3e02f8f5, 0xcf0029c2, 0x99c700f9, 0x0099b34c, 0x90b30098, 0x02f8f501, 0x0029d73e, 0xc700f9cf, 0x90b34c99, 0x90b36e00, 0x02f8f601, 0x0029ec3e, - 0x007c0d7e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd9007e21, 0x02000000, 0x000000df, 0xb409ff04, - 0xf4940fff, 0xbffd060b, 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, - 0x7e0008c4, 0xfe009f2c, 0x99900149, 0xd99fbf04, 0x0000062c, 0xf9a699bf, 0x00e10bf5, 0x002b353e, + 0x007bff7e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd9007e13, 0x02000000, 0x000000df, 0xb409ff04, + 0xf4940fff, 0xbffd060b, 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000130c, 0xaab89abf, + 0x7e0008c4, 0xfe009efa, 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x00e10bf5, 0x002b353e, 0x01c20089, 0xff0099cf, 0x0995049d, 0x0194b31f, 0x2a003e97, 0xa4efb800, 0x00890008, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890029ec, 0xcf01c200, 0x008f009d, 0xd73e01c0, 0xefb80029, 0x89000890, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0029c23e, 0x01c20089, 0xff0099cf, 0x00d9049d, 0xff010000, 0x0bf59409, 0x8f3efeb9, 0xefb80029, 0x89000898, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x00297a3e, 0x01c20089, 0x8f009dcf, 0x3e01c000, 0xb8002965, 0x000884ef, 0x01c10089, 0xdf009ff6, - 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x29503e9f, 0x42e97e00, 0x0405fb00, 0x00062cdf, + 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x29503e9f, 0x42e97e00, 0x0405fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0x8f9fa001, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b341, 0x3e02f8f6, 0xcf002b4f, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8a002b63, 0xcf01c200, 0x49fe00aa, - 0xd99fbf01, 0x0000062c, 0xaac799bf, 0xf4f9a601, 0xb83e2d0b, 0xafb8002b, 0x89000380, 0xf601c100, + 0xd99fbf01, 0x000005dc, 0xaac799bf, 0xf4f9a601, 0xb83e2d0b, 0xafb8002b, 0x89000380, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x002b633e, 0x0042e97e, 0xf80430f4, - 0xfc30f400, 0x00062cd9, 0xbf82f900, 0x014ffe99, 0xa024ff90, 0x00a933f9, 0x04bd0087, 0x002a94d7, + 0xfc30f400, 0x0005dcd9, 0xbf82f900, 0x014ffe99, 0xa024ff90, 0x00a933f9, 0x04bd0087, 0x002838d7, 0x8314bd00, 0x8601c000, 0xd501c100, 0x800000f1, 0x01c20084, 0x7b987abf, 0x7e0cb201, 0xf0004212, 0x0bf401a4, 0xbd0bb248, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83300a4, 0x0004002a, 0xc70039cf, 0x99b34c99, 0xb300dc00, 0xf8f50190, 0x2c203e02, 0x0039cf00, 0xb34c99c7, 0x00b90099, - 0xf50190b3, 0x353e02f8, 0x0090002c, 0x00119101, 0xa42404b3, 0xa00014b3, 0x002cda3e, 0x94d804bd, - 0xbd00002a, 0xc0008314, 0xc1008701, 0x00f1d601, 0x00858000, 0xfe0401c2, 0x8b988abf, 0x7e0cb201, + 0xf50190b3, 0x353e02f8, 0x0090002c, 0x00119101, 0xa42404b3, 0xa00014b3, 0x002cda3e, 0x38d804bd, + 0xbd000028, 0xc0008314, 0xc1008701, 0x00f1d601, 0x00858000, 0xfe0401c2, 0x8b988abf, 0x7e0cb201, 0xf0004212, 0x0bf401a4, 0xbd0bb246, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83100a4, 0x0004002a, 0xc70039cf, 0x90b34c99, 0x90b37300, 0x02f8f601, 0x002ca43e, 0xc70039cf, 0x90b34c99, 0x90b35100, 0x02f8f601, 0x002cb83e, 0x91010090, 0x04b30011, 0x14b3a624, 0x49fea200, 0x24999001, - 0x2cd99fbf, 0xbf000006, 0xa6a43d99, 0x410bf4f9, 0x002d2a3e, 0xf0004bcf, 0x6f7e01b5, 0x4a3e0047, + 0xdcd99fbf, 0xbf000005, 0xa6a43d99, 0x410bf4f9, 0x002d2a3e, 0xf0004bcf, 0x6f7e01b5, 0x4a3e0047, 0x6af6002c, 0x0035f700, 0x3e0039cf, 0xcf002c35, 0xb4fd005b, 0x476f7e04, 0x2ccc3e00, 0x007af600, - 0xcf0036f7, 0xb83e0039, 0xe97e002c, 0x85fb0042, 0xfc30f404, 0x00062cdf, 0xbf02f900, 0x0149feff, + 0xcf0036f7, 0xb83e0039, 0xe97e002c, 0x85fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, 0xa0049990, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb34f0090, 0xf8f60190, 0x2d493e02, 0x00f9cf00, 0xb34c99c7, 0xb32a0090, 0xf8f60190, 0x2d5d3e02, 0x2dda7e00, 0x3009c400, 0x7e070bf4, 0xc4002e5a, 0x0bf44009, 0x2e927e3d, 0x2dbf3e00, 0xc2008900, 0x0090cf01, 0xf40109c4, 0x713ede0b, 0x488f002d, 0x008901b0, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xfe002d5d, - 0x99900149, 0xd99fbf04, 0x0000062c, 0xf9a699bf, 0x7e070bf4, 0xfb0042e9, 0x2cdf0405, 0xbf000006, + 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0405, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x2ded3e02, 0x00f9cf00, 0xb34c99c7, 0xb3390090, 0xf8f60190, 0x2e013e02, 0xad248f00, 0xc1008901, 0x009ff601, 0x99b8f4bd, 0xf6000100, 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002e013e, - 0xbf0149fe, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, - 0x0000062c, 0x048a19bf, 0xb4bd01ad, 0x900140fe, 0x09a00800, 0x0047e97e, 0x01ad848a, 0xe97eb4bd, - 0x0fbf0047, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x2cdf0415, 0xbf000006, 0xfc30f4ff, 0xa00149fe, + 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, + 0x000005dc, 0x048a19bf, 0xb4bd01ad, 0x900140fe, 0x09a00800, 0x0047e97e, 0x01ad848a, 0xe97eb4bd, + 0x0fbf0047, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x2ea53e02, 0x00f9cf00, 0xb34c99c7, 0xb3390090, 0xf8f60190, 0x2eb93e02, 0xada48f00, 0xc1008901, 0x009ff601, 0x99b8f4bd, 0xf6000100, - 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002eb93e, 0xbf0149fe, 0x062cd99f, - 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cdf00f8, 0xbf000006, 0xfc30f4ff, 0x950149fe, - 0x9fa018be, 0xb995adb2, 0x05a8df10, 0x94760000, 0x08b5b608, 0x3ee59eff, 0x26002f5c, 0x1c1bf49b, + 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002eb93e, 0xbf0149fe, 0x05dcd99f, + 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0x950149fe, + 0x9fa018be, 0xb995adb2, 0x055cdf10, 0x94760000, 0x08b5b608, 0x3ee59eff, 0x26002f5c, 0x1c1bf49b, 0x6601f958, 0x141bf49e, 0xa43df97f, 0x5808d975, 0xdf7501ff, 0x2f643e09, 0x04ff9000, 0x9433f93f, - 0x010add00, 0xbf0149fe, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cdf00f8, - 0xbf000006, 0xfc30f4ff, 0xa00149fe, 0x0aa9b29f, 0x00b0b302, 0x0895b60b, 0xb920a43d, 0xbf0149fe, - 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x062cdffc, 0x02f90000, - 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0x6500a0b3, 0xb305a998, 0xd95e0090, 0x0000140c, 0xaab89abf, + 0x010add00, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcdf00f8, + 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x0aa9b29f, 0x00b0b302, 0x0895b60b, 0xb920a43d, 0xbf0149fe, + 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x05dcdffc, 0x02f90000, + 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0x6500a0b3, 0xb305a998, 0xd95e0090, 0x0000130c, 0xaab89abf, 0x7e0004e8, 0xe7001c22, 0xb30168a9, 0x4c0fff9a, 0x470090b3, 0xb314a5b6, 0x400fffaa, 0x3b00a0b3, 0xb6050e98, 0xaf940c94, 0xa0a43d0c, 0x050e98e9, 0xf9bce9bf, 0x01efb5f0, 0xbd070f98, 0x98f9a094, 0x0f980509, 0x9299bf07, 0xf9b50199, 0x30393e01, 0x3e350a00, 0x0a003039, 0x0149fe2e, 0xbf049990, - 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, 0xd9fc30f4, 0x0000062c, 0x99bf32f9, + 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, 0xd9fc30f4, 0x000005dc, 0x99bf32f9, 0x90014ffe, 0xf9a010ff, 0xb9c4afb2, 0xf4020a03, 0xc9c4321b, 0xb8f2b2ff, 0x00392899, 0x01a2b3e7, 0xbd029194, 0x309a3e04, 0x901ab200, 0x227e0100, 0x1190001c, 0x902aa004, 0x03a60422, 0x3ded08f4, - 0x0149fea4, 0xbf109990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0435fb00, 0xf9fc30f4, - 0x18a9bf12, 0xab1809af, 0x062cd008, 0x99b80000, 0x94003969, 0x09bf029a, 0xf00141fe, 0x119001f4, + 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0435fb00, 0xf9fc30f4, + 0x18a9bf12, 0xab1809af, 0x05dcd008, 0x99b80000, 0x94003969, 0x09bf029a, 0xf00141fe, 0x119001f4, 0xf0ffbc08, 0x44d919a0, 0xf0008800, 0xb9fd01b4, 0x05bffd05, 0x001cb17e, 0x09bf1fbf, 0xf9a6a43d, - 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0x062cdffc, 0x22f90000, 0x49feffbf, 0x0c999001, 0x9fa0a0b2, + 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0x05dcdffc, 0x22f90000, 0x49feffbf, 0x0c999001, 0x9fa0a0b2, 0xc2b2b132, 0x00b3350a, 0x09bf6900, 0x610094b3, 0xb3010998, 0x8a5a0094, 0x7e00e204, 0xc4001c22, 0xa9c4ff1e, 0xf49ea601, 0x943d091b, 0x0031813e, 0x09080f18, 0x01e4f0f3, 0xf002abc5, 0xb9fd01f4, 0x02f4b604, 0xbffdfe09, 0xe2048a05, 0x04b9fd00, 0x7e05befd, 0x8a001cb1, 0x7e00e204, 0x09001c22, - 0x0020b301, 0x3d292006, 0x318f3ea4, 0xfe010a00, 0x99900149, 0xd99fbf0c, 0x0000062c, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0x062cdff8, 0x52f90000, 0x49feffbf, 0x1c999001, 0x9fa0a3b2, + 0x0020b301, 0x3d292006, 0x318f3ea4, 0xfe010a00, 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, + 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0x05dcdff8, 0x52f90000, 0x49feffbf, 0x1c999001, 0x9fa0a3b2, 0xc272b0b2, 0x350ad4b2, 0xc70039b3, 0x00c97300, 0xd9b300ba, 0xbf00b500, 0x009db339, 0x399800b4, 0x009db301, 0x088a00ac, 0x227e00e2, 0xa9c4001c, 0x0d0bf401, 0x02a2a9e7, 0xbb0294b6, 0x4cfe0209, 0x3d3ab201, 0x1bcc90b4, 0x00310a7e, 0x8300ad33, 0x00008900, 0x0301c430, 0x09bc0405, 0xff19c400, 0xb20209bb, 0x1c227e0a, 0xff19c400, 0xe4f259bc, 0xa6ffff29, 0x071df4f9, 0xffff2fe4, 0xf4bdfe32, 0x0032563e, 0xf090913c, 0x94b60394, 0x95a9bc03, 0x90f9493c, 0xf93201ff, 0x08f4fe26, 0xffe9c4ea, 0x7b040090, 0x20730229, 0x49bc0d00, 0x3e143d40, 0xfe003223, 0x99900149, 0xb29b3f1b, 0x7ec4bd3a, - 0x3e00310a, 0x0a00328f, 0x328f3e02, 0xfe010a00, 0x99900149, 0xd99fbf1c, 0x0000062c, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40855, 0x062cdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0a0b2, + 0x3e00310a, 0x0a00328f, 0x328f3e02, 0xfe010a00, 0x99900149, 0xd99fbf1c, 0x000005dc, 0xf9a699bf, + 0x7e070bf4, 0xfb0042e9, 0x30f40855, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0xa0b3350e, 0xb43d1a00, 0x0a7ec4bd, 0xae320031, 0x0c00a433, 0xbc7e0ab2, 0xae320030, 0x900149fe, - 0x9fbf0499, 0x00062cd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x05fb0042, 0xf430f404, 0x00062cd9, + 0x9fbf0499, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x05fb0042, 0xf430f404, 0x0005dcd9, 0xbf12f900, 0x014ffe99, 0x4b10ff90, 0xf9a003e8, 0x0016fc7e, 0x4afea0b2, 0x08aa9001, 0x817ea1b2, 0xa08a0015, 0x227e00e5, 0xa6b0001c, 0x1c1ff400, 0x9c7e1ab2, 0xa0a60015, 0x0a090df4, 0x334b3e04, - 0x000e7e00, 0x33223e00, 0xfea43d00, 0x99900149, 0xd99fbf10, 0x0000062c, 0xf9a699bf, 0x7e070bf4, - 0xfb0042e9, 0x30f40c15, 0x062cdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0b0b2, 0x3f01ad58, + 0x000e7e00, 0x33223e00, 0xfea43d00, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, + 0xfb0042e9, 0x30f40c15, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0b0b2, 0x3f01ad58, 0x02a958af, 0x000000de, 0xffdce480, 0x03f4f0ff, 0xb60093f0, 0x9cbc12f4, 0x05fefd90, 0xf0019992, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, 0x001cb17e, 0xf97e0ab2, 0x49fe0032, 0x04999001, - 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xf830f404, 0x00062cdf, 0xbf52f900, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xf830f404, 0x0005dcdf, 0xbf52f900, 0x0149feff, 0xb21c9990, 0x729fa0a3, 0x71020ab1, 0xf40100b6, 0x44fe450c, 0xe4a08201, 0x18449000, 0x723e54bd, 0x45a00034, 0x16701072, 0x050df404, 0x3bb20400, 0xffff0ce4, 0x7e7e4ab2, 0x4bbf000b, 0x107b2ab2, 0x04229002, 0x7e0003f0, 0xbc001cb1, 0x14733030, 0xa43dd400, 0x900149fe, 0x9fbf1c99, - 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, 0x2cd9fc30, 0xf9000006, 0xfe99bf32, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, 0xdcd9fc30, 0xf9000005, 0xfe99bf32, 0xff90014f, 0xa0b2b210, 0x58c3b2f9, 0xbb5802b9, 0x00a0b301, 0x0093f056, 0x9990fc0f, 0xffb0e403, 0x149fffff, 0xb30b1bf4, 0x3e0c0004, 0xb3003507, 0xb20e0000, 0x34157eda, 0x00a43300, 0x8b2ab230, 0x7e07a120, 0x33003366, 0xb32200a4, 0xb01e0010, 0xccf00006, 0x01c6f00b, 0x1b723ab2, 0x7e05c436, - 0x3e003054, 0x0a003509, 0x0149fe35, 0xbf109990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, - 0x0435fb00, 0xdff830f4, 0x0000062c, 0xffbf12f9, 0x900149fe, 0x40fe0c99, 0x909fa001, 0xb1b20800, + 0x3e003054, 0x0a003509, 0x0149fe35, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, + 0x0435fb00, 0xdff830f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0x40fe0c99, 0x909fa001, 0xb1b20800, 0xe87e0cb2, 0x0fbf0050, 0x9802f958, 0x93f003ff, 0x0c94b600, 0x0035653e, 0x0bf491a6, 0x06ff9815, 0x100099b8, 0x00f4b300, 0x3e350af3, 0x98003584, 0xf99802fe, 0xbcffbf05, 0x9ea6909f, 0xf0089cf0, - 0x9a320196, 0x900149fe, 0x9fbf0c99, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40815fb, - 0x2cdfe030, 0xf9000006, 0xb0ffbf82, 0x49fe09b1, 0x40999001, 0xa00140fe, 0x3c00909f, 0x0cb2a4b2, + 0x9a320196, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40815fb, + 0xdcdfe030, 0xf9000005, 0xb0ffbf82, 0x49fe09b1, 0x40999001, 0xa00140fe, 0x3c00909f, 0x0cb2a4b2, 0x0050e87e, 0x395803bf, 0x03319802, 0xb60093f0, 0xe63e0c94, 0xe0b40035, 0xf49ea609, 0x1198130b, 0x0099b806, 0x14b30010, 0xb83ef000, 0x19980037, 0x031f9805, 0xb6041e98, 0x9fbc0395, 0xf42ea620, 0x43fe4f0c, 0x904ab201, 0x2bb23833, 0x3db2010c, 0x0031aa7e, 0xad33a032, 0xbf01a400, 0xff004f39, 0x90014efe, 0x99bc34ee, 0x059ffd90, 0x2cb24ab2, 0xe9a0ebb2, 0x4a7e040d, 0xa032004b, 0x7e00ad33, - 0x05199801, 0xb5019990, 0xba3e0519, 0xd4d90037, 0x9800002a, 0x49fe049e, 0x3c999001, 0x9ea09fb2, + 0x05199801, 0xb5019990, 0xba3e0519, 0x7cd90037, 0x98000028, 0x49fe049e, 0x3c999001, 0x9ea09fb2, 0x0036703e, 0x33091918, 0x98130090, 0xf1a00411, 0x14b3f1bf, 0xd43ef200, 0x39350037, 0x36a83e08, 0x08b91800, 0x13009033, 0xa004bb98, 0xb31bbf1b, 0x3ef200b4, 0xbf0037b8, 0x7e4ab2bb, 0x32004a98, 0x00ad33a0, 0x11bf0119, 0xbf011f98, 0x0142fe3b, 0x3fb54ab2, 0x04195801, 0x0c302290, 0x752db204, @@ -479,21 +479,21 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb24ab201, 0x7e040d7b, 0x33004b4a, 0xa07500a4, 0x031b9823, 0x040c4ab2, 0xbb928db2, 0x31aa7e04, 0x00a43300, 0x032c985f, 0x8bb24ab2, 0xcc92040d, 0x4b4a7e04, 0x00a43300, 0x021f984b, 0x29b594bd, 0x0066b805, 0x2fb50010, 0x06229802, 0xb3061198, 0xff6f001d, 0x0037ba3e, 0x49fe3500, 0x40999001, - 0x2cd99fbf, 0xbf000006, 0xa60a3299, 0x1d0bf4f9, 0x0037e63e, 0xa00141fe, 0x3c1190fe, 0x00368d3e, - 0xba3ea032, 0xe97e0037, 0x85fb0042, 0xfc30f420, 0x00062cdf, 0xbf02f900, 0x0149feff, 0xb2049990, - 0xb39fa0a0, 0x985100a0, 0x90b306a9, 0x0cd94a00, 0xbf000014, 0xe0aab89a, 0x227e0004, 0xa9e4001c, + 0xdcd99fbf, 0xbf000005, 0xa60a3299, 0x1d0bf4f9, 0x0037e63e, 0xa00141fe, 0x3c1190fe, 0x00368d3e, + 0xba3ea032, 0xe97e0037, 0x85fb0042, 0xfc30f420, 0x0005dcdf, 0xbf02f900, 0x0149feff, 0xb2049990, + 0xb39fa0a0, 0x985100a0, 0x90b306a9, 0x0cd94a00, 0xbf000013, 0xe0aab89a, 0x227e0004, 0xa9e4001c, 0x9ab30fff, 0xb3380fff, 0xe7330090, 0xb3016caa, 0x2b0fffaa, 0x2600a0b3, 0xb6060e98, 0xaf940c94, 0xa0a43d0c, 0x060e98e9, 0xf9bce9bf, 0x01efb5f0, 0x00385c3e, 0x5c3e350a, 0x2e0a0038, 0x900149fe, - 0x9fbf0499, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0x2cdfd830, 0xf9000006, + 0x9fbf0499, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0xdcdfd830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0a6b248, 0x00a0b39f, 0x06a09821, 0x0bbffd09, 0xa601bf92, 0x110cf4f9, 0x09010f98, 0xf4f9a6ff, 0xf4b3070b, 0x02f81100, 0x6db30205, 0x3e027d00, 0x92003b3c, 0x100c10bb, - 0x002ad4dd, 0x31aa7e00, 0x33a53200, 0x026400ad, 0x002ad4da, 0x0068db00, 0x080c0000, 0x000ba87e, + 0x00287cdd, 0x31aa7e00, 0x33a53200, 0x026400ad, 0x00287cda, 0x0068db00, 0x080c0000, 0x000ba87e, 0x7e00adb3, 0x01099802, 0xf9a60fbf, 0x027818f5, 0x0ffffee4, 0x02701bf5, 0xfe066f98, 0x99900149, 0xbf843d44, 0x0af1b0ff, 0x94bd9ea0, 0x3e0b91b0, 0x3d003b19, 0x7e140ba4, 0xb20040e5, 0x00a4b3a3, 0x0502f80c, 0x3b2f3e05, 0x0ae0b400, 0xb6ff89c4, 0x9ebc0c94, 0xa094bdb0, 0x04a9b5ab, 0x0fffb9e4, 0x02241bf5, 0xb2014dfe, 0x90040c6a, 0xaa7e44dd, 0xa0330031, 0xa5320a00, 0x003b2b3e, 0xf11190b4, 0x750fff94, 0x90b40239, 0x6c99e711, 0x03397501, 0xb61190b4, 0x39351f95, 0x11f0b408, 0x0ffff9e4, - 0x0fff9ab3, 0x6cf9e713, 0xff9ab301, 0x01090a0f, 0xbf093935, 0x0099b339, 0xd4df0090, 0x1800002a, + 0x0fff9ab3, 0x6cf9e713, 0xff9ab301, 0x01090a0f, 0xbf093935, 0x0099b339, 0x7cdf0090, 0x18000028, 0x99900dfb, 0x0ffc4a04, 0xf00991b0, 0xbb7effb4, 0x94bd0016, 0x91b0743d, 0xfffc090d, 0x91b094a9, 0x3af13e0c, 0x0ba43d00, 0x40e57e1c, 0xb3a1b200, 0xf80c00a4, 0x3e050002, 0xb4003b58, 0x7ac40cb0, 0x16fc7eff, 0xb5e4bd00, 0xb0b4061e, 0xfe040c09, 0xdd90014d, 0xb0babc40, 0x1bb56ab2, 0x31aa7e01, @@ -504,58 +504,58 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x2b906ab2, 0x904cb204, 0x857e38dd, 0xad330051, 0xbf00c800, 0x0ef0b419, 0xa0909fbc, 0x3aca3e19, 0x07f4b300, 0xffffde29, 0x9efd00ff, 0x042b9004, 0xb50219b5, 0x1bb50414, 0xb24cb203, 0x141d906a, 0x0051857e, 0xd23ea032, 0x2290003a, 0xf424a604, 0x0d338d0d, 0x98008600, 0x94b30339, 0x31b50b00, - 0x3aeb3e03, 0x0df0b400, 0x1006f1b5, 0x11b00177, 0x2ad4de0d, 0xe9180000, 0xf579260d, 0x98feca08, - 0x94b304e9, 0xe3b50b00, 0x3b133e04, 0x0bf0b400, 0x1004f3b5, 0x31b00188, 0x2ad4de0b, 0xe9180000, + 0x3aeb3e03, 0x0df0b400, 0x1006f1b5, 0x11b00177, 0x287cde0d, 0xe9180000, 0xf579260d, 0x98feca08, + 0x94b304e9, 0xe3b50b00, 0x3b133e04, 0x0bf0b400, 0x1004f3b5, 0x31b00188, 0x287cde0b, 0xe9180000, 0xf589260c, 0x3efdf008, 0x33003b3c, 0x98110050, 0xff0f0669, 0x69989fa0, 0x019fb506, 0x900149fe, - 0x9fbf4899, 0x00062cd9, 0x3299bf00, 0xf4f9a65a, 0x6a3e1f0b, 0xa032003b, 0x2b3e0532, 0x3505003b, - 0x003b2f3e, 0x2f3e0205, 0xe97e003b, 0x85fb0042, 0xf430f428, 0x00062cdf, 0xbf22f900, 0x0149feff, - 0xfe149990, 0x9fa00142, 0x229094bd, 0x7e29a00c, 0x33004863, 0x0b5600a0, 0x2a9cda04, 0xbcb20000, + 0x9fbf4899, 0x0005dcd9, 0x3299bf00, 0xf4f9a65a, 0x6a3e1f0b, 0xa032003b, 0x2b3e0532, 0x3505003b, + 0x003b2f3e, 0x2f3e0205, 0xe97e003b, 0x85fb0042, 0xf430f428, 0x0005dcdf, 0xbf22f900, 0x0149feff, + 0xfe149990, 0x9fa00142, 0x229094bd, 0x7e29a00c, 0x33004863, 0x0b5600a0, 0x2844da04, 0xbcb20000, 0x397e2db2, 0xa032004e, 0x4300a433, 0x900141fe, 0x1ab21011, 0x003c087e, 0xa433a032, 0x1cbf3100, - 0xa4bd2bbf, 0x001428d1, 0xd1797e00, 0xb31aa000, 0x3d1a00a0, 0xd2117eb4, 0x00a0b300, 0x001abf12, - 0xd74b7eff, 0x3beb3e00, 0xfeff0000, 0x99900149, 0xd99fbf14, 0x0000062c, 0x0a3299bf, 0x0bf4f9a6, - 0x42e97e07, 0x0c25fb00, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x09f9a001, 0xbfa9a00e, 0x3de9bfff, - 0xf4f9a6a4, 0xe97e070b, 0x30f40042, 0xf400f804, 0x2cdfd830, 0xf9000006, 0xf4ffbf62, 0x49fef430, + 0xa4bd2bbf, 0x001324d1, 0xd1477e00, 0xb31aa000, 0x3d1a00a0, 0xd1df7eb4, 0x00a0b300, 0x001abf12, + 0xd7197eff, 0x3beb3e00, 0xfeff0000, 0x99900149, 0xd99fbf14, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x42e97e07, 0x0c25fb00, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x09f9a001, 0xbfa9a00e, 0x3de9bfff, + 0xf4f9a6a4, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdfd830, 0xf9000005, 0xf4ffbf62, 0x49fef430, 0x4c999001, 0xa93f9fa0, 0xa398a6b2, 0x01903301, 0x489d330d, 0x3c3e0360, 0x3018003e, 0x010d3304, - 0x3298011b, 0x04319803, 0xdc4ba43d, 0x01004c10, 0x000680d5, 0x40cb7e00, 0xb35aa000, 0xf80c00a4, - 0x3e050102, 0xfe003fb3, 0x99900149, 0x2af4d428, 0x1cb20000, 0xb50741b5, 0x2bb20191, 0xb5154035, + 0x3298011b, 0x04319803, 0xdc4ba43d, 0x01004c10, 0x000630d5, 0x40cb7e00, 0xb35aa000, 0xf80c00a4, + 0x3e050102, 0xfe003fb3, 0x99900149, 0x289cd428, 0x1cb20000, 0xb50741b5, 0x2bb20191, 0xb5154035, 0x92a00642, 0xdc4ed4bd, 0x26727e10, 0x33a13200, 0x015900ad, 0x993f59bf, 0x0d009033, 0xf0014998, - 0x49b50895, 0x0680d901, 0x99bf0000, 0x33699918, 0xdf130090, 0x00002af4, 0xf101f998, 0xb5400095, - 0xf4da01f9, 0x7e00002a, 0x9800b9ce, 0x027e0230, 0xebd90001, 0xb20000a6, 0x0091b0ac, 0xb4bd0db2, - 0xc8da04bd, 0xb000002f, 0x01300101, 0x7e010e08, 0xd90013c8, 0x00002af4, 0x000000df, 0x5090351e, - 0x900149fe, 0x42fe3499, 0x909fa001, 0x010a3822, 0xcd7e2bb2, 0xa43300b1, 0x2bbf1b1f, 0xf401b9c4, - 0xb5f0141b, 0xa0010a01, 0xb20f7e2b, 0x1fa03300, 0xbd09f806, 0x7e020ab4, 0xda00b20f, 0x00002af4, - 0x00b85d7e, 0xbd014afe, 0x0dc4bdb4, 0x34aa9001, 0x0090537e, 0x003e0d3e, 0x32020433, 0x000680d9, - 0xb39abf00, 0xd97f00a0, 0x00002b0c, 0xbf019c98, 0xd9f43d9b, 0x00002af4, 0x9f35d4bd, 0x10dc4e15, - 0x0026727e, 0x083ea132, 0x0d33003e, 0x7e020703, 0x1800010e, 0x90330839, 0x3e982400, 0x2b94d903, - 0x9cdf0000, 0xa000002b, 0x043e989e, 0x98019eb5, 0xf9a00539, 0xb5063e98, 0x391801fe, 0x0090331c, - 0x2af4df21, 0x39980000, 0x2dfe9808, 0xfd2efd98, 0xf9b5059e, 0x0939982d, 0xb5059dfd, 0x087e2ef9, + 0x49b50895, 0x0630d901, 0x99bf0000, 0x33699918, 0xdf130090, 0x0000289c, 0xf101f998, 0xb5400095, + 0x9cda01f9, 0x7e000028, 0x9800b99c, 0x027e0230, 0xb9d90001, 0xb20000a6, 0x0091b0ac, 0xb4bd0db2, + 0x70da04bd, 0xb000002d, 0x01300101, 0x7e010e08, 0xd90013c8, 0x0000289c, 0x000000df, 0x5090351e, + 0x900149fe, 0x42fe3499, 0x909fa001, 0x010a3822, 0x9b7e2bb2, 0xa43300b1, 0x2bbf1b1f, 0xf401b9c4, + 0xb5f0141b, 0xa0010a01, 0xb1dd7e2b, 0x1fa03300, 0xbd09f806, 0x7e020ab4, 0xda00b1dd, 0x0000289c, + 0x00b82b7e, 0xbd014afe, 0x0dc4bdb4, 0x34aa9001, 0x0090217e, 0x003e0d3e, 0x32020433, 0x000630d9, + 0xb39abf00, 0xd97f00a0, 0x000028b4, 0xbf019c98, 0xd9f43d9b, 0x0000289c, 0x9f35d4bd, 0x10dc4e15, + 0x0026727e, 0x083ea132, 0x0d33003e, 0x7e020703, 0x1800010e, 0x90330839, 0x3e982400, 0x293cd903, + 0x44df0000, 0xa0000029, 0x043e989e, 0x98019eb5, 0xf9a00539, 0xb5063e98, 0x391801fe, 0x0090331c, + 0x289cdf21, 0x39980000, 0x2dfe9808, 0xfd2efd98, 0xf9b5059e, 0x0939982d, 0xb5059dfd, 0x087e2ef9, 0x143d0001, 0x003e0d3e, 0xab001d33, 0x016b1801, 0x817e3ab2, 0x0209000f, 0x90014ffe, 0xf92048ff, 0xf935943d, 0x03331802, 0xb4bd0409, 0xf335fab2, 0x01f93503, 0x000f717e, 0x003fb33e, 0xfe0140fe, - 0x00900141, 0x40119044, 0xb20142fe, 0x3c22900a, 0x2cb21bb2, 0x537ed43d, 0x39980090, 0x0a0fbf02, - 0xf4f9a601, 0x70de3c1b, 0x3f000005, 0x009033e9, 0x0a943d0e, 0x3ee9201e, 0xd9003e9f, 0x200000ff, - 0xb394f9ff, 0xb2121c94, 0xb21bb20a, 0xb6647e2c, 0x3e9f3e00, 0xb20ab200, 0x7e2cb21b, 0xfe00a9ff, + 0x00900141, 0x40119044, 0xb20142fe, 0x3c22900a, 0x2cb21bb2, 0x217ed43d, 0x39980090, 0x0a0fbf02, + 0xf4f9a601, 0x24de3c1b, 0x3f000005, 0x009033e9, 0x0a943d0e, 0x3ee9201e, 0xd9003e9f, 0x200000ff, + 0xb394f9ff, 0xb2121c94, 0xb21bb20a, 0xb6327e2c, 0x3e9f3e00, 0xb20ab200, 0x7e2cb21b, 0xfe00a9cd, 0xbb90014b, 0xc4bebf44, 0xffdf1fa9, 0xb6e0ffff, 0xeffd1894, 0xe59eff04, 0x00d9bea0, 0xff400000, 0x0bf494e9, 0x1fa4336b, 0x0149fe68, 0xbf409990, 0x0499929d, 0xe4339cbf, 0x03df421e, 0x89ff0000, 0xff3fffff, 0xd9fff4ef, 0x0294b694, 0xb3e5f9ff, 0xc50b00c0, 0x093e03e9, 0xfd09003f, 0xfd16df95, 0xf0b304e9, 0xe9c50d00, 0x3eb9a001, 0x09003f2d, 0x94e9fffe, 0x003f093e, 0x000000df, 0xffffd9ff, 0xefff00ff, 0x94d9fff4, 0xa005f9fd, 0x0149febf, 0x90014ffe, 0xff904099, 0xbf9ebf44, 0x049992ff, - 0x99929dbf, 0x929fa004, 0x9ea00499, 0xa0049992, 0x0a747e9d, 0x2af4d900, 0x99180000, 0x00943348, + 0x99929dbf, 0x929fa004, 0x9ea00499, 0xa0049992, 0x0a747e9d, 0x289cd900, 0x99180000, 0x00943348, 0x3e02f80a, 0x33003f6b, 0xfe1e0190, 0xee90014e, 0xdfe9bf38, 0xe0ffffff, 0xdf049ffd, 0x01000000, - 0xa0059ffd, 0xd9f43de9, 0x00002af4, 0x9f35010d, 0x014bfe48, 0x90014cfe, 0xcc9034bb, 0x014afe30, - 0x7e38aa90, 0x7e009053, 0x3d000a9b, 0x3fb33e14, 0xfee40100, 0x99900149, 0xd99fbf4c, 0x0000062c, + 0xa0059ffd, 0xd9f43de9, 0x0000289c, 0x9f35010d, 0x014bfe48, 0x90014cfe, 0xcc9034bb, 0x014afe30, + 0x7e38aa90, 0x7e009021, 0x3d000a9b, 0x3fb33e14, 0xfee40100, 0x99900149, 0xd99fbf4c, 0x000005dc, 0x1a3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0c30f400, 0x922865fb, 0x9ba004a9, 0xb548ae92, 0x008906ec, - 0xe9a03000, 0x94bdafb2, 0xb24cff92, 0xf8f9a0fa, 0x7e02f900, 0xb300715d, 0xbd0a00a4, 0x40373e04, + 0xe9a03000, 0x94bdafb2, 0xb24cff92, 0xf8f9a0fa, 0x7e02f900, 0xb300714f, 0xbd0a00a4, 0x40373e04, 0x16898900, 0x0093fe00, 0x00163389, 0x890090fe, 0xfe001671, 0xa4bd0091, 0x897eb4bd, 0xa0b2000a, 0xf400a6b0, 0xa4bd0c1f, 0x7efe0b4b, 0x7e000a95, 0x3e004140, 0xb200162b, 0x7e01fb0a, 0xf8000ad6, 0x8f22f900, 0xb200ffff, 0xf4bfa6c0, 0xc0b3720c, 0xc9926f00, 0x049cfd01, 0xa6651bf4, 0x600cf4cf, - 0x0903bf90, 0x14f9fffc, 0x7e550bf4, 0x82000a74, 0x7f003244, 0x3240892d, 0x899abf00, 0xc2003246, + 0x0903bf90, 0x14f9fffc, 0x7e550bf4, 0x82000a74, 0x7f003044, 0x3040892d, 0x899abf00, 0xc2003046, 0x9b7f0f0f, 0x5201ff79, 0x907c01d9, 0xc4f9ff90, 0x08f4cd66, 0xd0c17c21, 0xffffd9e4, 0x08f491a6, 0xf4db6615, 0xc9e4100c, 0x2d60ffff, 0x3e009abc, 0xbd0040b5, 0x0a9b7e04, 0x40bf3e00, 0xb204bd00, 0x0c21fb0a, 0x40417e04, 0xf900f800, 0x7eb1b212, 0xb2004041, 0x00a0b3a0, 0xbd1cb20c, 0x0b947eb4, - 0xfb0ab200, 0x7e040c11, 0xf80040cb, 0x3dabb200, 0x40e57ea4, 0x8f00f800, 0xbf001110, 0x1b9918f9, - 0x20069536, 0x18f9bfa9, 0x99c71b99, 0xf8b92024, 0x11108c00, 0x14cdbf00, 0xbec406af, 0x04e43603, + 0xfb0ab200, 0x7e040c11, 0xf80040cb, 0x3dabb200, 0x40e57ea4, 0x8f00f800, 0xbf0010d4, 0x1b9918f9, + 0x20069536, 0x18f9bfa9, 0x99c71b99, 0xf8b92024, 0x10d48c00, 0x14cdbf00, 0xbec406af, 0x04e43603, 0xf01bd918, 0xf9fd3f94, 0x1bdf3505, 0xf918cfbf, 0xcf94f01b, 0x3505e9fd, 0x327e1bfe, 0x00f80019, - 0x00111089, 0x9a1899bf, 0x24abc71b, 0x7e06a536, 0xf8001932, 0x18ff7e00, 0xf400f800, 0x82f9e030, + 0x0010d489, 0x9a1899bf, 0x24abc71b, 0x7e06a536, 0xf8001932, 0x18ff7e00, 0xf400f800, 0x82f9e030, 0xffffc1e4, 0xb210c295, 0xffa0e4c5, 0x10a395ff, 0x48fea4b2, 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, 0x1ab28aa0, 0x0016fc7e, 0xa6b20bb2, 0xfc7e2ab2, 0x3bb20016, 0x1ab2a0b2, 0x0016fc7e, 0xa1b23bb2, 0xfc7e2ab2, 0x10bc0016, 0x10699500, 0x09bcadb2, 0xf410a600, 0x00890a0d, @@ -566,88 +566,88 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x9801afb5, 0xaabf01ab, 0xf81030f4, 0x014afe00, 0xbd019fb9, 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x483eaabf, 0x30f40042, 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, 0x0096b002, 0xbc211df4, 0x4efef4bc, 0x95a9bc01, 0xbc059ffd, 0xe9b5f4ac, 0x98efa001, 0xeabf01eb, 0xf81030f4, - 0x014efe00, 0xbd019fb9, 0xf4afbc94, 0xefb5e9a0, 0x98eabf01, 0x9c3e01eb, 0x2cde0042, 0xbf000006, - 0xfc30f4e9, 0xdd014ffe, 0x00000000, 0x34d9f9a0, 0xbf000014, 0xbf9da0ff, 0xa6a43de9, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, 0x00062cdf, 0xbf12f900, + 0x014efe00, 0xbd019fb9, 0xf4afbc94, 0xefb5e9a0, 0x98eabf01, 0x9c3e01eb, 0xdcde0042, 0xbf000005, + 0xfc30f4e9, 0xdd014ffe, 0x00000000, 0x30d9f9a0, 0xbf000013, 0xbf9da0ff, 0xa6a43de9, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001cb1, 0x3f80014a, 0xaa904c4b, 0x7ea1b208, 0x8a001581, 0x7e12004c, 0xf0001c22, 0x1bf43fa4, 0x3e010a09, 0xb2004346, 0x159c7e1a, 0xf4a0a600, - 0x02f8e40d, 0x49fea43d, 0x10999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x15fb0042, - 0xfc30f40c, 0x00062cdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb39fa0b1, 0xb02101a0, 0x08f401a6, + 0x02f8e40d, 0x49fea43d, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, + 0xfc30f40c, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb39fa0b1, 0xb02101a0, 0x08f401a6, 0xb3ff0e0e, 0x00be02ad, 0x0044113e, 0x0049020f, 0x009ff60a, 0x00441f3e, 0xcf0a0049, 0xfe0e009f, 0xf604fefd, 0xd033009f, 0x004f2d00, 0x00f9cf08, 0xf9f694bd, 0x09004000, 0x4b0009cf, 0xcab203e8, 0x0016fc7e, 0x0200aab8, 0x0aa5b600, 0x3e000af6, 0x400043f9, 0x09cf0800, 0x03e84b00, 0xfc7ecab2, - 0xaab80016, 0xb6000200, 0xaa920aa5, 0x000af601, 0xcf090049, 0x9af6009f, 0x2a4cd900, 0x004f0000, + 0xaab80016, 0xb6000200, 0xaa920aa5, 0x000af601, 0xcf090049, 0x9af6009f, 0x2828d900, 0x004f0000, 0x0191b50a, 0xf000f9cf, 0xf9f60195, 0x443f3e00, 0x0a004e00, 0x0f00e9cf, 0x049ffdfe, 0x4f00e9f6, - 0xf9cf0800, 0xf694bd00, 0x004f00f9, 0x00f9cf09, 0xf9f694bd, 0xd9f4bd00, 0x00002a4c, 0x3d019fb5, - 0x0149fee4, 0xbf089990, 0x062cd99f, 0x99bf0000, 0xf9a6ea32, 0x7e070bf4, 0xfb0042e9, 0x2cdf0415, - 0xbf000006, 0xfc30f4ff, 0xa00149fe, 0x2a4cd99f, 0x99980000, 0x0194b301, 0x7e797e0c, 0x44833e00, - 0xfe02f800, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, - 0x2cd122f9, 0xbf000006, 0xfea2b219, 0x148a0140, 0x009008d1, 0x7e09a00c, 0x3f001c22, 0xbf0ebf29, - 0x08aac71f, 0xa6ff94f0, 0x0bacf0a9, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xdffc30f4, 0x0000062c, + 0xf9cf0800, 0xf694bd00, 0x004f00f9, 0x00f9cf09, 0xf9f694bd, 0xd9f4bd00, 0x00002828, 0x3d019fb5, + 0x0149fee4, 0xbf089990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, + 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x2828d99f, 0x99980000, 0x0194b301, 0x7e6b7e0c, 0x44833e00, + 0xfe02f800, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, + 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x148a0140, 0x009008d1, 0x7e09a00c, 0x3f001c22, 0xbf0ebf29, + 0x08aac71f, 0xa6ff94f0, 0x0bacf0a9, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xdffc30f4, 0x000005dc, 0xffbf02f9, 0x900149fe, 0x9fa00499, 0x0189008f, 0xf000f9ce, 0xf9f78095, 0x43004e00, 0x0f00e9ce, - 0x049ffdfe, 0xd000e9f7, 0x0000140c, 0xaab80abf, 0x7e00034c, 0xbf001c22, 0x03abc509, 0x034c9ab8, - 0x1cb17e00, 0x0149fe00, 0xbf049990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, - 0xdffc30f4, 0x0000062c, 0xffbf12f9, 0xfef430f4, 0x99900149, 0x8f9fa014, 0xcf01c000, 0x99c700f9, + 0x049ffdfe, 0xd000e9f7, 0x0000130c, 0xaab80abf, 0x7e00034c, 0xbf001c22, 0x03abc509, 0x034c9ab8, + 0x1cb17e00, 0x0149fe00, 0xbf049990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, + 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0xfef430f4, 0x99900149, 0x8f9fa014, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30085, 0x02f8f501, 0x00455b3e, 0xc700f9cf, 0x90b34c99, 0x90b35f00, 0x02f8f601, 0x0045703e, 0x001b957e, 0x0bb204bd, 0xd4bdc4bd, 0x6b7e0b0a, 0xa1900024, 0x7e1ab268, 0xe4001c22, 0xb30e00ab, 0x0b0e00be, 0xb17e1ab2, 0x0090001c, 0x2404b301, 0xbd94bdd9, 0x089130b4, 0xb00091b0, - 0xc4bd0191, 0xe43dd4bd, 0x001414da, 0x13c87e00, 0x46073e00, 0xc2008900, 0x0099cf01, 0xf40194f0, + 0xc4bd0191, 0xe43dd4bd, 0x001310da, 0x13c87e00, 0x46073e00, 0xc2008900, 0x0099cf01, 0xf40194f0, 0x843e280b, 0x1c8f0045, 0x00890285, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, - 0x3e9fb200, 0xfe004570, 0x99900149, 0xd99fbf14, 0x0000062c, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, - 0x15fb0c30, 0xfc30f404, 0x2cd112f9, 0xbf000006, 0xf430f419, 0x1c8ab4bd, 0x40fe0285, 0x14009001, - 0xb17e09a0, 0x027e001c, 0x40d90001, 0xb0000045, 0x94bd0091, 0x9130acb2, 0x0191b008, 0x001414da, + 0x3e9fb200, 0xfe004570, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, + 0x15fb0c30, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0xf430f419, 0x1c8ab4bd, 0x40fe0285, 0x14009001, + 0xb17e09a0, 0x027e001c, 0x40d90001, 0xb0000045, 0x94bd0091, 0x9130acb2, 0x0191b008, 0x001310da, 0x4db4bd00, 0x010e2710, 0x0013c87e, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0c30f400, 0xf40415fb, - 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00280f, 0xa619bf0f, 0x070bf4f9, - 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0027d6, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, - 0x7e09a008, 0xbf00279d, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, + 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00280f, 0xa619bf0f, 0x070bf4f9, + 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0027d6, + 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, + 0x7e09a008, 0xbf00279d, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0028db, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, - 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00291c, 0xa619bf0f, 0x070bf4f9, - 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x00062cd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf0065ad, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, 0x0000062c, 0x30f4ffbf, 0x0149fefc, 0x008f9fa0, + 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00291c, 0xa619bf0f, 0x070bf4f9, + 0x0042e97e, 0xf40415fb, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf00659f, + 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, 0x000005dc, 0x30f4ffbf, 0x0149fefc, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x823e02f8, 0xf9cf0047, 0x4c99c700, 0x330090b3, 0xf60190b3, 0x963e02f8, 0x00890047, 0x9af601c1, 0x0099b800, 0x9bf60001, 0x00f2df00, 0x99b88000, - 0xf6020200, 0x9fcf009f, 0x3e9fb200, 0xfe004796, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0x062cdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x01c0008f, 0xc700f9cf, + 0xf6020200, 0x9fcf009f, 0x3e9fb200, 0xfe004796, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x01c0008f, 0xc700f9cf, 0x90b34c99, 0x90b32200, 0x02f8f601, 0x0047fc3e, 0xc700f9cf, 0x90b34c99, 0x90b33300, 0x02f8f601, 0x0048103e, 0x01c10089, 0xb8009af6, 0x00010099, 0xdf009bf6, 0x800000f2, 0x020099b8, 0x009ff602, - 0xb2009fcf, 0x48103e9f, 0x0149fe00, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x1ed9f9a0, 0xbf000011, 0xbf9a3fff, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xf400f804, 0x42f9f030, 0x00062cd4, 0xb249bf00, 0xbd0601a2, 0xfe1cb2b4, + 0xb2009fcf, 0x48103e9f, 0x0149fe00, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, + 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0xe2d9f9a0, 0xbf000010, 0xbf9a3fff, 0xf4f9a6e9, + 0xe97e070b, 0x30f40042, 0xf400f804, 0x42f9f030, 0x0005dcd4, 0xb249bf00, 0xbd0601a2, 0xfe1cb2b4, 0x43fe0140, 0x16009001, 0xb2203390, 0x7e39a00a, 0xbd000b94, 0x014dfe94, 0xa01cdd90, 0x75d120d9, 0x29180209, 0xb22ab204, 0x20c4bd0b, 0x35180909, 0x01090109, 0x7e010975, 0xbf003493, 0xa649bf3f, - 0x070bf4f9, 0x0042e97e, 0xf41045fb, 0x2cdfec30, 0xf9000006, 0xfeffbf22, 0x99900149, 0xa0a1b21c, + 0x070bf4f9, 0x0042e97e, 0xf41045fb, 0xdcdfec30, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a1b21c, 0xb2060c9f, 0x0140feb2, 0x0090b4bd, 0x7e0ab20e, 0xbd000b94, 0x014ffe94, 0xa018ff90, 0x041e18f9, 0x41fe1ab2, 0x14119001, 0x010919a0, 0x75020975, 0x05090109, 0x1909f920, 0x0bb20e20, 0xb2010935, - 0x7e1cb2fd, 0x32003493, 0x00a433a0, 0xb21abf0c, 0x2f7e7e2b, 0x0149fe00, 0xbf1c9990, 0x062cd99f, - 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0x30f41425, 0x062cd9f0, 0x42f90000, 0x4ffe99bf, + 0x7e1cb2fd, 0x32003493, 0x00a433a0, 0xb21abf0c, 0x2f7e7e2b, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, + 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0x30f41425, 0x05dcd9f0, 0x42f90000, 0x4ffe99bf, 0x20ff9001, 0xf9a0a3b2, 0xe84bbab2, 0x16fc7e03, 0x0142fe00, 0x04bda1b2, 0x90014afe, 0xaa901c22, 0x7ea4b214, 0x3e001581, 0xb20049b7, 0x159c7e4a, 0x7ea0b200, 0xb200000e, 0x7e2bb23a, 0x330048eb, 0xbf1600a4, 0x0194f029, 0x0d009033, 0x08f401a6, 0x49e03edd, 0xf401a600, 0xa43d0918, 0x0049e23e, - 0x49fe040a, 0x20999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x45fb0042, 0xf030f410, - 0x00062cdf, 0xbf22f900, 0x0149feff, 0x32189990, 0xa0a2b2b0, 0x488b7e9f, 0x00a43300, 0x00043364, + 0x49fe040a, 0x20999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x45fb0042, 0xf030f410, + 0x0005dcdf, 0xbf22f900, 0x0149feff, 0x32189990, 0xa0a2b2b0, 0x488b7e9f, 0x00a43300, 0x00043364, 0x3e143d0a, 0x18004a30, 0x94f01129, 0x0291140f, 0x060cb4bd, 0x900140fe, 0x0ab20e00, 0x000b947e, 0x4ffe94bd, 0x14ff9001, 0xf135f9a0, 0x02097501, 0xb2042918, 0xb2fdb20b, 0x0909202a, 0x09f92001, 0x01093518, 0xc4bd0209, 0x7e010975, 0x33003493, 0xb20e00a4, 0x86a08b2a, 0x49727e01, 0x0149fe00, - 0xbf189990, 0x062cd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x1025fb00, 0xd9f030f4, 0x0000062c, + 0xbf189990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x1025fb00, 0xd9f030f4, 0x000005dc, 0x99bf22f9, 0x90014ffe, 0xa1b218ff, 0xb2b2f9a0, 0xb4bd060c, 0x90014afe, 0x947e0eaa, 0x94bd000b, 0xb20140fe, 0x1400901a, 0x8b7e09a0, 0xa4330048, 0x19186100, 0x0499c711, 0x0a0094b3, 0xe43e2009, 0xd709004a, 0x19180920, 0x014efe04, 0xfe0eee90, 0xe920014f, 0x90102995, 0xf93514ff, 0x08299501, 0x0902f935, 0x01e93518, 0xe9750409, 0xb2947d01, 0x03f235eb, 0xe975fdb2, 0xbd1ab202, 0x34937ec4, - 0x00a43300, 0x8b1ab20e, 0x7e07a120, 0xfe004972, 0x99900149, 0xd99fbf18, 0x0000062c, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f41025, 0x062cdfec, 0x72f90000, 0x49feffbf, 0x30999001, 0x9fa0a1b2, + 0x00a43300, 0x8b1ab20e, 0x7e07a120, 0xfe004972, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, + 0x7e070bf4, 0xfb0042e9, 0x30f41025, 0x05dcdfec, 0x72f90000, 0x49feffbf, 0x30999001, 0x9fa0a1b2, 0xc3b2b7b2, 0xa9b3d672, 0x71009e00, 0xf50100d6, 0xbd00950c, 0x0cb4bd54, 0x0140fe06, 0x900142fe, 0x22902000, 0x7505a02c, 0x25a00205, 0x900144fe, 0x4ab22644, 0x000b947e, 0x8b7e1ab2, 0xa4330048, 0x23356800, 0x04191803, 0x05750bb2, 0x202db202, 0x20020909, 0x10399529, 0x95012935, 0x29350839, 0x35080902, 0x04090109, 0x09751ab2, 0x7ec4bd01, 0x33003493, 0x753300a4, 0x45750146, 0x04191802, 0x7db24bb2, 0x49201ab2, 0xc4bd1009, 0x7e014935, 0x33003493, 0xb21300a4, 0x32004b1a, 0x0049727e, - 0x004c063e, 0x49fe350a, 0x30999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x75fb0042, - 0xfc30f414, 0x00062cdf, 0xbf62f900, 0xfea3b2ff, 0x99900149, 0x989fa01c, 0xc4b205aa, 0xfd09d6b2, + 0x004c063e, 0x49fe350a, 0x30999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x75fb0042, + 0xfc30f414, 0x0005dcdf, 0xbf62f900, 0xfea3b2ff, 0x99900149, 0x989fa01c, 0xc4b205aa, 0xfd09d6b2, 0xbebcaebf, 0x01ef9220, 0x0cf4f9a6, 0x01af9823, 0xf9a6ff09, 0xb3190bf4, 0xa61600f0, 0x1008f42e, 0xa690c2bc, 0x0808f492, 0x0df49fa6, 0x1802f805, 0x010a1139, 0xb30599c7, 0xb2410094, 0x32aa7e3a, 0x33a53200, 0xbd3300a4, 0x4cb13e14, 0x0241bc00, 0x010006b1, 0x40060df4, 0x3ab20100, 0xb2b061bc, 0x7e0d722c, 0x33004b4a, 0xbc1100a4, 0x10bc2020, 0xf414a610, 0x5a32da08, 0x900149fe, 0x9fbf1c99, - 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40465fb, 0x2cd9fc30, 0xf9000006, 0xfe99bf72, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40465fb, 0xdcd9fc30, 0xf9000005, 0xfe99bf72, 0xff90014f, 0xa0a0b220, 0x05ae98f9, 0xfd02c5b2, 0xf992efbf, 0xf492a601, 0xee98260c, 0xa6ff0101, 0x1c0bf4e1, 0x1900e0b3, 0xa630bfbc, 0x1008f43f, 0xa690c3bc, 0x0808f493, 0x0df49ea6, 0x0e02f80b, 0x4dc33e35, 0x11a91800, 0x99c7010e, 0x009db305, 0xaa7e0096, 0xa4320032, 0x8900ad33, 0xb227b200, @@ -655,20 +655,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x01f99821, 0x0bf496a6, 0x0090b319, 0xb20ab216, 0x35247e1b, 0x00a03300, 0x3e030e0a, 0xb2004dc3, 0x7e1bb20a, 0x32004a98, 0x00a433ae, 0x060f983a, 0x9992f9bf, 0xf497a601, 0xf9981d0c, 0xf496a601, 0x90b3150b, 0x1bb21200, 0x9f7e0ab2, 0xae320035, 0x1300a433, 0x100022b8, 0x1023bc00, 0x08f425a6, - 0xfe4e3289, 0x99900149, 0xd99fbf20, 0x0000062c, 0xea3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0475fb00, - 0xd9fc30f4, 0x0000062c, 0x99bf02f9, 0x90014ffe, 0xb0b204ff, 0xb9bff9a0, 0xa6b0c9bc, 0x1708f4b9, + 0xfe4e3289, 0x99900149, 0xd99fbf20, 0x000005dc, 0xea3299bf, 0x0bf4f9a6, 0x42e97e07, 0x0475fb00, + 0xd9fc30f4, 0x000005dc, 0x99bf02f9, 0x90014ffe, 0xb0b204ff, 0xb9bff9a0, 0xa6b0c9bc, 0x1708f4b9, 0xffffd9e4, 0xa6f09bbc, 0x0b08f4fb, 0xa6010998, 0x050df4f9, 0xdc7202f8, 0xaa7eedb2, 0x49fe0031, - 0x04999001, 0x2cd99fbf, 0xbf000006, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0x2cd112f9, - 0xbf000006, 0x0140fe19, 0xb2080090, 0xb209a0cf, 0x05ab98b9, 0x9cb2deb2, 0xe07efd72, 0x0fbf004d, + 0x04999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, + 0xbf000005, 0x0140fe19, 0xb2080090, 0xb209a0cf, 0x05ab98b9, 0x9cb2deb2, 0xe07efd72, 0x0fbf004d, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0xf0fc0415, 0xf9fc30f4, 0xf430f4f0, 0x90b472f9, 0xfeb0b20d, - 0xbb90014b, 0x01b9b520, 0x00062cd9, 0xfe99bf00, 0xff90014f, 0xa0a5b228, 0xa009bff9, 0x0ce1b0be, + 0xbb90014b, 0x01b9b520, 0x0005dcd9, 0xfe99bf00, 0xff90014f, 0xa0a5b228, 0xa009bff9, 0x0ce1b0be, 0xc9bcd4b2, 0xf439a630, 0xd3bc1f08, 0xf4f3a6f0, 0x09981708, 0xf4f9a601, 0xb6b20f0c, 0x010024bd, 0x273efc07, 0x02f8004f, 0x2c3e0100, 0x42bc004f, 0x0096b192, 0x060df401, 0x90010049, 0xb4bd0399, - 0x4c1497ff, 0x00da0100, 0x7e000012, 0xb2000b94, 0x723bb25a, 0x1200dd1c, 0xaa7e0000, 0xa0320031, - 0x2c00a433, 0x6c986bbf, 0x1200da01, 0x2db20000, 0x7e01004e, 0x330026d8, 0xf80a00a0, 0x4f2c3e02, - 0x3031bc00, 0xa62021bc, 0xa508f424, 0x900149fe, 0x9fbf2899, 0x00062cd9, 0x3299bf00, 0xf4f9a60a, - 0xe97e070b, 0x70fb0042, 0xfc0c30f4, 0x0430f4f0, 0x30f4f4f9, 0x062cdfe4, 0x42f90000, 0x49feffbf, - 0x2c999001, 0x9fa0a1b2, 0x00111ed9, 0x33993f00, 0x3d0a0090, 0x50c13e04, 0xfef4bd00, 0x99900149, + 0x4c1497ff, 0x00da0100, 0x7e000011, 0xb2000b94, 0x723bb25a, 0x1100dd1c, 0xaa7e0000, 0xa0320031, + 0x2c00a433, 0x6c986bbf, 0x1100da01, 0x2db20000, 0x7e01004e, 0x330026d8, 0xf80a00a0, 0x4f2c3e02, + 0x3031bc00, 0xa62021bc, 0xa508f424, 0x900149fe, 0x9fbf2899, 0x0005dcd9, 0x3299bf00, 0xf4f9a60a, + 0xe97e070b, 0x70fb0042, 0xfc0c30f4, 0x0430f4f0, 0x30f4f4f9, 0x05dcdfe4, 0x42f90000, 0x49feffbf, + 0x2c999001, 0x9fa0a1b2, 0x0010e2d9, 0x33993f00, 0x3d0a0090, 0x50c13e04, 0xfef4bd00, 0x99900149, 0x929fa024, 0x9fa00499, 0x98049992, 0xa49805a2, 0x7e9fa006, 0x32002fb6, 0x00a033a0, 0x2ea43308, 0x982bbf6b, 0xb9a60129, 0x013318f5, 0x0fffb9e4, 0x012b1bf5, 0xb20143fe, 0x1c33901a, 0x3db2040c, 0x0031aa7e, 0xa433a032, 0x3fbf4200, 0x4ad93500, 0xa6534646, 0x331bf4f9, 0xed7e1ab2, 0xa4330037, @@ -678,26 +678,26 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0104fdb2, 0x9f090920, 0x1909f920, 0x09010935, 0x01047503, 0xfe020975, 0x1ab20142, 0xb2242290, 0x34937e2c, 0x33a03200, 0xbf5a00a4, 0x7e1ab22b, 0x32002f12, 0x00a433a0, 0x1112184c, 0xb30529c7, 0xfe390094, 0x1ab20143, 0xb2203390, 0x48eb7e3b, 0x00a43300, 0x943fbf15, 0x94f00229, 0x049ffd3c, - 0x35060bf4, 0x1ab22014, 0xfd7eb43d, 0xa0330049, 0xa0320a00, 0x0050c13e, 0x1ed9010f, 0x20000011, - 0x0149fe9f, 0xbf2c9990, 0x062cd99f, 0x99bf0000, 0xf9a60a32, 0x3e110bf4, 0x000050e1, 0x50083e02, - 0x42e97e00, 0x1c45fb00, 0x00062cdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0x982100a0, 0xfd0f06aa, + 0x35060bf4, 0x1ab22014, 0xfd7eb43d, 0xa0330049, 0xa0320a00, 0x0050c13e, 0xe2d9010f, 0x20000010, + 0x0149fe9f, 0xbf2c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x3e110bf4, 0x000050e1, 0x50083e02, + 0x42e97e00, 0x1c45fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0x982100a0, 0xfd0f06aa, 0x9992a9bf, 0xf49fa601, 0xaa98110c, 0xa6ff0901, 0x070bf4a9, 0x0c00a4b3, 0x020a02f8, 0x00516b3e, - 0x0fffb9e4, 0x1bf4020a, 0x2ad4d945, 0x9f980000, 0x51633e04, 0x08f91800, 0x28009033, 0x3309f918, + 0x0fffb9e4, 0x1bf4020a, 0x287cd945, 0x9f980000, 0x51633e04, 0x08f91800, 0x28009033, 0x3309f918, 0x58210090, 0xfe5802f9, 0x0093f003, 0xa60c94b6, 0x0f08f4b9, 0xffffe9e4, 0xa60c94b6, 0x0a0df4b9, - 0xb304ff98, 0xa0d200f4, 0xfe350acf, 0x9fbf0149, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xf80430f4, 0xf830f400, 0x00062cdf, 0xbf52f900, 0xfea4b2ff, 0x42fe0149, 0x1c999001, 0xc3b2b0b2, + 0xb304ff98, 0xa0d200f4, 0xfe350acf, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, + 0xf80430f4, 0xf830f400, 0x0005dcdf, 0xbf52f900, 0xfea4b2ff, 0x42fe0149, 0x1c999001, 0xc3b2b0b2, 0x9fa0d5b2, 0x350a14bd, 0x3e182290, 0xb200523c, 0x0c0bb24a, 0x7e2db204, 0x330031aa, 0x008900ad, 0x94b329bf, 0x11900e00, 0x04009020, 0x00523c3e, 0xfd019eb9, 0x008904e9, 0xe9ffff00, 0x0bfcf094, 0xd901f6f0, 0xff00ff00, 0xf094e9ff, 0xb6f00bbc, 0xf0f0d901, 0xe9fff0f0, 0x0bccf094, 0xd901c6f0, 0xcccccccc, 0xf094e9ff, 0xd6f00bdc, 0xaaaad901, 0xf4b6aaaa, 0x03b4b604, 0xb602c4b6, 0xe9fd01d4, 0x0b9cf004, 0xfd0196f0, 0xfbfd05f9, 0x05fcfd05, 0xa005fdfd, 0x101fbc2f, 0x0052423e, 0x0df503a6, - 0x51a0ff71, 0x900149fe, 0x9fbf1c99, 0x00062cd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, - 0x2cdffc30, 0xf9000006, 0xb2ffbf42, 0xfec2b2a0, 0xe3b20149, 0xb2149990, 0xb29fa0b4, 0x3ec4bdea, + 0x51a0ff71, 0x900149fe, 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40855fb, + 0xdcdffc30, 0xf9000005, 0xb2ffbf42, 0xfec2b2a0, 0xe3b20149, 0xb2149990, 0xb29fa0b4, 0x3ec4bdea, 0xf00052de, 0xf99407e2, 0xf0ffbc03, 0xbcf0f9bc, 0xbe3ff0fe, 0x9030ff92, 0xbab201bb, 0x3030e912, 0x0df40996, 0x00f4b3e1, 0x33010f06, 0x312d64e0, 0xf40064e6, 0xe4330b1c, 0xca3e2862, 0xe0330052, 0xe4330c73, 0xd13e1c77, 0xcfbc0052, 0x52de3ec0, 0x90ffbc00, 0x0052db3e, 0xbc02f994, 0xae3fc0c9, 0x0d00e033, 0xbd01ab90, 0x529a3ef4, 0x20c6b000, 0xf8090df4, 0x54063e02, 0x00d0b300, 0xbfdca006, - 0x90c2bc0f, 0x9fa6ff01, 0x01000cf5, 0x002a9cda, 0x07a99800, 0xbf010098, 0xbc0db29b, 0xaa7eb02b, + 0x90c2bc0f, 0x9fa6ff01, 0x01000cf5, 0x002844da, 0x07a99800, 0xbf010098, 0xbc0db29b, 0xaa7eb02b, 0xa1320031, 0xe400ad33, 0xb242b200, 0xff00440a, 0x0053f73e, 0xc203c994, 0xccbc07be, 0xbcdb3ff0, 0xdd90f0f9, 0xf0febc01, 0xb230fc92, 0x30b912d3, 0xf4099630, 0xc4b3e10d, 0x010c0600, 0xf03e20b2, 0xb0330053, 0xb6315b64, 0x1cf40064, 0x62bd330c, 0x833e0099, 0xb0330053, 0xbd331973, 0x3e008c77, @@ -705,1104 +705,1104 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x53e63e05, 0x01a91800, 0xad90af3f, 0xff94f002, 0xb6fff4f0, 0x9fff0894, 0x53e63ef5, 0x03ad1800, 0x3f02af18, 0x01a918ae, 0xf018d4b6, 0xf4b6fff4, 0xffe4f010, 0xb6ff94f0, 0x9efd0894, 0x059ffd05, 0x90f59dff, 0x0fa004ad, 0x9001cc92, 0xdab20400, 0xcdb302b2, 0x3fff7000, 0x00b0333b, 0x013d900f, - 0x4b3ec4bd, 0xff010053, 0x900149fe, 0x9fbf1499, 0x00062cd9, 0x3299bf00, 0xf4f9a61a, 0xe97e070b, - 0x45fb0042, 0xf830f404, 0x2cd222f9, 0xbf000006, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, + 0x4b3ec4bd, 0xff010053, 0x900149fe, 0x9fbf1499, 0x0005dcd9, 0x3299bf00, 0xf4f9a61a, 0xe97e070b, + 0x45fb0042, 0xf830f404, 0xdcd222f9, 0xbf000005, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, 0xb2d4bd19, 0x0074de0b, 0x5f7e0000, 0x1fbf0052, 0x0a7f29bf, 0x0bf4f9a6, 0x42e97e07, 0x0825fb00, - 0xf9f830f4, 0x062cd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, + 0xf9f830f4, 0x05dcd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, 0x000076de, 0x525f7e00, 0xbf1fbf00, 0xa60abf29, 0x070bf4f9, 0x0042e97e, 0xf40825fb, 0x22f9f830, - 0x00062cd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, - 0x00525f7e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb0042e9, 0x30f40825, 0x062cdff0, 0x62f90000, - 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, 0x1c339000, 0x05242290, 0xbf040402, - 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2a9cda04, + 0x0005dcd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, + 0x00525f7e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb0042e9, 0x30f40825, 0x05dcdff0, 0x62f90000, + 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001304d6, 0x1c339000, 0x05242290, 0xbf040402, + 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2844da04, 0x94330000, 0x527e0a00, 0xa032004f, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, - 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40054ff, 0x2cdff430, 0xf9000006, 0xbdffbf22, - 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0xd4d21499, 0xa000002f, 0x7e01b29f, 0x3e008f2c, - 0x98005592, 0x993f0119, 0x0a099433, 0x2f7e0ab2, 0xc8da003c, 0x7e00002f, 0xb2001475, 0xb22abfad, - 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002fc8, 0x0014b57e, 0x0055923e, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, - 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, - 0x42e97e07, 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, - 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, - 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, - 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, - 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cde00f8, - 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, - 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, - 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, - 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, - 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, + 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40054ff, 0xdcdff430, 0xf9000005, 0xbdffbf22, + 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, 0xa000002d, 0x7e01b29f, 0x3e008efa, + 0x98005592, 0x993f0119, 0x0a099433, 0x2f7e0ab2, 0x70da003c, 0x7e00002d, 0xb2001475, 0xb22abfad, + 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002d70, 0x0014b57e, 0x0055923e, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, + 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, + 0x42e97e07, 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, + 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, + 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, + 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, + 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcde00f8, + 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, + 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, + 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, + 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, + 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, + 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, + 0x014ffefc, 0x943df9a0, 0xffbfa920, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, - 0x062cde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0x2cde00f8, 0xbf000006, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xde00f804, 0x0000062c, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, - 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x00062cde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, - 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x062cde00, 0xe9bf0000, 0xfefc30f4, - 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x062cdffc, - 0x12f90000, 0x30f4ffbf, 0x0149fed4, 0xa0349990, 0x49ff0f9f, 0x9ff70500, 0x5c997e00, 0x71c67e00, - 0x42ba7e00, 0x5f737e00, 0x00a93300, 0x060f02d6, 0xf7110049, 0x837e009f, 0xed7e005e, 0xb57e005e, - 0xbf7e0061, 0x1f7e005b, 0xb17e0064, 0xe67e0064, 0x657e005c, 0x497e0065, 0x7e7e0066, 0xe27e0066, - 0x387e0066, 0x8e7e0067, 0xe47e0067, 0xc37e0067, 0xb77e0089, 0x847e0068, 0x797e006d, 0x617e0063, - 0x314c0068, 0x00c3f177, 0x01943d00, 0x28913002, 0x30009130, 0x91300891, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x300111b0, 0x10da0c11, 0xdb000006, 0x0000018c, 0x804e010d, 0x71d87e00, - 0x00ad3300, 0x08da023e, 0x0b000014, 0x7e010c04, 0x33006e05, 0x022c00ad, 0xf17ed24c, 0x000000c3, + 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, + 0x0430f400, 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0x20943df9, 0xbfffbfa9, 0xf4f9a6e9, + 0xe97e070b, 0x30f40042, 0xde00f804, 0x000005dc, 0x30f4e9bf, 0x014ffefc, 0x943df9a0, 0xffbfa920, + 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4e9bf00, 0x4ffefc30, 0x3df9a001, + 0xbfa92094, 0xa6e9bfff, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, + 0xf9a0014f, 0xa920943d, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x05dcdffc, + 0x12f90000, 0x30f4ffbf, 0x0149fed4, 0xa0349990, 0x49ff0f9f, 0x9ff70500, 0x5c997e00, 0x71b87e00, + 0x42ba7e00, 0x5f737e00, 0x00a93300, 0x060f02d6, 0xf7110049, 0x837e009f, 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0xbd5d0bf4, + 0xbdc4bdb4, 0x7e0d0ad4, 0x0c00246b, 0xb2d4bd01, 0x0ab4bda1, 0x246b7e0e, 0x90a0b200, 0x227e0c1a, + 0xabc5001c, 0x0c0a9010, 0x001cb17e, 0xc4bdb4bd, 0x0f0ad4bd, 0x00246b7e, 0xa1b2b4bd, 0xd4bd010c, + 0x6b7e100a, 0xa0b20024, 0x7e0c1a90, 0xc5001c22, 0x0a9010ab, 0x1cb17e0c, 0x0149fe00, 0xbf089990, + 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, + 0x900140fe, 0x28da0800, 0xa0000028, 0x1330d909, 0x99bf0000, 0xf9119998, 0xbf0fbf95, 0xf4f9a619, + 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0x0140fe19, 0x0090a4bd, 0xa0b4bd08, + 0x3dc4bd09, 0x43617ed4, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xffbf0000, + 0xfefc30f4, 0x30da0149, 0xa0000028, 0x7eb43d9f, 0xd900733f, 0x00002830, 0x94b399bf, 0x02f80600, + 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, + 0x000005dc, 0x40fe19bf, 0x08009001, 0x002d8bda, 0xd909a000, 0x00001330, 0x943d9fbf, 0xf998a920, + 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0xcf007af7, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8f007b0b, + 0xcf01c200, 0x00d900ff, 0xbf000013, 0x0608de9a, 0xf9c70000, 0x19ffc711, 0x3515e935, 0x4bfe14ef, + 0x90080c01, 0x6e7e10bb, 0x49fe0000, 0x18999001, 0xdcd99fbf, 0xbf000005, 0xf5f9a699, 0x3e00a10b, + 0x90007bf8, 0x008960df, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, + 0x89007b0b, 0xcf01c200, 0x95b60099, 0x009fe410, 0xff9ee420, 0x00fdb33f, 0xde3eff45, 0x448f007a, + 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x89007ac5, + 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efecc00, 0x8f007a9e, 0x89066f40, 0xf601c100, + 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x007a853e, 0x0042e97e, 0xf40c35fb, + 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x7e09a008, 0x7e007a21, 0xbf00467f, 0xa619bf0f, + 0x070bf4f9, 0x0042e97e, 0xdf0415fb, 0x00000608, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, + 0x0005dcdf, 0xbdffbf00, 0x3591a014, 0x01030191, 0x99909320, 0xa0a43208, 0xb228029f, 0xb2b4bd0a, + 0x0b947e2c, 0x35050900, 0x03350102, 0x08013504, 0x35090435, 0x01350201, 0x8f092003, 0xcf01c000, + 0x99c700f9, 0x0099b34c, 0x90b30166, 0x02f8f501, 0x007c7f3e, 0xc700f9cf, 0x99b34c99, 0xb3013900, + 0xf8f50190, 0x7c943e02, 0x00008f00, 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x8f03f9b5, 0xcf01c000, + 0x99c700f9, 0x0099b34c, 0x90b300ed, 0x02f8f501, 0x007cbf3e, 0xc700f9cf, 0x99b34c99, 0xb300c000, + 0xf8f50190, 0x7cd43e02, 0x00008f00, 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x3304f9b5, 0xd9370040, + 0x0000130c, 0x008e9fbf, 0xe9cf01c0, 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0x0a3e02f8, 0xf9cf007d, + 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0x1e3e02f8, 0x00d9007d, 0xbf000013, 0x014bfe9a, 0xbb90080c, + 0x006e7e14, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0x0c3e00ba, 0x0089007e, + 0x99cf01c2, 0x0608de00, 0x9fc70000, 0x1899c710, 0x3515ef35, 0x323e14e9, 0xff90007d, 0xc1008960, + 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0x1e3e9fb2, 0x0089007d, 0x99cf01c2, + 0x009fe400, 0xff94f120, 0x00fdb33f, 0xed3eff40, 0x448f007c, 0x0089066f, 0x9ff601c1, 0x00f1df00, + 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x89007cd4, 0xcf01c200, 0x9fe40099, 0x94f12000, + 0xfdb33fff, 0x3efec700, 0x8f007cad, 0x89066f40, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, + 0xcf009ff7, 0x9fb2009f, 0x007c943e, 0x0042e97e, 0xf40c45fb, 0xdcdffc30, 0xf9000005, 0xd9ffbf02, + 0x00000604, 0x49fe90bf, 0x04999001, 0xa77e9fa0, 0x010a0046, 0x002bc17e, 0x2b7e010a, 0x010a007c, + 0xd43d0cb2, 0x617eabb2, 0xa0330043, 0x02f80600, 0x900149fe, 0x9fbf0499, 0x0005dcd9, 0xa699bf00, + 0x070bf4f9, 0x0042e97e, 0xd90405fb, 0x000005dc, 0x30f499bf, 0x014ffefc, 0x587ef9a0, 0xa4330078, + 0xb4bd2800, 0xd43dc4bd, 0x617e020a, 0xa43d0043, 0x002bc17e, 0x2b7ea43d, 0x487e007c, 0xcf7e0028, + 0xaa3e0046, 0xc17e007e, 0x49fe002b, 0xd99fbf01, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, + 0x00f80430, 0xdfcc30f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, + 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000013, + 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, + 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x18007f43, 0x0b98050a, 0x78e27e02, 0x3ea13200, + 0x18007fb1, 0x2b320801, 0x817e0ab2, 0x040f000f, 0x45354320, 0x024f3503, 0x0c001033, 0x7e011433, + 0x007f863e, 0xb2020998, 0xa07bb24a, 0x08099079, 0xb5019f98, 0x9f98017f, 0x027fb502, 0xb5039998, + 0xa43e0379, 0x0f98007f, 0x08099002, 0x6bb24ab2, 0x9f986fa0, 0x016fb501, 0xb5029f98, 0x9998026f, + 0x0369b503, 0x49351409, 0x0f617e01, 0x7efa3e00, 0x320ab200, 0x0f817e2b, 0x3d050f00, 0x358f2094, + 0x00180289, 0xb2040f03, 0x018f358a, 0xbd038035, 0x0f717eb4, 0x00193300, 0x02f8ff25, 0x007efa3e, + 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0xb02c02b0, 0x0cf402b6, 0x01b4b30b, 0x800f3e10, + 0x03b0b300, 0x04b0b32d, 0x3e020e3f, 0xbf008051, 0x8fe43da9, 0x3e0c0000, 0xbf00803d, 0xffff8fa9, + 0xfde43df3, 0x008f049f, 0x3d3e0800, 0xa9bf0080, 0xf3ffff8f, 0x9ffde43d, 0x00008f04, 0x059ffd04, + 0x00804f3e, 0xff8fa9bf, 0xe43df3ff, 0xa0049ffd, 0x0149fea9, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, + 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd252f9, 0xbf000005, 0xb2b3b229, 0xb2d5b2c4, + 0x0141fea0, 0x0880008a, 0xa0181190, 0x1c227e19, 0xb60a6000, 0x3a6010a5, 0x08802c8a, 0x001c227e, + 0xa5b64a60, 0xbf5a6010, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40455fb, 0x22f9fc30, 0x0005dcd1, + 0xb219bf00, 0x0140fea2, 0x08d5008a, 0xa00c0090, 0x1c227e09, 0xf00fbf00, 0x2aa000a3, 0xf9a619bf, + 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0xd122f9fc, 0x000005dc, 0xa2b219bf, 0x8a0140fe, 0x9008d540, + 0x09a00c00, 0x001c227e, 0xa3f00fbf, 0xbf2aa000, 0xf4f9a619, 0xe97e070b, 0x25fb0042, 0xfc30f404, + 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x808a0140, 0x009008d5, 0x7e09a00c, 0xbf001c22, 0x00a3f00f, + 0x19bf2aa0, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, + 0xd5808a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, + 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, 0xd6408a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, + 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, + 0x88548a01, 0x0c009008, 0x227e09a0, 0x0fbf001c, 0xa000a3f0, 0xa619bf2a, 0x070bf4f9, 0x0042e97e, + 0xf40425fb, 0x42f9fc30, 0x0005dcd1, 0xb219bf00, 0xb2b2b2a3, 0x0140fec4, 0x0884ac8a, 0xa0140090, + 0x1c227e09, 0xe8a9c700, 0xa9c729a0, 0xb639a0f0, 0x4aa018a5, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, + 0x0445fb00, 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0xa0b20899, 0xb1b29fa0, 0x0880888a, + 0x001c227e, 0xb370a9c7, 0xb01a0290, 0x0cf40296, 0x0194b30b, 0x82613e1d, 0x0390b300, 0x0494b308, + 0xc709a011, 0xa4b3b4aa, 0x9a3e1004, 0x94bd0082, 0xb43e09a0, 0xa6b00082, 0x0f0cf404, 0x1801a0b3, + 0x3002a4b3, 0x0082943e, 0x1808a0b3, 0x2410a4b3, 0x0082aa3e, 0xa43e1aa0, 0x03090082, 0x0082a23e, + 0x19a00409, 0xb63ea43d, 0x05090082, 0x0082a23e, 0x19a094bd, 0x49feff0a, 0x08999001, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, + 0xb2049990, 0x8a9fa0a0, 0x7e088088, 0xc7001c22, 0xa0b370aa, 0xa6b01a02, 0x0b0cf402, 0x1801a4b3, + 0x00830c3e, 0x0803a0b3, 0x0c04a4b3, 0xa43d0aa0, 0x00831a3e, 0xff0a94bd, 0x49fe09a0, 0x04999001, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, + 0x0140fe19, 0x08c0408a, 0xa0080090, 0x1c227e09, 0xbf0fbf00, 0x1fa4f019, 0xa60bacf0, 0x070bf4f9, + 0x0042e97e, 0xd90415fb, 0x000005dc, 0x30f499bf, 0x014ffefc, 0x357ef9a0, 0xa4330083, 0xa4bd0a00, + 0x00838f3e, 0x08d32c8a, 0x001c227e, 0xfe12aac7, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd222f9, 0xbf000005, 0xfea0b229, 0x008a0141, 0x119008d1, + 0x7e19a00c, 0x89001c22, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1cb17eb5, 0xbf1fbf00, + 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0xdcdff830, 0xf9000005, 0xfeffbf62, 0x99900149, + 0xb29c201f, 0x01999096, 0x9fa0a432, 0xb2c4d3b2, 0x7e080aff, 0xd9001c22, 0x40000000, 0x010504bd, + 0x3e14a9ff, 0xbc008451, 0x5abca002, 0x83a97ea4, 0x0014b300, 0x449dda1d, 0x6bb20000, 0xa97e3cb2, + 0xa4330015, 0x09f80c00, 0x583e040a, 0x00900084, 0xf4402601, 0xa43dd40c, 0x900149fe, 0x9fbf2099, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40865fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, + 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001cb1, 0x00008367, 0x00dcb4bd, 0x7e01312d, + 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x82d17e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, + 0x3e0e050b, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x15fb0042, + 0xfc30f408, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb29fa0b0, 0xd1008aa1, 0x1c227e08, + 0x00008900, 0xff04f1ff, 0xb4a9ffff, 0x08d1008a, 0x7eb50bff, 0x8a001cb1, 0xf108d170, 0xdb03ff14, + 0xc0000000, 0xff1014b6, 0xb17eb51b, 0x748a001c, 0x227e08d1, 0x0089001c, 0xa3f00201, 0x009af700, + 0x900149fe, 0x9fbf0899, 0x0005dcd9, 0x3d99bf00, 0xf4f9a6a4, 0xe97e070b, 0x15fb0042, 0xfc30f404, + 0xdcd232f9, 0xbf000005, 0x32c13229, 0xd1708ab0, 0x0000db08, 0x43fec229, 0x10339001, 0xb17e39a0, + 0x748a001c, 0x227e08d1, 0xa4f1001c, 0x02dbfff8, 0xffa22900, 0x708ab5ab, 0xb17e08d1, 0x04f0001c, + 0x0f14f0ff, 0x940c0994, 0x94f1081f, 0x708affff, 0x04b608d1, 0x0000db04, 0x04f0a22a, 0x0509fdff, + 0xfd0501fd, 0x0bff050f, 0x1cb17eb5, 0xbf3fbf00, 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40435fb, + 0x72f9d430, 0xfe15f0b4, 0x99900149, 0xb5a23220, 0xf0b4019f, 0x32b43214, 0xa0d632c5, 0x05dcdf9f, + 0xffbf0000, 0xb2289990, 0xb39fa0e3, 0x3d0a00e4, 0x872d3e24, 0x3dff0000, 0x32f4bd14, 0x953fbc0e, + 0xf40194f0, 0x0e260d0b, 0x32051bf4, 0x011110f0, 0xb301ff90, 0x30ea10f4, 0x0cf41016, 0xff1fc412, + 0xbcff09c4, 0x76b070f9, 0x0b0df410, 0x020209f8, 0x00872d3e, 0xa97e3ab2, 0x5c320083, 0x4b326d32, + 0x5d7e2a32, 0x3ab20085, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xffff7f49, 0x148ab4a9, 0xb17e08d1, + 0x1a32001c, 0xc43d0b32, 0xef7e640d, 0xa2320083, 0x9d00ad33, 0x7e3ab200, 0x8a0083a9, 0x7e08d114, + 0xe5001c22, 0x8a4080ab, 0x7e08d114, 0x32001cb1, 0x0c0b321a, 0x25a08d01, 0x83ef7e26, 0x33a23200, + 0xb26e00a4, 0x83a97e3a, 0xd1148a00, 0x1c227e08, 0xbf7f4900, 0xff0143fe, 0x0132b4a9, 0x08d1148a, + 0x7e283390, 0x04001cb1, 0x870a3e01, 0xa440bc00, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xb69000bc, + 0x39bc10a5, 0x01111090, 0x10c49a60, 0xf407a6ff, 0x49fede1e, 0x20999001, 0xbf019c98, 0xbd3ab29b, + 0x7e200ed4, 0x330026d8, 0xf80600a0, 0x0149fe02, 0xbf489990, 0x05dcd99f, 0x99bf0000, 0xf9a62a32, + 0x7e070bf4, 0xfb0042e9, 0x30f42c75, 0x05dcd9e8, 0x52f90000, 0x4ffe99bf, 0x2cff9001, 0xf9a0a2b2, + 0x08b8c08a, 0x001c227e, 0xc08aa5b2, 0x5bc508b8, 0x1cb17e04, 0x8335da00, 0xb4bd0000, 0x030d408c, + 0xa97e0400, 0xa9330015, 0x8a00a800, 0x7e08c040, 0xfe001c22, 0x2bb20141, 0xa0281190, 0x7e1ab21a, + 0x32007fe0, 0x00ad33a0, 0x19bf0089, 0x13b2f00f, 0xfd014afe, 0x95f0049f, 0x18aa9001, 0xa4b219a0, + 0xfaf07fd1, 0x15817e02, 0xb23abf00, 0x84737e2b, 0x33a03200, 0xb2213ea4, 0x159c7e4a, 0xf4a1a600, + 0x3abfea0d, 0x737e2bb2, 0xa4330084, 0x0400df3e, 0x0087f83e, 0x3a00a033, 0x900149fe, 0x99bf2899, + 0xfe0141fe, 0x11900142, 0x20229024, 0x2ab219a0, 0x0082d17e, 0x1a00a433, 0x1ab22bbf, 0x007fe07e, + 0x0e00a433, 0x408a1bbf, 0xb17e08c0, 0xc08a001c, 0x5bb208b8, 0x001cb17e, 0x900149fe, 0x9fbf2c99, + 0x0005dcd9, 0x3299bf00, 0xf4f9a60a, 0xe97e070b, 0x55fb0042, 0xdc30f418, 0x0005dcdf, 0xbf82f900, + 0xf830f4ff, 0x900149fe, 0x9fa04c99, 0x920140fe, 0xf4bd0c99, 0xfe2c0090, 0x93b20142, 0xa0019fb5, + 0x1320d89f, 0x22900000, 0x06020748, 0x0c059004, 0x3bb28abf, 0xff0d080c, 0x0000c17e, 0xf400a433, + 0x3f013198, 0x0a943319, 0x011998eb, 0x18041f18, 0x09a00134, 0x98041990, 0x0eb5019e, 0x029e9801, + 0x98020eb5, 0x0eb5039e, 0x04999803, 0x330409b5, 0x302a01f0, 0x08f401f6, 0x02f0330f, 0x03f4332e, + 0x89123eb3, 0x010a1800, 0x18030b18, 0x0d18020c, 0x855d7e04, 0x89303e00, 0x010a9800, 0x7e020b98, + 0x3e0084e1, 0x98008930, 0x4a7e010a, 0x303e0087, 0x59bf0089, 0x18010a18, 0x0c18030b, 0x040d1802, + 0xb0020e98, 0x59980091, 0x0191b001, 0x0085df7e, 0x6000ad33, 0x022a35ff, 0x1e182720, 0xb24b3203, + 0x0126351a, 0x7e032e35, 0xb2000f81, 0x7eb4bd2a, 0x3e000f71, 0xd9008890, 0x000005d4, 0xf9fc30f4, + 0x05dcd112, 0x9abf0000, 0x10db19bf, 0x0c000013, 0x0140fe01, 0xa0080090, 0x72e57e09, 0x89cc7e00, + 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0x0140fe19, + 0xda080090, 0x00002d8d, 0x30d909a0, 0xbf000013, 0x20943d9f, 0x02f998a9, 0x0fbf95f9, 0xa43d19bf, + 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, 0x09a00800, + 0x0046257e, 0x0044d87e, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xd9f430f4, 0x000005dc, + 0x99bf22f9, 0xfefc30f4, 0x4ffe0140, 0x10009001, 0xa018ff90, 0x010db50c, 0xb2b2a1b2, 0x637ef9a0, + 0xff0e0048, 0x1e00a033, 0xda010998, 0x00002844, 0x2db21cb2, 0xbf0091b0, 0x07ab980e, 0x004e6e7e, + 0x49feae32, 0x18999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x0042e97e, 0xfb0430f4, + 0xdcdf0c25, 0xbf000005, 0xf030f4ff, 0x900149fe, 0x9fa00c99, 0x002844d9, 0x079f9800, 0xa00149fe, + 0x019bb59a, 0xff98febf, 0x08999001, 0xd4bdbcb2, 0xb202febb, 0xb29fa0ab, 0x7e040e9a, 0x330026d8, + 0xf80800a0, 0xfe010a02, 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, + 0x00f81030, 0xd9c030f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0x46fe60ff, 0xbdf9a001, 0x2c669094, + 0xb01691b0, 0x44fe1591, 0x0148fe01, 0x90046990, 0x88904044, 0x0991b05c, 0x008c423e, 0x3f1650b4, + 0x0b9d3359, 0x5e980141, 0x045f1801, 0xa0045990, 0x55e0344e, 0x982be130, 0x4eb5019e, 0x029e9801, + 0x98024eb5, 0x4eb5039e, 0x04999803, 0x330449b5, 0x302d01f0, 0x08f401f6, 0x02fd330c, 0x7c3e0107, + 0x4998008b, 0x014a9802, 0xb40269b5, 0x6ab509e0, 0x01eb9801, 0x008a627e, 0x008c133e, 0x98024998, + 0x4b98014c, 0x034a9804, 0xb40269b5, 0x6cb509e0, 0x01ed9801, 0x0089f87e, 0x008c133e, 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0x33080bf4, 0x00d000a9, 0x3ab294bd, 0xb01491b0, + 0x91b01391, 0x5b913012, 0x90014bfe, 0xd37e5bbb, 0xa0b200c7, 0xef00adb3, 0x5b903400, 0x11009033, + 0xb37e3ab2, 0xa0b200ca, 0xdb00adb3, 0x0d00b400, 0xfe1140b4, 0xff90014f, 0x942eb250, 0xf1b0070d, + 0x00804101, 0x010b3ab2, 0x11b04cb2, 0xc5777e00, 0xb20bb200, 0xfe3ab22c, 0xdd90014d, 0xc3d27e4c, + 0x14e0b400, 0x1cb2a0b2, 0xb4bd3ab2, 0x987e0db2, 0x0db300c5, 0xb4009100, 0x4afe13b0, 0x34aa9001, + 0x00ca377e, 0xb40c3a98, 0x4cfe0db0, 0x48cc9001, 0x00d7597e, 0xa4b3a0b2, 0x90b46d00, 0xa6f00112, + 0x321bf491, 0xcd014e98, 0xf4b370ef, 0x700f0600, 0xf0062918, 0x9ebcff94, 0x029fbb90, 0x3e0149b5, + 0xb200cf73, 0xb23ab20b, 0xc32c7e2c, 0xb3a0b200, 0xbb3400a4, 0x4afe0265, 0x34aa9001, 0x00c7327e, + 0x200060b3, 0xbc0b90b4, 0x95bc8085, 0x0b91b090, 0x00cdbf3e, 0xa33e0200, 0x030000cf, 0x00cfa33e, + 0xb20c00b4, 0x7e2bb23a, 0xbd00c623, 0x0579b594, 0x00cfbc3e, 0xbc3e0300, 0x020000cf, 0x900149fe, + 0x9fbf5c99, 0x0005dcd9, 0xb299bf00, 0xf4f9a60a, 0xe23e170b, 0x291800cf, 0x009d3306, 0x9a3efe4f, + 0xe97e00cf, 0x30f40042, 0x3485fb08, 0xdfdc30f4, 0x000005dc, 0xffbf82f9, 0xfef830f4, 0x99900149, + 0xb09fa04c, 0xc2b20bb1, 0xe6b2d4b2, 0xb9b3a5b2, 0xb3011700, 0x011200e9, 0x41fe94bd, 0x90c43d01, + 0x19a04811, 0x9d7e1db2, 0xa0b200c6, 0xfb00adb3, 0xbc19bf00, 0x9998f042, 0xf59fa601, 0xb200ea08, + 0x7e03005a, 0xb200c5da, 0x00a9b3a3, 0x1bbf00de, 0xfe0c5c98, 0x00900140, 0x7e0ab230, 0xb200c666, + 0x702bcc0a, 0x00c7707e, 0xadb3a8b2, 0xcd00ad00, 0x47fe7021, 0x00804201, 0x3e447790, 0xb400d112, + 0x94bd0c00, 0xf00979a0, 0x1bf409a6, 0x3e020009, 0x0900d119, 0xf409a6f0, 0x0300090d, 0x00d1193e, + 0xb60bc0b4, 0xe4bd0704, 0x5ab20db2, 0x21b0b4bd, 0x0171b000, 0x00c5777e, 0x0bb25abf, 0x3db22cb2, + 0x00d9997e, 0xa0b27ebf, 0x5ab23bb2, 0x0db22cb2, 0x00c5987e, 0x450004b3, 0xb4bd3ab2, 0x00c2d37e, + 0xa4b3a0b2, 0x70003700, 0xa60201bb, 0x050df404, 0x1b9040b2, 0xbc6ab210, 0x0cb2b03b, 0x00d9fd7e, + 0xbb014afe, 0xaa900240, 0x6060bc30, 0x00c7327e, 0x4db314bd, 0xb2ff6d00, 0xb25ab280, 0xc6237e3b, + 0xd1273e00, 0xfe020000, 0x99900149, 0xd99fbf4c, 0x000005dc, 0x0ab299bf, 0x0bf4f9a6, 0x42e97e07, + 0x0830f400, 0xf42485fb, 0xdcd9f830, 0xf9000005, 0xfe99bf32, 0xff90014f, 0xa0a1b214, 0xb294bdf9, + 0xfec3b2b2, 0x204b0140, 0x10009003, 0x0ab209a0, 0x00da257e, 0x90b309bf, 0xa4b34c00, 0x91a04800, + 0x92b509bf, 0x490fbf01, 0xf9b51000, 0x090fbf04, 0x05f9b520, 0x93b509bf, 0x090fbf06, 0x1cf93501, + 0x9a3509bf, 0x090fbf2c, 0x0af9b5f0, 0xf9900fbf, 0x0ef9b540, 0xf9900fbf, 0x0ff9b5c0, 0xc43e0abf, + 0xa4bd00d1, 0x900149fe, 0x9fbf1499, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40835fb, + 0xdcdfd030, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0a3b250, 0xb302059f, 0x04fb00a9, 0xf000b630, + 0xa9350b9c, 0xb594bd2c, 0xda7e0ca9, 0xa0b200c5, 0xb4bd3abf, 0xb200804c, 0xd9997e0d, 0xb3a5b200, + 0x04b100ad, 0x9d33093f, 0x1804a24a, 0x9d330109, 0x18049a46, 0x9d330209, 0x18049246, 0x9d330309, + 0x18048a53, 0x0918040e, 0x060f1805, 0xf0070d18, 0x94f0ffe4, 0xfff4f0ff, 0xb60894b6, 0x9efd10f4, + 0x18d4b605, 0xfd05f9fd, 0x0bf505df, 0x0505045e, 0xf503d6b0, 0xb5045d0c, 0xd4b3013d, 0x00490e01, + 0x0239b550, 0x00d2b23e, 0x18080d18, 0x0f180909, 0x0b0e180a, 0xf0ffd4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xe4b6059d, 0x05f9fd18, 0xb505effd, 0x3ab2023e, 0x237e0bb2, 0x3a9800c6, 0xa6ff0902, + 0x091bf4a9, 0xc83e04bd, 0xa5b600d6, 0x303b9007, 0x7e033ab5, 0xb200d88f, 0x00adb3a5, 0x3b9803f5, + 0x90c00903, 0xbb90343a, 0x04b9fd3f, 0x7e03b5b6, 0xb200da25, 0x00adb3a5, 0x47fe03d9, 0x0148fe01, + 0xbd407790, 0x01799044, 0xb03c8890, 0x223e0991, 0xe4bd00d4, 0x44b38ea0, 0x3a980f00, 0x0cb4bd0c, + 0xd3453efe, 0xb23ab200, 0x7e7cb24b, 0xb200c4b8, 0x00adb3a5, 0x793f039d, 0xf40194f0, 0x3a98120b, + 0x0c4bb20c, 0xd7977eff, 0xd41f3e00, 0x7e7ab200, 0xb300c1c9, 0x980f00a0, 0x4bb20c3a, 0x453efd0c, + 0x793f00d3, 0xf40294f0, 0x3a980e1b, 0x0c4bb20c, 0xd4143efd, 0x09b0b400, 0x010c3ab2, 0x9d7e8db2, + 0xa0b300c6, 0x793f5d00, 0x24bd3fb2, 0x900299c7, 0x91b00199, 0x54f5980a, 0x390054b3, 0xbc09b0b4, + 0x030c0022, 0xb60002bc, 0x01b80304, 0xbc000140, 0x1ab21031, 0x00d9fd7e, 0xb80030bc, 0x00014309, + 0x02b59520, 0x0af0b453, 0xa0540fb5, 0xd3df3e81, 0x01229000, 0xb318ff90, 0x3ebe1424, 0xbf00d70c, + 0x58793f8e, 0x7d18027f, 0x03ee9807, 0xc70d3a98, 0xf3f00299, 0x70ffcc00, 0xb21f96cb, 0xd8e6cb4b, + 0xd6cb010c, 0xe0f6ebf0, 0xc0f27e01, 0x0c3a9800, 0x6cb24bb2, 0x00d7977e, 0xadb3a5b2, 0x9002b400, + 0x3b980144, 0xf54ba603, 0xbdfeeb08, 0xb0bbbc94, 0x8ab289a0, 0x00da597e, 0xadb3a5b2, 0xb2029400, + 0x9884bd37, 0x88bc547f, 0x9098bc90, 0xb80394b6, 0x00014099, 0xb09039bc, 0xf9b30b91, 0x98025300, + 0xa0b4033c, 0xbdb43d0f, 0xc0ccbc24, 0xd27e44bd, 0x60b400d9, 0xd53d3e0f, 0x0d3a9800, 0x41b02bb2, + 0xc1467e0c, 0x00a93300, 0x3a9800b5, 0x014cfe0c, 0xcc902bb2, 0xd7597e38, 0x00adb300, 0xe0b4020c, + 0x0e90b40b, 0xc703ef98, 0x9fa6d899, 0x008e1bf5, 0xb20d3a98, 0x7e010c2b, 0xfe00c11c, 0x3ab2014c, + 0xcc902bb2, 0xc4fc7e30, 0x06a4b300, 0x0c3a9813, 0xfd0c2bb2, 0x00d7977e, 0x00d53a3e, 0xcb00adb3, + 0x1c907401, 0xbc0093f0, 0x69bc9099, 0xe4017f00, 0xf4ffff19, 0x0260091b, 0x00d53a3e, 0xfe0c3a98, + 0x1be4014c, 0xcc90ffff, 0xd7597e34, 0x00adb300, 0xf0340198, 0x3690343a, 0x0df4f926, 0xe4026010, + 0x98ffff1b, 0x2f3e0c3a, 0x3a9800d5, 0x0c2bb20c, 0xd7977efd, 0x00adb300, 0x22900170, 0x033a9801, + 0x08f52aa6, 0x64b2ff37, 0xb43d6eb2, 0xf4bdd43d, 0x713ec4bd, 0xe97f00d5, 0x0a009473, 0x6b3e010d, + 0xd03300d5, 0x010b0600, 0x9001cc90, 0xee9001ff, 0xf4faa602, 0xc4b3e308, 0x7cb50b00, 0xd6ad3e54, + 0x00b93300, 0x399800a6, 0x0296b001, 0x09300cf4, 0xb56db203, 0xe4bd5479, 0xb03ef4bd, 0xd97f00d5, + 0x0a009073, 0x90f9697c, 0xee9001ff, 0x02dd9001, 0xa6033998, 0xe908f4e9, 0x00d6273e, 0xf10b94bd, + 0xbd5479b5, 0x3eb1b224, 0x7f00d601, 0xff09e440, 0x260bf4ff, 0xbfa6f10f, 0xe40b1bf4, 0x3effff0b, + 0x9800d5f9, 0x0ce40c3a, 0x977effff, 0xadb300d7, 0xe400b900, 0xb2ffff0b, 0x01229019, 0xb2024490, + 0x03399891, 0x08f429a6, 0xa6f109c5, 0xa00bf5b9, 0x0c3a9800, 0x7e0a3c98, 0xb300d797, 0x008c00ad, + 0x3e0a31b5, 0x7f00d6ad, 0x9294bd6f, 0x79b501c1, 0x00f3f051, 0x7fb504bd, 0xd6653e52, 0x584b7f00, + 0x3a98014c, 0x0100900c, 0xf000b3f0, 0x449000c3, 0xd7977e02, 0x00a4b300, 0x0be0b452, 0x9001e998, + 0xe9b57099, 0xf401a601, 0x607cd608, 0x0c3a9808, 0x0be4f00c, 0x977effff, 0xa4b300d7, 0x4cfe2d00, + 0xff0be401, 0x903ab2ff, 0xb87e40cc, 0xa4b300c4, 0x90341900, 0x517f9846, 0xbcff94f0, 0x7fb5f0f9, + 0xd6ad3e51, 0xb2030a00, 0xd6b83ea5, 0x01889000, 0xb3187790, 0xfd90148d, 0x900149fe, 0x9abf3c99, + 0x00d9067e, 0x00d6ce3e, 0xd03e0305, 0x04bd00d6, 0x3ab20bb2, 0x00c6237e, 0x1a0050b3, 0xbd0c3a98, + 0xd85e7e04, 0x0d3a9800, 0x7e0c30b5, 0xb500d906, 0x49fe0d30, 0x50999001, 0xdcd99fbf, 0xbf000005, + 0xa65ab299, 0x110bf4f9, 0x00d7123e, 0xce3e0105, 0xe97e00d6, 0x85fb0042, 0xfc30f430, 0xdcd222f9, + 0xbf000005, 0xfea0b229, 0x11900141, 0x7e19a00c, 0x9800c5b9, 0x5e7e0c0a, 0x0a9800d8, 0xd9067e0d, + 0x7e0ab200, 0xbf00d906, 0xbd29bf1f, 0xf4f9a6a4, 0xe97e070b, 0x25fb0042, 0x05dcd904, 0x99bf0000, + 0xfefc30f4, 0xaeb2014f, 0xa9bff9a0, 0xb9a6020a, 0x900d18f4, 0xe9bc01b9, 0xa0a4bd98, 0x0149fec9, + 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, + 0x014ffefc, 0xf9a0aeb2, 0x020aa9bf, 0x18f4b9a6, 0x01b9900b, 0xecbca4bd, 0x0149fe99, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, 0x014ffefc, + 0xb9bff9a0, 0x08f4c9a6, 0x3ef10c09, 0xb500d7f7, 0xaca002ab, 0xfe01acb5, 0x9fbf0149, 0x0005dcd9, + 0xb299bf00, 0xf4f9a6ca, 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, + 0x9fa0aebf, 0xbc02a998, 0xaba0b0be, 0xb9a699bf, 0xbc0808f4, 0xa9a092b9, 0xbf01a998, 0xf4a9a6aa, + 0xf10a051b, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcd900f8, + 0xbf000005, 0xfc30f499, 0xa0014ffe, 0x00a0b3f9, 0xd9067e08, 0x0149fe00, 0xdcd99fbf, 0xbf000005, + 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdff830, 0xf9000005, 0xfeffbf32, 0x99900149, + 0xa0a0b214, 0xb3b3b29f, 0x024200a0, 0xf4a2a6fd, 0xab903a0c, 0x0141fe01, 0x9002b4b6, 0x1ab21011, + 0x00da597e, 0x2700a4b3, 0x1db219bf, 0xe4bd2cb2, 0xdfbf90a0, 0xb201e990, 0x99fcbc9e, 0x08f490a6, + 0xa0ddbff4, 0xd8eb3e3d, 0xfe020a00, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4, + 0xfb0042e9, 0xdcdf0835, 0xbf000005, 0xfc30f4fe, 0xa00149fe, 0xbf9ebf9e, 0xf4e9a6f9, 0xe97e070b, + 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x44da0140, 0x90000028, 0x09a00800, + 0x004cd37e, 0x19bf0fbf, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, + 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0xda0140fe, 0x00002844, 0xa0080090, 0x4c217e09, 0xbf0fbf00, + 0x00a63019, 0xf00bacf0, 0xaab901a6, 0xf4f9a601, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, + 0xbf000005, 0x0140fe19, 0x002844da, 0x08009000, 0x397e09a0, 0x0fbf004e, 0xa63019bf, 0x0bacf000, + 0xb901a6f0, 0xf9a601aa, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x000005dc, 0xb4f019bf, + 0x0140feff, 0xa0080090, 0x0b947e09, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0xfc30f404, + 0xdcd112f9, 0xbf000005, 0x0140fe19, 0xa0080090, 0x0b7e7e09, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, + 0x15fb0042, 0xfc30f404, 0xdcd122f9, 0xbf000005, 0xfea2b219, 0xa43d0140, 0xa00c0090, 0x40e57e09, + 0xbf2aa000, 0xb019bf0f, 0xacf000a6, 0xf4f9a60b, 0xe97e070b, 0x25fb0042, 0xfc30f404, 0xdcd122f9, + 0xbf000005, 0xfea2b219, 0xa43d0140, 0xa00c0090, 0x40c37e09, 0xbf2aa000, 0xb019bf0f, 0xacf000a6, + 0xf4f9a60b, 0xe97e070b, 0x25fb0042, 0xe430f404, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0x900145fe, + 0x47fe3c99, 0x909fa001, 0x77902455, 0x131cd934, 0x9abf0000, 0x0c014bfe, 0x2cbb9008, 0xc17eff0d, + 0xa4330000, 0x30b4eb00, 0x33393f0c, 0x18e20c94, 0x10330431, 0x19330f00, 0x3d00b001, 0xdc333e04, + 0x023f9800, 0x00132cd9, 0x04319800, 0xa00a3458, 0x989f3f5f, 0x36900339, 0x0159b518, 0x79a0ff09, + 0x1800f433, 0x003b717e, 0xad33a032, 0x09012900, 0x132cdf01, 0xf9200000, 0x43f01272, 0x3e14bd00, + 0xbc00db73, 0x06b10241, 0x0df40100, 0x01004006, 0x000b947e, 0x001324d9, 0xe49abf00, 0xb2ffff2c, + 0xde0db26b, 0x00001200, 0x00cfec7e, 0xadb37aa0, 0xbf00d400, 0x015c985b, 0xb2041d90, 0x20207c0e, + 0xda1010bc, 0x00001200, 0x0026d87e, 0xad33a032, 0xbd00c500, 0x01004cb4, 0x001200da, 0xf414a600, + 0x223ea408, 0x3f9800dc, 0x132cd902, 0x34980000, 0x0a325804, 0x9f3f5fa0, 0x90033998, 0x59b51838, + 0xa0ff0901, 0x00f43379, 0x3b717e16, 0x33a03200, 0x008400ad, 0x00132cdf, 0xe4f12000, 0xbdffff26, + 0xdc133e24, 0x1262bc00, 0x010016b1, 0x41060df4, 0x947e0100, 0x5bbf000b, 0x90015c98, 0x1eb2042d, + 0x001200da, 0x26727e00, 0xff4ce400, 0x2021bcff, 0x8bb2a032, 0x00de1db2, 0x7c000012, 0xa4334041, + 0x24d93500, 0xbf000013, 0xcd167e9a, 0xb37aa000, 0xbd1300a4, 0x01004cb4, 0x001200da, 0xf426a600, + 0x5bbfa608, 0xb2015c98, 0x0ed4bd7a, 0x26d87e04, 0x34a03200, 0x3ab22db0, 0x000f817e, 0x71000d33, + 0x3a0130fe, 0xf130020f, 0x03331838, 0x4afe0409, 0x39913001, 0xbd3b3130, 0x38aa90b4, 0x000f717e, + 0x00daad3e, 0x002830d9, 0xfc30f400, 0x0005dcdf, 0xb202f900, 0xbfffbfa0, 0x0149fe9a, 0x0b049990, + 0x7e9fa064, 0x0e0000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, 0x8a009ff6, 0x4b02a600, + 0xc4bd1000, 0xbd27104d, 0x1b0f7ee4, 0x00a43300, 0x2830d915, 0x9abf0000, 0x00009b7e, 0xea3e040e, + 0x0ab200dc, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, 0x9af601aa, 0x01114f00, + 0x020099b8, 0x009ff600, 0x49fee43d, 0x04999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, + 0x0042e97e, 0x000405fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1825,9 +1825,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000021db, 0x00002222, 0x00002253, 0x00002292, 0x00001f4e, 0x00001f95, 0x00001fc6, 0x00002017, 0x00002088, 0x000020cf, 0x00002119, 0x0000216a, 0x00001e2a, - 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000024c, 0x0000001a, 0x00000384, 0x00000009, 0x000003f0, - 0x00000004, 0x00000420, 0x00000002, 0x00000438, 0x00000009, 0x000004a4, 0x00000004, 0x000004d4, - 0x00000004, 0x00000504, 0x00000002, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, + 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, 0x00000000, 0x00000013, 0x00000001, 0x00000001, 0x00000013, 0x00000001, 0x00000002, 0x00000013, 0x00000001, 0x00000003, 0x00000013, 0x00000001, 0x00000004, 0x00000013, 0x00000001, 0x00000005, 0x00000013, 0x00000001, 0x00000006, 0x00000013, 0x00000001, 0x00000007, 0x00000013, 0x00000001, @@ -1836,41 +1834,27 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000004, 0x00000002, 0x00000005, 0x00000004, 0x00000002, 0x00000006, 0x00000004, 0x00000002, 0x00000007, 0x00000004, 0x00000002, 0x00000008, 0x00000005, 0x00000003, 0x00000000, 0x00000015, 0x00000004, 0x00000000, 0x00000015, 0x00000004, 0x00000001, 0x00000015, 0x00000004, 0x00000002, - 0x00000015, 0x00000004, 0x00000003, 0x00000016, 0x00000005, 0x00000000, 0x0000000e, 0x00000012, + 0x00000015, 0x00000004, 0x00000003, 0x00000016, 0x00000005, 0x00000000, 0x0000000e, 0x00000011, 0x00000000, 0x00000006, 0x00000007, 0x00000000, 0x00000006, 0x00000007, 0x00000001, 0x00000006, 0x00000007, 0x00000002, 0x00000006, 0x00000007, 0x00000003, 0x0000001a, 0x00000008, 0x00000000, 0x0000001a, 0x00000008, 0x00000001, 0x0000001a, 0x00000008, 0x00000002, 0x0000001a, 0x00000008, - 0x00000003, 0x00000004, 0x00000015, 0x00000000, 0x00000002, 0x0000000b, 0x00000000, 0x00000002, - 0x0000000b, 0x00000001, 0x00000002, 0x0000000b, 0x00000002, 0x00000002, 0x0000000b, 0x00000003, - 0x00000003, 0x0000000c, 0x00000000, 0x00000001, 0x0000000a, 0x00000000, 0x00000001, 0x00000009, - 0x00000000, 0x00000001, 0x00000009, 0x00000001, 0x00000001, 0x00000009, 0x00000002, 0x00000001, - 0x00000009, 0x00000003, 0x00000001, 0x00000009, 0x00000004, 0x00000001, 0x00000009, 0x00000005, - 0x00000001, 0x00000009, 0x00000006, 0x00000001, 0x00000009, 0x00000007, 0x00000001, 0x00000009, - 0x00000008, 0x00000001, 0x0000000d, 0x00000000, 0x00000001, 0x0000000d, 0x00000001, 0x00000001, - 0x0000000d, 0x00000002, 0x00000001, 0x0000000d, 0x00000003, 0x00000002, 0x0000000f, 0x00000000, - 0x00000002, 0x0000000f, 0x00000001, 0x00000002, 0x0000000f, 0x00000002, 0x00000002, 0x0000000f, - 0x00000003, 0x00000003, 0x00000010, 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, - 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, - 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, - 0x12000000, 0x12400000, 0x12800000, 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, - 0x0000bd08, 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, - 0x0000ffff, 0x00004300, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, - 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, - 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000002, 0x0000000b, 0x00000000, 0x00000002, 0x0000000b, 0x00000001, 0x00000002, + 0x0000000b, 0x00000002, 0x00000002, 0x0000000b, 0x00000003, 0x00000001, 0x00000009, 0x00000000, + 0x00000001, 0x00000009, 0x00000001, 0x00000001, 0x00000009, 0x00000002, 0x00000001, 0x00000009, + 0x00000003, 0x00000001, 0x00000009, 0x00000004, 0x00000001, 0x00000009, 0x00000005, 0x00000001, + 0x00000009, 0x00000006, 0x00000001, 0x00000009, 0x00000007, 0x00000001, 0x00000009, 0x00000008, + 0x00000003, 0x0000000c, 0x00000000, 0x00000001, 0x0000000a, 0x00000000, 0x00000002, 0x0000000f, + 0x00000000, 0x00000002, 0x0000000f, 0x00000001, 0x00000002, 0x0000000f, 0x00000002, 0x00000002, + 0x0000000f, 0x00000003, 0x00000001, 0x0000000d, 0x00000000, 0x00000001, 0x0000000d, 0x00000001, + 0x00000001, 0x0000000d, 0x00000002, 0x00000001, 0x0000000d, 0x00000003, 0x00000003, 0x00000010, + 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, + 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, + 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, + 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, + 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00004300, 0x46020f1f, + 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, + 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, + 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2211,7 +2195,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00560000, 0x00420074, 0x007f0078, 0x008c0089, 0x004200c0, 0x00dc0042, 0x00051f00, 0x35040b08, 0x0200001d, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, - 0x00003650, 0xc8b00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00003450, 0xcab00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2492,7 +2476,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003300, 0x00000000, 0x0000de00, 0x00000000, + 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003100, 0x00000000, 0x0000de00, 0x00000000, 0xe4f7f5ef, 0xee6f0434, 0xa742283d, 0xb837517d, 0x49e4d804, 0xd8d4d342, 0xa7c8bf31, 0xe15c25cf, 0x3acb76c7, 0x6ca73cfc, 0xc5002b4d, 0x9dc59b12, 0x8f11945c, 0xe814622b, 0xc745df38, 0xc179824e, 0x50ed0464, 0x40f4b2de, 0x4ea86960, 0xacb935cf, 0xf1b2d5f8, 0xa4ba5e6f, 0x90a0a1eb, 0x69da0dfa, @@ -2557,8 +2541,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x3a16e326, 0xba6b6ea3, 0x87a41305, 0x8f25c7a1, 0x33c8446a, 0xc71830a5, 0xa6396ea5, 0xaca6ee44, - 0x58e60046, 0xb8c9d1da, 0x5b48c2ac, 0x7c81985b, 0xa3c7950d, 0x475262b8, 0xc32028c8, 0xcda615d9, + 0x7a9040dd, 0x0251d13c, 0x4450ac04, 0xc13389f9, 0x1f789ab9, 0x340dcaa2, 0xa6b485f7, 0xee512b70, + 0x59823fc0, 0xf12a3ca4, 0x45b67ae9, 0xd31002ea, 0x6d8e8937, 0x3b58b368, 0x0fce515f, 0x46a7c8f4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2630,26 +2614,26 @@ const NvU32 soe_ucode_header_lr10_prd[] = { /* .appCodeImemOffset = */ 0, /* .appCodeIsSecure = */ 0, /* .appDataStartOffset = */ 56832, - /* .appDataSize = */ 13056, + /* .appDataSize = */ 12544, /* .appDataDmemOffset = */ 0, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 69888, + /* .appCodeStartOffset = */ 69376, /* .appCodeSize = */ 1024, /* .appCodeImemOffset = */ 56832, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 74240, + /* .appDataStartOffset = */ 73728, /* .appDataSize = */ 7424, /* .appDataDmemOffset = */ 56832, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 70912, + /* .appCodeStartOffset = */ 70400, /* .appCodeSize = */ 3328, /* .appCodeImemOffset = */ 57856, /* .appCodeIsSecure = */ 1, - /* .appDataStartOffset = */ 81664, + /* .appDataStartOffset = */ 81152, /* .appDataSize = */ 0, /* .appDataDmemOffset = */ 0, }; -const NvU32 soe_ucode_data_size_lr10_prd = 20416; +const NvU32 soe_ucode_data_size_lr10_prd = 20288; #endif //_SOE_UCODE_LR10_PRD_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h index 8fd9cfd9d..3028282b6 100644 --- a/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h @@ -116,5 +116,6 @@ typedef struct { // HAL functions void soeSetupHal_LR10(struct SOE *pSoe); +void soeSetupHal_LS10(struct SOE *pSoe); #endif //_HALDEFS_SOE_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h index 95f21ad74..d999b76f2 100644 --- a/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h @@ -37,10 +37,8 @@ NvlStatus soeInit(struct nvswitch_device *device, PSOE pSoe, NvU32 pci_device_id void soeDestroy(struct nvswitch_device *device, PSOE pSoe); //HAL functions -NV_STATUS soeProcessMessages (struct nvswitch_device *device, PSOE pSoe); -NV_STATUS soeWaitForInitAck (struct nvswitch_device *device, PSOE pSoe); - - +NV_STATUS soeProcessMessages_HAL (struct nvswitch_device *device, PSOE pSoe); +NV_STATUS soeWaitForInitAck_HAL (struct nvswitch_device *device, PSOE pSoe); NvU32 soeService_HAL (struct nvswitch_device *device, PSOE pSoe); void soeServiceHalt_HAL (struct nvswitch_device *device, PSOE pSoe); void soeEmemTransfer_HAL (struct nvswitch_device *device, PSOE pSoe, NvU32 dmemAddr, NvU8 *pBuf, NvU32 sizeBytes, NvU8 port, NvBool bCopyFrom); diff --git a/src/common/nvswitch/kernel/lr10/intr_lr10.c b/src/common/nvswitch/kernel/lr10/intr_lr10.c index df231362c..29d9fae35 100644 --- a/src/common/nvswitch/kernel/lr10/intr_lr10.c +++ b/src/common/nvswitch/kernel/lr10/intr_lr10.c @@ -1190,34 +1190,286 @@ _nvswitch_service_priv_ring_lr10 return NVL_SUCCESS; } +static NvlStatus +_nvswitch_collect_nport_error_info_lr10 +( + nvswitch_device *device, + NvU32 link, + NVSWITCH_RAW_ERROR_LOG_TYPE *data, + NvU32 *idx, + NvU32 register_start, + NvU32 register_end +) +{ + NvU32 register_block_size; + NvU32 i = *idx; + + if ((register_start > register_end) || + (register_start % sizeof(NvU32) != 0) || + (register_end % sizeof(NvU32) != 0)) + { + return -NVL_BAD_ARGS; + } + + register_block_size = (register_end - register_start)/sizeof(NvU32) + 1; + if ((i + register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE) || + (register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE)) + { + return -NVL_BAD_ARGS; + } + + do + { + data->data[i] = NVSWITCH_ENG_OFF_RD32(device, NPORT, , link, register_start); + register_start += sizeof(NvU32); + i++; + + } + while (register_start <= register_end); + + *idx = i; + return NVL_SUCCESS; +} + static void -_nvswitch_save_route_err_header_lr10 +_nvswitch_collect_error_info_lr10 ( nvswitch_device *device, NvU32 link, + NvU32 collect_flags, // NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_* NVSWITCH_RAW_ERROR_LOG_TYPE *data ) { NvU32 val; NvU32 i = 0; + NvBool data_collect_error = NV_FALSE; + NvlStatus status = NVL_SUCCESS; + + // + // The requested data 'collect_flags' is captured, if valid. + // if the error log buffer fills, then the currently captured data block + // could be truncated and subsequent blocks will be skipped. + // The 'flags' field in the log structure describes which blocks are + // actually captured. + // Captured blocks are packed, in order. + // + + data->flags = 0; + + // ROUTE + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_ROUTE_ERR_TIMESTAMP_LOG, + NV_ROUTE_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME; + NVSWITCH_PRINT(device, INFO, + "ROUTE: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "ROUTE: TIMESTAMP: Error collecting error data\n"); + } + } - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_TIMESTAMP_LOG); val = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_VALID); if (FLD_TEST_DRF_NUM(_ROUTE, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) { - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_MISC_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_1); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_2); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_3); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_4); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_5); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_6); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_7); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_8); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_9); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_10); + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_ROUTE_ERR_MISC_LOG_0, + NV_ROUTE_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC; + NVSWITCH_PRINT(device, INFO, + "ROUTE: MISC: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "ROUTE: MISC: Error collecting error data\n"); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_ROUTE_ERR_HEADER_LOG_0, + NV_ROUTE_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR; + NVSWITCH_PRINT(device, INFO, + "ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n", + data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9], + data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]); + NVSWITCH_PRINT(device, INFO, + "ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "ROUTE: HEADER: Error collecting error data\n"); + } + } + } + + // INGRESS + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_INGRESS_ERR_TIMESTAMP_LOG, + NV_INGRESS_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME; + NVSWITCH_PRINT(device, INFO, + "INGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "INGRESS: TIMESTAMP: Error collecting error data\n"); + } + } + + val = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_VALID); + + if (FLD_TEST_DRF_NUM(_INGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_INGRESS_ERR_MISC_LOG_0, + NV_INGRESS_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC; + NVSWITCH_PRINT(device, INFO, + "INGRESS: MISC: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "INGRESS: MISC: Error collecting error data\n"); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_INGRESS_ERR_HEADER_LOG_0, + NV_INGRESS_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR; + NVSWITCH_PRINT(device, INFO, + "INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n", + data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9], + data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]); + NVSWITCH_PRINT(device, INFO, + "INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "INGRESS: HEADER: Error collecting error data\n"); + } + } + } + + // EGRESS + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_EGRESS_ERR_TIMESTAMP_LOG, + NV_EGRESS_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME; + NVSWITCH_PRINT(device, INFO, + "EGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "EGRESS: TIMESTAMP: Error collecting error data\n"); + } + } + + val = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_VALID); + + if (FLD_TEST_DRF_NUM(_EGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_EGRESS_ERR_MISC_LOG_0, + NV_EGRESS_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC; + NVSWITCH_PRINT(device, INFO, + "EGRESS: MISC: 0x%08x\n", data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "EGRESS: MISC: Error collecting error data\n"); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR) + { + status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i, + NV_EGRESS_ERR_HEADER_LOG_0, + NV_EGRESS_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR; + NVSWITCH_PRINT(device, INFO, + "EGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n", + data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9], + data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]); + NVSWITCH_PRINT(device, INFO, + "EGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]); + } + else + { + data_collect_error = NV_TRUE; + NVSWITCH_PRINT(device, ERROR, + "EGRESS: HEADER: Error collecting error data\n"); + } + } + } + + while (i < NVSWITCH_RAW_ERROR_LOG_DATA_SIZE) + { + data->data[i++] = 0; + } + + if (data_collect_error) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error collecting error info 0x%x. Only 0x%x error data collected.\n", + __FUNCTION__, collect_flags, data->flags); } } @@ -1231,7 +1483,7 @@ _nvswitch_service_route_fatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_STATUS_0); @@ -1248,7 +1500,11 @@ _nvswitch_service_route_fatal_lr10 report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_FIRST_0); contain = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_CONTAIN_EN_0); - _nvswitch_save_route_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _ROUTEBUFERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -1371,7 +1627,7 @@ _nvswitch_service_route_nonfatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_STATUS_0); @@ -1386,7 +1642,11 @@ _nvswitch_service_route_nonfatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_FIRST_0); - _nvswitch_save_route_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _NOPORTDEFINEDERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -1463,41 +1723,6 @@ _nvswitch_service_route_nonfatal_lr10 // Ingress // -static void -_nvswitch_save_ingress_err_header_lr10 -( - nvswitch_device *device, - NvU32 link, - NVSWITCH_RAW_ERROR_LOG_TYPE *data -) -{ - NvU32 val; - NvU32 i = 0; - - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_TIMESTAMP_LOG); - - val = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_VALID); - if (FLD_TEST_DRF_NUM(_INGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) - { - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_MISC_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_1); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_2); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_3); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_4); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_5); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_6); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_7); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_8); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_9); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_10); - } - else - { - data->data[i++] = 0xdeadbeef; - } -} - static NvlStatus _nvswitch_service_ingress_fatal_lr10 ( @@ -1508,7 +1733,7 @@ _nvswitch_service_ingress_fatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_STATUS_0); @@ -1524,7 +1749,11 @@ _nvswitch_service_ingress_fatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_FIRST_0); contain = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_CONTAIN_EN_0); - _nvswitch_save_ingress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _CMDDECODEERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -1704,7 +1933,7 @@ _nvswitch_service_ingress_nonfatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_STATUS_0); @@ -1719,7 +1948,11 @@ _nvswitch_service_ingress_nonfatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_FIRST_0); - _nvswitch_save_ingress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _REQCONTEXTMISMATCHERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -1820,41 +2053,6 @@ _nvswitch_service_ingress_nonfatal_lr10 // Egress // -static void -_nvswitch_save_egress_err_header_lr10 -( - nvswitch_device *device, - NvU32 link, - NVSWITCH_RAW_ERROR_LOG_TYPE *data -) -{ - NvU32 val; - NvU32 i = 0; - - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_TIMESTAMP_LOG); - - val = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_VALID); - if (FLD_TEST_DRF_NUM(_EGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) - { - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_MISC_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_0); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_1); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_2); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_3); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_4); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_5); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_6); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_7); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_8); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_9); - data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_10); - } - else - { - data->data[i++] = 0xdeadbeef; - } -} - static NvlStatus _nvswitch_service_tstate_nonfatal_lr10 ( @@ -1865,7 +2063,7 @@ _nvswitch_service_tstate_nonfatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _TSTATE, _ERR_STATUS_0); @@ -1906,7 +2104,11 @@ _nvswitch_service_tstate_nonfatal_lr10 NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, "TS tag store single-bit threshold"); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, data); _nvswitch_construct_ecc_error_event(&err_event, @@ -1943,7 +2145,11 @@ _nvswitch_service_tstate_nonfatal_lr10 NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "TS crumbstore single-bit threshold"); - _nvswitch_save_ingress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data); _nvswitch_construct_ecc_error_event(&err_event, @@ -1992,7 +2198,7 @@ _nvswitch_service_tstate_fatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _TSTATE, _ERR_STATUS_0); @@ -2014,7 +2220,11 @@ _nvswitch_service_tstate_fatal_lr10 if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOLBUFERR, "TS pointer crossover", NV_FALSE); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOLBUFERR, data); nvswitch_clear_flags(&unhandled, bit); } @@ -2039,7 +2249,11 @@ _nvswitch_service_tstate_fatal_lr10 NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, "TS tag store fatal ECC", NV_FALSE); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, data); nvswitch_clear_flags(&unhandled, bit); @@ -2061,7 +2275,11 @@ _nvswitch_service_tstate_fatal_lr10 if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, "TS crumbstore", NV_FALSE); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, data); nvswitch_clear_flags(&unhandled, bit); } @@ -2086,7 +2304,11 @@ _nvswitch_service_tstate_fatal_lr10 NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, "TS crumbstore fatal ECC", NV_FALSE); - _nvswitch_save_ingress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, data); nvswitch_clear_flags(&unhandled, bit); @@ -2119,7 +2341,11 @@ _nvswitch_service_tstate_fatal_lr10 if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CAMRSP_ERR, "Rsp Tag value out of range", NV_FALSE); - _nvswitch_save_ingress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CAMRSP_ERR, data); nvswitch_clear_flags(&unhandled, bit); } @@ -2160,7 +2386,7 @@ _nvswitch_service_egress_nonfatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = { { 0 } }; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_STATUS_0); @@ -2175,7 +2401,11 @@ _nvswitch_service_egress_nonfatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_FIRST_0); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -2293,9 +2523,9 @@ _nvswitch_service_egress_fatal_lr10 lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; - NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }}; - NVSWITCH_RAW_ERROR_LOG_TYPE credit_data = { { 0 } }; - NVSWITCH_RAW_ERROR_LOG_TYPE buffer_data = { { 0 } }; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE credit_data = {0, { 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE buffer_data = {0, { 0 }}; INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_STATUS_0); @@ -2311,7 +2541,11 @@ _nvswitch_service_egress_fatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_FIRST_0); contain = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_CONTAIN_EN_0); - _nvswitch_save_egress_err_header_lr10(device, link, &data); + _nvswitch_collect_error_info_lr10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _EGRESSBUFERR, 1); if (nvswitch_test_flags(pending, bit)) diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index f48d55388..c59ad3657 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -77,10 +77,10 @@ nvswitch_setup_link_loopback_mode_lr10 } } - if (device->link[link->linkNumber].ned) + if (device->link[link->linkNumber].nedr) { NVSWITCH_PRINT(device, ERROR, - "%s: Setting NED on link %d\n", + "%s: Setting NEDR on link %d\n", __FUNCTION__, link->linkNumber); // setting NEDR @@ -92,7 +92,14 @@ nvswitch_setup_link_loopback_mode_lr10 "%s: SETNEDR CMD failed for link %d.\n", __FUNCTION__, link->linkNumber); } + } + if (device->link[link->linkNumber].nedw) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Setting NEDW on link %d\n", + __FUNCTION__, link->linkNumber); + // setting NEDW status = nvswitch_minion_send_command(device, link->linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW, 0); @@ -147,7 +154,7 @@ _nvswitch_ioctrl_setup_link_plls_lr10 // Request Minion to setup the NVLink clocks status = nvswitch_minion_send_command(device, linkId, - NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL, 0); + NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL, 0); if (status != NV_OK) { NVSWITCH_PRINT(device, ERROR, @@ -297,8 +304,8 @@ nvswitch_init_dlpl_interrupts_lr10 nvlink_link *link ) { - nvswitch_device *device = link->dev->pDevInfo; - NvU32 linkNumber = link->linkNumber; + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short; NvU32 crcLongRegkeyVal = device->regkeys.crc_bit_error_rate_long; NvU32 intrRegVal; @@ -1027,7 +1034,7 @@ nvswitch_corelib_set_dl_link_mode_lr10 NVSWITCH_PRINT(device, ERROR, "%s : INITPHASE1 failed for link (%s):(%s).\n", __FUNCTION__, device->name, link->linkName); - NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CONFIGURATION_ERROR, + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CONFIGURATION_ERROR, NVBIT32(link->linkNumber), INITPHASE1_ERROR); return NV_ERR_NVLINK_CONFIGURATION_ERROR; } @@ -1539,7 +1546,7 @@ nvswitch_corelib_get_tx_mode_lr10 *mode = NVLINK_SUBLINK_STATE_TX_OFF; return NVL_SUCCESS; } - + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TX, _SLSM_STATUS_TX); tx_sublink_state = DRF_VAL(_NVLDL_TX, _SLSM_STATUS_TX, _PRIMARY_STATE, data); @@ -1761,7 +1768,7 @@ nvswitch_corelib_get_rx_mode_lr10 *mode = NVLINK_SUBLINK_STATE_RX_OFF; return NVL_SUCCESS; } - + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _SLSM_STATUS_RX); rx_sublink_state = DRF_VAL(_NVLDL_RX, _SLSM_STATUS_RX, _PRIMARY_STATE, data); @@ -2036,3 +2043,13 @@ nvswitch_apply_recal_settings_lr10 return; } +NvlStatus +nvswitch_launch_ALI_link_training_lr10 +( + nvswitch_device *device, + nvlink_link *link, + NvBool bSync +) +{ + return NVL_ERR_NOT_IMPLEMENTED; +} diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index daa678dd6..cb80bbc53 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -400,17 +400,6 @@ _nvswitch_setup_link_system_registers_lr10 DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, vbios_link_entry->nvLinkparam6), regval); } - else - { - // - // Default working configuration for LR10 - // This will be provided by VBIOS once support available (bug 2767390) - // - NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_MANTISSA = 0x5 forced by driver\n", - __FUNCTION__); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, 0x5, regval); - } fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_EXPONENT, device->regkeys.txtrain_control); @@ -427,17 +416,6 @@ _nvswitch_setup_link_system_registers_lr10 DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, vbios_link_entry->nvLinkparam6), regval); } - else - { - // - // Default working configuration for LR10 - // This will be provided by VBIOS once support available (bug 2767390) - // - NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_EXPONENT = 0x4 forced by driver\n", - __FUNCTION__); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, 0x4, regval); - } NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval); @@ -646,6 +624,27 @@ _nvswitch_vbios_read_structure &unpacked_bytes, NULL); } + +NvlStatus +nvswitch_vbios_read_structure_lr10 +( + nvswitch_device *device, + void *structure, + NvU32 offset, + NvU32 *ppacked_size, + const char *format +) +{ + if (NV_OK == _nvswitch_vbios_read_structure(device, structure, offset, ppacked_size, format)) + { + return NVL_SUCCESS; + } + else + { + return -NVL_ERR_GENERIC; + } +} + NvU8 _nvswitch_vbios_read8 ( @@ -974,19 +973,19 @@ _nvswitch_read_vbios_link_base_entry return status; } -NV_STATUS -_nvswitch_read_vbios_link_entries +NvlStatus +nvswitch_read_vbios_link_entries_lr10 ( - nvswitch_device *device, - NvU32 tblPtr, - NvU32 expected_link_entriesCount, - NVLINK_CONFIG_DATA_LINKENTRY *link_entries, - NvU32 *identified_link_entriesCount + nvswitch_device *device, + NvU32 tblPtr, + NvU32 expected_link_entriesCount, + NVLINK_CONFIG_DATA_LINKENTRY *link_entries, + NvU32 *identified_link_entriesCount ) { NV_STATUS status = NV_ERR_INVALID_PARAMETER; NvU32 i; - NVLINK_VBIOS_CONFIG_DATA_LINKENTRY vbios_link_entry; + NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20 vbios_link_entry; *identified_link_entriesCount = 0; for (i = 0; i < expected_link_entriesCount; i++) @@ -994,7 +993,7 @@ _nvswitch_read_vbios_link_entries status = _nvswitch_vbios_read_structure(device, &vbios_link_entry, tblPtr, (NvU32 *)0, - NVLINK_CONFIG_DATA_LINKENTRY_FMT); + NVLINK_CONFIG_DATA_LINKENTRY_FMT_20); if (status != NV_OK) { NVSWITCH_PRINT(device, ERROR, @@ -1009,7 +1008,7 @@ _nvswitch_read_vbios_link_entries link_entries[i].nvLinkparam4 = (NvU8)vbios_link_entry.nvLinkparam4; link_entries[i].nvLinkparam5 = (NvU8)vbios_link_entry.nvLinkparam5; link_entries[i].nvLinkparam6 = (NvU8)vbios_link_entry.nvLinkparam6; - tblPtr += sizeof(NVLINK_CONFIG_DATA_LINKENTRY); + tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32)); NVSWITCH_PRINT(device, SETUP, "<<<---- NvLink ID 0x%x ---->>>\n", i); @@ -1038,7 +1037,7 @@ NV_STATUS _nvswitch_vbios_fetch_nvlink_entries ( nvswitch_device *device, - NVSWITCH_BIOS_NVLINK_CONFIG *bios_config + NVSWITCH_BIOS_NVLINK_CONFIG *bios_config ) { NvU32 tblPtr; @@ -1063,6 +1062,7 @@ _nvswitch_vbios_fetch_nvlink_entries switch (version) { case NVLINK_CONFIG_DATA_HEADER_VER_20: + case NVLINK_CONFIG_DATA_HEADER_VER_30: size = _nvswitch_vbios_read8(device, tblPtr + 1); if (size == NVLINK_CONFIG_DATA_HEADER_20_SIZE) { @@ -1105,7 +1105,10 @@ _nvswitch_vbios_fetch_nvlink_entries "Reserved \t0x%x\n", header.ver_20.Reserved); NVSWITCH_PRINT(device, SETUP, "<<<---- NvLink Header ---->>>\n"); - + if (header.ver_20.Version == NVLINK_CONFIG_DATA_HEADER_VER_20) + { + device->bIsNvlinkVbiosTableVersion2 = NV_TRUE; + } expected_base_entry_count = header.ver_20.BaseEntryCount; if (expected_base_entry_count > NVSWITCH_NUM_BIOS_NVLINK_CONFIG_BASE_ENTRY) { @@ -1130,13 +1133,19 @@ _nvswitch_vbios_fetch_nvlink_entries // Grab Nvlink Config Data Base Entry _nvswitch_read_vbios_link_base_entry(device, tblPtr, &bios_config->link_vbios_base_entry[base_entry_index]); tblPtr += header.ver_20.BaseEntrySize; - - _nvswitch_read_vbios_link_entries(device, + device->hal.nvswitch_read_vbios_link_entries(device, tblPtr, expected_link_entriesCount, bios_config->link_vbios_entry[base_entry_index], &bios_config->identified_Link_entries[base_entry_index]); - tblPtr += (expected_link_entriesCount * sizeof(NVLINK_CONFIG_DATA_LINKENTRY)); + if (device->bIsNvlinkVbiosTableVersion2) + { + tblPtr += (expected_link_entriesCount * (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32))); + } + else + { + tblPtr += (expected_link_entriesCount * (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30)/sizeof(NvU32))); + } } vbios_fetch_nvlink_entries_done: return status; @@ -1233,7 +1242,7 @@ _nvswitch_setup_link_vbios_overrides if (_nvswitch_vbios_fetch_nvlink_entries(device, bios_config) != NV_OK) { NVSWITCH_PRINT(device, ERROR, - "%s: Error on identifying pci image loc\n", + "%s: Error on fetching nvlink entries\n", __FUNCTION__); status = NV_ERR_GENERIC; goto setup_link_vbios_overrides_done; @@ -1880,8 +1889,8 @@ nvswitch_initialize_ip_wrappers_lr10 // // Bring units out of warm reset on boot. Used by driver load. // -static void -_nvswitch_init_warm_reset_lr10 +void +nvswitch_init_warm_reset_lr10 ( nvswitch_device *device ) @@ -3302,8 +3311,8 @@ _nvswitch_process_firmware_info_lr10 } } -static void -_nvswitch_init_npg_multicast_lr10 +void +nvswitch_init_npg_multicast_lr10 ( nvswitch_device *device ) @@ -4029,8 +4038,8 @@ nvswitch_initialize_device_state_lr10 goto nvswitch_initialize_device_state_exit; } - _nvswitch_init_warm_reset_lr10(device); - _nvswitch_init_npg_multicast_lr10(device); + nvswitch_init_warm_reset(device); + nvswitch_init_npg_multicast(device); retval = nvswitch_clear_nport_rams(device); if (NVL_SUCCESS != retval) { @@ -4352,6 +4361,11 @@ nvswitch_ctrl_get_nvlink_status_lr10 ret->linkInfo[i].nvlinkVersion = NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_0; ret->linkInfo[i].nciVersion = NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_0; } + else if (nvlink_caps_version == NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0) + { + ret->linkInfo[i].nvlinkVersion = NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_4_0; + ret->linkInfo[i].nciVersion = NVSWITCH_NVLINK_STATUS_NCI_VERSION_4_0; + } else { NVSWITCH_PRINT(device, WARN, @@ -4872,6 +4886,22 @@ nvswitch_ctrl_get_info_lr10 } } break; + case NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE: + { + NvU32 remap_ram_sel; + NvlStatus status; + + status = nvswitch_get_remap_table_selector(device, NVSWITCH_TABLE_SELECT_REMAP_MULTICAST, &remap_ram_sel); + if (status == NVL_SUCCESS) + { + p->info[i] = nvswitch_get_ingress_ram_size(device, remap_ram_sel); + } + else + { + p->info[i] = 0; + } + } + break; case NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE: p->info[i] = nvswitch_get_ingress_ram_size(device, NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM); break; @@ -5838,6 +5868,9 @@ nvswitch_reset_and_drain_links_lr10 } FOR_EACH_INDEX_IN_MASK_END; + // Launch ALI training if applicable + (void)nvswitch_launch_ALI(device); + nvswitch_reset_and_drain_links_exit: nvswitch_os_free(nport_reg_val); return status; @@ -6828,6 +6861,62 @@ nvswitch_ctrl_get_rb_stall_busy_lr10 return -NVL_ERR_NOT_SUPPORTED; } +/* + * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR + */ +static NvlStatus +nvswitch_ctrl_get_multicast_id_error_vector_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p +) +{ + NVSWITCH_PRINT(device, ERROR, + "GET_MULTICAST_ID_ERROR_VECTOR should not be called on LR10\n"); + return -NVL_ERR_NOT_SUPPORTED; +} + +/* + * CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR + */ +static NvlStatus +nvswitch_ctrl_clear_multicast_id_error_vector_lr10 +( + nvswitch_device *device, + NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p +) +{ + NVSWITCH_PRINT(device, ERROR, + "CLEAR_MULTICAST_ID_ERROR_VECTOR should not be called on LR10\n"); + return -NVL_ERR_NOT_SUPPORTED; +} + +/* + * CTRL_NVSWITCH_INBAND_SEND_DATA + */ +NvlStatus +nvswitch_ctrl_inband_send_data_lr10 +( + nvswitch_device *device, + NVSWITCH_INBAND_SEND_DATA_PARAMS *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +/* + * CTRL_NVSWITCH_INBAND_RECEIVE_DATA + */ +NvlStatus +nvswitch_ctrl_inband_read_data_lr10 +( + nvswitch_device *device, + NVSWITCH_INBAND_READ_DATA_PARAMS *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + /* * @brief: This function retrieves the NVLIPT public ID for a given global link idx * @params[in] device reference to current nvswitch device @@ -6943,14 +7032,23 @@ void nvswitch_init_scratch_lr10 continue; } - reg = NVSWITCH_LINK_RD32_LR10(device, linkId, NPORT, _NPORT, _SCRATCH_WARM); + reg = NVSWITCH_LINK_RD32(device, linkId, NPORT, _NPORT, _SCRATCH_WARM); if (reg == NV_NPORT_SCRATCH_WARM_DATA_INIT) { - NVSWITCH_LINK_WR32_LR10(device, linkId, NPORT, _NPORT, _SCRATCH_WARM, 0); + NVSWITCH_LINK_WR32(device, linkId, NPORT, _NPORT, _SCRATCH_WARM, 0); } } } +NvlStatus +nvswitch_launch_ALI_lr10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + NvlStatus nvswitch_set_training_mode_lr10 ( @@ -6984,6 +7082,7 @@ nvswitch_parse_bios_image_lr10 status = _nvswitch_setup_link_vbios_overrides(device, bios_config); if ((status != NV_OK) && device->pSoe) { + //To enable LS10 bringup (VBIOS is not ready and SOE is disabled), fail the device init only when SOE is enabled and vbios overrides has failed NVSWITCH_PRINT(device, ERROR, "%s: error=0x%x\n", __FUNCTION__, status); @@ -7063,4 +7162,5 @@ void nvswitch_setup_hal_lr10(nvswitch_device *device) } NVSWITCH_INIT_HAL(device, lr10); + NVSWITCH_INIT_HAL_LS10(device, lr10); } diff --git a/src/common/nvswitch/kernel/lr10/pmgr_lr10.c b/src/common/nvswitch/kernel/lr10/pmgr_lr10.c index cbe0f733c..9f5bc75c9 100644 --- a/src/common/nvswitch/kernel/lr10/pmgr_lr10.c +++ b/src/common/nvswitch/kernel/lr10/pmgr_lr10.c @@ -30,6 +30,7 @@ #include "lr10/pmgr_lr10.h" #include "nvswitch/lr10/dev_pmgr.h" +// Shared with LS10 void _nvswitch_i2c_set_port_pmgr(nvswitch_device *device, NvU32 port); /*! The number of nanoseconds we will wait for slave clock stretching. diff --git a/src/common/nvswitch/kernel/lr10/soe_lr10.c b/src/common/nvswitch/kernel/lr10/soe_lr10.c index 9d7995011..8a7d2f251 100644 --- a/src/common/nvswitch/kernel/lr10/soe_lr10.c +++ b/src/common/nvswitch/kernel/lr10/soe_lr10.c @@ -45,23 +45,6 @@ #include "rmflcncmdif_nvswitch.h" -/* - * @Brief : Selects SOE core (Falcon or Riscv) - * - * @param[in] device Bootstrap SOE on this device - * - * Does nothing on LR10 - */ -NvlStatus -nvswitch_soe_set_ucode_core_lr10 -( - nvswitch_device *device, - NvBool bFalcon -) -{ - return NVL_SUCCESS; -} - /* * @Brief : Reset SOE at the engine level. * @@ -74,7 +57,6 @@ _nvswitch_reset_soe ) { NvU32 value; - NvlStatus status; // Assert reset value = NVSWITCH_SOE_RD32_LR10(device, 0, _SOE_FALCON, _ENGINE); @@ -92,15 +74,6 @@ _nvswitch_reset_soe value = FLD_SET_DRF(_SOE, _FALCON, _ENGINE_RESET, _FALSE, value); NVSWITCH_SOE_WR32_LR10(device, 0, _SOE_FALCON, _ENGINE, value); - // Set SOE ucode core to falcon - status = nvswitch_soe_set_ucode_core(device, NV_TRUE); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, - "Failed to set SOE core\n"); - return status; - } - // Wait for reset to complete if (flcnWaitForResetToFinish_HAL(device, device->pSoe->pFlcn) != NV_OK) { @@ -257,8 +230,8 @@ _nvswitch_soe_send_test_cmd return status; } -NvlStatus -nvswitch_get_soe_ucode_binaries_lr10 +static NvlStatus +_nvswitch_get_soe_ucode_binaries ( nvswitch_device *device, const NvU32 **soe_ucode_data, @@ -307,7 +280,7 @@ _nvswitch_load_soe_ucode_image const NvU32 *soe_ucode_data; const NvU32 *soe_ucode_header; - status = nvswitch_get_soe_ucode_binaries(device, &soe_ucode_data, &soe_ucode_header); + status = _nvswitch_get_soe_ucode_binaries(device, &soe_ucode_data, &soe_ucode_header); if (status != NVL_SUCCESS) { NVSWITCH_PRINT(device, ERROR, @@ -774,8 +747,8 @@ _nvswitch_soe_request_reset_permissions /* * @Brief : Execute SOE pre-reset sequence for secure reset. */ -NvlStatus -nvswitch_soe_prepare_for_reset_lr10 +static NvlStatus +_nvswitch_soe_prepare_for_reset ( nvswitch_device *device ) @@ -835,7 +808,7 @@ nvswitch_init_soe_lr10 NvlStatus status; // Prepare SOE for reset. - status = nvswitch_soe_prepare_for_reset(device); + status = _nvswitch_soe_prepare_for_reset(device); if (status != NVL_SUCCESS) { NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_RESET, @@ -1086,7 +1059,7 @@ _soeService_LR10 NVSWITCH_PRINT(device, INFO, "%s: Received a message from SOE via SWGEN0\n", __FUNCTION__); - soeProcessMessages(device, pSoe); + soeProcessMessages_HAL(device, pSoe); bRecheckMsgQ = NV_TRUE; } @@ -2161,6 +2134,413 @@ _soeSetPcieLinkSpeed_LR10 return NVL_SUCCESS; } +/*! + * Use the SOE INIT Message to construct and initialize all SOE Queues. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * @param[in] pMsg Pointer to the INIT Message + * + * @return 'NV_OK' upon successful creation of all SOE Queues + */ +static NV_STATUS +_soeQMgrCreateQueuesFromInitMsg +( + nvswitch_device *device, + PFLCNABLE pSoe, + RM_FLCN_MSG_SOE *pMsg +) +{ + RM_SOE_INIT_MSG_SOE_INIT *pInit; + NvU32 i; + NvU32 queueLogId; + NV_STATUS status; + FLCNQUEUE *pQueue; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + PFALCON_QUEUE_INFO pQueueInfo; + + NVSWITCH_ASSERT(pFlcn != NULL); + + pQueueInfo = pFlcn->pQueueInfo; + NVSWITCH_ASSERT(pQueueInfo != NULL); + + pInit = &pMsg->msg.init.soeInit; + NVSWITCH_ASSERT(pInit->numQueues <= pFlcn->numQueues); + + for (i = 0; i < pFlcn->numQueues; i++) + { + queueLogId = pInit->qInfo[i].queueLogId; + NVSWITCH_ASSERT(queueLogId < pFlcn->numQueues); + pQueue = &pQueueInfo->pQueues[queueLogId]; + status = flcnQueueConstruct_dmem_nvswitch( + device, + pFlcn, + &pQueue, // ppQueue + queueLogId, // Logical ID of the queue + pInit->qInfo[i].queuePhyId, // Physical ID of the queue + pInit->qInfo[i].queueOffset, // offset + pInit->qInfo[i].queueSize, // size + RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error constructing SOE Queue (status=" + "0x%08x).\n", __FUNCTION__, status); + NVSWITCH_ASSERT(0); + return status; + } + } + return NV_OK; +} + +/*! + * Purges all the messages from the SOE's message queue. Each message will + * be analyzed, clients will be notified of status, and events will be routed + * to all registered event listeners. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * + * @return 'NV_OK' if the message queue was successfully purged. + */ +static NV_STATUS +_soeProcessMessages_LR10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + RM_FLCN_MSG_SOE soeMessage; + NV_STATUS status; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + // keep processing messages until no more exist in the message queue + while (NV_OK == (status = flcnQueueReadData( + device, + pFlcn, + SOE_RM_MSGQ_LOG_ID, + (RM_FLCN_MSG *)&soeMessage, NV_TRUE))) + { + NVSWITCH_PRINT(device, INFO, + "%s: unitId=0x%02x, size=0x%02x, ctrlFlags=0x%02x, " \ + "seqNumId=0x%02x\n", + __FUNCTION__, + soeMessage.hdr.unitId, + soeMessage.hdr.size, + soeMessage.hdr.ctrlFlags, + soeMessage.hdr.seqNumId); + + // check to see if the message is a reply or an event. + if ((soeMessage.hdr.ctrlFlags &= RM_FLCN_QUEUE_HDR_FLAGS_EVENT) != 0) + { + flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage, NV_OK); + } + // the message is a response from a previously queued command + else + { + flcnQueueResponseHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage); + } + } + + // + // Status NV_ERR_NOT_READY implies, Queue is empty. + // Log the message in other error cases. + // + if (status != NV_ERR_NOT_READY) + { + NVSWITCH_PRINT(device, ERROR, + "%s: unexpected error while purging message queue (status=0x%x).\n", + __FUNCTION__, (status)); + } + + return status; +} + +/*! + * @brief Read the INIT message directly out of the Message Queue. + * + * This function accesses the Message Queue directly using the HAL. It does + * NOT and may NOT use the queue manager as it has not yet been constructed and + * initialized. The Message Queue may not be empty when this function is called + * and the first message in the queue MUST be the INIT message. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * @param[out] pMsg Message structure to fill with the INIT message data + * + * @return 'NV_OK' upon successful extraction of the INIT message. + * @return + * 'NV_ERR_INVALID_STATE' if the first message found was not an INIT + * message or if the message was improperly formatted. + */ +static NV_STATUS +_soeGetInitMessage +( + nvswitch_device *device, + PSOE pSoe, + RM_FLCN_MSG_SOE *pMsg +) +{ + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + NV_STATUS status = NV_OK; + NvU32 tail = 0; + PFALCON_QUEUE_INFO pQueueInfo; + // on the GPU, rmEmemPortId = sec2RmEmemPortIdGet_HAL(...); + NvU8 rmEmemPortId = 0; + + if (pFlcn == NULL) + { + NVSWITCH_ASSERT(pFlcn != NULL); + return NV_ERR_INVALID_POINTER; + } + + pQueueInfo = pFlcn->pQueueInfo; + if (pQueueInfo == NULL) + { + NVSWITCH_ASSERT(pQueueInfo != NULL); + return NV_ERR_INVALID_POINTER; + } + + // + // Message queue 0 is used by SOE to communicate with RM + // Check SOE_CMDMGMT_MSG_QUEUE_RM in //uproc/soe/inc/soe_cmdmgmt.h + // + pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID].queuePhyId = 0; + + // read the header starting at the current tail position + (void)flcnMsgQueueTailGet(device, pFlcn, + &pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], &tail); + if (pFlcn->bEmemEnabled) + { + // + // We use the offset in DMEM for the src address, since + // EmemCopyFrom automatically converts it to the offset in EMEM + // + flcnableEmemCopyFrom( + device, pFlcn->pFlcnable, + tail, // src + (NvU8 *)&pMsg->hdr, // pDst + RM_FLCN_QUEUE_HDR_SIZE, // numBytes + rmEmemPortId); // port + } + else + { + status = flcnDmemCopyFrom(device, + pFlcn, + tail, // src + (NvU8 *)&pMsg->hdr, // pDst + RM_FLCN_QUEUE_HDR_SIZE, // numBytes + 0); // port + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to copy from SOE DMEM\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + goto _soeGetInitMessage_exit; + } + } + + if (pMsg->hdr.unitId != RM_SOE_UNIT_INIT) + { + status = NV_ERR_INVALID_STATE; + NVSWITCH_ASSERT(0); + goto _soeGetInitMessage_exit; + } + + // read the message body and update the tail position + if (pFlcn->bEmemEnabled) + { + // + // We use the offset in DMEM for the src address, since + // EmemCopyFrom automatically converts it to the offset in EMEM + // + flcnableEmemCopyFrom( + device, pFlcn->pFlcnable, + tail + RM_FLCN_QUEUE_HDR_SIZE, // src + (NvU8 *)&pMsg->msg, // pDst + pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes + rmEmemPortId); // port + } + else + { + status = flcnDmemCopyFrom(device, + pFlcn, + tail + RM_FLCN_QUEUE_HDR_SIZE, // src + (NvU8 *)&pMsg->msg, // pDst + pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes + 0); // port + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to copy from SOE DMEM\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + goto _soeGetInitMessage_exit; + } + } + + tail += NV_ALIGN_UP(pMsg->hdr.size, SOE_DMEM_ALIGNMENT); + flcnMsgQueueTailSet(device, pFlcn, + &pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], tail); + +_soeGetInitMessage_exit: + return status; +} + +/*! + * This function exists to solve a natural chicken-and-egg problem that arises + * due to the fact that queue information (location, size, id, etc...) is + * relayed to the RM as a message in a queue. Queue construction is done when + * the message arrives and the normal queue read/write functions are not + * available until construction is complete. Construction cannot be done until + * the message is read from the queue. Therefore, the very first message read + * from the Message Queue must be considered as a special-case and must NOT use + * any functionality provided by the SOE's queue manager. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * + * @return 'NV_OK' + * Upon successful extraction and processing of the first SOE message. + */ +static NV_STATUS +_soeProcessMessagesPreInit_LR10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + RM_FLCN_MSG_SOE msg; + NV_STATUS status; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + // extract the "INIT" message (this is never expected to fail) + status = _soeGetInitMessage(device, pSoe, &msg); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to extract the INIT message " + "from the SOE Message Queue (status=0x%08x).", + __FUNCTION__, status); + NVSWITCH_ASSERT(0); + return status; + } + + // + // Now hookup the "real" message-processing function and handle the "INIT" + // message. + // + pSoe->base.pHal->processMessages = _soeProcessMessages_LR10; + return flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&msg, NV_OK); +} + +/*! + * @brief Process the "INIT" message sent from the SOE ucode application. + * + * When the SOE ucode is done initializing, it will post an INIT message in + * the Message Queue that contains all the necessary attributes that are + * needed to enqueuing commands and extracting messages from the queues. + * The packet will also contain the offset and size of portion of DMEM that + * the RM must manage. Upon receiving this message it will be assume that + * the SOE is ready to start accepting commands. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * @param[in] pMsg Pointer to the event's message data + * + * @return 'NV_OK' if the event was successfully handled. + */ +static NV_STATUS +_soeHandleInitEvent_LR10 +( + nvswitch_device *device, + PFLCNABLE pSoe, + RM_FLCN_MSG *pGenMsg +) +{ + NV_STATUS status; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg; + + if (pFlcn == NULL) + { + NVSWITCH_ASSERT(pFlcn != NULL); + return NV_ERR_INVALID_POINTER; + } + + NVSWITCH_PRINT(device, INFO, + "%s: Received INIT message from SOE\n", + __FUNCTION__); + + // + // Pass the INIT message to the queue manager to allow it to create the + // queues. + // + status = _soeQMgrCreateQueuesFromInitMsg(device, pSoe, pMsg); + if (status != NV_OK) + { + NVSWITCH_ASSERT(0); + return status; + } + + flcnDbgInfoDmemOffsetSet(device, pFlcn, + pMsg->msg.init.soeInit.osDebugEntryPoint); + + // the SOE ucode is now initialized and ready to accept commands + pFlcn->bOSReady = NV_TRUE; + + return NV_OK; +} + +/*! + * Loop until SOE RTOS is loaded and gives us an INIT message + * + * @param[in] device nvswitch_device object pointer + * @param[in] pSoe SOE object pointer + */ +static NV_STATUS +_soeWaitForInitAck_LR10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + NVSWITCH_TIMEOUT timeout; + NvBool bKeepPolling; + + // If INIT message is already loaded, return. + if (pFlcn->bOSReady) + { + return NV_OK; + } + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + do + { + bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + soeService_HAL(device, pSoe); + if (pFlcn->bOSReady) + { + return NV_OK; + } + + nvswitch_os_sleep(1); + } + while (bKeepPolling); + + if (!pFlcn->bOSReady) + { + NVSWITCH_PRINT(device, ERROR, + "%s Timeout while waiting for SOE bootup\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return NV_ERR_TIMEOUT; + } + + return NV_OK; +} + /*! * @brief set hal function pointers for functions defined in LR10 (i.e. this file) * @@ -2182,6 +2562,7 @@ soeSetupHal_LR10 pParentHal->destruct = _soeDestruct_LR10; pParentHal->getExternalConfig = _soeGetExternalConfig_LR10; pParentHal->fetchEngines = _soeFetchEngines_LR10; + pParentHal->handleInitEvent = _soeHandleInitEvent_LR10; // set any functions specific to SOE pHal->service = _soeService_LR10; @@ -2201,4 +2582,6 @@ soeSetupHal_LR10 pHal->forceThermalSlowdown = _soeForceThermalSlowdown_LR10; pHal->setPcieLinkSpeed = _soeSetPcieLinkSpeed_LR10; pHal->getPexEomStatus = _soeGetPexEomStatus_LR10; + pHal->processMessages = _soeProcessMessagesPreInit_LR10; + pHal->waitForInitAck = _soeWaitForInitAck_LR10; } diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index 5b7eeee85..b1f3ce11b 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -61,17 +61,22 @@ break; \ } \ -// -// HW's device id list can be found here - -// P4hw:2001: hw\doc\engr\Dev_ID\DeviceID_master_list.txt -// - const static NvU32 nvswitch_lr10_device_ids[] = { 0x1AE8, 0x1AF0, 0x1AF1, 0x1AF2, 0x1AF3, 0x1AF4, 0x1AF5, 0x1AF6, 0x1AF7, 0x1AF8, 0x1AF9, 0x1AFA, 0x1AFB, 0x1AFC, 0x1AFD, 0x1AFE, 0x1AFF }; +const static NvU32 nvswitch_ls10_device_ids[] = +{ + // PCIE endpoint to manage the NVLink switch HW + 0x22A0, 0x22A1, 0x22A2, 0x22A3, 0x22A4, 0x22A5, 0x22A6, 0x22A7, + // PCI-PCI Bridge, Laguna Switch Function 0 + 0x22A8, 0x22A9, 0x22AA, 0x22AB, + // Non-Transparent Bridge, Laguna Switch Function 1 + 0x22AC, 0x22AD, 0x22AE, 0x22AF +}; + nvlink_link_handlers link_handlers; static NvBool @@ -107,6 +112,18 @@ nvswitch_is_lr10_device_id return _nvswitch_is_device_id_present(nvswitch_lr10_device_ids, count, device_id); } +NvBool +nvswitch_is_ls10_device_id +( + NvU32 device_id +) +{ + NvU32 count = (sizeof(nvswitch_ls10_device_ids) / + sizeof(nvswitch_ls10_device_ids[0])); + + return _nvswitch_is_device_id_present(nvswitch_ls10_device_ids, count, device_id); +} + /* * NVLink corelib callbacks are used by the NVLink library separate from the * NVSwitch driver, therefore they do not take a device lock and can not modify @@ -283,6 +300,16 @@ _nvswitch_corelib_write_discovery_token return NVL_SUCCESS; } +static NV_API_CALL NvlStatus +_nvswitch_corelib_ali_training +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + return device->hal.nvswitch_launch_ALI_link_training(device, link, NV_FALSE); +} + void nvswitch_get_link_handlers ( @@ -310,6 +337,7 @@ nvswitch_get_link_handlers nvswitch_link_handlers->training_complete = _nvswitch_corelib_training_complete; nvswitch_link_handlers->get_uphy_load = _nvswitch_corelib_get_uphy_load; nvswitch_link_handlers->write_discovery_token = _nvswitch_corelib_write_discovery_token; + nvswitch_link_handlers->ali_training = _nvswitch_corelib_ali_training; } #define NVSWITCH_INIT_REGKEY(_private, _regkey, _string, _default_val) \ @@ -358,7 +386,7 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF); // - // Private internal use regkeys + // Debug use regkeys // Not available on release build kernel drivers // NVSWITCH_INIT_REGKEY(_PRIVATE, external_fabric_mgmt, @@ -429,9 +457,6 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_SOE_DISABLE, NV_SWITCH_REGKEY_SOE_DISABLE_NO); - NVSWITCH_INIT_REGKEY(_PUBLIC, soe_boot_core, - NV_SWITCH_REGKEY_SOE_BOOT_CORE, - NV_SWITCH_REGKEY_SOE_BOOT_CORE_DEFAULT); NVSWITCH_INIT_REGKEY(_PRIVATE, latency_counter, NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING, NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING_ENABLE); @@ -472,6 +497,10 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES, NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, link_training_mode, + NV_SWITCH_REGKEY_LINK_TRAINING_SELECT, + NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, i2c_access_control, NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL, NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_DEFAULT); @@ -604,15 +633,6 @@ nvswitch_is_smbpbi_supported return device->hal.nvswitch_is_smbpbi_supported(device); } -NvlStatus -nvswitch_soe_prepare_for_reset -( - nvswitch_device *device -) -{ - return device->hal.nvswitch_soe_prepare_for_reset(device); -} - NvBool nvswitch_is_soe_supported ( @@ -628,16 +648,6 @@ nvswitch_is_soe_supported return device->hal.nvswitch_is_soe_supported(device); } -NvlStatus -nvswitch_soe_set_ucode_core -( - nvswitch_device *device, - NvBool bFalcon -) -{ - return device->hal.nvswitch_soe_set_ucode_core(device, bFalcon); -} - NvlStatus nvswitch_init_soe ( @@ -1145,6 +1155,12 @@ nvswitch_lib_initialize_device nvListInit(&device->client_events_list); + for (link_num=0; link_num < nvswitch_get_num_links(device); link_num++) + { + nvListInit(&device->link[link_num].inbandData.persistent_list); + nvListInit(&device->link[link_num].inbandData.nonpersistent_list); + } + retval = nvswitch_lib_load_platform_info(device); if (retval != NVL_SUCCESS) { @@ -1363,6 +1379,10 @@ nvswitch_lib_validate_device_id { return NV_TRUE; } + if (nvswitch_is_ls10_device_id(device_id)) + { + return NV_TRUE; + } return NV_FALSE; } @@ -1414,6 +1434,8 @@ nvswitch_lib_post_init_device nvswitch_smbpbi_post_init(device); + (void)nvswitch_launch_ALI(device); + return NVL_SUCCESS; } @@ -1862,6 +1884,10 @@ nvswitch_lib_register_device // _nvswitch_init_device_regkeys(device); + // After regkeys have been set then only set the enableALI field. + device->nvlink_device->enableALI = (device->regkeys.link_training_mode == + NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI) ? NV_TRUE:NV_FALSE; + retval = nvlink_lib_register_device(device->nvlink_device); if (NVL_SUCCESS != retval) { @@ -2390,6 +2416,24 @@ _nvswitch_ctrl_set_ganged_link_table return device->hal.nvswitch_ctrl_set_ganged_link_table(device, p); } +void +nvswitch_init_npg_multicast +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_init_npg_multicast(device); +} + +void +nvswitch_init_warm_reset +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_init_warm_reset(device); +} + static NvlStatus _nvswitch_ctrl_set_remap_policy ( @@ -2710,6 +2754,150 @@ _nvswitch_ctrl_get_rb_stall_busy return device->hal.nvswitch_ctrl_get_rb_stall_busy(device, p); } +NvlStatus +nvswitch_ctrl_get_multicast_id_error_vector +( + nvswitch_device *device, + NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p +) +{ + return device->hal.nvswitch_ctrl_get_multicast_id_error_vector(device, p); +} + +NvlStatus +nvswitch_ctrl_clear_multicast_id_error_vector +( + nvswitch_device *device, + NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p +) +{ + return device->hal.nvswitch_ctrl_clear_multicast_id_error_vector(device, p); +} + +static NvlStatus +_nvswitch_ctrl_inband_send_data +( + nvswitch_device *device, + NVSWITCH_INBAND_SEND_DATA_PARAMS *p +) +{ + return device->hal.nvswitch_ctrl_inband_send_data(device, p); +} + +static NvlStatus +_nvswitch_ctrl_inband_read_data +( + nvswitch_device *device, + NVSWITCH_INBAND_READ_DATA_PARAMS *p +) +{ + return device->hal.nvswitch_ctrl_inband_read_data(device, p); +} + +/* + * @Brief : Deletes all the entires in persistant or nonpersistant list + * + * @Description : + * + * @param[in] device NvSwitch device to contain this link + * @param[in] linkId link number of the link + * + */ +static void +_nvswitch_inband_clear_list +( + nvswitch_device *device, + NvU32 linkId +) +{ + nvswitch_inband_data_list *curr = NULL; + nvswitch_inband_data_list *next = NULL; + + nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.persistent_list, entry) + { + nvListDel(&curr->entry); + nvswitch_os_free(curr); + } + + nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.nonpersistent_list, entry) + { + nvListDel(&curr->entry); + nvswitch_os_free(curr); + } +} + +static NvlStatus +_nvswitch_ctrl_inband_flush_data +( + nvswitch_device *device, + NVSWITCH_INBAND_FLUSH_DATA_PARAMS *p +) +{ + NvU32 i; + NvU64 enabledLinkMask; + + if (p->linkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "Nothing to clear\n"); + return NVL_SUCCESS; + } + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + + FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask) + { + if (nvswitch_is_link_valid(device, i) && + (enabledLinkMask & NVBIT(i))) + { + _nvswitch_inband_clear_list(device, i); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_ctrl_inband_pending_data_stats +( + nvswitch_device *device, + NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS *p +) +{ + NvU32 link_num; + NvU64 enabledLinkMask, persistent_mask = 0, nonpersistent_mask = 0; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + + for (link_num = 0; link_num < nvswitch_get_num_links(device); link_num++) + { + if (nvswitch_is_link_valid(device, link_num) && + (enabledLinkMask & NVBIT(link_num))) + { + if (!nvListIsEmpty(&device->link[link_num].inbandData.persistent_list)) + { + persistent_mask |= NVBIT(link_num); + } + + if (!nvListIsEmpty(&device->link[link_num].inbandData.nonpersistent_list)) + { + nonpersistent_mask |= NVBIT(link_num); + } + } + } + + if (persistent_mask > 0) + { + p->linkMask = persistent_mask; + } + else + { + p->linkMask = nonpersistent_mask; + } + + return NVL_SUCCESS; +} + static NvlStatus _nvswitch_ctrl_i2c_smbus_command ( @@ -2884,6 +3072,72 @@ _nvswitch_lib_validate_privileged_ctrl return -NVL_ERR_INSUFFICIENT_PERMISSIONS; } +/* + * @Brief : Copy the data from the persistant or nonpersistant list + * + * @Description : + * + * @param[in] device NvSwitch device to contain this link + * @param[out] data Destination Data + * @param[in] linkId link number of the link + * @param[out] dataSize Size of data copied + * + * @returns NVL_SUCCESS if action succeeded, + * -NVL_NOT_FOUND if link doesnt have data + */ +NvlStatus +nvswitch_inband_read_data +( + nvswitch_device *device, + NvU8 *dest, + NvU32 linkId, + NvU32 *dataSize +) +{ + nvswitch_inband_data_list *curr = NULL; + NVListRec *list; + + if (nvListIsEmpty(&device->link[linkId].inbandData.persistent_list) && + nvListIsEmpty(&device->link[linkId].inbandData.nonpersistent_list)) + { + *dataSize = 0; + return -NVL_NOT_FOUND; + } + + list = nvListIsEmpty(&device->link[linkId].inbandData.persistent_list) ? + &device->link[linkId].inbandData.nonpersistent_list : + &device->link[linkId].inbandData.persistent_list; + + nvListForEachEntry(curr, list, entry) + { + *dataSize = curr->dataSize; + nvswitch_os_memcpy(dest, curr->data, curr->dataSize); + nvListDel(&curr->entry); + nvswitch_os_free(curr); + break; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Moves the data into persistant or nonpersistant list + * + * @Description : + * + * @param[in] device NvSwitch device to contain this link + * @param[in] linkId link number of the link + * + */ +void +nvswitch_filter_messages +( + nvswitch_device *device, + NvU32 linkId +) +{ +} + /* * @Brief : Constructs an NVS link struct with the given data * @@ -3769,17 +4023,6 @@ nvswitch_pri_ring_init return(device->hal.nvswitch_pri_ring_init(device)); } -NvlStatus -nvswitch_get_soe_ucode_binaries -( - nvswitch_device *device, - const NvU32 **soe_ucode_data, - const NvU32 **soe_ucode_header -) -{ - return device->hal.nvswitch_get_soe_ucode_binaries(device, soe_ucode_data, soe_ucode_header); -} - NvlStatus nvswitch_get_remap_table_selector ( @@ -3874,6 +4117,15 @@ nvswitch_init_lpwr_regs device->hal.nvswitch_init_lpwr_regs(link); } +NvlStatus +nvswitch_launch_ALI +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_launch_ALI(device); +} + NvlStatus nvswitch_set_training_mode ( @@ -3935,6 +4187,17 @@ nvswitch_apply_recal_settings return device->hal.nvswitch_apply_recal_settings(device, link); } +NvlStatus +nvswitch_launch_ALI_link_training +( + nvswitch_device *device, + nvlink_link *link, + NvBool bSync +) +{ + return device->hal.nvswitch_launch_ALI_link_training(device, link, bSync); +} + NvlStatus nvswitch_lib_ctrl ( @@ -4195,6 +4458,32 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_RB_STALL_BUSY, _nvswitch_ctrl_get_rb_stall_busy, NVSWITCH_GET_RB_STALL_BUSY); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR, + nvswitch_ctrl_get_multicast_id_error_vector, + NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR, + nvswitch_ctrl_clear_multicast_id_error_vector, + NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_INBAND_SEND_DATA, + _nvswitch_ctrl_inband_send_data, + NVSWITCH_INBAND_SEND_DATA_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_INBAND_READ_DATA, + _nvswitch_ctrl_inband_read_data, + NVSWITCH_INBAND_READ_DATA_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_INBAND_FLUSH_DATA, + _nvswitch_ctrl_inband_flush_data, + NVSWITCH_INBAND_FLUSH_DATA_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS, + _nvswitch_ctrl_inband_pending_data_stats, + NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS, + osPrivate, flags); NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( CTRL_NVSWITCH_GET_SW_INFO, _nvswitch_ctrl_get_sw_info, diff --git a/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c b/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c index 70551a46a..516ce5c18 100644 --- a/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c +++ b/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c @@ -343,3 +343,35 @@ soeSetPcieLinkSpeed_HAL return pSoe->base.pHal->setPcieLinkSpeed(device, linkSpeed); } + +NV_STATUS +soeProcessMessages_HAL +( + nvswitch_device *device, + PSOE pSoe +) +{ + if (pSoe->base.pHal->processMessages == NULL) + { + NVSWITCH_ASSERT(0); + return 0; + } + + return pSoe->base.pHal->processMessages(device, pSoe); +} + +NV_STATUS +soeWaitForInitAck_HAL +( + nvswitch_device *device, + PSOE pSoe +) +{ + if (pSoe->base.pHal->waitForInitAck == NULL) + { + NVSWITCH_ASSERT(0); + return 0; + } + + return pSoe->base.pHal->waitForInitAck(device, pSoe); +} diff --git a/src/common/nvswitch/kernel/soe/soe_nvswitch.c b/src/common/nvswitch/kernel/soe/soe_nvswitch.c index a012917b9..b83b76577 100644 --- a/src/common/nvswitch/kernel/soe/soe_nvswitch.c +++ b/src/common/nvswitch/kernel/soe/soe_nvswitch.c @@ -31,365 +31,6 @@ #include "rmflcncmdif_nvswitch.h" #include "common_nvswitch.h" -static NV_STATUS _soeGetInitMessage(nvswitch_device *device, PSOE pSoe, RM_FLCN_MSG_SOE *pMsg); - -/*! - * Use the SOE INIT Message to construct and initialize all SOE Queues. - * - * @param[in] device nvswitch_device pointer - * @param[in] pSoe SOE object pointer - * @param[in] pMsg Pointer to the INIT Message - * - * @return 'NV_OK' upon successful creation of all SOE Queues - */ -static NV_STATUS -_soeQMgrCreateQueuesFromInitMsg -( - nvswitch_device *device, - PFLCNABLE pSoe, - RM_FLCN_MSG_SOE *pMsg -) -{ - RM_SOE_INIT_MSG_SOE_INIT *pInit; - NvU32 i; - NvU32 queueLogId; - NV_STATUS status; - FLCNQUEUE *pQueue; - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - PFALCON_QUEUE_INFO pQueueInfo; - - NVSWITCH_ASSERT(pFlcn != NULL); - - pQueueInfo = pFlcn->pQueueInfo; - NVSWITCH_ASSERT(pQueueInfo != NULL); - - pInit = &pMsg->msg.init.soeInit; - NVSWITCH_ASSERT(pInit->numQueues <= pFlcn->numQueues); - - for (i = 0; i < pFlcn->numQueues; i++) - { - queueLogId = pInit->qInfo[i].queueLogId; - NVSWITCH_ASSERT(queueLogId < pFlcn->numQueues); - pQueue = &pQueueInfo->pQueues[queueLogId]; - status = flcnQueueConstruct_dmem_nvswitch( - device, - pFlcn, - &pQueue, // ppQueue - queueLogId, // Logical ID of the queue - pInit->qInfo[i].queuePhyId, // Physical ID of the queue - pInit->qInfo[i].queueOffset, // offset - pInit->qInfo[i].queueSize, // size - RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize - if (status != NV_OK) - { - NVSWITCH_PRINT(device, ERROR, - "%s: Error constructing SOE Queue (status=" - "0x%08x).\n", __FUNCTION__, status); - NVSWITCH_ASSERT(0); - return status; - } - } - return NV_OK; -} - -/*! - * Purges all the messages from the SOE's message queue. Each message will - * be analyzed, clients will be notified of status, and events will be routed - * to all registered event listeners. - * - * @param[in] device nvswitch_device pointer - * @param[in] pSoe SOE object pointer - * - * @return 'NV_OK' if the message queue was successfully purged. - */ -static NV_STATUS -_soeProcessMessages_IMPL -( - nvswitch_device *device, - PSOE pSoe -) -{ - RM_FLCN_MSG_SOE soeMessage; - NV_STATUS status; - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - - // keep processing messages until no more exist in the message queue - while (NV_OK == (status = flcnQueueReadData( - device, - pFlcn, - SOE_RM_MSGQ_LOG_ID, - (RM_FLCN_MSG *)&soeMessage, NV_TRUE))) - { - NVSWITCH_PRINT(device, INFO, - "%s: unitId=0x%02x, size=0x%02x, ctrlFlags=0x%02x, " \ - "seqNumId=0x%02x\n", - __FUNCTION__, - soeMessage.hdr.unitId, - soeMessage.hdr.size, - soeMessage.hdr.ctrlFlags, - soeMessage.hdr.seqNumId); - - // check to see if the message is a reply or an event. - if ((soeMessage.hdr.ctrlFlags &= RM_FLCN_QUEUE_HDR_FLAGS_EVENT) != 0) - { - flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage, NV_OK); - } - // the message is a response from a previously queued command - else - { - flcnQueueResponseHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage); - } - } - - // - // Status NV_ERR_NOT_READY implies, Queue is empty. - // Log the message in other error cases. - // - if (status != NV_ERR_NOT_READY) - { - NVSWITCH_PRINT(device, ERROR, - "%s: unexpected error while purging message queue (status=0x%x).\n", - __FUNCTION__, (status)); - } - - return status; -} - -/*! - * This function exists to solve a natural chicken-and-egg problem that arises - * due to the fact that queue information (location, size, id, etc...) is - * relayed to the RM as a message in a queue. Queue construction is done when - * the message arives and the normal queue read/write functions are not - * available until construction is complete. Construction cannot be done until - * the message is read from the queue. Therefore, the very first message read - * from the Message Queue must be considered as a special-case and must NOT use - * any functionality provided by the SOE's queue manager. - * - * @param[in] device nvswitch_device pointer - * @param[in] pSoe SOE object pointer - * - * @return 'NV_OK' - * Upon successful extraction and processing of the first SOE message. - */ -static NV_STATUS -_soeProcessMessagesPreInit_IMPL -( - nvswitch_device *device, - PSOE pSoe -) -{ - RM_FLCN_MSG_SOE msg; - NV_STATUS status; - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - - // extract the "INIT" message (this is never expected to fail) - status = _soeGetInitMessage(device, pSoe, &msg); - if (status != NV_OK) - { - NVSWITCH_PRINT(device, ERROR, - "%s: Failed to extract the INIT message " - "from the SOE Message Queue (status=0x%08x).", - __FUNCTION__, status); - NVSWITCH_ASSERT(0); - return status; - } - - // - // Now hookup the "real" message-processing function and handle the "INIT" - // message. - // - pSoe->base.pHal->processMessages = _soeProcessMessages_IMPL; - return flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&msg, NV_OK); -} - -/*! - * @brief Process the "INIT" message sent from the SOE ucode application. - * - * When the SOE ucode is done initializing, it will post an INIT message in - * the Message Queue that contains all the necessary attributes that are - * needed to enqueuing commands and extracting messages from the queues. - * The packet will also contain the offset and size of portion of DMEM that - * the RM must manage. Upon receiving this message it will be assume that - * the SOE is ready to start accepting commands. - * - * @param[in] device nvswitch_device pointer - * @param[in] pSoe SOE object pointer - * @param[in] pMsg Pointer to the event's message data - * - * @return 'NV_OK' if the event was successfully handled. - */ -static NV_STATUS -_soeHandleInitEvent_IMPL -( - nvswitch_device *device, - PFLCNABLE pSoe, - RM_FLCN_MSG *pGenMsg -) -{ - NV_STATUS status; - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg; - - if (pFlcn == NULL) - { - NVSWITCH_ASSERT(pFlcn != NULL); - return NV_ERR_INVALID_POINTER; - } - - NVSWITCH_PRINT(device, INFO, - "%s: Received INIT message from SOE\n", - __FUNCTION__); - - // - // Pass the INIT message to the queue manager to allow it to create the - // queues. - // - status = _soeQMgrCreateQueuesFromInitMsg(device, pSoe, pMsg); - if (status != NV_OK) - { - NVSWITCH_ASSERT(0); - return status; - } - - flcnDbgInfoDmemOffsetSet(device, pFlcn, - pMsg->msg.init.soeInit.osDebugEntryPoint); - - // the SOE ucode is now initialized and ready to accept commands - pFlcn->bOSReady = NV_TRUE; - - return NV_OK; -} - -/*! - * @brief Read the INIT message directly out of the Message Queue. - * - * This function accesses the Message Queue directly using the HAL. It does - * NOT and may NOT use the queue manager as it has not yet been constructed and - * initialized. The Message Queue may not be empty when this function is called - * and the first message in the queue MUST be the INIT message. - * - * @param[in] device nvswitch_device pointer - * @param[in] pSoe SOE object pointer - * @param[out] pMsg Message structure to fill with the INIT message data - * - * @return 'NV_OK' upon successful extraction of the INIT message. - * @return - * 'NV_ERR_INVALID_STATE' if the first message found was not an INIT - * message or if the message was improperly formatted. - */ -static NV_STATUS -_soeGetInitMessage -( - nvswitch_device *device, - PSOE pSoe, - RM_FLCN_MSG_SOE *pMsg -) -{ - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - NV_STATUS status = NV_OK; - NvU32 tail = 0; - PFALCON_QUEUE_INFO pQueueInfo; - // on the GPU, rmEmemPortId = sec2RmEmemPortIdGet_HAL(...); - NvU8 rmEmemPortId = 0; - - if (pFlcn == NULL) - { - NVSWITCH_ASSERT(pFlcn != NULL); - return NV_ERR_INVALID_POINTER; - } - - pQueueInfo = pFlcn->pQueueInfo; - if (pQueueInfo == NULL) - { - NVSWITCH_ASSERT(pQueueInfo != NULL); - return NV_ERR_INVALID_POINTER; - } - - // - // Message queue 0 is used by SOE to communicate with RM - // Check SOE_CMDMGMT_MSG_QUEUE_RM in //uproc/soe/inc/soe_cmdmgmt.h - // - pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID].queuePhyId = 0; - - // read the header starting at the current tail position - (void)flcnMsgQueueTailGet(device, pFlcn, - &pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], &tail); - if (pFlcn->bEmemEnabled) - { - // - // We use the offset in DMEM for the src address, since - // EmemCopyFrom automatically converts it to the offset in EMEM - // - flcnableEmemCopyFrom( - device, pFlcn->pFlcnable, - tail, // src - (NvU8 *)&pMsg->hdr, // pDst - RM_FLCN_QUEUE_HDR_SIZE, // numBytes - rmEmemPortId); // port - } - else - { - status = flcnDmemCopyFrom(device, - pFlcn, - tail, // src - (NvU8 *)&pMsg->hdr, // pDst - RM_FLCN_QUEUE_HDR_SIZE, // numBytes - 0); // port - if (status != NV_OK) - { - NVSWITCH_PRINT(device, ERROR, - "%s: Failed to copy from SOE DMEM\n", __FUNCTION__); - NVSWITCH_ASSERT(0); - goto _soeGetInitMessage_exit; - } - } - - if (pMsg->hdr.unitId != RM_SOE_UNIT_INIT) - { - status = NV_ERR_INVALID_STATE; - NVSWITCH_ASSERT(0); - goto _soeGetInitMessage_exit; - } - - // read the message body and update the tail position - if (pFlcn->bEmemEnabled) - { - // - // We use the offset in DMEM for the src address, since - // EmemCopyFrom automatically converts it to the offset in EMEM - // - flcnableEmemCopyFrom( - device, pFlcn->pFlcnable, - tail + RM_FLCN_QUEUE_HDR_SIZE, // src - (NvU8 *)&pMsg->msg, // pDst - pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes - rmEmemPortId); // port - } - else - { - status = flcnDmemCopyFrom(device, - pFlcn, - tail + RM_FLCN_QUEUE_HDR_SIZE, // src - (NvU8 *)&pMsg->msg, // pDst - pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes - 0); // port - if (status != NV_OK) - { - NVSWITCH_PRINT(device, ERROR, - "%s: Failed to copy from SOE DMEM\n", __FUNCTION__); - NVSWITCH_ASSERT(0); - goto _soeGetInitMessage_exit; - } - } - - tail += NV_ALIGN_UP(pMsg->hdr.size, SOE_DMEM_ALIGNMENT); - flcnMsgQueueTailSet(device, pFlcn, - &pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], tail); - -_soeGetInitMessage_exit: - return status; -} - /*! * Copies 'sizeBytes' from DMEM address 'src' to 'pDst' using EMEM access port. * @@ -444,43 +85,6 @@ _soeEmemCopyTo_IMPL soeEmemTransfer_HAL(device, (PSOE)pSoe, dst, pSrc, sizeBytes, port, NV_FALSE); } -/*! - * Loop until SOE RTOS is loaded and gives us an INIT message - * - * @param[in] device nvswitch_device object pointer - * @param[in] pSoe SOE object pointer - */ -static NV_STATUS -_soeWaitForInitAck_IMPL -( - nvswitch_device *device, - PSOE pSoe -) -{ - PFLCN pFlcn = ENG_GET_FLCN(pSoe); - // POBJMC pMc = GPU_GET_MC(device); - NVSWITCH_TIMEOUT timeout; - - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); - while (!pFlcn->bOSReady && !nvswitch_timeout_check(&timeout)) - { - // Once interrupt handling is ready, might need to replace this with - //mcServiceSingle_HAL(device, pMc, MC_ENGINE_IDX_SOE, NV_FALSE); - soeService_HAL(device, pSoe); - nvswitch_os_sleep(1); - } - - if (!pFlcn->bOSReady) - { - NVSWITCH_PRINT(device, ERROR, - "%s Timeout while waiting for SOE bootup\n", - __FUNCTION__); - NVSWITCH_ASSERT(0); - return NV_ERR_TIMEOUT; - } - return NV_OK; -} - /*! * @brief Retrieves a pointer to the engine specific SEQ_INFO structure. * @@ -585,15 +189,10 @@ soeSetupHal pHal = pSoe->base.pHal; pParentHal = (flcnable_hal *)pHal; //set any functions we want to override - pParentHal->handleInitEvent = _soeHandleInitEvent_IMPL; pParentHal->ememCopyTo = _soeEmemCopyTo_IMPL; pParentHal->ememCopyFrom = _soeEmemCopyFrom_IMPL; pParentHal->queueSeqInfoGet = _soeQueueSeqInfoGet_IMPL; pParentHal->queueCmdValidate = _soeQueueCmdValidate_IMPL; - - //set any functions specific to SOE - pHal->processMessages = _soeProcessMessagesPreInit_IMPL; - pHal->waitForInitAck = _soeWaitForInitAck_IMPL; } SOE * diff --git a/src/common/sdk/nvidia/inc/class/cl0000.h b/src/common/sdk/nvidia/inc/class/cl0000.h index c33bdb4c0..713eb7b84 100644 --- a/src/common/sdk/nvidia/inc/class/cl0000.h +++ b/src/common/sdk/nvidia/inc/class/cl0000.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,63 +21,32 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl0000_h_ -#define _cl0000_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0000.finn +// -#include "nvtypes.h" #include "nvlimits.h" +#include "cl0000_notification.h" /* object NV01_NULL_OBJECT */ -#define NV01_NULL_OBJECT (0x00000000) -/* obsolete alises */ -#define NV1_NULL_OBJECT NV01_NULL_OBJECT - -/*event values*/ -#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0) -#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1) -#define NV0000_NOTIFIERS_VM_START (2) -#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3) -#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4) -#define NV0000_NOTIFIERS_MAXCOUNT (5) +#define NV01_NULL_OBJECT (0x00000000) -/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/ - -#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0) - -//--------------------------------------------------------------------------- +/* obsolete alises */ +#define NV1_NULL_OBJECT NV01_NULL_OBJECT -#define NV01_ROOT (0x00000000) -/* NvNotification[] fields and values */ -#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV01_ROOT (0x00000000) /* NvAlloc parameteters */ -typedef struct { +#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U) + +typedef struct NV0000_ALLOC_PARAMETERS { NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */ NvU32 processID; char processName[NV_PROC_NAME_MAX_LENGTH]; } NV0000_ALLOC_PARAMETERS; - /* pio method data structure */ -typedef volatile struct _cl0000_tag0 { - NvV32 Reserved00[0x7c0]; -} Nv000Typedef, Nv01Root; - -/* obsolete aliases */ -#define NV000_TYPEDEF Nv01Root -#define Nv1Root Nv01Root -#define nv1Root Nv01Root -#define nv01Root Nv01Root - -/*event values*/ -#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1) - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl0000_h_ */ - diff --git a/src/common/sdk/nvidia/inc/class/cl0000_notification.h b/src/common/sdk/nvidia/inc/class/cl0000_notification.h new file mode 100644 index 000000000..79b51d9ed --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl0000_notification.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0000_notification_h_ +#define _cl0000_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*event values*/ +#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0) +#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1) +#define NV0000_NOTIFIERS_VM_START (2) +#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3) +#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4) +#define NV0000_NOTIFIERS_MAXCOUNT (5) + +/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/ + +#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0) + +//--------------------------------------------------------------------------- + +/* NvNotification[] fields and values */ +#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + + +/* pio method data structure */ +typedef volatile struct _cl0000_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv000Typedef, Nv01Root; + +/* obsolete aliases */ +#define NV000_TYPEDEF Nv01Root +#define Nv1Root Nv01Root +#define nv1Root Nv01Root +#define nv01Root Nv01Root + +/*event values*/ +#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0000_notification_h_ */ + diff --git a/src/common/sdk/nvidia/inc/class/cl0005.h b/src/common/sdk/nvidia/inc/class/cl0005.h index af4ddcc0b..a963d15b6 100644 --- a/src/common/sdk/nvidia/inc/class/cl0005.h +++ b/src/common/sdk/nvidia/inc/class/cl0005.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,39 +21,32 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl0005_h_ -#define _cl0005_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0005.finn +// -#define NV01_EVENT (0x00000005) -/* NvNotification[] fields and values */ -#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) -/* pio method data structure */ -typedef volatile struct _cl0005_tag0 { - NvV32 Reserved00[0x7c0]; -} Nv005Typedef, Nv01Event; -#define NV005_TYPEDEF Nv01Event -/* obsolete stuff */ -#define NV1_TIMER (0x00000004) -#define Nv1Event Nv01Event -#define nv1Event Nv01Event -#define nv01Event Nv01Event +#include "cl0005_notification.h" + +#define NV01_EVENT (0x00000005) /* NvRmAlloc() parameters */ -typedef struct { +#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U) + +typedef struct NV0005_ALLOC_PARAMETERS { NvHandle hParentClient; NvHandle hSrcResource; NvV32 hClass; NvV32 notifyIndex; - NvP64 data NV_ALIGN_BYTES(8); + NV_DECLARE_ALIGNED(NvP64 data, 8); } NV0005_ALLOC_PARAMETERS; + /* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the * notifyIndex value itself, plus flags, and optionally a subdevice field if * flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_* @@ -63,9 +56,3 @@ typedef struct { #define NV0005_NOTIFY_INDEX_INDEX 15:0 #define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16 #define NV0005_NOTIFY_INDEX_FLAGS 31:24 - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl0005_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl0005_notification.h b/src/common/sdk/nvidia/inc/class/cl0005_notification.h new file mode 100644 index 000000000..5e6b32ef7 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl0005_notification.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0005_notification_h_ +#define _cl0005_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0005_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv005Typedef, Nv01Event; + +#define NV005_TYPEDEF Nv01Event + +/* obsolete stuff */ +#define NV1_TIMER (0x00000004) +#define Nv1Event Nv01Event +#define nv1Event Nv01Event +#define nv01Event Nv01Event + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0005_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl000f.h b/src/common/sdk/nvidia/inc/class/cl000f.h index 43663d191..961a619d2 100644 --- a/src/common/sdk/nvidia/inc/class/cl000f.h +++ b/src/common/sdk/nvidia/inc/class/cl000f.h @@ -21,25 +21,26 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl000f_h_ -#define _cl000f_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl000f.finn +// -#define FABRIC_MANAGER_SESSION (0x0000000F) +#define FABRIC_MANAGER_SESSION (0x0000000F) -#define NV000F_NOTIFIERS_FABRIC_EVENT (0) +#define NV000F_NOTIFIERS_FABRIC_EVENT (0) -#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0 -#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0 -#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1 +#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1 -typedef struct -{ +#define NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID (0x000fU) + +typedef struct NV000F_ALLOCATION_PARAMETERS { // // capDescriptor is a file descriptor for unix RM clients, but a void // pointer for windows RM clients. @@ -52,9 +53,3 @@ typedef struct NvU32 flags; } NV000F_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl000f_h_ */ - diff --git a/src/common/sdk/nvidia/inc/class/cl0060.h b/src/common/sdk/nvidia/inc/class/cl0060.h index 91fddcb6e..bc1eb8e5b 100644 --- a/src/common/sdk/nvidia/inc/class/cl0060.h +++ b/src/common/sdk/nvidia/inc/class/cl0060.h @@ -21,26 +21,21 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _cl0060_h_ -#define _cl0060_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0060.finn +// -#define NV0060_SYNC_GPU_BOOST (0x00000060) +#define NV0060_SYNC_GPU_BOOST (0x00000060) /*! */ -typedef struct { +#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U) + +typedef struct NV0060_ALLOC_PARAMETERS { NvU32 gpuBoostGroupId; } NV0060_ALLOC_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif // _cl0060_h - diff --git a/src/common/sdk/nvidia/inc/class/cl0070.h b/src/common/sdk/nvidia/inc/class/cl0070.h index e9202df9e..fd7fd70ac 100644 --- a/src/common/sdk/nvidia/inc/class/cl0070.h +++ b/src/common/sdk/nvidia/inc/class/cl0070.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2001-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,17 +20,17 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl0070_h_ -#define _cl0070_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0070.finn +// -#define NV01_MEMORY_VIRTUAL (0x00000070) -#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070) +#define NV01_MEMORY_VIRTUAL (0x00000070) +#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070) /* * NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS @@ -61,17 +61,13 @@ extern "C" { * limit - When limit is zero the maximum limit used. If a non-zero limit * is specified then it will be used. The final limit is returned. */ -typedef struct -{ - NvU64 offset NV_ALIGN_BYTES(8); // [IN] - offset into address space - NvU64 limit NV_ALIGN_BYTES(8); // [IN/OUT] - limit of address space - NvHandle hVASpace; // [IN] - Address space handle -} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; +#define NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID (0x0070U) -#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE (0xffffffffu) +typedef struct NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); // [IN] - offset into address space + NV_DECLARE_ALIGNED(NvU64 limit, 8); // [IN/OUT] - limit of address space + NvHandle hVASpace; // [IN] - Address space handle +} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE 0xffffffffU -#endif /* _cl0070_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl0080.h b/src/common/sdk/nvidia/inc/class/cl0080.h index 7a920feed..e1f6a94c3 100644 --- a/src/common/sdk/nvidia/inc/class/cl0080.h +++ b/src/common/sdk/nvidia/inc/class/cl0080.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,27 +21,23 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl0080_h_ -#define _cl0080_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0080.finn +// #include "nvlimits.h" -#include "nvtypes.h" +#include "cl0080_notification.h" -#define NV01_DEVICE_0 (0x00000080) -/* NvNotification[] fields and values */ -#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) -/* pio method data structure */ -typedef volatile struct _cl0080_tag0 { - NvV32 Reserved00[0x7c0]; -} Nv080Typedef, Nv01Device0; -#define NV080_TYPEDEF Nv01Device0 +#define NV01_DEVICE_0 (0x00000080) /* NvAlloc parameteters */ -#define NV0080_MAX_DEVICES NV_MAX_DEVICES +#define NV0080_MAX_DEVICES NV_MAX_DEVICES + /** * @brief Alloc param * @@ -51,21 +47,18 @@ typedef volatile struct _cl0080_tag0 { * NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE * NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES * Detailed description of these modes is in nvos.h - **/ -typedef struct { - NvU32 deviceId; - NvHandle hClientShare; - NvHandle hTargetClient; - NvHandle hTargetDevice; - NvV32 flags; - NvU64 vaSpaceSize NV_ALIGN_BYTES(8); - NvU64 vaStartInternal NV_ALIGN_BYTES(8); - NvU64 vaLimitInternal NV_ALIGN_BYTES(8); - NvV32 vaMode; -} NV0080_ALLOC_PARAMETERS; + **/ -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV0080_ALLOC_PARAMETERS_MESSAGE_ID (0x0080U) -#endif /* _cl0080_h_ */ +typedef struct NV0080_ALLOC_PARAMETERS { + NvU32 deviceId; + NvHandle hClientShare; + NvHandle hTargetClient; + NvHandle hTargetDevice; + NvV32 flags; + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8); + NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8); + NvV32 vaMode; +} NV0080_ALLOC_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl0080_notification.h b/src/common/sdk/nvidia/inc/class/cl0080_notification.h new file mode 100644 index 000000000..a976d3fdd --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl0080_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0080_notification_h_ +#define _cl0080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv080Typedef, Nv01Device0; + +#define NV080_TYPEDEF Nv01Device0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0080_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl00c2.h b/src/common/sdk/nvidia/inc/class/cl00c2.h index eca77e53e..195971377 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c2.h +++ b/src/common/sdk/nvidia/inc/class/cl00c2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,26 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl00c2_h_ -#define _cl00c2_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c2.finn +// -#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2) +#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2) -typedef struct -{ - NvU64 memSize NV_ALIGN_BYTES(8); // [OUT] +#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) + +typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] NvU32 format; // [IN] - PTE format to use NvU32 pageSize; // [IN] - Page size to use } NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl00c2_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl00c3.h b/src/common/sdk/nvidia/inc/class/cl00c3.h index 8d100bc10..b9b31bc1f 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c3.h +++ b/src/common/sdk/nvidia/inc/class/cl00c3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,20 +20,24 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef SDK_CL00C3_H -#define SDK_CL00C3_H +#pragma once -#include "nvtypes.h" +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c3.finn +// #define NV01_MEMORY_SYNCPOINT 0x00C3 /* -* NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint -through NvRmAlloc. -*/ -typedef struct -{ - NvU32 syncpointId; + * NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint + * through NvRmAlloc. + */ +#define NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID (0x00c3U) + +typedef struct NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS { + NvU32 syncpointId; } NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS; -#endif // SDK_CL00C3_H diff --git a/src/common/sdk/nvidia/inc/class/cl00db.h b/src/common/sdk/nvidia/inc/class/cl00db.h index bc1a549f7..a076cd9af 100644 --- a/src/common/sdk/nvidia/inc/class/cl00db.h +++ b/src/common/sdk/nvidia/inc/class/cl00db.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,25 +21,23 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl00db_h_ -#define _cl00db_h_ -#ifdef __cplusplus -extern "C" { -#endif +#pragma once -#include "nvtypes.h" +#include -#define NV40_DEBUG_BUFFER (0x000000db) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00db.finn +// + +#define NV40_DEBUG_BUFFER (0x000000db) /* NvRmAlloc() parameters */ -typedef struct { +#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU) + +typedef struct NV00DB_ALLOCATION_PARAMETERS { NvU32 size; /* Desired message size / actual size returned */ NvU32 tag; /* Protobuf tag for message location in dump message */ } NV00DB_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl00db_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl00f3.h b/src/common/sdk/nvidia/inc/class/cl00f3.h index 1f5093777..1cb95c2f4 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f3.h +++ b/src/common/sdk/nvidia/inc/class/cl00f3.h @@ -21,7 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f3.finn +// + + /* * Class definition for creating a memory descriptor from a FLA range in RmAllocMemory. @@ -31,46 +40,36 @@ * other parameters are passed as Nv01MemoryFla structure. */ -#ifndef _cl00f3_h_ -#define _cl00f3_h_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define NV01_MEMORY_FLA (0x000000f3) +#define NV01_MEMORY_FLA (0x000000f3) /* * Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS * * */ -typedef struct { - NvU32 type; /* FBMEM: NVOS32_TYPE_* */ - NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ - NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ - NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ - NvU64 base; /* base of FLA range */ - NvU64 align; /* alignment for FLA range*/ - NvU64 limit NV_ALIGN_BYTES(8); +#define NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00f3U) + +typedef struct NV_FLA_MEMORY_ALLOCATION_PARAMS { + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NV_DECLARE_ALIGNED(NvU64 base, 8); /* base of FLA range */ + NV_DECLARE_ALIGNED(NvU64 align, 8); /* alignment for FLA range*/ + NV_DECLARE_ALIGNED(NvU64 limit, 8); // // For Direct connected systems, clients need to program this hSubDevice with // the exporting GPU, for RM to route the traffic to the destination GPU // Clients need not program this for NvSwitch connected systems // - NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */ + NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */ // // Instead of base and limit, clients can also pass the FLA handle (or hExportHandle) // being exported from destination side to import on the access side // - NvHandle hExportHandle; /* FLA handle being exported or Export handle */ + NvHandle hExportHandle; /* FLA handle being exported or Export handle */ // The RM client used to export memory - NvHandle hExportClient; - NvU32 flagsOs02; + NvHandle hExportClient; + NvU32 flagsOs02; } NV_FLA_MEMORY_ALLOCATION_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _cl00f3_h - diff --git a/src/common/sdk/nvidia/inc/class/cl00f8.h b/src/common/sdk/nvidia/inc/class/cl00f8.h index 662eafd9c..a3a6c4ce9 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f8.h +++ b/src/common/sdk/nvidia/inc/class/cl00f8.h @@ -19,22 +19,24 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. -*/ + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f8.finn +// + -#include "nvtypes.h" /* * Class definition for allocating a contiguous or discontiguous FLA. */ -#ifndef _cl00f8_h_ -#define _cl00f8_h_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define NV_MEMORY_FABRIC (0x000000f8) +#define NV_MEMORY_FABRIC (0x000000f8) /* * alignment [IN] @@ -86,16 +88,18 @@ extern "C" { * Clients should pass 0 as of now. */ -#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 -#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 -#define NV00F8_ALLOC_FLAGS_DEFAULT 0 +#define NV00F8_ALLOC_FLAGS_DEFAULT 0 #define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) #define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) #define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2) #define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3) -typedef struct { +#define NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f8U) + +typedef struct NV00F8_ALLOCATION_PARAMETERS { NV_DECLARE_ALIGNED(NvU64 alignment, 8); NV_DECLARE_ALIGNED(NvU64 allocSize, 8); @@ -109,10 +113,5 @@ typedef struct { NvHandle hVidMem; NvU32 flags; } map; - } NV00F8_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif /* _cl00f8_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl2080.h b/src/common/sdk/nvidia/inc/class/cl2080.h index b43209c12..68eaabfc0 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080.h +++ b/src/common/sdk/nvidia/inc/class/cl2080.h @@ -54,9 +54,9 @@ extern "C" { #define NV2080_NOTIFIERS_NVDEC2 (16) #define NV2080_NOTIFIERS_NVDEC3 (17) #define NV2080_NOTIFIERS_NVDEC4 (18) -#define NV2080_NOTIFIERS_RESERVED19 (19) -#define NV2080_NOTIFIERS_RESERVED20 (20) -#define NV2080_NOTIFIERS_RESERVED21 (21) +#define NV2080_NOTIFIERS_NVDEC5 (19) +#define NV2080_NOTIFIERS_NVDEC6 (20) +#define NV2080_NOTIFIERS_NVDEC7 (21) #define NV2080_NOTIFIERS_PDEC (22) // also known as VP #define NV2080_NOTIFIERS_CE0 (23) #define NV2080_NOTIFIERS_CE1 (24) @@ -158,19 +158,19 @@ extern "C" { #define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) #define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) #define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) -#define NV2080_NOTIFIERS_RESERVED_122 (122) +#define NV2080_NOTIFIERS_RESERVED122 (122) #define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) #define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) #define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) #define NV2080_NOTIFIERS_NVJPG (126) #define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG -#define NV2080_NOTIFIERS_RESERVED127 (127) -#define NV2080_NOTIFIERS_RESERVED128 (128) -#define NV2080_NOTIFIERS_RESERVED129 (129) -#define NV2080_NOTIFIERS_RESERVED130 (130) -#define NV2080_NOTIFIERS_RESERVED131 (131) -#define NV2080_NOTIFIERS_RESERVED132 (132) -#define NV2080_NOTIFIERS_RESERVED133 (133) +#define NV2080_NOTIFIERS_NVJPEG1 (127) +#define NV2080_NOTIFIERS_NVJPEG2 (128) +#define NV2080_NOTIFIERS_NVJPEG3 (129) +#define NV2080_NOTIFIERS_NVJPEG4 (130) +#define NV2080_NOTIFIERS_NVJPEG5 (131) +#define NV2080_NOTIFIERS_NVJPEG6 (132) +#define NV2080_NOTIFIERS_NVJPEG7 (133) #define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) #define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) #define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) @@ -216,12 +216,10 @@ extern "C" { #define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) // Indexed NVDEC notifier reference #define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) - -#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC4)) - +#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) // Indexed NVJPEG notifier reference #define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) -#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG0)) +#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) #define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin)) #define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin)) @@ -259,9 +257,9 @@ extern "C" { #define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) #define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) #define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) -#define NV2080_ENGINE_TYPE_RESERVED18 (0x00000018) -#define NV2080_ENGINE_TYPE_RESERVED19 (0x00000019) -#define NV2080_ENGINE_TYPE_RESERVED1A (0x0000001a) +#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) +#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) +#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) #define NV2080_ENGINE_TYPE_MSENC (0x0000001b) #define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ #define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) @@ -282,24 +280,21 @@ extern "C" { #define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) #define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) #define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG -#define NV2080_ENGINE_TYPE_RESERVED2C (0x0000002c) -#define NV2080_ENGINE_TYPE_RESERVED2D (0x0000002d) -#define NV2080_ENGINE_TYPE_RESERVED2E (0x0000002e) -#define NV2080_ENGINE_TYPE_RESERVED2F (0x0000002f) -#define NV2080_ENGINE_TYPE_RESERVED30 (0x00000030) -#define NV2080_ENGINE_TYPE_RESERVED31 (0x00000031) -#define NV2080_ENGINE_TYPE_RESERVED32 (0x00000032) +#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) +#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) +#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) +#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) +#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) +#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) +#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) #define NV2080_ENGINE_TYPE_OFA (0x00000033) #define NV2080_ENGINE_TYPE_LAST (0x00000034) #define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) #define NV2080_ENGINE_TYPE_COPY_SIZE 10 #define NV2080_ENGINE_TYPE_NVENC_SIZE 3 - -#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 1 - -#define NV2080_ENGINE_TYPE_NVDEC_SIZE 5 - +#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 +#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 #define NV2080_ENGINE_TYPE_GR_SIZE 8 // Indexed engines diff --git a/src/common/sdk/nvidia/inc/class/cl30f1.h b/src/common/sdk/nvidia/inc/class/cl30f1.h index 3ce657bfb..2a8e3c97f 100644 --- a/src/common/sdk/nvidia/inc/class/cl30f1.h +++ b/src/common/sdk/nvidia/inc/class/cl30f1.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,77 +21,36 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl30f1_h_ -#define _cl30f1_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl30f1.finn +// -/* class NV30_GSYNC */ -#define NV30_GSYNC (0x000030F1) - -/* - * A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as - * notify index when allocating event, if separate event notifications are needed for - * separate event types. - * - * A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and - * NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required. - * In this case RM would set event data equal to a pointer to NvNotification structure. - * The info32 field of NvNotification structure would be equal a bitmask of - * NV30F1_GSYNC_NOTIFIERS_* values. - */ - -/* NvNotification[] fields and values */ - -/* Framelock sync gain and loss events. These are connector specific events. */ -#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c)) -#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c)) - -/* Framelock stereo gain and loss events. These are connector specific events. */ -#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c)) -#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c)) - -/* House cable gain(plug in) and loss(plug out) events. */ -#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10) -#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11) - -/* RJ45 cable gain(plug in) and loss(plug out) events. */ -#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12) -#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13) +#include "cl30f1_notification.h" -#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14) - -/* - * For handling all event types. - * Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only - * signal an event but not handle over any information. - */ -#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT +/* class NV30_GSYNC */ +#define NV30_GSYNC (0x000030F1) +#define NV30F1_GSYNC_CONNECTOR_ONE (0) +#define NV30F1_GSYNC_CONNECTOR_TWO (1) +#define NV30F1_GSYNC_CONNECTOR_THREE (2) +#define NV30F1_GSYNC_CONNECTOR_FOUR (3) -#define NV30F1_GSYNC_CONNECTOR_ONE (0) -#define NV30F1_GSYNC_CONNECTOR_TWO (1) -#define NV30F1_GSYNC_CONNECTOR_THREE (2) -#define NV30F1_GSYNC_CONNECTOR_FOUR (3) +#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE +#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO -#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE -#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO +#define NV30F1_GSYNC_CONNECTOR_COUNT (4) -#define NV30F1_GSYNC_CONNECTOR_COUNT (4) +/* NvRmAlloc parameters */ +#define NV30F1_MAX_GSYNCS (0x0000004) +#define NV30F1_ALLOC_PARAMETERS_MESSAGE_ID (0x30f1U) -/* NvRmAlloc parameters */ -#define NV30F1_MAX_GSYNCS (0x0000004) -typedef struct { - NvU32 gsyncInstance; +typedef struct NV30F1_ALLOC_PARAMETERS { + NvU32 gsyncInstance; } NV30F1_ALLOC_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl30f1_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl30f1_notification.h b/src/common/sdk/nvidia/inc/class/cl30f1_notification.h new file mode 100644 index 000000000..290eb5c11 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl30f1_notification.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl30f1_notification_h_ +#define _cl30f1_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as + * notify index when allocating event, if separate event notifications are needed for + * separate event types. + * + * A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and + * NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required. + * In this case RM would set event data equal to a pointer to NvNotification structure. + * The info32 field of NvNotification structure would be equal a bitmask of + * NV30F1_GSYNC_NOTIFIERS_* values. + */ + +/* NvNotification[] fields and values */ + +/* Framelock sync gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c)) +#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c)) + +/* Framelock stereo gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c)) +#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c)) + +/* House cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10) +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11) + +/* RJ45 cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12) +#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13) + +#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14) + +/* + * For handling all event types. + * Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only + * signal an event but not handle over any information. + */ +#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl30f1_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl503b.h b/src/common/sdk/nvidia/inc/class/cl503b.h index d0b5850b1..5f63be473 100644 --- a/src/common/sdk/nvidia/inc/class/cl503b.h +++ b/src/common/sdk/nvidia/inc/class/cl503b.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,23 +21,26 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl503b_h_ -#define _cl503b_h_ -#ifdef __cplusplus -extern "C" { -#endif +#pragma once -#include "nvtypes.h" +#include -#define NV50_P2P (0x0000503b) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503b.finn +// + +#define NV50_P2P (0x0000503b) #define NV503B_FLAGS_P2P_TYPE 0:0 -#define NV503B_FLAGS_P2P_TYPE_GPA 0 -#define NV503B_FLAGS_P2P_TYPE_SPA 1 +#define NV503B_FLAGS_P2P_TYPE_GPA 0 +#define NV503B_FLAGS_P2P_TYPE_SPA 1 /* NvRmAlloc parameters */ -typedef struct { +#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) + +typedef struct NV503B_ALLOC_PARAMETERS { NvHandle hSubDevice; /* subDevice handle of local GPU */ NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */ NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice @@ -46,15 +49,9 @@ typedef struct { NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice * A value of 0 defaults to RM selected * PeerIdMasks must match in loopback */ - NvU64 mailboxBar1Addr; /* P2P Mailbox area base offset in BAR1 + NV_DECLARE_ALIGNED(NvU64 mailboxBar1Addr, 8); /* P2P Mailbox area base offset in BAR1 * Must have the same value across the GPUs */ NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area * Must have the same value across the GPUs */ NvU32 flags; /* Flag to indicate types/attib of p2p */ } NV503B_ALLOC_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl503b_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl503c.h b/src/common/sdk/nvidia/inc/class/cl503c.h index 99c334f1d..9b9bd3e19 100644 --- a/src/common/sdk/nvidia/inc/class/cl503c.h +++ b/src/common/sdk/nvidia/inc/class/cl503c.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,29 +21,27 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl503c_h_ -#define _cl503c_h_ -#ifdef __cplusplus -extern "C" { -#endif +#pragma once -#include "nvtypes.h" +#include -#define NV50_THIRD_PARTY_P2P (0x0000503c) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503c.finn +// + +#define NV50_THIRD_PARTY_P2P (0x0000503c) /* NvRmAlloc parameters */ -typedef struct { +#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU) + +typedef struct NV503C_ALLOC_PARAMETERS { NvU32 flags; } NV503C_ALLOC_PARAMETERS; #define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0 -#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000) -#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001) -#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002) - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002) -#endif /* _cl503c_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl5070.h b/src/common/sdk/nvidia/inc/class/cl5070.h index 0c7fca6dc..d8a7f2d25 100644 --- a/src/common/sdk/nvidia/inc/class/cl5070.h +++ b/src/common/sdk/nvidia/inc/class/cl5070.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,37 +20,24 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl5070_h_ -#define _cl5070_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5070.finn +// -#define NV50_DISPLAY (0x00005070) +#include "cl5070_notification.h" -/* event values */ -#define NV5070_NOTIFIERS_SW (0) -#define NV5070_NOTIFIERS_MAXCOUNT (1) +#define NV50_DISPLAY (0x00005070) -#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) -#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) -#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) -#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) -#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display +typedef struct NV5070_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display } NV5070_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl5070_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl5070_notification.h b/src/common/sdk/nvidia/inc/class/cl5070_notification.h new file mode 100644 index 000000000..fd0628aa1 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl5070_notification.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl5070_notification_h_ +#define _cl5070_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV5070_NOTIFIERS_SW (0) +#define NV5070_NOTIFIERS_MAXCOUNT (1) + +#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5070_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl5080.h b/src/common/sdk/nvidia/inc/class/cl5080.h index 686956745..c9c8caaa1 100644 --- a/src/common/sdk/nvidia/inc/class/cl5080.h +++ b/src/common/sdk/nvidia/inc/class/cl5080.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -20,34 +20,27 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl5080_h_ -#define _cl5080_h_ -#ifdef __cplusplus -extern "C" { -#endif +#pragma once -#include "nvtypes.h" +#include -#define NV50_DEFERRED_API_CLASS (0x00005080) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5080.finn +// + +#include "cl5080_notification.h" + +#define NV50_DEFERRED_API_CLASS (0x00005080) /* NvRmAlloc parameters */ -typedef struct { +#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U) + +typedef struct NV5080_ALLOC_PARAMS { // Should the deferred api completion trigger an event NvBool notifyCompletion; } NV5080_ALLOC_PARAMS; -/* dma method offsets, fields, and values */ -#define NV5080_SET_OBJECT (0x00000000) -#define NV5080_NO_OPERATION (0x00000100) -#define NV5080_DEFERRED_API (0x00000200) -#define NV5080_DEFERRED_API_HANDLE 31:0 - // Class-specific allocation capabilities -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl5080_h_ */ - diff --git a/src/common/sdk/nvidia/inc/class/cl5080_notification.h b/src/common/sdk/nvidia/inc/class/cl5080_notification.h new file mode 100644 index 000000000..170c8fb6c --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl5080_notification.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl5080_notification_h_ +#define _cl5080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* dma method offsets, fields, and values */ +#define NV5080_SET_OBJECT (0x00000000) +#define NV5080_NO_OPERATION (0x00000100) +#define NV5080_DEFERRED_API (0x00000200) +#define NV5080_DEFERRED_API_HANDLE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5080_notification_h_ */ + diff --git a/src/common/sdk/nvidia/inc/class/cl83de.h b/src/common/sdk/nvidia/inc/class/cl83de.h index 2968227e7..62c507c0d 100644 --- a/src/common/sdk/nvidia/inc/class/cl83de.h +++ b/src/common/sdk/nvidia/inc/class/cl83de.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,17 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ +#pragma once -#ifndef _cl83de_h_ -#define _cl83de_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl83de.finn +// -#include "nvtypes.h" - -#define GT200_DEBUGGER (0x000083de) +#define GT200_DEBUGGER (0x000083de) /* * Creating the GT200_DEBUGGER object: @@ -47,15 +46,10 @@ extern "C" { * NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, ¶ms); */ -typedef struct { - NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero) - NvHandle hAppClient; - NvHandle hClass3dObject; -} NV83DE_ALLOC_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl83de_h_ */ +#define NV83DE_ALLOC_PARAMETERS_MESSAGE_ID (0x83deU) +typedef struct NV83DE_ALLOC_PARAMETERS { + NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero) + NvHandle hAppClient; + NvHandle hClass3dObject; +} NV83DE_ALLOC_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl85b5sw.h b/src/common/sdk/nvidia/inc/class/cl85b5sw.h index 37ce6516b..63e1160c0 100644 --- a/src/common/sdk/nvidia/inc/class/cl85b5sw.h +++ b/src/common/sdk/nvidia/inc/class/cl85b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,25 +21,18 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _cl85b5sw_h_ -#define _cl85b5sw_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl85b5sw.finn +// -/* This file is *not* auto-generated. */ +#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) -typedef struct -{ - NvU32 version; // set to 0 - NvU32 engineInstance; // CE instance +typedef struct NV85B5_ALLOCATION_PARAMETERS { + NvU32 version; // set to 0 + NvU32 engineInstance; // CE instance } NV85B5_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _cl85b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/cl9072.h b/src/common/sdk/nvidia/inc/class/cl9072.h index 020adecd7..fe3d91b86 100644 --- a/src/common/sdk/nvidia/inc/class/cl9072.h +++ b/src/common/sdk/nvidia/inc/class/cl9072.h @@ -21,33 +21,26 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9072_h_ -#define _cl9072_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9072.finn +// -#define GF100_DISP_SW 0x00009072 +#include "cl9072_notification.h" -#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9) -#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +#define GF100_DISP_SW 0x00009072 +#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U) -typedef struct -{ - NvU32 logicalHeadId; +typedef struct NV9072_ALLOCATION_PARAMETERS { + NvU32 logicalHeadId; /* * 0 implies use Head argument only (i.e. whatever is currently setup on this head) */ - NvU32 displayMask; - NvU32 caps; + NvU32 displayMask; + NvU32 caps; } NV9072_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl9072_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl9072_notification.h b/src/common/sdk/nvidia/inc/class/cl9072_notification.h new file mode 100644 index 000000000..21b48f8be --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl9072_notification.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl9072_notification_h_ +#define _cl9072_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9) +#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9072_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl9170.h b/src/common/sdk/nvidia/inc/class/cl9170.h index 082ea5bcf..9f774a611 100644 --- a/src/common/sdk/nvidia/inc/class/cl9170.h +++ b/src/common/sdk/nvidia/inc/class/cl9170.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2004, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9170_h_ -#define _cl9170_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9170.finn +// -#define NV9170_DISPLAY (0x00009170) +#define NV9170_DISPLAY (0x00009170) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9170_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U) -#endif /* _cl9170_h_ */ +typedef struct NV9170_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9170_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl9270.h b/src/common/sdk/nvidia/inc/class/cl9270.h index e2ffbf712..c6ce40b30 100644 --- a/src/common/sdk/nvidia/inc/class/cl9270.h +++ b/src/common/sdk/nvidia/inc/class/cl9270.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2010, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9270_h_ -#define _cl9270_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9270.finn +// -#define NV9270_DISPLAY (0x00009270) +#define NV9270_DISPLAY (0x00009270) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9270_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U) -#endif /* _cl9270_h_ */ +typedef struct NV9270_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9270_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl9470.h b/src/common/sdk/nvidia/inc/class/cl9470.h index bedd82dd6..f7b1519ea 100644 --- a/src/common/sdk/nvidia/inc/class/cl9470.h +++ b/src/common/sdk/nvidia/inc/class/cl9470.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9470_h_ -#define _cl9470_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9470.finn +// -#define NV9470_DISPLAY (0x00009470) +#define NV9470_DISPLAY (0x00009470) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9470_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U) -#endif /* _cl9470_h_ */ +typedef struct NV9470_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9470_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl9570.h b/src/common/sdk/nvidia/inc/class/cl9570.h index ab5e6ccd0..8f8876383 100644 --- a/src/common/sdk/nvidia/inc/class/cl9570.h +++ b/src/common/sdk/nvidia/inc/class/cl9570.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9570_h_ -#define _cl9570_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9570.finn +// -#define NV9570_DISPLAY (0x00009570) +#define NV9570_DISPLAY (0x00009570) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9570_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U) -#endif /* _cl9570_h_ */ +typedef struct NV9570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9570_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl9770.h b/src/common/sdk/nvidia/inc/class/cl9770.h index 28ab00d0b..87dccee58 100644 --- a/src/common/sdk/nvidia/inc/class/cl9770.h +++ b/src/common/sdk/nvidia/inc/class/cl9770.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9770_h_ -#define _cl9770_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9770.finn +// -#define NV9770_DISPLAY (0x00009770) +#define NV9770_DISPLAY (0x00009770) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9770_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U) -#endif /* _cl9770_h_ */ +typedef struct NV9770_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9770_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl9870.h b/src/common/sdk/nvidia/inc/class/cl9870.h index bcfc9900e..2307a6b3b 100644 --- a/src/common/sdk/nvidia/inc/class/cl9870.h +++ b/src/common/sdk/nvidia/inc/class/cl9870.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,27 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl9870_h_ -#define _cl9870_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9870.finn +// -#define NV9870_DISPLAY (0x00009870) +#define NV9870_DISPLAY (0x00009870) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numDacs; // Number of DACs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display -} NV9870_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U) -#endif /* _cl9870_h_ */ +typedef struct NV9870_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9870_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cla06fsw.h b/src/common/sdk/nvidia/inc/class/cla06fsw.h index 2194da927..99c3b8a7a 100644 --- a/src/common/sdk/nvidia/inc/class/cla06fsw.h +++ b/src/common/sdk/nvidia/inc/class/cla06fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/cla16fsw.h b/src/common/sdk/nvidia/inc/class/cla16fsw.h index f76ac352d..cea256f00 100644 --- a/src/common/sdk/nvidia/inc/class/cla16fsw.h +++ b/src/common/sdk/nvidia/inc/class/cla16fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clb06fsw.h b/src/common/sdk/nvidia/inc/class/clb06fsw.h index 9a9a39150..3e1c74ba9 100644 --- a/src/common/sdk/nvidia/inc/class/clb06fsw.h +++ b/src/common/sdk/nvidia/inc/class/clb06fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clb8b0.h b/src/common/sdk/nvidia/inc/class/clb8b0.h new file mode 100644 index 000000000..b2d0e0928 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clb8b0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8b0_h__ +#define __gh100_clb8b0_h__ +#define NVB8B0_VIDEO_DECODER (0x0000B8B0) +#endif // __gh100_clb8b0_h__ diff --git a/src/common/sdk/nvidia/inc/class/clb8d1.h b/src/common/sdk/nvidia/inc/class/clb8d1.h new file mode 100644 index 000000000..e6c8e4c35 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clb8d1.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8d1_h__ +#define __gh100_clb8d1_h__ +#define NVB8D1_VIDEO_NVJPG (0x0000B8D1) +#endif // __gh100_clb8d1_h__ diff --git a/src/common/sdk/nvidia/inc/class/clb8fa.h b/src/common/sdk/nvidia/inc/class/clb8fa.h new file mode 100644 index 000000000..19edb2327 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clb8fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb8fa_h_ +#define _clb8fa_h_ + +#define NVB8FA_VIDEO_OFA (0x0000B8FA) + +#endif /* _clb8fa_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc06fsw.h b/src/common/sdk/nvidia/inc/class/clc06fsw.h index 8dc2c0755..4e000c6d3 100644 --- a/src/common/sdk/nvidia/inc/class/clc06fsw.h +++ b/src/common/sdk/nvidia/inc/class/clc06fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clc36fsw.h b/src/common/sdk/nvidia/inc/class/clc36fsw.h index e05b2d997..b54c50592 100644 --- a/src/common/sdk/nvidia/inc/class/clc36fsw.h +++ b/src/common/sdk/nvidia/inc/class/clc36fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clc46fsw.h b/src/common/sdk/nvidia/inc/class/clc46fsw.h index 4137f0f74..7438195cf 100644 --- a/src/common/sdk/nvidia/inc/class/clc46fsw.h +++ b/src/common/sdk/nvidia/inc/class/clc46fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clc56fsw.h b/src/common/sdk/nvidia/inc/class/clc56fsw.h index 38ef41244..13496be17 100644 --- a/src/common/sdk/nvidia/inc/class/clc56fsw.h +++ b/src/common/sdk/nvidia/inc/class/clc56fsw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/class/clc661.h b/src/common/sdk/nvidia/inc/class/clc661.h new file mode 100644 index 000000000..d9f8a484a --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc661.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc661_h__ +#define __gh100_clc661_h__ +#define HOPPER_USERMODE_A (0xc661) +#endif // __gh100_clc661_h__ diff --git a/src/common/sdk/nvidia/inc/class/clc770.h b/src/common/sdk/nvidia/inc/class/clc770.h index 53851df53..940d7762c 100644 --- a/src/common/sdk/nvidia/inc/class/clc770.h +++ b/src/common/sdk/nvidia/inc/class/clc770.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,13 +31,6 @@ extern "C" { #define NVC770_DISPLAY (0x0000C770) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numDsis; // Number of DSIs in this chip/display -} NVC770_ALLOCATION_PARAMETERS; - #ifdef __cplusplus }; /* extern "C" */ #endif diff --git a/src/common/sdk/nvidia/inc/class/clc771.h b/src/common/sdk/nvidia/inc/class/clc771.h new file mode 100644 index 000000000..b2b19769f --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc771.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _clc771_h_ +#define _clc771_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC771_DISP_SF_USER (0x000C771) + +typedef volatile struct _clc771_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvC771DispSfUser, NvC771DispSfUserMap; + +#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ + +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(i,j) (0x000E0208-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(i,j) (0x000E020C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(i,j) (0x000E0210-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(i,j) (0x000E0214-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(i,j) (0x000E0218-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(i,j) (0x000E021C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(i,j) (0x000E0220-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(i,j) (0x000E0224-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc773.h b/src/common/sdk/nvidia/inc/class/clc773.h new file mode 100644 index 000000000..db5505a0c --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc773.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc773_h_ +#define _clc773_h_ + +#define NVC773_DISP_CAPABILITIES 0xC773 + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc77d.h b/src/common/sdk/nvidia/inc/class/clc77d.h new file mode 100644 index 000000000..f46235a26 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc77d.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc77d_h_ +#define _clc77d_h_ + +#define NVC77D_CORE_CHANNEL_DMA (0x0000C77D) + +#define NVC77D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC77D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc86f.h b/src/common/sdk/nvidia/inc/class/clc86f.h new file mode 100644 index 000000000..712466c2b --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc86f.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc86f_h__ +#define __gh100_clc86f_h__ + +typedef volatile struct Nvc86fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc86fControl, HopperAControlGPFifo; + +#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F) +#define NVC86F_SET_OBJECT (0x00000000) +#define NVC86F_SEM_ADDR_LO (0x0000005c) +#define NVC86F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC86F_SEM_ADDR_HI (0x00000060) +#define NVC86F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC86F_SEM_PAYLOAD_LO (0x00000064) +#define NVC86F_SEM_PAYLOAD_HI (0x00000068) +#define NVC86F_SEM_EXECUTE (0x0000006c) +#define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#endif // __gh100_clc86f_h__ diff --git a/src/common/sdk/nvidia/inc/class/clc86fsw.h b/src/common/sdk/nvidia/inc/class/clc86fsw.h new file mode 100644 index 000000000..dce4dfd56 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc86fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc86f_sw_h_ +#define _clc86f_sw_h_ + +#define NVC86F_NOTIFIERS_RC (0) +#define NVC86F_NOTIFIERS_REFCNT (1) +#define NVC86F_NOTIFIERS_NONSTALL (2) +#define NVC86F_NOTIFIERS_EVENTBUFFER (3) +#define NVC86F_NOTIFIERS_IDLECHANNEL (4) +#define NVC86F_NOTIFIERS_ENDCTX (5) +#define NVC86F_NOTIFIERS_SW (6) +#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC86F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC86F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc8b5.h b/src/common/sdk/nvidia/inc/class/clc8b5.h new file mode 100644 index 000000000..38fd8be9a --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc8b5.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc8b5_h__ +#define __gh100_clc8b5_h__ +#define HOPPER_DMA_COPY_A (0x0000C8B5) +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#endif // __gh100_clc8b5_h__ diff --git a/src/common/sdk/nvidia/inc/class/clc997.h b/src/common/sdk/nvidia/inc/class/clc997.h new file mode 100644 index 000000000..8aa2487a4 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc997.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc997_h_ +#define _clc997_h_ + +#define ADA_A 0xC997 + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc9b0.h b/src/common/sdk/nvidia/inc/class/clc9b0.h new file mode 100644 index 000000000..604fe53b9 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc9b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b0_h_ +#define _clc9b0_h_ + +#define NVC9B0_VIDEO_DECODER (0x0000C9B0) + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc9b7.h b/src/common/sdk/nvidia/inc/class/clc9b7.h new file mode 100644 index 000000000..6a0caef9f --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc9b7.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b7_h_ +#define _clc9b7_h_ + +#define NVC9B7_VIDEO_ENCODER (0x0000C9B7) + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc9c0.h b/src/common/sdk/nvidia/inc/class/clc9c0.h new file mode 100644 index 000000000..35da97fce --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc9c0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9c0_h_ +#define _clc9c0_h_ + +#define ADA_COMPUTE_A 0xC9C0 + +#endif diff --git a/src/common/sdk/nvidia/inc/class/clc9d1.h b/src/common/sdk/nvidia/inc/class/clc9d1.h new file mode 100644 index 000000000..6849f96ee --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc9d1.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9d1_h_ +#define _clc9d1_h_ + +#define NVC9D1_VIDEO_NVJPG (0x0000C9D1) + +#endif // _clc9d1_h diff --git a/src/common/sdk/nvidia/inc/class/clc9fa.h b/src/common/sdk/nvidia/inc/class/clc9fa.h new file mode 100644 index 000000000..6b4a20acc --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc9fa.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9fa_h_ +#define _clc9fa_h_ + +#define NVC9FA_VIDEO_OFA (0x0000C9FA) + +#endif // _clc9fa_h + diff --git a/src/common/sdk/nvidia/inc/class/clcb97.h b/src/common/sdk/nvidia/inc/class/clcb97.h new file mode 100644 index 000000000..44bd064ff --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clcb97.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clcb97_h__ +#define __gh100_clcb97_h__ +#define HOPPER_A 0xCB97 +#endif // __gh100_clcb97_h__ diff --git a/src/common/sdk/nvidia/inc/class/clcbc0.h b/src/common/sdk/nvidia/inc/class/clcbc0.h new file mode 100644 index 000000000..bed5e9456 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clcbc0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clcbc0_h__ +#define __gh100_clcbc0_h__ +#define HOPPER_COMPUTE_A 0xCBC0 +#endif // __gh100_clcbc0_h__ diff --git a/src/common/sdk/nvidia/inc/class/clcbca.h b/src/common/sdk/nvidia/inc/class/clcbca.h new file mode 100644 index 000000000..4570cc9e9 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clcbca.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CLCBCA_H_ +#define _CLCBCA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV_COUNTER_COLLECTION_UNIT (0x0000CBCA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _CLCBCA_H_ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h index f88db2e66..00de834ef 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl0000/ctrl0000base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV01_ROOT (client) control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h index 1bca5a183..1c1d7903c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000client.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h index 5fb7008fe..9b72f207b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000diag.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h index 906df53c4..1679f841d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0000/ctrl0000event.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index f67696af7..76e5bf5a6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0000/ctrl0000gpu.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h index 07f1cbcf5..6f8ff132b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h index e4597f3a5..2df6c426b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000gsync.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h index 359b6e830..41a4954f3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0000/ctrl0000nvd.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h index a97d28db7..9a48202ff 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0000/ctrl0000proc.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h index 1ccecbdd1..b8e921e4a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 4391ae46d..0c8cc540d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl0000/ctrl0000system.finn // - - - #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl0000/ctrl0000base.h" @@ -223,6 +220,27 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { NvU32 coresOnDie; /* cpu cores per die */ } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; +// Macros for CPU family information +#define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 + +// Macros for CPU model information +#define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 + +// Macros for AMD CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 + +// Macros for Intel CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 + /* processor type values */ #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000) /* Intel types */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h index 33696f640..3402552a2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0000/ctrl0000unix.finn // - - - #include "ctrl/ctrl0000/ctrl0000base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h index fcec6291f..046c93194 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0002.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h index 39b59d5ee..91431cee5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0004.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV01_TIMER control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h index afc8fd89e..ecabf3350 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl000f.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h index 484042ecf..60f668464 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0020.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV0020_CTRL_CMD(cat,idx) \ NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx) @@ -72,8 +69,6 @@ * NV_OK * NV_ERR_INVALID_ARGUMENT */ - - #define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */ #define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h b/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h index 59d29f4a4..880fcc8ca 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl003e.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV01_MEMORY_SYSTEM control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h index 7f87a6e1d..6ff491b89 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h @@ -31,9 +31,6 @@ // #include "nvos.h" - - - #include "ctrl/ctrlxxxx.h" /* NV04_MEMORY control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h index d860f9c8b..970ea3b97 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl0073/ctrl0073base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV04_DISPLAY_COMMON control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index 675aff0de..b3b3eb207 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0073/ctrl0073dfp.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -1095,11 +1092,53 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { * vActive * This parameter specifies the vertical lines of the active pixel * data in the raster. +* hFrontPorch +* This parameter specifies the number of horizontal front porch +* blanking pixels in the raster. +* vFrontPorch +* This parameter specifies the numer of lines of the vertical front +* porch in the raster. +* hBackPorch +* This parameter specifies the number of horizontal back porch +* blanking pixels in the raster. +* vBackPorch +* This parameter specifies the numer of lines of the vertical back +* porch in the raster. +* hSyncWidth +* This parameter specifies the number of horizontal sync pixels in +* the raster. +* vSyncWidth +* This parameter specifies the numer of lines of the vertical sync +* in the raster. * bpp * This parameter specifies the depth (Bits per Pixel) of the output * display stream. * refresh * This parameter specifies the refresh rate of the panel (in Hz). +* pclkHz +* This parameter specifies the pixel clock rate in Hz. +* numLanes +* Number of DSI data lanes. +* dscEnable +* Flag to indicate if DSC an be enabled, which in turn indicates if +* panel supports DSC. +* dscBpp +* DSC Bits per pixel +* dscNumSlices +* Number of slices for DSC. +* dscDuaDsc +* Flag to indicate if panel supports DSC streams from two DSI +* controllers. +* dscSliceHeight +* Height of DSC slices. +* dscBlockPrediction +* Flag to indicate if DSC Block Prediction needs to be enabled. +* dscDecoderVersionMajor +* Major version number of DSC decoder on Panel. +* dscDecoderVersionMinor +* Minor version number of DSC decoder on Panel. +* dscEncoderCaps +* Capabilities of DSC encoder in SoC. * * Possible status values returned are: * NV_OK @@ -1116,10 +1155,107 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { NvU32 displayId; NvU32 hActive; NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; NvU32 bpp; NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + + struct { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; + } dscEncoderCaps; } NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; +/* + * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING + * + * This control call is used to retrieve the display mode timing info that's + * specified for a given DFP from an offline configuration blob (e.g., Device Tree). + * This display timing info is intended to replace the timings exposed in a + * sink's EDID. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the timings should be retrieved. + * stream (in) + * For MST connectors with static topologies (e.g., DP serializers), + * this parameter further identifies the video stream for which the + * timings should be retrieved. + * valid (out) + * Indicates whether a valid display timing was found for this DFP. + * hActive (out) + * Horizontal active width in pixels + * hFrontPorch (out) + * Horizontal front porch + * hSyncWidth (out) + * Horizontal sync width + * hBackPorch (out) + * Horizontal back porch + * vActive (out) + * Vertical active height in lines + * vFrontPorch (out) + * Vertical front porch + * vSyncWidth (out) + * Vertical sync width + * vBackPorch (out) + * Vertical back porch + * pclkKHz (out) + * Pixel clock frequency in KHz + * rrx1k (out) + * Refresh rate in units of 0.001Hz + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ + +#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 stream; + + NvBool valid; + + NvU16 hActive; + NvU16 hFrontPorch; + NvU16 hSyncWidth; + NvU16 hBackPorch; + + NvU16 vActive; + NvU16 vFrontPorch; + NvU16 vSyncWidth; + NvU16 vBackPorch; + + NvU32 pclkKHz; + NvU32 rrx1k; +} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; + /* _ctrl0073dfp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index 2236abd59..57a7ca3e3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0073/ctrl0073dp.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -1839,40 +1836,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) -/* - * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES - * - * This command returns the following info - * - * subDeviceInstance - * This parameter specifies the subdevice instance within the - * NV04_DISPLAY_COMMON parent device to which the operation should be - * directed. This parameter must specify a value between zero and the - * total number of subdevices within the parent device. This parameter - * should be set to zero for default behavior. - * displayId - * should be for DP only - * bEnableMSA - * To enable or disable MSA - * bStereoPhaseInverse - * To enable or disable Stereo Phase Inverse value - * bCacheMsaOverrideForNextModeset - * Cache the values and don't apply them until next modeset - * featureMask - * Enable/Disable mask of individual MSA property - * featureValues - * MSA property value to write - * pFeatureDebugValues - * It will actual MSA property value being written on HW. - * If its NULL then no error but return nothing - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - * NV_ERR_NOT_SUPPORTED - * NV_ERR_TIMEOUT - * - */ #define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U) @@ -2730,8 +2693,6 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { NvBool bOdStatus; } NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS; -/* _ctrl0073dp_h_ */ - /* valid commands */ #define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000 #define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001 @@ -2742,3 +2703,57 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { #define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000 #define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002 #define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003 + +/* + * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * bCacheMsaOverrideForNextModeset + * Cache the values and don't apply them until next modeset + * featureMask + * Enable/Disable mask of individual MSA property + * featureValues + * MSA property value to write + * bDebugValues + * To inform whether actual MSA values need to be returned + * pFeatureDebugValues + * It will actual MSA property value being written on HW. + * If its NULL then no error but return nothing + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NvBool bDebugValues; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; + +/* _ctrl0073dp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h index ce48ef905..2b4965d45 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl0073/ctrl0073internal.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" #include "ctrl/ctrl0073/ctrl0073system.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index c79409ab2..2163c3197 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0073/ctrl0073specific.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" #include "ctrl/ctrlxxxx.h" @@ -1790,4 +1787,55 @@ typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS { NvU32 infoframeIndex; } NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS; +/* + * NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE + * + * This command is used to do I2C R/W to slave on display i2c instance. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * i2cPort + * This parameter specifies the I2C CCB port ID. + * i2cSlaveAddress + * This parameter specifies the I2C slave address. + * readWriteFlag + * This parameter specifies whether its read/write operation. + * readWriteLen + * This parameter specifies the length of the read/write buffer + * readBuffer + * This parameter reads the data from slave address and copies to this + * buffer + * writeBuffer + * This parameter specifies this buffer data that would be written to + * slave address + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU) + +typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS { + NvU32 subDeviceInstance; + NvU32 i2cPort; + NvU32 i2cSlaveAddress; + NvU32 readWriteFlag; + NvU32 readWriteLen; + NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; + NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; +} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) + /* _ctrl0073specific_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h index b636475a4..9a585aa57 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0073/ctrl0073stereo.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index 987f2fcb2..5a54df7dc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0073/ctrl0073system.finn // - - - #include "ctrl/ctrl0073/ctrl0073base.h" /* NV04_DISPLAY_COMMON system-level control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h index f79b8f988..4b20dc12c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl0080/ctrl0080base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h index a1a80229b..05a18bf76 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080bif.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* @@ -117,5 +114,25 @@ typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS { #define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001 #define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000 +/* + * NV0080_CTRL_BIF_ASPM_CYA_UPDATE + * + * bL0sEnable + * bL1Enable + * ASPM CYA update by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { + NvBool bL0sEnable; + NvBool bL1Enable; +} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; + /* _ctrl0080bif_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h index c0164684c..d4911f55e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,8 +29,6 @@ // Source file: ctrl/ctrl0080/ctrl0080bsp.finn // - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h index c92b35798..cf2f90e3a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080dma.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h index 21c2a1002..7fcc696f7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080fb.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h index f7538255b..b7b13f8ca 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080fifo.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h index f49875a6d..58f2953e7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080gpu.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index c6f465a12..fe7c63a08 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080gr.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" typedef struct NV0080_CTRL_GR_ROUTE_INFO { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h index 99a138eaa..096c451bf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080host.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h index 6255ecfc0..8607cc2f5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -32,9 +32,6 @@ #include "nvlimits.h" #include "ctrl0080gr.h" - - - #include "ctrl/ctrl0080/ctrl0080base.h" #include "ctrl/ctrl0080/ctrl0080perf.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h index 9d46708dc..60af5a6f7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080msenc.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h index 30a461430..689fe4bcc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h index f5f16a3b5..30010767a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080perf.finn // - - #define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h index ccd000918..100a61262 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl0080/ctrl0080rc.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h index 297e55ab2..c48b4125b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080unix.finn // - - - #include "ctrl/ctrl0080/ctrl0080base.h" /* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index c62c1998e..ceb6caf87 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl00f8.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) @@ -67,15 +64,33 @@ * * allocFlags [OUT] * Flags passed during the allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). */ #define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ +/* + * addressSpace + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE. + * + * compressionCoverage + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + */ +typedef struct NV_PHYSICAL_MEMORY_ATTRS { + NvU32 addressSpace; + NvU32 compressionCoverage; +} NV_PHYSICAL_MEMORY_ATTRS; + #define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) typedef struct NV00F8_CTRL_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvU64 size, 8); - NvU32 pageSize; - NvU32 allocFlags; + NvU32 pageSize; + NvU32 allocFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; } NV00F8_CTRL_GET_INFO_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h index c7fc38e9a..f7b7e6a1f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h @@ -40,6 +40,8 @@ #include "ctrl2080/ctrl2080mc.h" #include "ctrl2080/ctrl2080fifo.h" #include "ctrl2080/ctrl2080fb.h" + + #include "ctrl2080/ctrl2080gr.h" #include "ctrl2080/ctrl2080bus.h" #include "ctrl2080/ctrl2080thermal.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h index 6578262af..7df6a6d84 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl2080/ctrl2080base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV20_SUBDEVICE_XX control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h index e70480be8..9cbad13db 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080bios.finn // - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX bios-related control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index 0cdd10536..307b66f1f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -30,9 +30,7 @@ // Source file: ctrl/ctrl2080/ctrl2080bus.finn // - - - +#include "nvcfg_sdk.h" #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX bus control commands and parameters */ @@ -1264,7 +1262,172 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS { NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES]; } NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS; +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS + * + * This command returns the PCIe requester atomics operation capabilities + * from GPU to coherent SYSMEM. + * + * atomicsCaps[OUT] + * Mask of supported PCIe atomic operations in the form of + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS { + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000) +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS + * + * This command returns the supported GPU atomic operations + * that map to the capable PCIe atomic operations from GPU to + * coherent SYSMEM. + * + * atomicOp[OUT] + * Array of structure that contains the atomic operation + * supported status and its attributes. The array can be + * indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_* + * + * bSupported[OUT] + * Is the GPU atomic operation natively supported by the PCIe? + * + * attributes[OUT] + * Provides the attributes mask of the GPU atomic operation when supported + * in the form of + * NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_* + * + */ +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12 + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { + struct { + NvBool bSupported; + NvU32 attributes; + } atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT]; +} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0 + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_INFO + * + * This command returns the C2C links information. + * + * bIsLinkUp[OUT] + * NV_TRUE if the C2C links are present and the links are up. + * The below remaining fields are valid only if return value is + * NV_OK and bIsLinkUp is NV_TRUE. + * nrLinks[OUT] + * Total number of C2C links that are up. + * linkMask[OUT] + * Bitmask of the C2C links present and up. + * perLinkBwMBps[OUT] + * Theoretical per link bandwidth in MBps. + * remoteType[OUT] + * Type of the device connected to the remote end of the C2C link. + * Valid values are : + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + * Please also review the information below for additional information on + * select fields: + * + * remoteType[OUT] + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + */ + + + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { + NvBool bIsLinkUp; + NvU32 nrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; + +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1 +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2 /* * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS @@ -1290,5 +1453,42 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { NvBool bDisable; } NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO + * + * This command returns the C2C error info for a C2C links. + * + * errCnts[OUT] + * Array of structure that contains the error counts for + * number of times one of C2C fatal error interrupt has happened. + * The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES + * * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE. + * + * nrCrcErrIntr[OUT] + * Number of times CRC error interrupt triggered. + * nrReplayErrIntr[OUT] + * Number of times REPLAY error interrupt triggered. + * nrReplayB2bErrIntr[OUT] + * Number of times REPLAY_B2B error interrupt triggered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2 +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5 + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU) +typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { + struct { + NvU32 nrCrcErrIntr; + NvU32 nrReplayErrIntr; + NvU32 nrReplayB2bErrIntr; + } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE]; +} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h index f36ab7e1f..179297e43 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -182,7 +182,7 @@ typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { #define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_MAX_PCES 18 +#define NV2080_CTRL_MAX_PCES 32 #define NV2080_CTRL_MAX_GRCES 2 #define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) @@ -199,10 +199,13 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { * This command updates the PCE-LCE mappings * * pPceLceMap [IN] - * This parameter tracks the array of PCE-LCE mappings. + * This parameter contains the array of PCE to LCE mappings. + * The array is indexed by the PCE index, and contains the + * LCE index that the PCE is assigned to. A unused PCE is + * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. * * pGrceConfig [IN] - * This parameter tracks the array of GRCE configs. + * This parameter contains the array of GRCE configs. * 0xF -> GRCE does not share with any LCE * 0-MAX_LCE -> GRCE shares with the given LCE * @@ -233,6 +236,8 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { NvBool bUpdateNvlinkPceLce; } NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS; +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf + #define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h index 4f1956af8..20b8f4f9a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h @@ -31,8 +31,6 @@ /* _ctrl2080clk_h_ */ - - #include "nvfixedtypes.h" #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080boardobj.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h index 97ae7dc18..570987bbf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h @@ -30,9 +30,6 @@ - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080boardobj.h" #include "ctrl/ctrl2080/ctrl2080volt.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h index eb5ecab51..1ad616fff 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080dma.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX dma control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h index 59c7f0c44..411a59d89 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080ecc.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h index c1a47c9cd..e71eb810b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080event.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "nv_vgpu_types.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index 3ca18bbc8..b25e3cd3f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080fb.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX fb control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h index 97666947b..b7dcf078b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080fifo.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h index c3031a29e..7040d33f4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080fla.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX FLA control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h index 1961ec35d..37810dcf1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080flcn.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" @@ -83,196 +80,26 @@ typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS { * @defgroup NVOS_INST_EVT Instrumentation event types. * @{ */ -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RECALIBRATE 0x00U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_TICK 0x01U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_YIELD 0x02U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_INT0 0x03U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_BLOCK 0x04U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNBLOCK 0x05U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_BEGIN 0x06U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_END 0x07U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_SEND 0x08U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_RECV 0x09U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_BEGIN 0x0AU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_END 0x0BU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_SKIPPED 0x0CU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_BEGIN 0x0DU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_END 0x0EU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_BEGIN 0x0FU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_END 0x10U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_BEGIN 0x11U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_END 0x12U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_BEGIN 0x13U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_END 0x14U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_BEGIN 0x15U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_END 0x16U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_BEGIN 0x17U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_END 0x18U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_BEGIN 0x19U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_END 0x1AU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_BEGIN 0x1BU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_END 0x1CU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_BEGIN 0x1DU -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_END 0x1EU +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_BEGIN 0x09U +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU + +//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU + +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU /*!@}*/ -#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU - -/*! - * Interrupts and exceptions both use the same event type. Set the first bit - * for exceptions to differentiate between the two. - */ -#define NV2080_CTRL_FLCN_NVOS_INST_IRQ_ID(_irqId) (_irqId) -#define NV2080_CTRL_FLCN_NVOS_INST_EXCI_ID(_exciId) (_exciId | (1 << 7)) - -/*! - * @defgroup NV_INSTRUMENTATION_EVENT_DATA Instrumentation event struct entry. - * - * This is a binary-packed representation of event type and additional data, - * including timing data and tracking IDs. - * - * @{ - */ - -/*! - * Below DRF needs constants assigned to start and end so it can be represented in FINN properly - * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet - */ -#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT (31) -#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE (27) -#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE \ - (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT) : \ - (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE) - -#define NV_INSTRUMENTATION_EVENT_DATA_TASK_ID 26:19 -#define NV_INSTRUMENTATION_EVENT_DATA_EXTRA 26:19 -#define NV_INSTRUMENTATION_EVENT_DATA_TIME_DELTA 18:0 -#define NV_INSTRUMENTATION_EVENT_DATA_TIME_ABS 26:0 -/*!@}*/ - -/*! - * The maximum number of event types, calculated from the number of bits in the - * event structure. - */ -#define NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES (0x20U) /* finn: Evaluated from "(1 << (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT - NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE + 1))" */ - -/*! - * The number of bytes required in the event mask to contain all event types. - */ -#define NV2080_CTRL_FLCN_NVOS_INST_MASK_SIZE_BYTES (0x4U) /* finn: Evaluated from "(NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES / 8)" */ - -/*! - * Instrumentation event bitfield structure. Exact structure depends on the - * first five bits, which represent event type. - * - * For most event types, the structure is: - * - 5 bits of event type - * - 8 bits of ID - * - 19 bits of delta time (time since last event). If we've missed some - * events, it's the amount of time since the last event that was not - * skipped. If this time would overflow, a recalibration event is inserted - * instead (see below). - * - * The main exception is the recalibration event, which has no ID/delta time - * fields and instead has a 27-bit absolute timestamp. This event is used - * when the gap between two events is greater than the maximum 20-bit integer. - * - * All timestamps are represented in increments of 32ns - * (the finest possible timer resolution). - */ -typedef struct NVOS_INSTRUMENTATION_EVENT { - /*! - * Field containing the event type and data. - * - * Bitmask of @ref NV_INSTRUMENTATION_EVENT_DATA. - */ - NvU32 data; -} NVOS_INSTRUMENTATION_EVENT; -typedef struct NVOS_INSTRUMENTATION_EVENT *PNVOS_INSTRUMENTATION_EVENT; - -/* - * NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP/UNMAP - * - * Params for both RmCtrls are the same (out for _MAP, in for _UNMAP) - */ -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP (0x20803112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x12" */ - -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_UNMAP (0x20803113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x13" */ - -typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS { - //! The engine type, from NV2080_ENGINE_TYPE_* - NvU32 engine; - - //! The beginning of the instrumentation buffer, mapped to user memory. - NV_DECLARE_ALIGNED(NvP64 begin, 8); - - // Priv pointer for memory mapping. - NV_DECLARE_ALIGNED(NvP64 pPriv, 8); - - // The size of the user-mapped instrumentation buffer. - NV_DECLARE_ALIGNED(NvU64 size, 8); -} NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS; - -/* - * NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO - * - * Get static information about FLCN instrumentation. - */ -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO (0x20803114) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID (0x14U) - -typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS { - //! The engine type, from NV2080_ENGINE_TYPE_* - NvU32 engine; - - //! Whether or not instrumentation is enabled - NvBool bEnabled; - - /*! - * Whether we use PTIMER (resolution 32ns) or the 30us timer tick (NV_TRUE - * is PTIMER). - */ - NvBool bIsTimerPrecise; -} NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS; - -/* - * NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET/SET_CONTROL - * - * Get/set the event bitmask. - */ -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_CONTROL (0x20803115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x15" */ - -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_SET_CONTROL (0x20803116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x16" */ - -typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS { - //! The engine type, from NV2080_ENGINE_TYPE_* - NvU32 engine; - - /*! - * The bitmask of which event types to log. An event type corresponding to - * a bit with a zero will be ignored at the log site, which prevents it - * from filling up the resident buffer in the PMU. In general, set this to - * only log the event types you actually want to use. - * Refer to NVOS_BM_* in nvos_utility.h for usage. - */ - NvU8 mask[4]; -} NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS; - -/* - * NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE - * - * Send a recalibrate event to the intstrumentation. - */ -#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE (0x20803117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID (0x17U) - -typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS { - //! The engine type, from NV2080_ENGINE_TYPE_* - NvU32 engine; -} NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS; - +#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU /* * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH @@ -280,7 +107,7 @@ typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS { * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*. * */ -#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U) @@ -340,6 +167,50 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { /*!@}*/ +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN + * + * These DRFs define breakdown of the compact payload for various event IDs. + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON 10:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD 0x0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 0x1 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK 0x2 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK 0x3 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED 0x4 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT 23:11 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP 23:0 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT 10U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID 23:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED 0x000000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL 0x000001 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT 6U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID 11:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID 0x000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL 0x001 + +/*!@}*/ + + /*! * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h index a208afb28..2af63e764 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h @@ -32,4 +32,3 @@ /* _ctrl2080fuse_h_ */ - diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h index 774fc40a9..41f9767af 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -32,7 +32,5 @@ /* _ctrl2080gpio_h_ */ - - #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index aa53cfbd9..f87471dd9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -29,12 +29,10 @@ // Source file: ctrl/ctrl2080/ctrl2080gpu.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080gr.h" #include "ctrl/ctrl0000/ctrl0000system.h" +#include "nvcfg_sdk.h" @@ -366,7 +364,7 @@ typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { * This command sets the subdevice instance and mask value for the associated subdevice. * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction * provided by the NV36_CHANNEL_DMA and newer channel dma classes. - * It must be called before the GPU HW is initialized otherwise + * It must be called before the GPU HW is initialized otherwise * NV_ERR_INVALID_STATE is being returned. * * subdeviceMask [in] @@ -903,9 +901,9 @@ typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { * promoteEntry * List of context buffer entries to issue promotions for. * - * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be - * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so - * if both are specified, hVirtMemory has precedence. + * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be + * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so + * if both are specified, hVirtMemory has precedence. * * Possible status values returned are: * NV_OK @@ -1080,7 +1078,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { #define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000016) +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018) @@ -2398,28 +2396,6 @@ typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { #define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ -/* - * NV2080_CTRL_CMD_GPU_INTERRUPT_FUNCTION - * - * The command will trigger an interrupt to a specified PCIe Function. - * - * gfid[IN] - * - The GPU function identifier - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - * NV_ERR_NOT_SUPPORTED - */ - -#define NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS_MESSAGE_ID (0x71U) - -typedef struct NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS { - NvU32 gfid; -} NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS; - -#define NV2080_CTRL_CMD_GPU_INTERRUPT_FUNCTION (0x20800171) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS_MESSAGE_ID" */ - /* * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT * @@ -2545,34 +2521,43 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); } NV2080_CTRL_GPU_SET_PARTITION_INFO; -#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID -#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFF -#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008 -#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009 -#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008 -#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000c -#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008 +#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID +#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFF +#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008 +#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009 +#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008 +#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000c +#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000004 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 5 -#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 6 +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 -#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 -#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1 // TODO XXX Bug 2657907 Remove these once clients update #define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) @@ -2633,10 +2618,22 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { * - NvJpg Engines assigned to a partition. * * gpcCount[OUT] - * - Max GPCs assigned to a partition. + * - Max GPCs assigned to a partition, including the GfxCapable ones. + * + * virtualGpcCount[OUT] + * - Virtualized GPC count assigned to partition + * + * gfxGpcCount[OUT] + * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. * * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] - * - GPC count associated with every valid SMC/Gr. + * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount * * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] * - VEID count associated with every valid SMC. VEIDs within this SMC @@ -2670,7 +2667,11 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { NvU32 nvJpgCount; NvU32 nvOfaCount; NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; NV_DECLARE_ALIGNED(NvU64 memSize, 8); NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); @@ -3179,10 +3180,19 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { * partition * * [OUT] grCount - * - Number of SMC engines/GR engines + * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) + * + * [OUT] gfxGrCount + * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount * * [OUT] gpcCount - * - Number of GPCs in this partition + * - Number of GPCs in this partition, including the GFX Capable ones. + * + * [OUT] virtualGpcCount + * - Number of virtualized GPCs in this partition, including the GFX Capable ones. + * + * [OUT] gfxGpcCount + * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. * * [OUT] veidCount * - Number of VEIDS in this partition @@ -3210,7 +3220,10 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { NvU32 partitionFlag; NvU32 grCount; + NvU32 gfxGrCount; NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 grGpcCount; NvU32 veidCount; NvU32 smCount; NvU32 ceCount; @@ -3282,9 +3295,9 @@ typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { * Logical GPC id * count [OUT] * The number of MMUs per GPC - * grRouteInfo - * This parameter specifies the routing information used to - * disambiguate the target GR engine. When SMC is enabled, this + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this * is a mandatory parameter. */ #define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) @@ -3619,7 +3632,7 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES * * This command is used to retrieve the load time (latency) of each engine. - * + * * engineCount * This field specifies the number of entries of the following * three arrays. @@ -3653,10 +3666,10 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING * * This command is used to retrieve the mapping of engine ID and engine Name. - * + * * engineCount * This field specifies the size of the mapping. - * + * * engineID * An array of NvU32 which stores each engine's descriptor. * @@ -3681,7 +3694,7 @@ typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { * * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will * not allow any embedded pointers. The regOps array is inlined as part of the - * struct. + * struct. * NOTE: This intended for gsp plugin only as it may override regOp access * restrictions * @@ -3779,4 +3792,54 @@ typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; } NV2080_CTRL_GET_P2P_CAPS_PARAMS; + + +/*! + * NV2080_CTRL_GPU_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * id[OUT] + * - Total Number of GPCs in this partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_GPU_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + /* _ctrl2080gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index bb7993e3c..c7fb06425 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080gr.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */ @@ -514,7 +511,8 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { * * hClient * This parameter specifies the client handle of - * that owns the zcull context buffer. + * that owns the zcull context buffer. This field must match + * the hClient used in the control call for non-kernel clients. * hChannel * This parameter specifies the channel handle of * the channel that is to have its zcull context switch mode changed. @@ -1086,6 +1084,8 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS { #define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U +#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID 0xFFU + #define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU) typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS { @@ -1786,4 +1786,29 @@ typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS { NvU32 reasonCode; } NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS; +/* + * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO + * + * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * physGfxGpcMask [OUT] + * Physical mask of Gfx capable GPC's + * + * numGfxTpc [OUT] + * Total number of Gfx capable TPC's + */ +#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS; + /* _ctrl2080gr_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h index c36848a0f..481b59aae 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080grmgr.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX grmgr control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h index 19874c588..ee04d61a6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080gsp.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX GSP control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h index 35cbf239e..f0df6c526 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080hshub.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h index 07495303f..b3314d902 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080i2c.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX i2c-related control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index 84baf8f03..a92da4d0d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -31,9 +31,6 @@ // #include "nvimpshared.h" - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" @@ -316,6 +313,9 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { * zcullMask is always indexed by physical GPC ID */ NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { @@ -662,7 +662,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { /** * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE - * + * * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. */ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { @@ -852,10 +852,19 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { * Allocation flag to be used to allocate a partition with this profile. * * grCount [OUT] - * # GR engines + * # GR engines, including the GFX capable ones. + * + * gfxGrCount [OUT] + * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount * * gpcCount [OUT] - * # total gpcs + * # total gpcs, including the GFX capable ones. + * + * virtualGpcCount [OUT] + * # virtualized gpcs, including the GFX capable ones. + * + * gfxGpcCount [OUT] + * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. * * veidCount [OUT] * # total veids @@ -878,14 +887,17 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { * nvOfaCount [OUT] * # NVOFA engines */ -#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 10 +#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { NvU32 partitionFlag; NvU32 grCount; + NvU32 gfxGrCount; NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; NvU32 veidCount; NvU32 smCount; NvU32 ceCount; @@ -1484,7 +1496,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { * * memBoundaryCfg [OUT] * Memory boundary config (64KB aligned) - * + * * memBoundaryCfgValInit [OUT] * Memory boundary config initial value (64KB aligned) */ @@ -1591,7 +1603,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { * * bBridgeless [IN] * Bridgeless information, for now supporting only MIO bridges - * + * * currLimits * Array of limits that will be applied * @@ -1618,7 +1630,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { * hysteresis algorithm for SLI GPU Boost synchronization: * NV_TRUE -> enabled, * NV_FALSE -> disabled - * + * * bSliGpuBoostSyncEnable [OUT] * SLI GPU Boost feature is: * NV_TRUE -> enabled, @@ -1736,20 +1748,25 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR * gfId [IN] * This specifies Id of the Kernel RM that is requesting the Boost * + * bOverrideInfinite[IN] + * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. + * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM + * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. + * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_PARAM_STRUCT - * NV_ERR_INVALID_ARGUMENT * + * NV_ERR_INVALID_ARGUMENT */ #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { - - NvU32 flags; - NvU32 boostDuration; - NvU32 gfId; + NvU32 flags; + NvU32 boostDuration; + NvU32 gfId; + NvBool bOverrideInfinite; } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; /*! @@ -1893,6 +1910,7 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); NvU32 partitionFlags; NvU32 gpcMask; + NvU32 virtualGpcCount; NvU32 veidOffset; NvU32 veidCount; } NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; @@ -1934,8 +1952,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { */ #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ - - /*! * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO * @@ -1997,7 +2013,7 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { * * Possible status values returned are: * NV_OK - * + * */ #define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ @@ -2166,6 +2182,35 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { NvBool bRawMode; } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_MAP + * + * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it + * in physical-RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_ADDRESS + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 +#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); +} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP + * + * This command unmaps the shared buffer memory mapping in physical-RM + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB4" */ + /*! @@ -2223,15 +2268,99 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { NvBool enableRo; } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */ + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gfxGpcCount[OUT] + * - Total Number of GFX Supporting GPCs in this partition + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xbbU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; + + + +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL + * + * Returns number of active links allowed per IOCTRL + * + * [Out] numActiveLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD8U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { + NvU32 numActiveLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; + +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ad8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL + * + * Returns number of links per IOCTRL + * + * [Out] numLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD9U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { + NvU32 numLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; + +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ad9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ + /*! * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE * * Query Coherent FB Aperture Size. * */ -#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xbaU) +#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { // Get Coherent Fb Aperture Size diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h index 1ca6add91..068d4f2f8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -32,6 +32,3 @@ // _ctrl2080lpwr_h_ - - - diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h index dcdebaeb4..2bb1c3033 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h @@ -30,9 +30,8 @@ // Source file: ctrl/ctrl2080/ctrl2080mc.finn // - - #include "ctrl/ctrl2080/ctrl2080base.h" +#include "nvcfg_sdk.h" /* NV20_SUBDEVICE_XX mc control commands and parameters */ @@ -82,6 +81,8 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS { /* valid ARCHITECTURE_T23X implementation values */ + + #define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004) #define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h index 8c428735b..f1e490b10 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -30,10 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080nvd.finn // - - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 9cbfd5a66..23cce95d5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080nvlink.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX bus control commands and parameters */ @@ -136,16 +133,14 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U) #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U) #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U) - - +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U) - - +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U) /* * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS @@ -322,8 +317,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U) #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U) #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U) - - +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005U) #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U) #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC (0x00000008U) #define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX (0x0000000aU) @@ -331,7 +325,9 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { // NVLink Rx sublink states #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U) -#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER (0x00000004) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U) @@ -341,7 +337,9 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { // NVLink Tx sublink states #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U) -#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER (0x00000004) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U) #define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U) @@ -396,7 +394,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { #define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U) typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS { - NvU32 enabledLinkMask; + NvU32 enabledLinkMask; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8); } NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS; @@ -1341,7 +1340,99 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS { NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType; } NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS; - +/* + * NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE + * + * This command returns the presence and data fields of an NVLink Bridge EEPROM. + * + * [in] linkId + * The NVLink ID to check for a bridge EEPROM + * [out] bPresent + * NV_TRUE if the EEPROM chip is detected. + * [out] bValid + * NV_TRUE if the the data read passes validity checks. If so, the following + * fields are populated. + * [out] firmwareVersion + * The firmware version formatted as PPPP.SSSS.BB, e.g. 4931.0200.01.01, + * padded with one or more 0x00 + * [out] bridgeVendor + * The bridge vendor name, padded with one or more 0x00 + * [out] boardPartNumber + * The board part number, formatted as CCC-FPPPP-SSSS-RRR + * (e.g. 699-24931-0200-000), padded with one or more 0x00 + * [out] boardRevision + * The board revision, e.g. A00, padded with one or more 0x00 + * [out] configuration + * Bridge form factor (2-way/3-way/4-way). + * See NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_* + * [out] spacing + * # of slots spacing identifier. See NV2080_CTRL_NVLINK_BRIDGE_SPACING_* + * [out] interconnectType + * Type of interconnect. See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_* + * [out] interconnectWidth + * Width of interconnect NVHS lanes. + * See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_* + * [out] maximumLandDataRate + * Maximum data transfer rate in T/s, as an IEEE-754 32-bit float + * [out] featureIllumination + * Illumination feature supported. + * See NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_* + * [out] businessUnit + * Business unit identifier. + */ + + +#define NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE (0x20803010U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID" */ + +// ASCII bytes plus space for null terminator +#define NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH (0x11U) /* finn: Evaluated from "(16 + 1)" */ +#define NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */ +#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */ +#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH (0x4U) /* finn: Evaluated from "(3 + 1)" */ + + + +#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_UNDEFINED (0x00U) +#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_2_WAY (0x02U) +#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_3_WAY (0x03U) +#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_4_WAY (0x04U) + +#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_UNDEFINED (0x00U) +#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_2_SLOT (0x02U) +#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_3_SLOT (0x03U) +#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_4_SLOT (0x04U) + +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_UNDEFINED (0x00U) +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_2 (0x02U) +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_3 (0x03U) + +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_UNDEFINED (0x00U) +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_4_LANES (0x02U) +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_8_LANES (0x03U) +#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_16_LANES (0x04U) + +#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_NONE (0x00U) +#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_SINGLE_COLOR (0x01U) +#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_RGB (0x02U) + +#define NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS { + NvU32 linkId; + NvBool bPresent; + NvBool bValid; + char firmwareVersion[NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH]; + char bridgeVendor[NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH]; + char boardPartNumber[NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH]; + char boardRevision[NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH]; + NvU8 businessUnit; + NvU8 configuration; + NvU8 spacing; + NvU8 interconnectType; + NvU8 interconnectWidth; + NvF32 maximumLaneDataRate; + NvU8 featureIllumination; +} NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS; /* * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES @@ -1659,8 +1750,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { #define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U #define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U #define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U - - +#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU #define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU #define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU #define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU @@ -1676,8 +1766,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { #define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U #define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U #define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU - - +#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU +#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU +#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU #define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU /* @@ -1686,6 +1777,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { */ #define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U #define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U #define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U #define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U #define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U @@ -1702,6 +1794,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { */ #define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U #define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U #define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U #define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U #define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U @@ -1970,7 +2063,21 @@ typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS { #define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED + * + * Returns if ALI is enabled + * + * [Out] bEnableAli + * Output boolean for ALI enablement + */ +#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS { + NvBool bEnableAli; +} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID @@ -2229,7 +2336,22 @@ typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS { #define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U) +typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ // // Read Refresh counter - the pass/fail occurrences @@ -2301,7 +2423,22 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS { #define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU) + +typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES { NvBool bValid; @@ -2524,6 +2661,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES { typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS { NvU32 linkMask; NvU32 nvlinkRefClkSpeedKHz; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; } NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS; @@ -2720,4 +2858,31 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS { #define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL + * + * cmd [IN] enum identifying the EOM related command for the driver to process + * link [IN] linkId + * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd + * + * Params Packing is specified in Minion IAS + */ + +typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND { + NVLINK_EOM_CONTROL_START_EOM = 0, + NVLINK_EOM_CONTROL_END_EOM = 1, + NVLINK_EOM_CONTROL_CONFIG_EOM = 2, + NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3, +} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND; + +#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU) + +typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { + NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd; + NvU32 linkId; + NvU32 params; +} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ + /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h index 0c5d77957..e5dbf055c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080perf.finn // - - - #include "nvfixedtypes.h" #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h index f1a7149bb..8eb6c01fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h @@ -31,4 +31,3 @@ /* _ctrl2080perf_cf_h_ */ - diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h index 0421473de..e2471c302 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080rc.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h index 3bf7b5c8e..d018e201f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080tmr.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_TIMER related control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h index 16d6cac35..782e182c8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl2080/ctrl2080unix.finn // - - - #include "ctrl/ctrl2080/ctrl2080base.h" /* NV20_SUBDEVICE_XX OS control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h index 193e3dff8..a5a9db11b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h @@ -31,8 +31,6 @@ /* _ctrl2080vfe_h_ */ - - #include "nvfixedtypes.h" #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080boardobj.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h index 37348eb4a..eacd59600 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h @@ -32,9 +32,6 @@ /* _ctrl2080volt_h_ */ - - - #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl2080/ctrl2080boardobj.h" #include "ctrl/ctrl2080/ctrl2080pmumon.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h index 114a6a090..eb08864fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl208f/ctrl208fbase.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h index f8511c9de..3499ef99a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fbif.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* @@ -130,8 +127,68 @@ typedef struct NV208F_CTRL_BIF_INFO_PARAMS { } NV208F_CTRL_BIF_INFO_PARAMS; /* valid bif info index values */ -#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED (0x00000000) -#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED (0x00000001) +#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED (0x00000000) +#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED (0x00000001) + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR + * + * This ctrl call injects PCI-E XPL-EP ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * errorUnit + * Specifies the HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR (0x208f0705) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + +#define NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for XPL-EP + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED (0x208f0706) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS; /* _ctrl208fbif_h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h index 62cdc66f3..11fd26e6d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fbus.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h index 2fbdd3954..a302d4220 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fdma.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h index 9cffa1a01..3777829d5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fevent.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* NV20_SUBDEVICE_DIAG event-related control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h index e9a81f840..88b861bc6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208ffb.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* @@ -586,4 +583,25 @@ typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { NvU32 sourceMask; } NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; +/* + * NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK + * + * This command calculates the floorswept fbpa mask by taking 1/2 HBM + * floorsweeping into account + * + * fbpaMask + * This value of the mask. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS { + NvU32 fbpaMask; +} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS; + /* _ctrl208ffb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h index ee7d3937b..a523160f9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208ffbio.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h index 2a7f3db42..dba64cdcb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208ffifo.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h index 4b0f00e0a..3dc607e56 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fgpu.finn // - - - #include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h index c5f7997b9..357ac1f59 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fgr.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" #include "ctrl/ctrl2080/ctrl2080gr.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h index 00cbaf0a7..77aeb17dd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl208f/ctrl208fmmu.finn // - - - #include "ctrl/ctrl208f/ctrl208fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h index 7854a45e4..fdfa8fb0a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl30f1.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV30_GSYNC_CTRL control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h index 928031296..eb9bef58e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl402c.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV40_I2C control commands and parameters */ #define NV402C_CTRL_CMD(cat,idx) \ @@ -110,8 +107,6 @@ */ - - #define NV402C_CTRL_CMD_I2C_GET_PORT_INFO (0x402c0101) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h index 6f3af2f0e..e3a9532e5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl503c.finn // - - - #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl503c/ctrl503cbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h index ee7d8b60c..22f3fbe3c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl503c/ctrl503cbase.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV50_THIRD_PARTY_P2P control commands and parameters */ #define NV503C_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x503C,NV503C_CTRL_##cat,idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h index 4297ac870..7fd7c369b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl506f.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV50_GPFIFO control commands and parameters */ @@ -78,8 +75,6 @@ */ - - #define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h index f795e866d..49297f7ad 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV5070_DISPLAY control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h index fb40cb8bc..1916d7fa9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070chnc.finn // - - - #include "ctrl/ctrl5070/ctrl5070base.h" #include "ctrl5070common.h" #include "nvdisptypes.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h index 83284cdfb..515463883 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070event.finn // - - - #include "ctrl/ctrl5070/ctrl5070base.h" /* NV50_DISPLAY event-related control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h index 6c38ab340..0052168ac 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h @@ -31,9 +31,6 @@ // #include "ctrl5070common.h" - - - #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h index 088ab11cd..f5dacc305 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070rg.finn // - - - #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h index 5467bf702..0da723f1b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070seq.finn // - - - #include "ctrl/ctrl5070/ctrl5070base.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h index 7efc5fc47..bbb07e686 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl5070/ctrl5070system.finn // - - - #include "ctrl/ctrl5070/ctrl5070base.h" #include "ctrl/ctrl5070/ctrl5070common.h" // NV5070_CTRL_CMD_MAX_HEADS diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h index 88510e95f..777bdabc4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h @@ -29,9 +29,6 @@ // Source file: ctrl/ctrl5080.finn // - - - #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl0080/ctrl0080dma.h" /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */ #include "ctrl/ctrl2080/ctrl2080dma.h" /* NV2080_CTRL_DMA_* */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h index f54d5a6f2..6ab74be32 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl83de/ctrl83debase.finn // - - - #include "ctrl/ctrlxxxx.h" /* GT200_DEBUG control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h index cf07d7235..746fc0698 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -31,9 +31,6 @@ // Source file: ctrl/ctrl83de/ctrl83dedebug.finn // - - - #include "ctrl/ctrl83de/ctrl83debase.h" #include "nvstatus.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h index e4a622555..43dada915 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl9010.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV9010_CTRL_CMD(cat,idx) \ NVXXXX_CTRL_CMD(0x9010, NV9010_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h index 491f7c8ae..62cb94861 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl9067.finn // - - - #include "ctrl/ctrlxxxx.h" /* Subcontext control commands and parameters */ #define NV9067_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9067, NV9067_CTRL_##cat, idx) @@ -137,8 +134,6 @@ typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS { * */ - - #define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */ #define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h index a491cfd62..8be99d220 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h @@ -174,8 +174,6 @@ typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ - - #define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ #define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U) @@ -204,8 +202,6 @@ typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { * Possible status values returned are: * NV_OK */ - - #define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */ #define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h index 75d9c1b80..8c3cceb4b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl9072.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV9072_CTRL_CMD(cat,idx) \ NVXXXX_CTRL_CMD(0x9072, NV9072_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h index d14fb3c20..47b8d2f2a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl9074.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV9074_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9074, NV9074_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h index 67bd155bd..4aaca210e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl9096.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV9096_CTRL_CMD(cat,idx) \ NVXXXX_CTRL_CMD(0x9096, NV9096_CTRL_##cat, idx) @@ -113,8 +110,6 @@ * NV_OK * NVOS_STATUS_INSUFFICIENT_RESOURCES */ - - #define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR (0x90960101U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID" */ #define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE 4U diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h index f0874a39e..707ec03c2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrl90cc/ctrl90ccbase.finn // - - - #include "ctrl/ctrlxxxx.h" /* GF100_PROFILER control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h index e8971fcb3..b1013f29d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn // - - - #include "ctrl/ctrl90cc/ctrl90ccbase.h" /* GF100_PROFILER HWPM control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h index 9717fd349..aa25ceb2c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90cc/ctrl90ccpower.finn // - - - #include "ctrl/ctrl90cc/ctrl90ccbase.h" /* GF100_PROFILER GPU control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h index 6e031bd35..29449abe4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90cd.finn // - - - #include "ctrl/ctrlxxxx.h" /* NV_EVENT_BUFFER control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h index 544f5613c..ad1d9fbe5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90e6.finn // - - - #include "ctrl/ctrlxxxx.h" #define NV90E6_CTRL_CMD(cat,idx) \ NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h index 59fe63a32..00094c198 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90ec.finn // - - - #include "ctrl/ctrlxxxx.h" /* GK104 HDACODEC control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h index 5b647f412..d63ae9db7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrl90f1.finn // - - - #include "ctrl/ctrlxxxx.h" #include "mmu_fmt_types.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h index 7a7b7670d..245673bbf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrla06f/ctrla06fevent.finn // - - #include "ctrl/ctrla06f/ctrla06fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h index 326bafbbc..699e6c68f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn // - - - #include "ctrl/ctrla06f/ctrla06fbase.h" /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h index 058f47a1f..7a37815a5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -28,8 +28,6 @@ // Source file: ctrl/ctrla06f/ctrla06finternal.finn // - - #include "ctrl/ctrla06f/ctrla06fbase.h" #include "ctrl/ctrla06f/ctrla06fgpfifo.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla083.h b/src/common/sdk/nvidia/inc/ctrl/ctrla083.h new file mode 100644 index 000000000..855ebd41f --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla083.h @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla083.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVA083_GRID_DISPLAYLESS control commands and parameters */ + +#define NVA083_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA083, NVA083_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA083_CTRL_RESERVED (0x00) +#define NVA083_CTRL_VIRTUAL_DISPLAY (0x01) + +/* + * NVA083_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NVA083_CTRL_CMD_NULL (0xa0830000) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_NUM_HEADS (0xa0830101) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS { + NvU32 numHeads; + NvU32 maxNumHeads; +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION + * + * This command returns the maximum resolution supported on a GPU with + * Displayless path enabled OR on a virtual GPU. + * + * headIndex + * This parameter specifies the head for which the maximum resolution is to be + * retrieved. + * + * maxHResolution + * This parameter returns the maximum horizontal resolution. + * + * maxVResolution + * This parameter returns the maximum vertical resolution. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION (0xa0830102) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS { + NvU32 headIndex; + NvU32 maxHResolution; + NvU32 maxVResolution; +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; + + + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_PIXELS (0xa0830106) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxPixels, 8); +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS; + +/* _ctrla083_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h index a9df5fdd4..7cf7069eb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h @@ -145,8 +145,6 @@ typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS { * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h index cb5169f04..6dcf9306a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h @@ -145,8 +145,6 @@ typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS { * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h index 8d4a65435..66eb26d3a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlb069.finn // - - - #include "ctrl/ctrlxxxx.h" /* MAXWELL_FAULT_BUFFER_A control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h index dbe489fb3..14a61997c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h @@ -149,8 +149,6 @@ typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS { * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; @@ -464,6 +462,66 @@ typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS { NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params; } NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS; +/* + * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU migration. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. The maximum size + * of engine context buffer is choosen to support only RAMFC and instance + * memory block. To use this RmCtrl for a higher sized buffer, like the GR + * context, the max size would have to be increased. + * + * engineCtxBuff + * This parameter specifies the context buffer data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA (0xb06f0111) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX 4096 + +#define NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NvU8 engineCtxBuff[NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX]; +} NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU migration. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA (0xb06f0112) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS { + NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params; +} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS; + /* _ctrlb06f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h index a16ae91ca..a6d2929f3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h @@ -28,9 +28,6 @@ // Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn // - - - #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP #define NVB0CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h index f98f2c88f..54e2dbdc4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn // - - - #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" #include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" /* Some controls derivative of b0ccprofiler */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index eb0c71db5..b472e6b7f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn // - - - #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h index 61fe390b4..1b493c7c6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h @@ -145,8 +145,6 @@ typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS { * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h index 9829b381a..fc23e132b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc365.finn // - - - #include "ctrl/ctrlxxxx.h" #define NVC365_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h index c4edd6afd..135de3380 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc369.finn // - - - #include "ctrl/ctrlxxxx.h" /* MMU_FAULT_BUFFER control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h index a4d405787..ddfce2014 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h @@ -149,8 +149,6 @@ typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS { * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h index 42a3ac982..c132cc07a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc370/ctrlc370base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NVC370_DISPLAY control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h index 355e93481..a231232ef 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrlc370/ctrlc370chnc.finn // - - #include "ctrl/ctrlc370/ctrlc370base.h" /* C370 is partially derived from 5070 */ #include "ctrl/ctrl5070/ctrl5070chnc.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h index 23a26a381..ef18c7d89 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc370/ctrlc370event.finn // - - - #include "ctrl/ctrlc370/ctrlc370base.h" /* C370 is partially derived from 5070 */ #include "ctrl/ctrl5070/ctrl5070event.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h index 6f7e5f21c..2a4928453 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrlc370/ctrlc370rg.finn // - - #include "ctrl/ctrlc370/ctrlc370base.h" /* C370 is partially derived from 5070 */ #include "ctrl/ctrl5070/ctrl5070rg.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h index 9520eb55c..d891974e5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h @@ -30,8 +30,6 @@ // Source file: ctrl/ctrlc370/ctrlc370verif.finn // - - #include "ctrl/ctrlc370/ctrlc370base.h" /* C370 is partially derived from 5070 */ #include "ctrl/ctrl5070/ctrl5070verif.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h index 50b017e6f..2d4aea5c5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc372/ctrlc372base.finn // - - - #include "ctrl/ctrlxxxx.h" /* NVC372_DISPLAY_SW control commands and parameters */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h index b4bc93435..0ceda2368 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc372/ctrlc372chnc.finn // - - - #include "nvdisptypes.h" #include "ctrl/ctrlc372/ctrlc372base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h index 142818d2f..c53e217b8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h @@ -107,8 +107,6 @@ typedef NVA06F_CTRL_BIND_PARAMS NVC46F_CTRL_BIND_PARAMS; * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC46F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h index fa9090481..a781b1abe 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h @@ -109,8 +109,6 @@ typedef NVA06F_CTRL_BIND_PARAMS NVC56F_CTRL_BIND_PARAMS; * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ - - #define NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC56F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h index d5cd13803..ce4db0bb9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc637.finn // - - - #include "ctrl/ctrlxxxx.h" /* AMPERE_SMC_PARTITION_REF commands and parameters */ @@ -59,8 +56,11 @@ * * This structure specifies resources in an execution partition * - * GpcCount[IN/OUT] - * - Number of GPCs in this partition + * gpcCount[IN/OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * gfxGpcCount[IN/OUT] + * - Number of GFX GPCs in this partition. This should be a subset of gpcs inlcuded in gpcCount * * VeidCount[OUT] * - Number of VEIDs available in this partition. @@ -88,6 +88,7 @@ */ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { NvU32 gpcCount; + NvU32 gfxGpcCount; NvU32 veidCount; NvU32 ceCount; NvU32 nvEncCount; @@ -147,8 +148,6 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { - - #define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */ /*! @@ -262,7 +261,7 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS { #define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS (0xc6370104) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID" */ /* - * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT + * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT * * Export the resource and placement information about an exec partition such * that a similar partition can be recreated from scratch in the same position. @@ -270,7 +269,7 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS { #define NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT (0xc6370105) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x5" */ /* - * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT + * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT * * Create an exec partition resembling the exported partition info. The imported * partition should behave identically with respect to fragmentation. diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h index 47429b0a7..f9cf5fb19 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h @@ -30,9 +30,6 @@ // Source file: ctrl/ctrlc638.finn // - - - #include "ctrl/ctrlxxxx.h" /* AMPERE_SMC_EXEC_PARTITION_REF commands and parameters */ @@ -79,8 +76,6 @@ - - #define NVC638_CTRL_CMD_GET_UUID (0xc6380101) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID << 8) | NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h new file mode 100644 index 000000000..eeb89236d --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. +*/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc86f.finn +// + + + +#include "nvcfg_sdk.h" + + + +/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#define NVC86F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC86F_CTRL_##cat, idx) + +/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC86F_CTRL_RESERVED (0x00) +#define NVC86F_CTRL_GPFIFO (0x01) +#define NVC86F_CTRL_EVENT (0x02) + +/* + * NVC86F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC86F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC86F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC86F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC86F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC86F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC86F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC86F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC86F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC86F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC86F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC86F_CTRL_BIND_PARAMS; + +/* + * NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC86F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC86F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC86F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC86F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlC86F.h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h new file mode 100644 index 000000000..026ad394e --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcbca.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_COUNTER_COLLECTION_UNIT control commands and parameters */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCBCA, NVCBCA_CTRL_##cat, idx) + +#define NVCBCA_CTRL_RESERVED (0x00) +#define NVCBCA_CTRL_COUNTER_COLLECTION_UNIT (0x01) + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL (0xcbca0000) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE + * + * This command is used to subscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE (0xcbca0101) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bufferSize, 8); + NvU32 counterBlockSize; +} NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE + * + * This command is used to unsubscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrlcbca_h_ */ + diff --git a/src/common/sdk/nvidia/inc/finn_rm_api.h b/src/common/sdk/nvidia/inc/finn_rm_api.h index e3aeb0f45..77fbdd11e 100644 --- a/src/common/sdk/nvidia/inc/finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/finn_rm_api.h @@ -9,6 +9,7 @@ #include +#include #define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) #define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) @@ -39,17 +40,17 @@ * FINN compiler version */ #define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 11 +#define FINN_VERSION_MINOR 13 #define FINN_VERSION_PATCH 0 typedef struct FINN_RM_API { - NV_DECLARE_ALIGNED(NvU64 version, 8); - NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); - NV_DECLARE_ALIGNED(NvU64 interface, 8); - NV_DECLARE_ALIGNED(NvU64 message, 8); - NV_DECLARE_ALIGNED(NvU64 fieldMask[0], 8); - } FINN_RM_API; + NV_DECLARE_ALIGNED(NvU64 version, 8); + NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); + NV_DECLARE_ALIGNED(NvU64 interface, 8); + NV_DECLARE_ALIGNED(NvU64 message, 8); +} FINN_RM_API; + /*! * @brief Serializes an RM API control params struct and copies it into the @@ -88,6 +89,7 @@ NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); /**@}*/ + /*! * @brief The following APIs deserialize a FINN message from the serialization * buffer and copy it into an RM API control params struct. @@ -156,610 +158,354 @@ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src */ NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); - - +#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) +typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; #define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; - - #define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; - - #define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) typedef FINN_RM_API FINN_NV01_ROOT_DIAG; - - #define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) typedef FINN_RM_API FINN_NV01_ROOT_EVENT; - - #define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) typedef FINN_RM_API FINN_NV01_ROOT_GPU; - - #define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; - - #define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; - - #define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) typedef FINN_RM_API FINN_NV01_ROOT_NVD; - - #define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) typedef FINN_RM_API FINN_NV01_ROOT_PROC; - - #define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; - - #define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; - - #define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; - - #define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; - - #define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; #define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; - - #define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; #define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) typedef FINN_RM_API FINN_NV01_TIMER_TMR; - - #define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; #define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; - - #define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; - - #define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; #define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; - - #define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; #define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; - - #define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; #define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; - - #define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; - - #define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; - - #define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; - - #define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; - - #define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; - - #define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; - - #define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; - - #define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; - - #define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; - - #define FINN_NV01_DEVICE_0_BSP_INTERFACE_ID (0x801cU) typedef FINN_RM_API FINN_NV01_DEVICE_0_BSP; - - #define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; - - #define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; - - #define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; - - #define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; - - #define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; - - #define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; - - #define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; - - #define FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID (0x801bU) typedef FINN_RM_API FINN_NV01_DEVICE_0_MSENC; - - #define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; - - #define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; - - #define FINN_NV01_DEVICE_0_RC_INTERFACE_ID (0x801dU) typedef FINN_RM_API FINN_NV01_DEVICE_0_RC; - - #define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; - - #define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; - - #define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; #define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; - - #define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; #define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; - - #define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; #define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; - - #define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; #define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; - - #define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; #define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; - - #define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; #define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; - - #define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; - - #define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; - - #define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; - - #define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; - - - - #define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; - - #define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; - - #define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; - - #define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; - - #define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; - - #define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; - - #define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; - - #define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; - - #define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; - - #define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; - - #define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; - - #define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; - - #define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; - - #define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; - - #define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; - - #define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; - - #define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; - - #define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; - - #define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; - - #define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; - - #define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; - - #define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; - - - - - - #define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; - - #define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; - - +#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; #define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; - - #define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; - - #define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; - - #define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; - - #define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; #define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) typedef FINN_RM_API FINN_NV2081_BINAPI; - - #define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; #define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) typedef FINN_RM_API FINN_NV2082_BINAPI; - - #define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; - - #define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; - - #define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; - - #define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; - - #define FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID (0x208f10U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_EVENT; - - #define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; - - #define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; - - #define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; - - #define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; - - #define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; - - #define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; - - #define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; #define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; - - #define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) typedef FINN_RM_API FINN_NV40_I2C_RESERVED; #define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) typedef FINN_RM_API FINN_NV40_I2C_I2C; - - #define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; - - #define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; - - #define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; #define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; - - #define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; - - #define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; - - #define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U) typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT; - - #define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) typedef FINN_RM_API FINN_NV50_DISPLAY_OR; - - #define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) typedef FINN_RM_API FINN_NV50_DISPLAY_RG; - - #define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U) typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ; - - #define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; - - #define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; #define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; - - #define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; - - #define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; - - #define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; - - #define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; - - #define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; #define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; - - #define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; #define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; #define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; - - #define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; #define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; #define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U) typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT; - - #define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; #define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; - - #define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; #define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; - - #define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; #define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; - - #define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; #define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; - - #define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; - - #define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; - - #define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; - - #define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) typedef FINN_RM_API FINN_GF100_PROFILER_POWER; - - #define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; #define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; - - #define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; #define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; - - #define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; #define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; - - #define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; #define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; - - #define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; #define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) @@ -767,45 +513,29 @@ typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; #define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; - - #define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; #define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; - - #define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; #define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; - - #define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; #define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; #define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; - - #define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; - - #define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; - - - #define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; - - #define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; - #define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; #define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) @@ -813,215 +543,149 @@ typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; #define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; - - #define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; #define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; - - #define FINN_NVA084_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_KERNEL_INTERFACE_ID (0xa08401U) typedef FINN_RM_API FINN_NVA084_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_KERNEL; - - #define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; - - #define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; - - #define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; #define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; - - #define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; #define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; - - #define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED; #define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO; #define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT; - - #define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED; #define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO; #define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT; - - #define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; #define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; - - #define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; #define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U) typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; - - #define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; - - #define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; - - #define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; - - #define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; #define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; - - #define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; - - #define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; - - #define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U) typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED; #define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U) typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U) typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT; - - #define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; #define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; - - #define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; #define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; - - #define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) typedef FINN_RM_API FINN_VOLTA_GSP_GSP; - - #define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; #define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; - - #define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; #define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; - - #define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; #define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U) typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT; - - #define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; - - #define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; - - #define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; - - #define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; - - #define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; - - #define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; - - #define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; - - #define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; #define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; - - #define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; #define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; - - #define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U) typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED; #define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U) typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U) typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT; - - #define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; #define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U) typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT; - - #define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; #define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; - - #define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; #define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; - - #define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; #define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; - - - +#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; + +#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; +#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; #define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; #define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) diff --git a/src/common/sdk/nvidia/inc/nvcfg_sdk.h b/src/common/sdk/nvidia/inc/nvcfg_sdk.h new file mode 100644 index 000000000..4ce8d4b66 --- /dev/null +++ b/src/common/sdk/nvidia/inc/nvcfg_sdk.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_CFG_SDK_INCLUDED +#define NV_CFG_SDK_INCLUDED + + +#endif // NV_CFG_SDK_INCLUDED diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index b60dc0787..bce7bea45 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -96,6 +96,7 @@ #define INFOROM_ERASE_LIMIT_EXCEEDED (93) #define ROBUST_CHANNEL_CONTAINED_ERROR (94) #define ROBUST_CHANNEL_UNCONTAINED_ERROR (95) +#define SEC_FAULT_ERROR (110) #define GSP_RPC_TIMEOUT (119) #define GSP_ERROR (120) #define C2C_ERROR (121) diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 2b127116b..99a4eb896 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -40,6 +40,7 @@ extern "C" { #include "nvgputypes.h" #include "rs_access.h" +#include "nvcfg_sdk.h" /* local defines here */ #define FILE_DEVICE_NV 0x00008000 @@ -1795,16 +1796,29 @@ typedef struct // have the option of directly mapping video memory over that connection. // During mapping you may specify a preference. // -#define NVOS33_FLAGS_BUS 21:20 -#define NVOS33_FLAGS_BUS_ANY 0 -#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 -#define NVOS33_FLAGS_BUS_PCIE 2 +#define NVOS33_FLAGS_BUS 21:20 +#define NVOS33_FLAGS_BUS_ANY 0 +#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 +#define NVOS33_FLAGS_BUS_PCIE 2 // Internal use only #define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 #define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) #define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001) +// +// For use in the linux mapping path. This flag sets the +// caching mode for pcie BAR mappings (from nv_memory_type.h). +// Internal use only. +// +#define NVOS33_FLAGS_CACHING_TYPE 25:23 +#define NVOS33_FLAGS_CACHING_TYPE_CACHED 0 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED 1 +#define NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED 2 +#define NVOS33_FLAGS_CACHING_TYPE_WRITEBACK 5 +#define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 + /* parameters */ typedef struct { @@ -3193,6 +3207,23 @@ typedef struct NvV32 status; // [OUT] status of call } NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS; +/** + * @brief HopperUsermodeAParams + * This set of optionalparameters is passed in on allocation of + * HOPPER_USERMODE_A object to specify whether a BAR1/GMMU + * privileged/non-privileged mapping is needed. + */ + +typedef struct +{ + /** + * [IN] Whether to allocate GMMU/BAR1 mapping or BAR0 mapping. + */ + NvBool bBar1Mapping; + /* [IN] Whether to allocate the PRIV page or regular VF page */ + NvBool bPriv; +} NV_HOPPER_USERMODE_A_PARAMS; + #ifdef __cplusplus }; diff --git a/src/common/sdk/nvidia/inc/rmcd.h b/src/common/sdk/nvidia/inc/rmcd.h index b4d8abcef..323295d59 100644 --- a/src/common/sdk/nvidia/inc/rmcd.h +++ b/src/common/sdk/nvidia/inc/rmcd.h @@ -208,6 +208,10 @@ typedef RmRC2GpuTimeout3_RECORD *PRmRC2GpuTimeout3_RECORD; #define NV_RM_ASSERT_HW_UNIT_NVDEC1 (0x13) #define NV_RM_ASSERT_HW_UNIT_NVDEC2 (0x14) #define NV_RM_ASSERT_HW_UNIT_NVDEC3 (0x15) +#define NV_RM_ASSERT_HW_UNIT_NVDEC4 (0x16) +#define NV_RM_ASSERT_HW_UNIT_NVDEC5 (0x17) +#define NV_RM_ASSERT_HW_UNIT_NVDEC6 (0x18) +#define NV_RM_ASSERT_HW_UNIT_NVDEC7 (0x19) #define NV_RM_ASSERT_HW_UNIT_ALLENGINES (0xff) // SW Module which generated the error #define NV_RM_ASSERT_SW_MODULE 15:8 diff --git a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c b/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c index 8b0f58175..09f5b3f5c 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c +++ b/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c @@ -968,6 +968,17 @@ static void libosExtractLogs_decode(LIBOS_LOG_DECODE *logDecode) pLog->putCopy = pLog->physicLogBuffer[0]; pLog->putIter = pLog->putCopy; + if (pLog->putIter < pLog->previousPut) + { + printf( + "**** %s-%s buffer put counter reset unexpectedly (cur=0x%llx, prev=0x%llx). Entries possibly lost. ****\n", + logDecode->sourceName, pLog->taskPrefix, pLog->putIter, pLog->previousPut); +#ifdef PORT_ASSERT + PORT_ASSERT(pLog->putIter >= pLog->previousPut); +#endif + pLog->previousPut = pLog->putIter; + } + libosExtractLog_ReadRecord(logDecode, pLog); } diff --git a/src/nvidia-modeset/include/g_nvkms-evo-states.h b/src/nvidia-modeset/include/g_nvkms-evo-states.h index c3b5ce2e4..425022771 100644 --- a/src/nvidia-modeset/include/g_nvkms-evo-states.h +++ b/src/nvidia-modeset/include/g_nvkms-evo-states.h @@ -38,3 +38,4 @@ void nvEvoStateStartNoLock(NVEvoSubDevPtr); #endif #endif /* __EVO_STATE_H__ */ + diff --git a/src/nvidia-modeset/include/nvkms-dpy.h b/src/nvidia-modeset/include/nvkms-dpy.h index 65dfadfd1..2b1e2acf1 100644 --- a/src/nvidia-modeset/include/nvkms-dpy.h +++ b/src/nvidia-modeset/include/nvkms-dpy.h @@ -44,9 +44,6 @@ void nvUpdateInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head); NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, const NVHwModeTimingsEvo *pTimings); -NVHwModeTimingsEvoPtr -nvGetCurrentModeTimingsForDpyEvo(const NVDpyEvoRec *pDpyEvo); - NVDpyEvoPtr nvGetDpyEvoFromDispEvo(const NVDispEvoRec *pDispEvo, NVDpyId dpyId); NVDpyEvoPtr nvGetDPMSTDpyEvo(NVConnectorEvoPtr pConnectorEvo, diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 744db402f..4f6a73255 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -222,6 +222,8 @@ void nvChooseCurrentColorSpaceAndRangeEvo( void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( NVDispEvoPtr pDispEvo, const NvU32 head, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState); void nvSetColorSpaceAndRangeEvo( diff --git a/src/nvidia-modeset/include/nvkms-modeset-types.h b/src/nvidia-modeset/include/nvkms-modeset-types.h index 35bede3b0..5054c654b 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-types.h +++ b/src/nvidia-modeset/include/nvkms-modeset-types.h @@ -35,8 +35,7 @@ typedef struct { NvU32 activeRmId; struct NvKmsSetLutCommonParams lut; NvU8 allowFlipLockGroup; - enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; - enum NvKmsDpyAttributeColorRangeValue colorRange; + NVAttributesSetEvoRec attributes; struct NvKmsModeValidationParams modeValidationParams; NvBool changed : 1; NvBool allowGsync : 1; diff --git a/src/nvidia-modeset/include/nvkms-modeset.h b/src/nvidia-modeset/include/nvkms-modeset.h index 3b63b235d..9540058a3 100644 --- a/src/nvidia-modeset/include/nvkms-modeset.h +++ b/src/nvidia-modeset/include/nvkms-modeset.h @@ -43,6 +43,14 @@ typedef NvBool (*NVShutDownHeadsTestFunc)( void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc); +NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, + NvU32 head, + NVVBlankCallbackProc pCallback, + void *pUserData); +void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + NvU32 head, + NVVBlankCallbackPtr pCallback); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index 11338146e..1d8c6c468 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -134,6 +134,7 @@ typedef struct _NVVblankSyncObjectRec *NVVblankSyncObjectPtr; typedef struct _NVDispHeadStateEvoRec *NVDispHeadStateEvoPtr; typedef struct _NVDispEvoRec *NVDispEvoPtr; typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr; +typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr; typedef struct _NVDpyEvoRec *NVDpyEvoPtr; typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr; typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr; @@ -841,7 +842,6 @@ typedef struct _NVEvoDevRec { NvU32 deviceHandle; struct NvKmsPerOpenDev *pNvKmsOpenDev; - /* SLI Info */ struct { NvBool mosaic; @@ -1141,6 +1141,13 @@ typedef struct _NVHwModeViewPortEvo { struct NvKmsUsageBounds guaranteedUsage; } NVHwModeViewPortEvo; +static inline NvBool nvIsImageSharpeningAvailable( + const NVHwModeViewPortEvo *pViewPort) +{ + return (pViewPort->out.width != pViewPort->in.width) || + (pViewPort->out.height != pViewPort->in.height); +} + enum nvKmsPixelDepth { NVKMS_PIXEL_DEPTH_18_444, NVKMS_PIXEL_DEPTH_24_444, @@ -1324,6 +1331,22 @@ static inline struct NvKmsRect nvEvoViewPortOutClientView( return viewPortOut; } +/* + * The ELD contains a subset of the digital display device's EDID + * information related to audio capabilities. The GPU driver sends the + * ELD to hardware and the audio driver reads it by issuing the ELD + * command verb. + */ + +#define NV_MAX_AUDIO_DEVICE_ENTRIES \ + (NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 + 1) + +typedef enum { + NV_ELD_PRE_MODESET = 0, + NV_ELD_POST_MODESET, + NV_ELD_POWER_ON_RESET, +} NvEldCase; + /* OR indices are per OR-type. The maximum OR index for each type * on each GPU is: * @@ -1390,6 +1413,8 @@ typedef struct _NVConnectorEvoRec { NvBool ycbcr422Capable; NvBool ycbcr444Capable; } colorSpaceCaps; + + NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; } NVConnectorEvoRec; static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( @@ -1513,9 +1538,6 @@ typedef struct _NVDispHeadStateEvoRec { NVAttributesSetEvoRec attributes; - NVEvoScalerTaps hTaps; - NVEvoScalerTaps vTaps; - /*! Cached, to preserve across modesets. */ struct NvKmsModeValidationParams modeValidationParams; @@ -1567,6 +1589,9 @@ typedef struct _NVDispHeadStateEvoRec { NvU8 numVblankSyncObjectsCreated; NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; NVDispHeadAudioStateEvoRec audio; + + NvU32 rmVBlankCallbackHandle; + NVListRec vblankCallbackList; } NVDispHeadStateEvoRec; typedef struct _NVDispEvoRec { @@ -1662,6 +1687,15 @@ typedef struct _NVDispEvoRec { struct nvkms_backlight_device *backlightDevice; } NVDispEvoRec; +/* + * XXX[2Head1OR] Remove nvHardwareHeadToApiHead(), before implementing logic to + * map multiple hardware heads onto the single api head. + */ +static inline NvU32 nvHardwareHeadToApiHead(const NvU32 head) +{ + return head; +} + typedef enum { NV_EVO_PASSIVE_DP_DONGLE_UNUSED, NV_EVO_PASSIVE_DP_DONGLE_DP2DVI, @@ -1682,14 +1716,23 @@ typedef struct _NVParsedEdidEvoRec { char serialNumberString[NVT_EDID_LDD_PAYLOAD_SIZE+1]; } NVParsedEdidEvoRec; +typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVVBlankCallbackPtr pCallbackData); + +typedef struct _NVVBlankCallbackRec { + NVListRec vblankCallbackListEntry; + NVVBlankCallbackProc pCallback; + void *pUserData; +} NVVBlankCallbackRec; + typedef struct _NVDpyEvoRec { NVListRec dpyListEntry; NVDpyId id; char name[NVKMS_DPY_NAME_SIZE]; - /* The hardware head to use with this dpy. */ - NvU32 head; + NvU32 apiHead; struct _NVDispEvoRec *pDispEvo; NVConnectorEvoPtr pConnectorEvo; @@ -1907,7 +1950,7 @@ static inline NvBool nvDpyUsesDPLib(const NVDpyEvoRec *pDpyEvo) */ static inline NvBool nvDpyEvoIsActive(const NVDpyEvoRec *pDpyEvo) { - return (pDpyEvo->head != NV_INVALID_HEAD); + return (pDpyEvo->apiHead != NV_INVALID_HEAD); } /* @@ -2252,6 +2295,14 @@ struct _NVSurfaceEvoRec { NvBool procFsFlag; #endif + /* + * Disallow DIFR if display caching is forbidden. This will be set for + * CPU accessible surfaces. + */ + NvBool noDisplayCaching; + + /* Keep track of prefetched surfaces. */ + NvU32 difrLastPrefetchPass; }; typedef struct _NVDeferredRequestFifoRec { diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index dcae93ee8..f7bc6842f 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -2430,6 +2430,15 @@ struct NvKmsRegisterSurfaceRequest { NvBool noDisplayHardwareAccess; + /* + * This flag should be set if the surface can potentially be updated + * directly on the screen after the flip. For example, this is the case + * if the surface is CPU mapped, accessible by more than one GPU, or in + * a similar situation. If this flag is set NVKMS knows not to consider + * the surface content cacheable between flips. + */ + NvBool noDisplayCaching; + /* * If isoType == NVKMS_MEMORY_NISO, NVKMS will create CPU and GPU mappings * for the surface memory. diff --git a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h index e37cb9598..dbaab771b 100644 --- a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h +++ b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h @@ -118,12 +118,6 @@ struct NvKmsKapiSurface { NvKmsSurfaceHandle hKmsHandle; }; - -enum NvKmsKapiAllocationType { - NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT = 0, - NVKMS_KAPI_ALLOCATION_TYPE_NOTIFIER = 1, -}; - static inline void *nvKmsKapiCalloc(size_t nmem, size_t size) { return nvInternalAlloc(nmem * size, NV_TRUE); diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index b9fdd1b7c..a63d8dfdf 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -416,6 +416,12 @@ struct NvKmsKapiCreateSurfaceParams { NvU8 log2GobsPerBlockY; }; +enum NvKmsKapiAllocationType { + NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT = 0, + NVKMS_KAPI_ALLOCATION_TYPE_NOTIFIER = 1, + NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2, +}; + struct NvKmsKapiFunctionsTable { /*! @@ -609,6 +615,8 @@ struct NvKmsKapiFunctionsTable { * \param [in] device A device allocated using allocateDevice(). * * \param [in] layout BlockLinear or Pitch. + * + * \param [in] type Allocation type. * * \param [in] size Size, in bytes, of the memory to allocate. * @@ -624,6 +632,7 @@ struct NvKmsKapiFunctionsTable { ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ); @@ -637,6 +646,8 @@ struct NvKmsKapiFunctionsTable { * \param [in] device A device allocated using allocateDevice(). * * \param [in] layout BlockLinear or Pitch. + * + * \param [in] type Allocation type. * * \param [in] size Size, in bytes, of the memory to allocate. * @@ -652,6 +663,7 @@ struct NvKmsKapiFunctionsTable { ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ); diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index 4c6100cc9..688e72538 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -452,7 +452,7 @@ NvBool nvKmsKapiAllocateSystemMemory(struct NvKmsKapiDevice *device, { NvU32 ret; NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { }; - const NvKmsDispIOCoherencyModes *pIOCoherencyModes; + const NvKmsDispIOCoherencyModes *pIOCoherencyModes = NULL; memAllocParams.owner = NVKMS_RM_HEAP_ID; memAllocParams.size = size; @@ -521,6 +521,9 @@ NvBool nvKmsKapiAllocateSystemMemory(struct NvKmsKapiDevice *device, pIOCoherencyModes = &device->nisoIOCoherencyModes; + break; + case NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN: + memAllocParams.flags |= NVOS32_ALLOC_FLAGS_NO_SCANOUT; break; default: nvKmsKapiLogDeviceDebug(device, "Unknown Allocation Type"); @@ -532,7 +535,7 @@ NvBool nvKmsKapiAllocateSystemMemory(struct NvKmsKapiDevice *device, memAllocParams.attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, memAllocParams.attr2); - if (!pIOCoherencyModes->coherent) { + if (pIOCoherencyModes == NULL || !pIOCoherencyModes->coherent) { memAllocParams.attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _WRITE_COMBINE, memAllocParams.attr); } else { @@ -673,6 +676,15 @@ NvBool nvKmsKapiAllocateVideoMemory(struct NvKmsKapiDevice *device, memAllocParams.attr); break; + case NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN: + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.flags |= + NVOS32_ALLOC_FLAGS_NO_SCANOUT | + NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP; + memAllocParams.attr = + FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS, + memAllocParams.attr); + break; default: nvKmsKapiLogDeviceDebug(device, "Unknown Allocation Type"); return NV_FALSE; @@ -1219,6 +1231,7 @@ static struct NvKmsKapiMemory* AllocateVideoMemory ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ) @@ -1236,7 +1249,7 @@ static struct NvKmsKapiMemory* AllocateVideoMemory hRmHandle, layout, size, - NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT, + type, compressible)) { nvKmsKapiFreeRmHandle(device, hRmHandle); FreeMemory(device, memory); @@ -1258,6 +1271,7 @@ static struct NvKmsKapiMemory* AllocateSystemMemory ( struct NvKmsKapiDevice *device, enum NvKmsSurfaceMemoryLayout layout, + enum NvKmsKapiAllocationType type, NvU64 size, NvU8 *compressible ) @@ -1275,7 +1289,7 @@ static struct NvKmsKapiMemory* AllocateSystemMemory hRmHandle, layout, size, - NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT, + type, compressible)) { nvKmsKapiFreeRmHandle(device, hRmHandle); FreeMemory(device, memory); diff --git a/src/nvidia-modeset/src/nvkms-attributes.c b/src/nvidia-modeset/src/nvkms-attributes.c index ce736adaa..f39305f4c 100644 --- a/src/nvidia-modeset/src/nvkms-attributes.c +++ b/src/nvidia-modeset/src/nvkms-attributes.c @@ -155,7 +155,8 @@ static NvBool GetScanLine(const NVDpyEvoRec *pDpyEvo, NvS64 *pScanLine) NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 ret; - const NvU32 head = pDpyEvo->head; + /* XXX[2Heads1OR] Get scanline of the primary hardware head. */ + const NvU32 head = pDpyEvo->apiHead; if (head == NV_INVALID_HEAD) { return FALSE; @@ -189,7 +190,7 @@ static NvBool GetScanLine(const NVDpyEvoRec *pDpyEvo, NvS64 *pScanLine) */ static NvBool GetHead(const NVDpyEvoRec *pDpyEvo, NvS64 *pHead) { - *pHead = (NvS64)pDpyEvo->head; + *pHead = (NvS64)pDpyEvo->apiHead; return TRUE; } @@ -205,12 +206,13 @@ static void SetDitheringCommon(NVDpyEvoPtr pDpyEvo) { NVEvoUpdateState updateState = { }; - if (pDpyEvo->head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; } + /* XXX[2Heads1OR] Broadcast dithering to the hardware heads. */ nvSetDitheringEvo(pDpyEvo->pDispEvo, - pDpyEvo->head, + pDpyEvo->apiHead, pDpyEvo->requestedDithering.state, pDpyEvo->requestedDithering.depth, pDpyEvo->requestedDithering.mode, @@ -425,6 +427,7 @@ static NvBool DigitalVibranceAvailable(const NVDpyEvoRec *pDpyEvo) static NvBool SetDigitalVibrance(NVDpyEvoRec *pDpyEvo, NvS64 dvc) { NVEvoUpdateState updateState = { }; + NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; if (!DigitalVibranceAvailable(pDpyEvo)) { return FALSE; @@ -433,12 +436,15 @@ static NvBool SetDigitalVibrance(NVDpyEvoRec *pDpyEvo, NvS64 dvc) dvc = NV_MAX(dvc, NV_EVO_DVC_MIN); dvc = NV_MIN(dvc, NV_EVO_DVC_MAX); + /* XXX[2Heads1OR] Broadcast vibrance setting to the hardware heads. */ nvSetDVCEvo(pDpyEvo->pDispEvo, - pDpyEvo->head, dvc, &updateState); + pDpyEvo->apiHead, dvc, &updateState); nvEvoUpdateAndKickOff(pDpyEvo->pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); + pDispEvo->headState[pDpyEvo->apiHead].attributes.dvc = dvc; + return TRUE; } @@ -497,12 +503,16 @@ static NvBool SetImageSharpening(NVDpyEvoRec *pDpyEvo, NvS64 imageSharpening) imageSharpening = NV_MAX(imageSharpening, NV_EVO_IMAGE_SHARPENING_MIN); imageSharpening = NV_MIN(imageSharpening, NV_EVO_IMAGE_SHARPENING_MAX); + /* XXX[2Heads1OR] Broadcast image sharpening setting to the hardware heads */ nvSetImageSharpeningEvo(pDispEvo, - pDpyEvo->head, imageSharpening, &updateState); + pDpyEvo->apiHead, imageSharpening, &updateState); nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); + pDispEvo->headState[pDpyEvo->apiHead].attributes.imageSharpening.value = + imageSharpening; + return TRUE; } @@ -569,23 +579,24 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) { NVEvoUpdateState updateState = { }; - if (pDpyEvo->head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; } + /* XXX[2Heads1OR] Broadcast color space settings to the hardware heads. */ /* * Recompute the current ColorSpace and ColorRange, given updated requested * values, and program any changes in EVO hardware. */ nvSetColorSpaceAndRangeEvo( pDpyEvo->pDispEvo, - pDpyEvo->head, + pDpyEvo->apiHead, pDpyEvo->requestedColorSpace, pDpyEvo->requestedColorRange, &updateState); /* Update InfoFrames as needed. */ - nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->head); + nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->apiHead); // Kick off nvEvoUpdateAndKickOff(pDpyEvo->pDispEvo, FALSE, &updateState, @@ -798,13 +809,21 @@ static NvBool GetDigitalLinkType(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { *pValue = nvRMLaneCountToNvKms(pDpyEvo->dp.laneCount); } else { - const NVHwModeTimingsEvo *pTimings = - nvGetCurrentModeTimingsForDpyEvo(pDpyEvo); + const NVHwModeTimingsEvo *pTimings; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + /* + * XXX[2Heads1OR] Track DIGITAL_LINK_TYPE as per head + * attributes set which get mirrored into NVDpyEvoRec::attributes + * after modeset. + */ + const NvU32 head = pDpyEvo->apiHead; - if (pTimings == NULL) { + if (head == NV_INVALID_HEAD) { return FALSE; } + pTimings = &pDispEvo->headState[head].timings; + *pValue = nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings) ? NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_DUAL : NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_SINGLE; @@ -953,20 +972,22 @@ static NvBool SetStereoEvo(NVDpyEvoPtr pDpyEvo, NvS64 value) { NvBool enable = !!value; - if (pDpyEvo->head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return FALSE; } - return nvSetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->head, enable); + /* XXX[2Heads1OR] Broadcast the stereo setting to the hardware heads. */ + return nvSetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->apiHead, enable); } static NvBool GetStereoEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) { - if (pDpyEvo->head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return FALSE; } - *pValue = !!nvGetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->head); + /* XXX[2Heads1OR] Loop over hardware heads to determine stereo status. */ + *pValue = !!nvGetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->apiHead); return TRUE; } @@ -1188,7 +1209,7 @@ NvBool nvSetDpyAttributeEvo(NVDpyEvoPtr pDpyEvo, return FALSE; } - if (pDpyEvo->head != NV_INVALID_HEAD) { + if (pDpyEvo->apiHead != NV_INVALID_HEAD) { NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; NVDpyEvoRec *pClonedDpyEvo; @@ -1200,7 +1221,7 @@ NvBool nvSetDpyAttributeEvo(NVDpyEvoPtr pDpyEvo, * apiHead -> pDpyEvo mapping will get implemented. */ FOR_ALL_EVO_DPYS(pClonedDpyEvo, pDispEvo->validDisplays, pDispEvo) { - if (pClonedDpyEvo->head != pDpyEvo->head) { + if (pClonedDpyEvo->apiHead != pDpyEvo->apiHead) { continue; } nvDpyUpdateCurrentAttributes(pClonedDpyEvo); diff --git a/src/nvidia-modeset/src/nvkms-console-restore.c b/src/nvidia-modeset/src/nvkms-console-restore.c index 891fdbd61..28e52d977 100644 --- a/src/nvidia-modeset/src/nvkms-console-restore.c +++ b/src/nvidia-modeset/src/nvkms-console-restore.c @@ -757,7 +757,7 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) FOR_ALL_EVO_DPYS(pDpyEvo, candidateDpys, pDispEvo) { NvBool isTiledDisplayFound = FALSE; - TiledDisplayInfo tiledDisplayInfo = { 0 }; + TiledDisplayInfo tiledDisplayInfo = { }; NvBool isTiledDisplayEnable = FALSE; const NVT_DISPLAYID_INFO *pDpyDisplayIdInfo = pDpyEvo->parsedEdid.valid ? diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index 7b23105f4..e5a5928d7 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -24,8 +24,6 @@ /* this source file contains routines for setting and moving the cursor. * NV50 specific */ - - #include "nvkms-cursor.h" #include "nvkms-types.h" #include "nvkms-dma.h" diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index 9c0c2686f..a41263c5d 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,6 +56,7 @@ DpyGetPassiveDpDongleType(const NVDpyEvoRec *pDpyEvo, NvU32 *passiveDpDongleMaxPclkKHz); static void CreateParsedEdidFromNVT_TIMING(NVT_TIMING *pTimings, + NvU8 bpc, NVParsedEdidEvoPtr pParsedEdid); static NvBool ReadEdidFromDP (const NVDpyEvoRec *pDpyEvo, @@ -81,7 +82,8 @@ static void ReadAndApplyEdidEvo (NVDpyEvoPtr pDpyEvo, struct NvKmsQueryDpyDynamicDataParams *pParams); static NvBool GetFixedModeTimings (NVDpyEvoPtr pDpyEvo); static NvBool ReadDSITimingsFromResman (const NVDpyEvoRec *pDpyEvo, - NVT_TIMING *pTimings); + NVT_TIMING *pTimings, + NvU8 *pBpc); static void AssignDpyEvoName (NVDpyEvoPtr pDpyEvo); static NvBool IsConnectorTMDS (NVConnectorEvoPtr); @@ -116,8 +118,9 @@ static NvBool DpyConnectEvo( ReadAndApplyEdidEvo(pDpyEvo, pParams); } - if (pDpyEvo->head != NV_INVALID_HEAD) { - nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->head); + if (pDpyEvo->apiHead != NV_INVALID_HEAD) { + /* XXX[2Heads1OR] Info frames should get programmed onky for the primary head. */ + nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->apiHead); } return TRUE; @@ -404,17 +407,11 @@ static void ApplyNewEdid( */ static NvBool ReadDSITimingsFromResman( const NVDpyEvoRec *pDpyEvo, - NVT_TIMING *pTimings) + NVT_TIMING *pTimings, + NvU8 *pBpc) { NvU32 ret; NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS dsiModeTimingParams = { 0 }; - // Values are currently hardcoded while waiting for full RM support - NvU32 hFrontPorch = 8; - NvU32 vFrontPorch = 2; - NvU32 hBackPorch = 56; - NvU32 vBackPorch = 51; - NvU32 hSyncWidth = 96; - NvU32 vSyncWidth = 2; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -442,31 +439,37 @@ static NvBool ReadDSITimingsFromResman( // Converts refresh (Hz) into appropriate units for rr1k (units of 0.001Hz) pTimings->etc.rrx1k = dsiModeTimingParams.refresh * 1000; pTimings->HVisible = dsiModeTimingParams.hActive; - pTimings->HFrontPorch = hFrontPorch; - pTimings->HSyncWidth = hSyncWidth; + pTimings->HFrontPorch = dsiModeTimingParams.hFrontPorch; + pTimings->HSyncWidth = dsiModeTimingParams.hSyncWidth; pTimings->HTotal = dsiModeTimingParams.hActive + - hFrontPorch + hSyncWidth + hBackPorch; + dsiModeTimingParams.hFrontPorch + + dsiModeTimingParams.hSyncWidth + + dsiModeTimingParams.hBackPorch; pTimings->VVisible = dsiModeTimingParams.vActive; - pTimings->VFrontPorch = vFrontPorch; - pTimings->VSyncWidth = vSyncWidth; + pTimings->VFrontPorch = dsiModeTimingParams.vFrontPorch; + pTimings->VSyncWidth = dsiModeTimingParams.vSyncWidth; pTimings->VTotal = dsiModeTimingParams.vActive + - vFrontPorch + vSyncWidth + vBackPorch; + dsiModeTimingParams.vFrontPorch + + dsiModeTimingParams.vSyncWidth + + dsiModeTimingParams.vBackPorch; + + pTimings->pclk = HzToKHz(dsiModeTimingParams.pclkHz) / 10; - pTimings->pclk = HzToKHz(pTimings->VTotal * - pTimings->HTotal * - dsiModeTimingParams.refresh) / 10; + // DSI only supports RGB444 + *pBpc = dsiModeTimingParams.bpp / 3; return TRUE; } static NvBool ReadDPSerializerTimings( const NVDpyEvoRec *pDpyEvo, - NVT_TIMING *pTimings) + NVT_TIMING *pTimings, + NvU8 *pBpc) { /* * TODO Add RM control call that will return the fixed timings - * that can be used with a given display. + * and bpc that can be used with a given display. */ pTimings->HVisible = 1920; pTimings->VVisible = 1080; @@ -481,6 +484,7 @@ static NvBool ReadDPSerializerTimings( pTimings->interlaced = 0; pTimings->pclk = 14850; pTimings->etc.rrx1k = 60000; + *pBpc = 0; return TRUE; } @@ -490,18 +494,20 @@ static NvBool GetFixedModeTimings( { NVT_TIMING timings = { }; NvBool ret = FALSE; + NvU8 bpc; if (pDpyEvo->pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { - ret = ReadDSITimingsFromResman(pDpyEvo, &timings); + ret = ReadDSITimingsFromResman(pDpyEvo, &timings, &bpc); } else if (nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { - ret = ReadDPSerializerTimings(pDpyEvo, &timings); + ret = ReadDPSerializerTimings(pDpyEvo, &timings, &bpc); } if (!ret) { return ret; } - CreateParsedEdidFromNVT_TIMING(&timings, &pDpyEvo->parsedEdid); + CreateParsedEdidFromNVT_TIMING(&timings, bpc, &pDpyEvo->parsedEdid); + AssignDpyEvoName(pDpyEvo); nvDpyProbeMaxPixelClock(pDpyEvo); @@ -1982,6 +1988,7 @@ static void PrePatchEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, */ static void CreateParsedEdidFromNVT_TIMING( NVT_TIMING *pTimings, + NvU8 bpc, NVParsedEdidEvoPtr pParsedEdid) { nvkms_memset(pParsedEdid, 0, sizeof(*pParsedEdid)); @@ -1991,6 +1998,7 @@ static void CreateParsedEdidFromNVT_TIMING( pParsedEdid->info.u.feature_ver_1_4_digital.continuous_frequency = FALSE; pParsedEdid->info.version = NVT_EDID_VER_1_4; pParsedEdid->info.input.isDigital = TRUE; + pParsedEdid->info.input.u.digital.bpc = bpc; pParsedEdid->limits.min_h_rate_hz = 1; pParsedEdid->limits.min_v_rate_hzx1k = 1; pParsedEdid->limits.max_h_rate_hz = NV_U32_MAX; @@ -2192,7 +2200,7 @@ NVDpyEvoPtr nvAllocDpyEvo(NVDispEvoPtr pDispEvo, pDpyEvo->pDispEvo = pDispEvo; pDpyEvo->pConnectorEvo = pConnectorEvo; - pDpyEvo->head = NV_INVALID_HEAD; + pDpyEvo->apiHead = NV_INVALID_HEAD; pDpyEvo->id = dpyId; nvListAdd(&pDpyEvo->dpyListEntry, &pDispEvo->dpyList); @@ -2428,34 +2436,6 @@ NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, return (pTimings->pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz); } - -/*! - * Return EVO mode timings currently used with the given pDpyEvo. - * - * \param[in] pDpyEvo dpy whose mode timings should be returned. - * - * \return NULL if pDpyEvo is not active. Otherwise, return the mode - * timings programmed in the head that is driving the dpy. - */ -NVHwModeTimingsEvoPtr -nvGetCurrentModeTimingsForDpyEvo(const NVDpyEvoRec *pDpyEvo) -{ - NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - NVDispHeadStateEvoPtr pHeadState = NULL; - const NvU32 head = pDpyEvo->head; - - if (head == NV_INVALID_HEAD) { - return NULL; - } - - pHeadState = &pDispEvo->headState[head]; - - nvAssert(nvDpyIdIsInDpyIdList(pDpyEvo->id, pHeadState->activeDpys)); - - return &pHeadState->timings; -} - - /*! * Return the NVDpyEvoPtr that corresponds to the given dpyId, on the * given NVDispEvoPtr, or NULL if no matching NVDpyEvoPtr can be @@ -2738,9 +2718,10 @@ void nvDpyUpdateCurrentAttributes(NVDpyEvoRec *pDpyEvo) { NVAttributesSetEvoRec newAttributes = pDpyEvo->currentAttributes; - if (pDpyEvo->head != NV_INVALID_HEAD) { + if (pDpyEvo->apiHead != NV_INVALID_HEAD) { + /* XXX[2Heads1OR] attributes should get stored in the api-head state. */ newAttributes = - pDpyEvo->pDispEvo->headState[pDpyEvo->head].attributes; + pDpyEvo->pDispEvo->headState[pDpyEvo->apiHead].attributes; } else { newAttributes.dithering.enabled = FALSE; newAttributes.dithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE; diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 055d5c431..97cdf9243 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -1707,14 +1707,12 @@ void nvChooseCurrentColorSpaceAndRangeEvo( void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( NVDispEvoPtr pDispEvo, const NvU32 head, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = - pHeadState->attributes.colorSpace; - const enum NvKmsDpyAttributeColorRangeValue colorRange = - pHeadState->attributes.colorRange; const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; nvAssert(pConnectorEvo != NULL); @@ -1858,7 +1856,11 @@ void nvSetColorSpaceAndRangeEvo( &pHeadState->attributes.colorRange); /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, pUpdateState); + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, + head, + pHeadState->attributes.colorSpace, + pHeadState->attributes.colorRange, + pUpdateState); } void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, @@ -2974,7 +2976,11 @@ NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val) NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoSubDevPtr pEvoSubDev; - const NvU32 head = pDpyEvo->head; + /* + * XXX[2Heads1OR] Loop over hardware heads to determine if this api-head + * is rasterlocked with any other api-head. + */ + const NvU32 head = pDpyEvo->apiHead; NVEvoHeadControlPtr pHC; if ((head == NV_INVALID_HEAD) || (pDevEvo->gpus == NULL)) { @@ -3136,7 +3142,12 @@ static NvBool UpdateFlipLock50(const NVDpyEvoRec *pDpyEvo, NvU32 *val, NvBool set) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - const NvU32 head = pDpyEvo->head; + /* + * XXX[2Heads1OR] Loop over hardware heads to determine is this api-head + * is rasterlocked with any other api-head and flip lock is not prohibited + * on its corresponding hardware heads. + */ + const NvU32 head = pDpyEvo->apiHead; NVEvoUpdateState updateState = { }; NvBool ret; @@ -3359,18 +3370,6 @@ void nvSetViewPortsEvo(NVDispEvoPtr pDispEvo, NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeViewPortEvo *pViewPort = &pHeadState->timings.viewPort; - // Image sharpening is available when scaling is enabled. - pHeadState->attributes.imageSharpening.available = - (pViewPort->out.width != pViewPort->in.width) || - (pViewPort->out.height != pViewPort->in.height); - - // cache HEAD_SET_CONTROL_OUTPUT_SCALER H/V taps for use in - // SetOutputScaler(). This is needed because SetOutputScaler may be called - // from nvSetImageSharpeningEvo where the NVHwModeViewPortEvo - // isn't as easily accessible. - pHeadState->hTaps = pViewPort->hTaps; - pHeadState->vTaps = pViewPort->vTaps; - nvPushEvoSubDevMaskDisp(pDispEvo); pDevEvo->hal->SetViewportInOut(pDevEvo, head, pViewPort, pViewPort, pViewPort, @@ -4111,8 +4110,6 @@ void nvSetDVCEvo(NVDispEvoPtr pDispEvo, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - pHeadState->attributes.dvc = dvc; - nvAssert(dvc >= NV_EVO_DVC_MIN); nvAssert(dvc <= NV_EVO_DVC_MAX); @@ -4139,9 +4136,6 @@ void nvSetImageSharpeningEvo(NVDispEvoRec *pDispEvo, const NvU32 head, NvU32 value, NVEvoUpdateState *updateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - - pHeadState->attributes.imageSharpening.value = value; /* * Evo values are from -128 to 127, with a default of 0. @@ -5300,13 +5294,23 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, } else if (pConnectorEvo->legacyType == NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) { - /* TMDS default, also acceptable for DSI */ - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - - /* Pick displayport pixel depths for raster timings */ - - if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { - + if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { + switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) { + case 10: + pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; + break; + case 6: + pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; + break; + default: + nvAssert(!"Invalid Pixel Depth for DSI"); + // fall through + case 8: + pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; + break; + } + } else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { + // Pick displayport pixel depths for raster timings. // Start off picking best possible depth based on monitor caps // If the monitor doesn't have an EDID version 1.4 or higher, assume // it's 8. @@ -5319,6 +5323,9 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; } } + } else { + /* TMDS default */ + pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; } } diff --git a/src/nvidia-modeset/src/nvkms-evo2.c b/src/nvidia-modeset/src/nvkms-evo2.c index 3be05733d..b19d49601 100644 --- a/src/nvidia-modeset/src/nvkms-evo2.c +++ b/src/nvidia-modeset/src/nvkms-evo2.c @@ -2008,7 +2008,7 @@ static void EvoFlip90(NVDevEvoPtr pDevEvo, sd, head, pHwState->pSurfaceEvo[NVKMS_LEFT])) { - const struct NvKmsCscMatrix zeroCscMatrix = { 0 }; + const struct NvKmsCscMatrix zeroCscMatrix = { }; nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); EvoPushSetCoreSurfaceMethodsForOneSd(pDevEvo, sd, head, @@ -2768,6 +2768,7 @@ static void EvoSetOutputScaler90(const NVDispEvoRec *pDispEvo, const NvU32 head, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeViewPortEvo *pViewPort = &pHeadState->timings.viewPort; NvU32 setControlOutputScaler = 0; NvU32 vTapsHw = 0, hTapsHw = 0; @@ -2775,7 +2776,7 @@ static void EvoSetOutputScaler90(const NVDispEvoRec *pDispEvo, const NvU32 head, nvAssert(pDevEvo->subDevMaskStackDepth > 0); nvUpdateUpdateState(pDevEvo, updateState, pChannel); - switch (pHeadState->vTaps) { + switch (pViewPort->vTaps) { case NV_EVO_SCALER_5TAPS: vTapsHw = NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5; break; @@ -2793,7 +2794,7 @@ static void EvoSetOutputScaler90(const NVDispEvoRec *pDispEvo, const NvU32 head, vTapsHw = NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1; break; } - switch (pHeadState->hTaps) { + switch (pViewPort->hTaps) { case NV_EVO_SCALER_8TAPS: hTapsHw = NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8; break; @@ -2814,7 +2815,7 @@ static void EvoSetOutputScaler90(const NVDispEvoRec *pDispEvo, const NvU32 head, DRF_NUM(917D, _HEAD_SET_CONTROL_OUTPUT_SCALER, _VERTICAL_TAPS, vTapsHw); - if (pHeadState->attributes.imageSharpening.available) { + if (nvIsImageSharpeningAvailable(&pHeadState->timings.viewPort)) { setControlOutputScaler = FLD_SET_DRF_NUM(917D, _HEAD_SET_CONTROL_OUTPUT_SCALER, _HRESPONSE_BIAS, imageSharpeningValue, @@ -3601,7 +3602,7 @@ static void EvoGetScanLine90(const NVDispEvoRec *pDispEvo, static NvU32 EvoGetActiveViewportOffset94(NVDispEvoRec *pDispEvo, NvU32 head) { - NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS params = {0}; + NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS params = { }; NvU32 ret; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -3626,13 +3627,13 @@ EvoClearSurfaceUsage91(NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo) { NvU32 sd; NvBool kickOff = FALSE; - NVEvoUpdateState updateState = { 0 }; + NVEvoUpdateState updateState = { }; for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { NvU32 head; for (head = 0; head < pDevEvo->numHeads; head++) { - const struct NvKmsCscMatrix zeroCscMatrix = { 0 }; + const struct NvKmsCscMatrix zeroCscMatrix = { }; const NVEvoSubDevHeadStateRec *pSdHeadState = &pDevEvo->gpus[sd].headState[head]; diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index 6cb390ef8..f9501bcf8 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -5176,16 +5176,17 @@ static void EvoSetOutputScalerC3(const NVDispEvoRec *pDispEvo, const NvU32 head, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeViewPortEvo *pViewPort = &pHeadState->timings.viewPort; /* These methods should only apply to a single pDpyEvo */ nvAssert(pDevEvo->subDevMaskStackDepth > 0); nvUpdateUpdateState(pDevEvo, updateState, pChannel); - NvU32 vTaps = pHeadState->vTaps > NV_EVO_SCALER_2TAPS ? + NvU32 vTaps = pViewPort->vTaps > NV_EVO_SCALER_2TAPS ? NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 : NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2; - NvU32 hTaps = pHeadState->hTaps > NV_EVO_SCALER_2TAPS ? + NvU32 hTaps = pViewPort->hTaps > NV_EVO_SCALER_2TAPS ? NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 : NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2; @@ -6675,7 +6676,7 @@ EvoEnableMidFrameAndDWCFWatermarkC5(NVDevEvoPtr pDevEvo, static NvU32 EvoGetActiveViewportOffsetC3(NVDispEvoRec *pDispEvo, NvU32 head) { - NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS params = {0}; + NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS params = { }; NvU32 ret; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index 1f23151a9..78abc04a5 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -1933,6 +1933,7 @@ void nvFlipEvoOneHead( } nvPushEvoSubDevMask(pDevEvo, subDeviceMask); + pDevEvo->hal->Flip(pDevEvo, pDevEvo->head[head].layer[layer], &pFlipState->layer[layer], diff --git a/src/nvidia-modeset/src/nvkms-framelock.c b/src/nvidia-modeset/src/nvkms-framelock.c index e6772f9e7..58a13af98 100644 --- a/src/nvidia-modeset/src/nvkms-framelock.c +++ b/src/nvidia-modeset/src/nvkms-framelock.c @@ -1129,7 +1129,8 @@ static NvBool FrameLockDpyCanBeServer(const NVDpyEvoRec *pDpyEvo) NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS gsyncGetControlSyncParams = { 0 }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVFrameLockEvoPtr pFrameLockEvo = pDispEvo->pFrameLockEvo; - const NvU32 head = pDpyEvo->head; + /* XXX[2Heads1OR] Get the primary hardware head. */ + const NvU32 head = pDpyEvo->apiHead; const NVDispHeadStateEvoRec *pHeadState; NvU32 ret; @@ -2171,7 +2172,8 @@ NvU32 nvGetFramelockServerHead(const NVDispEvoRec *pDispEvo) { const NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, pDispEvo->framelock.server); - return (pDpyEvo != NULL) ? pDpyEvo->head : NV_INVALID_HEAD; + /* XXX[2Heads1OR] Get the primary hardware head. */ + return (pDpyEvo != NULL) ? pDpyEvo->apiHead : NV_INVALID_HEAD; } NvU32 nvGetFramelockClientHeadsMask(const NVDispEvoRec *pDispEvo) @@ -2179,11 +2181,15 @@ NvU32 nvGetFramelockClientHeadsMask(const NVDispEvoRec *pDispEvo) NvU32 headsMask = 0x0; const NVDpyEvoRec *pDpyEvo; + /* + * XXX[2Heads1OR] Translate api-head -> hardware-heads, and make sure to + * include the secondary hardware-head of the server dpy. + */ FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->framelock.clients, pDispEvo) { - if (pDpyEvo->head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { continue; } - headsMask |= NVBIT(pDpyEvo->head); + headsMask |= NVBIT(pDpyEvo->apiHead); } return headsMask; } @@ -2199,7 +2205,8 @@ void nvUpdateGLSFramelock(const NVDispEvoRec *pDispEvo, const NvU32 head, * apiHead -> pDpyEvo mapping will get implemented. */ FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) { - if (pDpyEvo->head != head) { + /* XXX[2Heads1OR] Get the primary hardware head. */ + if (pDpyEvo->apiHead != head) { continue; } diff --git a/src/nvidia-modeset/src/nvkms-hal.c b/src/nvidia-modeset/src/nvkms-hal.c index 9b7934954..6eb3acab5 100644 --- a/src/nvidia-modeset/src/nvkms-hal.c +++ b/src/nvidia-modeset/src/nvkms-hal.c @@ -21,12 +21,13 @@ * DEALINGS IN THE SOFTWARE. */ - #include "nvkms-types.h" #include "nvkms-cursor.h" #include "nvkms-hal.h" #include "nvkms-rm.h" + + #include "class/cl9470.h" // NV9470_DISPLAY #include "class/cl9570.h" // NV9570_DISPLAY #include "class/cl9770.h" // NV9770_DISPLAY @@ -34,6 +35,7 @@ #include "class/clc370.h" // NVC370_DISPLAY #include "class/clc570.h" // NVC570_DISPLAY #include "class/clc670.h" // NVC670_DISPLAY +#include "class/clc770.h" // NVC770_DISPLAY #include "class/cl947d.h" // NV947D_CORE_CHANNEL_DMA #include "class/cl957d.h" // NV957D_CORE_CHANNEL_DMA @@ -45,6 +47,7 @@ #include "class/clc57e.h" // NVC57E_WINDOW_CHANNEL_DMA #include "class/clc67d.h" // NVC67D_CORE_CHANNEL_DMA #include "class/clc67e.h" // NVC67E_WINDOW_CHANNEL_DMA +#include "class/clc77d.h" // NVC67D_CORE_CHANNEL_DMA extern NVEvoHAL nvEvo94; extern NVEvoHAL nvEvoC3; @@ -155,14 +158,14 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) /* NVDisplay and later entries */ -#define ENTRY_NVD(_classPrefix, ...) \ - ENTRY(_classPrefix, __VA_ARGS__, \ +#define ENTRY_NVD(_coreClassPrefix, _windowClassPrefix, ...) \ + ENTRY(_coreClassPrefix, __VA_ARGS__, \ (1 << NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY), \ - DRF_MASK(NV ## _classPrefix ## 7E_SET_PLANAR_STORAGE_PITCH), \ - DRF_MASK(NV ## _classPrefix ## 7E_SET_PLANAR_STORAGE_PITCH) * \ + DRF_MASK(NV ## _windowClassPrefix ## 7E_SET_PLANAR_STORAGE_PITCH), \ + DRF_MASK(NV ## _windowClassPrefix ## 7E_SET_PLANAR_STORAGE_PITCH) * \ NVKMS_BLOCK_LINEAR_GOB_WIDTH, \ - DRF_MASK(NV ## _classPrefix ## 7E_SET_SIZE_IN_WIDTH), \ - DRF_MASK(NV ## _classPrefix ## 7E_SET_SIZE_IN_WIDTH), \ + DRF_MASK(NV ## _windowClassPrefix ## 7E_SET_SIZE_IN_WIDTH), \ + DRF_MASK(NV ## _windowClassPrefix ## 7E_SET_SIZE_IN_WIDTH), \ NVD_CORE_CHANNEL_DMA_ARMED_OFFSET, \ NVD_CORE_CHANNEL_DMA_ARMED_SIZE) @@ -173,22 +176,24 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) const NVEvoCapsRec evoCaps; } dispTable[] = { /* - * genericPageKind--------------------+ - * inputLutAppliesToBase --------+ | - * supportsHDMI20 ------------+ | | - * supportsDP13 -----------+ | | | - * inbandStereoSignaling+ | | | | - * pEvoHal ----------+ | | | | | - * classPrefix | | | | | | - * | | | | | | | + * genericPageKind------------------------+ + * inputLutAppliesToBase ------------+ | + * supportsHDMI20 ----------------+ | | + * supportsDP13 ---------------+ | | | + * inbandStereoSignaling----+ | | | | + * pEvoHal --------------+ | | | | | + * windowClassPrefix | | | | | | + * classPrefix | | | | | | | + * | | | | | | | | */ - ENTRY_NVD(C6, &nvEvoC6, 1, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C5, &nvEvoC5, 1, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C3, &nvEvoC3, 1, 1, 1, 0, FERMI_GENERIC_KIND), - ENTRY_EVO(98, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(97, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(95, &nvEvo94, 1, 0, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(94, &nvEvo94, 1, 0, 0, 1, FERMI_GENERIC_KIND), + ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 1, 0, FERMI_GENERIC_KIND), + ENTRY_EVO(98, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(97, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(95, &nvEvo94, 1, 0, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(94, &nvEvo94, 1, 0, 0, 1, FERMI_GENERIC_KIND), }; int i; diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index 2c3e727a4..c4c375b29 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -928,9 +928,6 @@ void nvHdmiDpConstructHeadAudioState(const NvU32 displayId, } } -#define MAX_AUDIO_DEVICE_ENTRIES \ - (NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 + 1) - /* * Returns audio device entry of connector, which should * be attached to given head. Returns NONE if head is inactive. @@ -955,7 +952,7 @@ static NvU32 GetAudioDeviceEntry(const NVDispEvoRec *pDispEvo, const NvU32 head) return NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE; } - ct_assert(MAX_AUDIO_DEVICE_ENTRIES == NVKMS_MAX_HEADS_PER_DISP); + ct_assert(NV_MAX_AUDIO_DEVICE_ENTRIES == NVKMS_MAX_HEADS_PER_DISP); if (nvConnectorUsesDPLib(pConnectorEvo) && (nvDPGetActiveLinkMode(pConnectorEvo->pDpLibConnector) == @@ -966,66 +963,10 @@ static NvU32 GetAudioDeviceEntry(const NVDispEvoRec *pDispEvo, const NvU32 head) return NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0; } -static NvBool IsAudioDeviceEntryActive( - const NVConnectorEvoRec *pConnectorEvo, const NvU32 deviceEntry) -{ - NvU32 primaryOrIndex; - NvU32 head, headsCount = 0; - NvBool isInMSTMode, isConnectorActive; - - if ((pConnectorEvo->or.mask == 0x0) || - (deviceEntry >= MAX_AUDIO_DEVICE_ENTRIES)) { - return FALSE; - } - - primaryOrIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); - - isInMSTMode = FALSE; - isConnectorActive = FALSE; - - FOR_EACH_INDEX_IN_MASK( - 32, - head, - pConnectorEvo->or.ownerHeadMask[primaryOrIndex]) { - - const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NVDpyEvoRec *pDpyEvo = nvGetOneArbitraryDpyEvo( - pHeadState->activeDpys, pDispEvo); - - if (headsCount == 0) { - isInMSTMode = nvDpyEvoIsDPMST(pDpyEvo); - } else { - nvAssert(isInMSTMode == nvDpyEvoIsDPMST(pDpyEvo)); - } - headsCount++; - isConnectorActive = TRUE; - } FOR_EACH_INDEX_IN_MASK_END - - if (!isConnectorActive) { - return FALSE; - } - - nvAssert(isInMSTMode || headsCount == 1); - - if (isInMSTMode) { - return (NVBIT(deviceEntry) & - pConnectorEvo->or.ownerHeadMask[primaryOrIndex]) ? TRUE : FALSE; - } else if (!isInMSTMode && deviceEntry == 0) { - return TRUE; - } - - return FALSE; -} - /*! * Send EDID-Like-Data (ELD) to RM. * - * The ELD contains a subset of the digital display device's EDID - * information related to audio capabilities. The GPU driver sends the - * ELD to hardware and the audio driver reads it by issuing the ELD - * command verb. The ELD should be updated under the following - * situations: + * ELD should be updated under the following situations: * * 1. Power on reset * 2. Pre modeset @@ -1042,6 +983,15 @@ static NvBool IsAudioDeviceEntryActive( * NV_ELD_PRE_MODESET : isPD = 1, isELDV = 0 * NV_ELD_POST_MODESET : isPD = 1, isELDV = 1 * + * The initial ELD case of each audio device entry in hardware is unknown. + * Fortunately, NVConnectorEvoRec::audioDevEldCase[] is zero-initialized, + * which means each audioDevEldCase[] array element will have initial + * value NV_ELD_PRE_MODESET=0. + * + * That ensures that nvRemoveUnusedHdmiDpAudioDevice(), during + * the first modeset, will reset all unused audio device entries to + * NV_ELD_POWER_ON_RESET. + * * \param[in] pDispEvo The disp of the displayId * \param[in] displayId The display device whose ELD should be updated. * This should be NVDispHeadStateEvoRec::activeRmId @@ -1054,14 +1004,11 @@ static NvBool IsAudioDeviceEntryActive( * extracted. * \param[in] eldCase The condition that requires updating the ELD. */ -typedef enum { - NV_ELD_POWER_ON_RESET, - NV_ELD_PRE_MODESET, - NV_ELD_POST_MODESET, -} NvEldCase; static void RmSetELDAudioCaps( - const NVDispEvoRec *pDispEvo, const NvU32 displayId, + const NVDispEvoRec *pDispEvo, + NVConnectorEvoRec *pConnectorEvo, + const NvU32 displayId, const NvU32 deviceEntry, const NvU32 maxFreqSupported, const NVEldEvoRec *pEld, const NvEldCase eldCase) @@ -1072,6 +1019,8 @@ static void RmSetELDAudioCaps( NvBool isPD, isELDV; NvU32 ret; + pConnectorEvo->audioDevEldCase[deviceEntry] = eldCase; + /* setup the ctrl flag */ switch(eldCase) { case NV_ELD_POWER_ON_RESET : @@ -1154,7 +1103,7 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, const NvU32 head, const NvBool enable) { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; const NvU32 deviceEntry = GetAudioDeviceEntry(pDispEvo, head); /* @@ -1173,6 +1122,7 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, if (enable) { /* Make sure to remove corresponding audio device */ RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, nvDpyIdToNvU32(pConnectorEvo->displayId), deviceEntry, 0 /* maxFreqSupported */, @@ -1188,6 +1138,7 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, /* Invalidate ELD buffer before disabling audio */ if (!enable) { RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, pHeadState->activeRmId, deviceEntry, 0 /* maxFreqSupported */, @@ -1206,6 +1157,7 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, /* Populate ELD buffer after enabling audio */ if (enable) { RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, pHeadState->activeRmId, deviceEntry, pHeadState->audio.maxFreqSupported, @@ -1235,7 +1187,7 @@ void nvDpyUpdateHdmiVRRCaps(NVDpyEvoPtr pDpyEvo) void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) { - const NVConnectorEvoRec *pConnectorEvo; + NVConnectorEvoRec *pConnectorEvo; const NvU32 activeSorMask = nvGetActiveSorMask(pDispEvo); FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { @@ -1258,14 +1210,24 @@ void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) } for (deviceEntry = 0; - deviceEntry < MAX_AUDIO_DEVICE_ENTRIES; + deviceEntry < NV_MAX_AUDIO_DEVICE_ENTRIES; deviceEntry++) { - if (IsAudioDeviceEntryActive(pConnectorEvo, deviceEntry)) { + /* + * Skip if the audio device is enabled (ELD case is set to + * NV_ELD_POST_MODESET by nvHdmiDpEnableDisableAudio()), or if the + * audio device is already disabled (ELD case is set to + * NV_ELD_POWER_ON_RESET). + */ + if ((pConnectorEvo->audioDevEldCase[deviceEntry] == + NV_ELD_POST_MODESET) || + (pConnectorEvo->audioDevEldCase[deviceEntry] == + NV_ELD_POWER_ON_RESET)) { continue; } RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, nvDpyIdToNvU32(pConnectorEvo->displayId), deviceEntry, 0 /* maxFreqSupported */, @@ -2114,10 +2076,4 @@ void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head) "HDMI FRL link training retried %d times.", retries); } - - nvAssert(pHeadState->attributes.digitalSignal == - NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_TMDS); - - pHeadState->attributes.digitalSignal = - NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL; } diff --git a/src/nvidia-modeset/src/nvkms-modeset.c b/src/nvidia-modeset/src/nvkms-modeset.c index 2c956537b..0ba1b8885 100644 --- a/src/nvidia-modeset/src/nvkms-modeset.c +++ b/src/nvidia-modeset/src/nvkms-modeset.c @@ -276,15 +276,15 @@ GetColorSpaceAndColorRange( nvChooseCurrentColorSpaceAndRangeEvo(&pProposedHead->timings, requestedColorSpace, requestedColorRange, - &pProposedHead->colorSpace, - &pProposedHead->colorRange); + &pProposedHead->attributes.colorSpace, + &pProposedHead->attributes.colorRange); /* * When colorspace is specified in modeset request, it should * match the proposed colorspace. */ if (pRequestHead->colorSpaceSpecified) { NvBool ret = FALSE; - switch (pProposedHead->colorSpace) { + switch (pProposedHead->attributes.colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: ret = (pRequestHead->colorSpace == NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB); @@ -310,7 +310,7 @@ GetColorSpaceAndColorRange( * match the proposed color range. */ if (pRequestHead->colorRangeSpecified && - (pProposedHead->colorRange != pRequestHead->colorRange)) { + (pProposedHead->attributes.colorRange != pRequestHead->colorRange)) { return FALSE; } @@ -381,8 +381,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; pProposedHead->modeValidationParams = pHeadState->modeValidationParams; - pProposedHead->colorSpace = pHeadState->attributes.colorSpace; - pProposedHead->colorRange = pHeadState->attributes.colorRange; + pProposedHead->attributes = pHeadState->attributes; pProposedHead->changed = FALSE; pProposedHead->hs10bpcHint = pHeadState->hs10bpcHint; pProposedHead->audio = pHeadState->audio; @@ -518,6 +517,31 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, continue; } + pProposedHead->attributes.digitalSignal = + nvGetDefaultDpyAttributeDigitalSignalValue(pProposedHead->pConnectorEvo); + if (pProposedHead->timings.hdmiFrlConfig.frlRate != + HDMI_FRL_DATA_RATE_NONE) { + nvAssert(pProposedHead->attributes.digitalSignal == + NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_TMDS); + pProposedHead->attributes.digitalSignal = + NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL; + } + + { + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, + pDispEvo); + + pProposedHead->attributes.dvc = + pDpyEvo->currentAttributes.dvc; + + /* Image sharpening is available when scaling is enabled. */ + pProposedHead->attributes.imageSharpening.available = + nvIsImageSharpeningAvailable(&pProposedHead->timings.viewPort); + pProposedHead->attributes.imageSharpening.value = + pDpyEvo->currentAttributes.imageSharpening.value; + } + /* * modesetOwnerChanged implies that there was a modeset * ownership change since the last modeset. If input/output lut not @@ -833,7 +857,7 @@ static NvBool DowngradeDpPixelDepth( if ((pProposedHead->pConnectorEvo == pConnectorEvo) && nvDowngradeHwModeTimingsDpPixelDepthEvo( pTimings, - pProposedHead->colorSpace)) { + pProposedHead->attributes.colorSpace)) { return TRUE; } } @@ -879,7 +903,7 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( head, pProposedHead->activeRmId, pProposedHead->dpyIdList, - pProposedHead->colorSpace, + pProposedHead->attributes.colorSpace, &pProposedHead->modeValidationParams, pTimings); @@ -921,7 +945,7 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( head, pProposedHead->activeRmId, pProposedHead->dpyIdList, - pProposedHead->colorSpace, + pProposedHead->attributes.colorSpace, &pProposedHead->timings); if (pProposedHead->pDpLibModesetState == NULL) { return FALSE; @@ -932,7 +956,35 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( return bResult; } +static void VBlankCallbackDeferredWork(void *dataPtr, NvU32 data32) +{ + NVVBlankCallbackPtr pVBlankCallbackTmp = NULL; + NVVBlankCallbackPtr pVBlankCallback = NULL; + NVDispEvoPtr pDispEvo = dataPtr; + NvU32 head = data32; + if (!nvHeadIsActive(pDispEvo, head)) { + return; + } + + nvListForEachEntry_safe(pVBlankCallback, + pVBlankCallbackTmp, + &pDispEvo->headState[head].vblankCallbackList, + vblankCallbackListEntry) { + pVBlankCallback->pCallback(pDispEvo, head, pVBlankCallback); + } +} + +static void VBlankCallback(void *pParam1, void *pParam2) +{ + const NvU32 head = (NvU32)(NvUPtr)pParam2; + + (void) nvkms_alloc_timer_with_ref_ptr( + VBlankCallbackDeferredWork, + pParam1, /* ref_ptr to pDispEvo */ + head, /* dataU32 */ + 0); /* timeout: schedule the work immediately */ +} /*! * Validate the proposed configuration on the specified disp. @@ -1415,7 +1467,7 @@ ApplyProposedModeSetHwStateOneHeadShutDown( nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, sizeof(pDevEvo->gpus[sd].headState[head])); - pDpyEvo->head = NV_INVALID_HEAD; + pDpyEvo->apiHead = NV_INVALID_HEAD; } static void @@ -1532,7 +1584,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( return; } - pDpyEvo->head = head; + pDpyEvo->apiHead = nvHardwareHeadToApiHead(head); AssignSor(pWorkArea, pProposedHead->pConnectorEvo); @@ -1583,9 +1635,11 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( nvEvoHeadSetControlOR(pDispEvo, head, updateState); /* Update hardware's current colorSpace and colorRange */ - pHeadState->attributes.colorSpace = pProposedHead->colorSpace; - pHeadState->attributes.colorRange = pProposedHead->colorRange; - nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, updateState); + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, + head, + pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorRange, + updateState); nvEvoAttachConnector(pProposedHead->pConnectorEvo, head, @@ -1597,18 +1651,15 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( nvSetImageSharpeningEvo( pDispEvo, head, - pDpyEvo->currentAttributes.imageSharpening.value, + pProposedHead->attributes.imageSharpening.value, updateState); nvSetDVCEvo(pDispEvo, head, - pDpyEvo->currentAttributes.dvc, + pProposedHead->attributes.dvc, updateState); - pHeadState->attributes.digitalSignal = - nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); - /* If required, nvHdmiFrlSetConfig() overrides attributes.digitalSignal */ nvHdmiFrlSetConfig(pDispEvo, head); /* @@ -1617,6 +1668,16 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( */ ReenableActiveCoreRGSyncObjects(pDispEvo->pDevEvo, pHeadState, head, updateState); + + pHeadState->attributes.digitalSignal = + pProposedHead->attributes.digitalSignal; + pHeadState->attributes.dvc = pProposedHead->attributes.dvc; + pHeadState->attributes.imageSharpening.available = + pProposedHead->attributes.imageSharpening.available; + pHeadState->attributes.imageSharpening.value = + pProposedHead->attributes.imageSharpening.value; + pHeadState->attributes.colorSpace = pProposedHead->attributes.colorSpace; + pHeadState->attributes.colorRange = pProposedHead->attributes.colorRange; } @@ -2625,6 +2686,71 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, return ret; } +/*! + * Register a callback to activate when vblank is reached on a given head. + * + * \param[in,out] pDispEvo The display engine to register the callback on. + * \param[in] head The head to register the callback on. + * \param[in] pCallback The function to call when vblank is reached on the + * provided pDispEvo+head combination. + * \param[in] pUserData A pointer to caller-provided custom data. + * + * \return Returns a pointer to a NVVBlankCallbackRec structure if the + * registration was successful. Otherwise, return NULL. + */ +NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, + NvU32 head, + NVVBlankCallbackProc pCallback, + void *pUserData) +{ + NVVBlankCallbackPtr pVBlankCallback = NULL; + + pVBlankCallback = nvCalloc(1, sizeof(*pVBlankCallback)); + if (pVBlankCallback == NULL) { + return NULL; + } + + pVBlankCallback->pCallback = pCallback; + pVBlankCallback->pUserData = pUserData; + + nvListAppend(&pVBlankCallback->vblankCallbackListEntry, + &pDispEvo->headState[head].vblankCallbackList); + + // If this is the first entry in the list, register the vblank callback + if (pDispEvo->headState[head].rmVBlankCallbackHandle == 0) { + + pDispEvo->headState[head].rmVBlankCallbackHandle = + nvRmAddVBlankCallback(pDispEvo, + head, + VBlankCallback); + } + return pVBlankCallback; +} + +/*! + * Un-register a vblank callback for a given head. + * + * \param[in,out] pDispEvo The display engine to register the callback on. + * \param[in] head The head to register the callback on. + * \param[in] pCallback A pointer to the NVVBlankCallbackRec to un-register. + * + */ +void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + NvU32 head, + NVVBlankCallbackPtr pCallback) +{ + nvListDel(&pCallback->vblankCallbackListEntry); + nvFree(pCallback); + + // If there are no more callbacks, disable the RM-level callback + if (nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)) { + nvRmRemoveVBlankCallback(pDispEvo, + pDispEvo->headState[head].rmVBlankCallbackHandle); + + pDispEvo->headState[head].rmVBlankCallbackHandle = 0; + } +} + /*! * Perform a modeset that disables some or all heads. * diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 2f1036536..206c90df3 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -238,6 +238,7 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) for (head = 0; head < ARRAY_LEN(pDispEvo->pSwapGroup); head++) { nvAssert(pDispEvo->pSwapGroup[head] == NULL); + nvAssert(nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)); } nvAssert(nvListIsEmpty(&pDispEvo->dpyList)); @@ -269,6 +270,7 @@ static inline NVDispEvoPtr AllocDisplay(NVDevEvoPtr pDevEvo) for (head = 0; head < ARRAY_LEN(pDispEvo->headState); head++) { pDispEvo->headState[head].activeDpys = nvEmptyDpyIdList(); pDispEvo->headState[head].attributes = NV_EVO_DEFAULT_ATTRIBUTES_SET; + nvListInit(&pDispEvo->headState[head].vblankCallbackList); } pDispEvo->ref_ptr = nvkms_alloc_ref_ptr(pDispEvo); @@ -1035,10 +1037,10 @@ static void MarkConnectorBootHeadActive(NVDispEvoPtr pDispEvo, NvU32 head) pHeadState = &pDispEvo->headState[head]; - nvAssert(pDpyEvo->head == NV_INVALID_HEAD); + nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); nvAssert(!nvHeadIsActive(pDispEvo, head)); - pDpyEvo->head = head; + pDpyEvo->apiHead = nvHardwareHeadToApiHead(head); pHeadState->activeDpys = nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index 3d78bb200..95f353865 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -504,6 +504,7 @@ void nvEvoRegisterSurface(NVDevEvoPtr pDevEvo, } pSurfaceEvo->requireCtxDma = !pRequest->noDisplayHardwareAccess; + pSurfaceEvo->noDisplayCaching = pRequest->noDisplayCaching; /* * Map the first plane of the surface only into the CPU's address space. diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index 31fadd312..c3a4f96a8 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -110,6 +110,15 @@ enum NvKmsPerOpenType { NvKmsPerOpenTypeUndefined, }; +enum NvKmsUnicastEventType { + /* Used by: + * NVKMS_IOCTL_JOIN_SWAP_GROUP */ + NvKmsUnicastEventTypeDeferredRequest, + + /* Undefined, this indicates the unicast fd is available for use. */ + NvKmsUnicastEventTypeUndefined, +}; + struct NvKmsPerOpenConnector { NVConnectorEvoPtr pConnectorEvo; NvKmsConnectorHandle nvKmsApiHandle; @@ -183,13 +192,13 @@ struct NvKmsPerOpen { * that object can generate events on the unicast event. Store a * pointer to that object, so that we can clear the pointer when the * unicast event NvKmsPerOpen is closed. - * - * So far, deferred request fifos with swap groups are the only - * users of unicast events. When we add more users, we can add an - * enum or similar to know which object type is using this unicast - * event. */ - NVDeferredRequestFifoPtr pDeferredRequestFifo; + enum NvKmsUnicastEventType type; + union { + struct { + NVDeferredRequestFifoPtr pDeferredRequestFifo; + } deferred; + } e; } unicastEvent; }; }; @@ -3701,6 +3710,17 @@ static const char *ProcFsPerOpenTypeString( return "unknown"; } +static const char *ProcFsUnicastEventTypeString( + enum NvKmsUnicastEventType type) +{ + switch (type) { + case NvKmsUnicastEventTypeDeferredRequest: return "DeferredRequest"; + case NvKmsUnicastEventTypeUndefined: return "undefined"; + } + + return "unknown"; +} + static const char *ProcFsPerOpenClientTypeString( enum NvKmsClientType clientType) { @@ -3851,10 +3871,18 @@ ProcFsPrintClients( pOpen->grantSwapGroup.pSwapGroup); } else if (pOpen->type == NvKmsPerOpenTypeUnicastEvent) { - nvEvoLogInfoString(&infoString, - " pDeferredRequestFifo : %p", - pOpen->unicastEvent.pDeferredRequestFifo); + " unicastEvent type : %s", + ProcFsUnicastEventTypeString(pOpen->unicastEvent.type)); + switch(pOpen->unicastEvent.type) { + case NvKmsUnicastEventTypeDeferredRequest: + nvEvoLogInfoString(&infoString, + " pDeferredRequestFifo : %p", + pOpen->unicastEvent.e.deferred.pDeferredRequestFifo); + break; + default: + break; + } } nvEvoLogInfoString(&infoString, ""); @@ -4612,6 +4640,7 @@ void nvSendUnicastEvent(struct NvKmsPerOpen *pOpen) } nvAssert(pOpen->type == NvKmsPerOpenTypeUnicastEvent); + nvAssert(pOpen->unicastEvent.type != NvKmsUnicastEventTypeUndefined); nvkms_event_queue_changed(pOpen->pOpenKernel, TRUE); } @@ -4626,12 +4655,21 @@ void nvRemoveUnicastEvent(struct NvKmsPerOpen *pOpen) nvAssert(pOpen->type == NvKmsPerOpenTypeUnicastEvent); - pDeferredRequestFifo = pOpen->unicastEvent.pDeferredRequestFifo; + switch(pOpen->unicastEvent.type) + { + case NvKmsUnicastEventTypeDeferredRequest: + pDeferredRequestFifo = + pOpen->unicastEvent.e.deferred.pDeferredRequestFifo; - if (pDeferredRequestFifo != NULL) { - pDeferredRequestFifo->swapGroup.pOpenUnicastEvent = NULL; - pOpen->unicastEvent.pDeferredRequestFifo = NULL; + pDeferredRequestFifo->swapGroup.pOpenUnicastEvent = NULL; + pOpen->unicastEvent.e.deferred.pDeferredRequestFifo = NULL; + break; + default: + nvAssert("Invalid Unicast Event Type!"); + break; } + + pOpen->unicastEvent.type = NvKmsUnicastEventTypeUndefined; } static void AllocSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo) diff --git a/src/nvidia-modeset/srcs.mk b/src/nvidia-modeset/srcs.mk index 8754b4455..bb3a9df77 100644 --- a/src/nvidia-modeset/srcs.mk +++ b/src/nvidia-modeset/srcs.mk @@ -124,6 +124,7 @@ SRCS += ../common/modeset/hdmipacket/nvhdmipkt_9471.c SRCS += ../common/modeset/hdmipacket/nvhdmipkt_9571.c SRCS += ../common/modeset/hdmipacket/nvhdmipkt_C371.c SRCS += ../common/modeset/hdmipacket/nvhdmipkt_C671.c +SRCS += ../common/modeset/hdmipacket/nvhdmipkt_C771.c SRCS += ../common/modeset/timing/nvt_cvt.c SRCS += ../common/modeset/timing/nvt_displayid20.c SRCS += ../common/modeset/timing/nvt_dmt.c diff --git a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h index 2a1c5bbb1..c43cbb22d 100644 --- a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h +++ b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h @@ -130,6 +130,7 @@ typedef NvU8 FLCN_STATUS; // because that will affect other binaries and their signatures // #define FLCN_ERR_CTXSW_ERROR (0x4EU) +#define FLCN_ERR_SE_SNPKA_HW_CRYPTO_OPERATION_FAILED (0x4FU) // VPR SEC2 task errors #define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U) @@ -232,6 +233,8 @@ typedef NvU8 FLCN_STATUS; #define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU) #define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU) #define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U) +#define FLCN_ERR_HS_INVALID_KEY (0xD1U) +#define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE (0xD2U) // @@ -283,4 +286,7 @@ typedef NvU8 FLCN_STATUS; #define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U) #define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U) +// Arithmetic errors +#define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU) + #endif // FLCNRETVAL_H diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h b/src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h new file mode 100644 index 000000000..fa117aaed --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * @file nvdm_payload_cmd_response.h + * @brief Header file containing the definition for the + * NVDM_PAYLOAD_COMMAND_RESPONSE structure, which + * is required for SMBPBI-specific payloads and needs + * to be visible by bothe the PMU and the driver sides. + */ + +#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H +#define _NVDM_PAYLOAD_CMD_RESPONSE_H + +#pragma pack(1) +typedef struct +{ + NvU32 taskId; + NvU32 commandNvdmType; + NvU32 errorCode; +} NVDM_PAYLOAD_COMMAND_RESPONSE; +#pragma pack() + +#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h new file mode 100644 index 000000000..eea7cfc2c --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSPIFPUB_H +#define GSPIFPUB_H + +#include + +/*! + * @file gspifpub.h + * @brief GSP Command/Message Interfaces - Published + */ + +/*! + * Target physical memory apertures supported for DMA + */ +typedef enum { + GSP_DMA_TARGET_LOCAL_FB, + GSP_DMA_TARGET_COHERENT_SYSTEM, + GSP_DMA_TARGET_NONCOHERENT_SYSTEM, + GSP_DMA_TARGET_COUNT +} GSP_DMA_TARGET; + +/*! + * @brief GSP-CC Microcode Initialization Parameters + */ +typedef struct GSP_CC_INIT_PARAMS +{ + // CC initialization "registry keys" + NvU32 regkeys; +} GSP_CC_INIT_PARAMS; + +/*! + * @brief GSP-ACR BOOT_GSP_RM Command Parameters + * + * The wprCarveout fields have no effect in environments where the WPR can be allocated + * implicitly by ACR. + */ +typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS +{ + // Physical memory aperture through which gspRmDescPa is accessed + GSP_DMA_TARGET target; + // Size in bytes of the GSP-RM descriptor structure + NvU32 gspRmDescSize; + // Physical offset in the target aperture of the GSP-RM descriptor structure + NvU64 gspRmDescOffset; + // Physical offset in FB to set the start of the WPR containing GSP-RM + NvU64 wprCarveoutOffset; + // Size in bytes of the WPR containing GSP-RM + NvU32 wprCarveoutSize; +} GSP_ACR_BOOT_GSP_RM_PARAMS; + +/*! + * @brief GSP-RM Parameters + */ +typedef struct GSP_RM_PARAMS +{ + // Physical memory aperture through which bootArgsPa is accessed + GSP_DMA_TARGET target; + // Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1) + NvU64 bootArgsOffset; +} GSP_RM_PARAMS; + +/*! + * @brief GSP-CC Microcode Parameters for Boot Partitions + */ +typedef struct GSP_CC_BOOT_PARAMS +{ + GSP_CC_INIT_PARAMS initParams; + GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; + GSP_RM_PARAMS gspRmParams; +} GSP_CC_BOOT_PARAMS; + +#endif // GSPIFPUB_H diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index 66a1c2643..1e2942f0a 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -61,6 +61,7 @@ CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc) CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc) CHIPSET_SETUP_FUNC(Intel_A301_setupFunc) CHIPSET_SETUP_FUNC(Intel_0685_setupFunc) +CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc) CHIPSET_SETUP_FUNC(Intel_4381_setupFunc) CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc) CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc) @@ -177,13 +178,13 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc}, {PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc}, - {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL}, + {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", Intel_IceLake_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, - {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL}, + {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", Intel_IceLake_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, @@ -196,7 +197,8 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, - + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc}, @@ -313,6 +315,8 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0 {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1 {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2 + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0 + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1 {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm" {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2 diff --git a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h index b4b65ed0a..41dcbf8ef 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h @@ -625,6 +625,7 @@ enum { , CS_NVIDIA_T186 , CS_NVIDIA_T194 , CS_NVIDIA_T234 +, CS_NVIDIA_T23x , CS_MARVELL_THUNDERX2 , CS_REDHAT_QEMU , CS_AMPERE_EMAG diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index b8410f667..546e12e4f 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -96,6 +96,8 @@ #define NV_MSGBOX_CMD_OPCODE_RESERVED_0 0x00000024 #define NV_MSGBOX_CMD_OPCODE_RESERVED_1 0x00000025 #define NV_MSGBOX_CMD_OPCODE_GET_POWER_HINT_INFO 0x00000026 +#define NV_MSGBOX_CMD_OPCODE_DYNAMIC_SYSTEM_INFORMATION 0x00000027 +#define NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING 0x00000028 #define NV_MSGBOX_CMD_ARG1 15:8 #define NV_MSGBOX_CMD_ARG1_NULL 0x00000000 @@ -105,7 +107,8 @@ #define NV_MSGBOX_CMD_ARG1_TEMP_BOARD 0x00000004 #define NV_MSGBOX_CMD_ARG1_TEMP_MEMORY 0x00000005 #define NV_MSGBOX_CMD_ARG1_TEMP_PWR_SUPPLY 0x00000006 -#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 7 +#define NV_MSGBOX_CMD_ARG1_TEMP_T_LIMIT 0x00000007 +#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8 #define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 #define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 /* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ @@ -318,6 +321,33 @@ #define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_NUM \ (NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES + 1) +// Arg1 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION 15:14 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_INSTANTANEOUS_METRIC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_SNAPSHOT_METRIC 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_CAPTURE_SNAPSHOT 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_SET_MULTIPLIER 0x00000003 + +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC 13:8 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_GRAPHICS_ENGINE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_ACTIVITY 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_OCCUPANCY 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_TENSOR_CORE_ACTIVITY 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP64_ACTIVITY 0x00000005 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP32_ACTIVITY 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP16_ACTIVITY 0x00000007 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH 0x0000000A +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH 0x0000000B +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH 0x0000000C +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH 0x0000000D +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010 + +#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000 #define NV_MSGBOX_CMD_ARG2 23:16 #define NV_MSGBOX_CMD_ARG2_NULL 0x00000000 @@ -409,6 +439,17 @@ #define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_TOTAL_PAGES \ (NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1) +// Arg2 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION 23:16 +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF + +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_2X 0x00000002 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_5X 0x00000005 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_10X 0x0000000A +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_100X 0x00000064 + #define NV_MSGBOX_CMD_STATUS 28:24 #define NV_MSGBOX_CMD_STATUS_NULL 0x00000000 @@ -502,6 +543,22 @@ */ #define NV_MSGBOX_CMD_NVLINK_INFO_GET_NVLINK_INFO_AVAILABILTY_PAGE_0 0x00000000 +/** + * This field is populated as response to the following metrics: + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH + */ +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY 2:0 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_B 0x00000000 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_KIB 0x00000001 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_MIB 0x00000002 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_GIB 0x00000003 + /* MSGBOX data, capability dword structure */ #define NV_MSGBOX_DATA_REG 31:0 @@ -526,6 +583,9 @@ #define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY 6:6 #define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT 7:7 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS 11:8 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ZERO 0x00000000 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002 @@ -759,9 +819,15 @@ #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11 #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001 -#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22 -#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000 -#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1 23:23 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001 /* ECC counters */ #define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 @@ -1194,6 +1260,8 @@ #define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_NOT_AVAILABLE 0 #define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_AVAILABLE 1 +#define NV_MSGBOX_DATA_DYN_SYS_INFO_SIZE_DRIVER_VERSION 64 + /* Event types */ typedef enum { @@ -1944,6 +2012,27 @@ typedef struct // new param starting from here. } NV_MSGBOX_POWER_HINT_PARAMS; +/*! + * @brief Union of all possible parameter struct. Used to determine the maximum + * amount of space parameter blocks can take. + */ +typedef union { + NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS tgpLimitControl; + NV_MSGBOX_THERMAL_FAN_V1_COUNT_PARAMS fanCountV1Get; + NV_MSGBOX_THERMAL_FAN_V1_INFO_PARAMS fanCountV1Info; + NV_MSGBOX_THERMAL_FAN_V1_STATUS_PARAMS fanCountV1Status; + NV_MSGBOX_OVERCLOCKING_LIMIT_CONTROL_PARAMS overclockingLimitControl; + NV_MSGBOX_ENERGY_COUNTER_STATUS_PARAMS energyCounterStatus; + NV_MSGBOX_VIOLATION_COUNTERS_STATUS_PARAMS violationCountersStatus; + NV_MSGBOX_UTILIZATION_RATE_PARAMS utilizationRate; + NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS oobClockLimitCtrlParams; + NV_MSGBOX_DEVICE_MODE_CONTROL_PARAMS deviceModeControlParams; + NV_MSGBOX_TEST_MESSAGE_SEND_PARAMS testMessageSend; + NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS clockLimitGet; + NV_MSGBOX_THERMAL_FAN_V3_FAN_CURVE_POINTS_PARAMS fanCurvePointsV3; + NV_MSGBOX_POWER_HINT_PARAMS powerHintParams; +} NV_MSGBOX_ASYNC_REQ_PARAMS_UNION; + #endif // !NV_MSGBOX_NO_PARAM_STRUCTS /* Utility command constructor macros */ @@ -2348,9 +2437,24 @@ typedef struct DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ADDR) \ ) -#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \ - ( \ - FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \ +#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \ + ( \ + FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \ + ) + +#define NV_MSGBOX_CMD_GPM_GET_METRIC(type, metric, partition) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \ + ) + +#define NV_MSGBOX_CMD_GPM_SET_INTERVAL(interval) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_INTERVAL) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_INTERVAL, (interval)) \ ) #define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd)) diff --git a/src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h b/src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h index 155371ed1..22a4c8826 100644 --- a/src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h +++ b/src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h @@ -37,8 +37,9 @@ typedef struct { // // Version 1 // Version 2 - // Vesrion 3 = for Partition boot - // Vesrion 4 = for eb riscv boot + // Version 3 = for Partition boot + // Version 4 = for eb riscv boot + // Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later. // NvU32 version; // structure version NvU32 bootloaderOffset; @@ -75,6 +76,14 @@ typedef struct { // NvU32 swbromDataOffset; NvU32 swbromDataSize; + // + // Total size of FB carveout (image and reserved space). + // + NvU32 fbReservedSize; + // + // Indicates whether the entire RISC-V image is signed as "code" in code section. + // + NvU32 bSignedAsCode; } RM_RISCV_UCODE_DESC; #endif // RM_RISCV_UCODE_H diff --git a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h index d7c17f85e..62b9c44f4 100644 --- a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h +++ b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h @@ -488,6 +488,11 @@ typedef struct _def_acr_reserved_dmem #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1 +// Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status. +#define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55 +#define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA +#define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00 + /*! * Size of ACR phase in dword */ diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 96324c7a2..ea85afeb6 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -281,6 +281,7 @@ typedef struct nv_usermap_access_params_s NvU64 access_size; NvU64 remap_prot_extra; NvBool contig; + NvU32 caching; } nv_usermap_access_params_t; /* @@ -298,6 +299,7 @@ typedef struct nv_alloc_mapping_context_s { NvU64 remap_prot_extra; NvU32 prot; NvBool valid; + NvU32 caching; } nv_alloc_mapping_context_t; typedef enum @@ -326,6 +328,9 @@ typedef struct nv_soc_irq_info_s { #define NV_MAX_DPAUX_NUM_DEVICES 4 #define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING +#define NV_IGPU_LEGACY_STALL_IRQ 70 +#define NV_IGPU_MAX_STALL_IRQS 3 +#define NV_IGPU_MAX_NONSTALL_IRQS 1 /* * per device state */ @@ -362,6 +367,7 @@ typedef struct nv_state_t nv_aperture_t *hdacodec_regs; nv_aperture_t *mipical_regs; nv_aperture_t *fb, ud; + nv_aperture_t *simregs; NvU32 num_dpaux_instance; NvU32 interrupt_line; @@ -374,6 +380,11 @@ typedef struct nv_state_t NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; + NvU32 igpu_nonstall_irq; + NvU32 num_stall_irqs; + NvU64 dma_mask; + NvBool primary_vga; NvU32 sim_env; @@ -451,6 +462,9 @@ typedef struct nv_state_t NvBool printed_openrm_enable_unsupported_gpus_error; + /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ + NvBool nvpcf_dsm_in_gpu_scope; + } nv_state_t; // These define need to be in sync with defines in system.h @@ -515,7 +529,7 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64); #define NV_FLAG_USES_MSIX 0x0040 #define NV_FLAG_PASSTHRU 0x0080 #define NV_FLAG_SUSPENDED 0x0100 -// Unused 0x0200 +#define NV_FLAG_SOC_IGPU 0x0200 // Unused 0x0400 #define NV_FLAG_PERSISTENT_SW_STATE 0x0800 #define NV_FLAG_IN_RECOVERY 0x1000 @@ -564,6 +578,9 @@ typedef enum #define NV_IS_SOC_DISPLAY_DEVICE(nv) \ ((nv)->flags & NV_FLAG_SOC_DISPLAY) +#define NV_IS_SOC_IGPU_DEVICE(nv) \ + ((nv)->flags & NV_FLAG_SOC_IGPU) + #define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) @@ -782,7 +799,7 @@ void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); -NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -961,7 +978,7 @@ void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 **, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 96b1a1d16..0aaf20521 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -125,6 +125,7 @@ NvU32 NV_API_CALL os_get_cpu_number (void); void NV_API_CALL os_disable_console_access (void); void NV_API_CALL os_enable_console_access (void); NV_STATUS NV_API_CALL os_registry_init (void); +NvU64 NV_API_CALL os_get_max_user_va (void); NV_STATUS NV_API_CALL os_schedule (void); NV_STATUS NV_API_CALL os_alloc_spinlock (void **); void NV_API_CALL os_free_spinlock (void *); @@ -193,6 +194,13 @@ void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *); int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int); void NV_API_CALL os_nv_cap_close_fd (int); +enum os_pci_req_atomics_type { + OS_INTF_PCIE_REQ_ATOMICS_32BIT, + OS_INTF_PCIE_REQ_ATOMICS_64BIT, + OS_INTF_PCIE_REQ_ATOMICS_128BIT +}; +NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); + extern NvU32 os_page_size; extern NvU64 os_page_mask; extern NvU8 os_page_shift; diff --git a/src/nvidia/arch/nvalloc/unix/include/osapi.h b/src/nvidia/arch/nvalloc/unix/include/osapi.h index 2b15d1efe..484351ec8 100644 --- a/src/nvidia/arch/nvalloc/unix/include/osapi.h +++ b/src/nvidia/arch/nvalloc/unix/include/osapi.h @@ -144,7 +144,7 @@ NV_STATUS rm_free_os_event (NvHandle, NvU32); NV_STATUS rm_get_event_data (nv_file_private_t *, NvP64, NvU32 *); void rm_client_free_os_events (NvHandle); -NV_STATUS rm_create_mmap_context (nv_state_t *, NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32); +NV_STATUS rm_create_mmap_context (nv_state_t *, NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32); NV_STATUS rm_update_device_mapping_info (NvHandle, NvHandle, NvHandle, void *, void *); NV_STATUS rm_access_registry (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *); diff --git a/src/nvidia/arch/nvalloc/unix/src/escape.c b/src/nvidia/arch/nvalloc/unix/src/escape.c index 7b173675f..585fe50f6 100644 --- a/src/nvidia/arch/nvalloc/unix/src/escape.c +++ b/src/nvidia/arch/nvalloc/unix/src/escape.c @@ -285,6 +285,7 @@ NV_STATUS RmIoctl( if (rm_create_mmap_context(nv, pParms->hRoot, pParms->hObjectParent, pParms->hObjectNew, pParms->pMemory, pParms->limit + 1, 0, + NV_MEMORY_DEFAULT, pApi->fd) != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -457,6 +458,8 @@ NV_STATUS RmIoctl( goto done; } + // Don't allow userspace to override the caching type + pParms->flags = FLD_SET_DRF(OS33, _FLAGS, _CACHING_TYPE, _DEFAULT, pParms->flags); Nv04MapMemoryWithSecInfo(pParms, secInfo); if (pParms->status == NV_OK) @@ -464,7 +467,9 @@ NV_STATUS RmIoctl( pParms->status = rm_create_mmap_context(nv, pParms->hClient, pParms->hDevice, pParms->hMemory, pParms->pLinearAddress, pParms->length, - pParms->offset, pApi->fd); + pParms->offset, + DRF_VAL(OS33, _FLAGS, _CACHING_TYPE, pParms->flags), + pApi->fd); if (pParms->status != NV_OK) { NVOS34_PARAMETERS params; diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c index 25398d464..da473ca29 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c @@ -75,7 +75,8 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( const NvU8 *pMdevUuid, NvU32 vgpuTypeId, NvU16 *vgpuId, - NvU32 gpuPciBdf + NvU32 gpuPciBdf, + NvBool *is_driver_vm ) { return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index 04a4fb439..eae8c433c 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -718,6 +718,11 @@ void osSpinLoop(void) { } +NvU64 osGetMaxUserVa(void) +{ + return os_get_max_user_va(); +} + NV_STATUS osSchedule(void) { return os_schedule(); @@ -3497,17 +3502,14 @@ osRemoveGpuSupported * - All address values are in the System Physical Address (SPA) space * - Targets can either be "Local" (bIsPeer=False) or for a specified "Peer" * (bIsPeer=True, peerIndex=#) GPU - * - Granularity of the target address space is returned as a bit shift value - * (e.g. granularity=37 implies a granularity of 128GiB) * - Target address and mask values have a specified bit width, and represent * the higher order bits above the target address granularity * * @param[in] pGpu GPU object pointer - * @param[out] pAddrSysPhys Pointer to hold SPA aligned at 128GB boundary + * @param[out] pAddrSysPhys Pointer to hold SPA * @param[out] pAddrWidth Address range width value pointer * @param[out] pMask Mask value pointer * @param[out] pMaskWidth Mask width value pointer - * @param[out] pGranularity Granularity value pointer * @param[in] bIsPeer NV_TRUE if this is a peer, local GPU otherwise * @param[in] peerIndex Peer index * @@ -3520,11 +3522,10 @@ NV_STATUS osGetAtsTargetAddressRange ( OBJGPU *pGpu, - NvU32 *pAddrSysPhys, + NvU64 *pAddrSysPhys, NvU32 *pAddrWidth, NvU32 *pMask, NvU32 *pMaskWidth, - NvU32 *pGranularity, NvBool bIsPeer, NvU32 peerIndex ) @@ -3548,27 +3549,21 @@ osGetAtsTargetAddressRange if (bIsPeer) { const int addrWidth = 0x10; - const NvU32 guestAddrGranularity = 37; *pAddrSysPhys = 0; *pAddrWidth = addrWidth; *pMask = 0; *pMaskWidth = addrMaskWidth; - *pGranularity = guestAddrGranularity; return NV_OK; } else { - NvU64 addrSysPhys; - - NV_STATUS status = nv_get_device_memory_config(nv, &addrSysPhys, NULL, - pAddrWidth, pGranularity, NULL); + NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL, + pAddrWidth, NULL); if (status == NV_OK) { *pMask = NVBIT(*pAddrWidth) - 1U; *pMaskWidth = addrMaskWidth; - - *pAddrSysPhys = addrSysPhys >> *pGranularity; } return status; } @@ -3615,7 +3610,7 @@ osGetFbNumaInfo nv = NV_GET_NV_STATE(pGpu); - NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, NULL, pNodeId); + NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, pNodeId); return status; #endif @@ -3901,7 +3896,7 @@ osNumaOnliningEnabled // Note that this numaNodeId value fetched from Linux layer might not be // accurate since it is possible to overwrite it with regkey on some configs // - if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, NULL, + if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, &numaNodeId) != NV_OK) { return NV_FALSE; @@ -4959,6 +4954,51 @@ osGetSyncpointAperture return NV_ERR_NOT_SUPPORTED; } +/*! + * @brief Enable PCIe AtomicOp Requester Enable and return + * the completer side capabilities that the requester can send. + * + * @param[in] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[out] pMask mask of supported atomic size, including one or more of: + * OS_PCIE_CAP_MASK_REQ_ATOMICS_32 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_64 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_128 + * + * @returns NV_STATUS, NV_OK if success + * NV_ERR_NOT_SUPPORTED if platform doesn't support this + * feature. + * NV_ERR_GENERIC for any other error + */ + +NV_STATUS +osConfigurePcieReqAtomics +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pMask +) +{ + if (pMask) + { + *pMask = 0U; + if (pOsGpuInfo) + { + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_32BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_32; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_64BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_64; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_128BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_128; + + if (*pMask != 0) + return NV_OK; + } + } + return NV_ERR_NOT_SUPPORTED; +} + /*! * @brief Check GPU is accessible or not * diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index b832852d4..dbe3a6cdf 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -1843,6 +1843,7 @@ static NV_STATUS RmCreateMmapContextLocked( NvP64 address, NvU64 size, NvU64 offset, + NvU32 cachingType, NvU32 fd ) { @@ -1884,6 +1885,7 @@ static NV_STATUS RmCreateMmapContextLocked( nvuap->addr = addr; nvuap->size = size; nvuap->offset = offset; + nvuap->caching = cachingType; // // Assume the allocation is contiguous until RmGetMmapPteArray @@ -1975,6 +1977,7 @@ NV_STATUS rm_create_mmap_context( NvP64 address, NvU64 size, NvU64 offset, + NvU32 cachingType, NvU32 fd ) { @@ -1995,7 +1998,7 @@ NV_STATUS rm_create_mmap_context( else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK) { rmStatus = RmCreateMmapContextLocked(hClient, hDevice, hMemory, - address, size, offset, fd); + address, size, offset, cachingType, fd); // UNLOCK: release GPUs lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); } @@ -3364,13 +3367,29 @@ static NV_STATUS RmNonDPAuxI2CTransfer break; case NV_I2C_CMD_SMBUS_WRITE: - params->transData.smbusByteData.bWrite = NV_TRUE; + if (len == 2) + { + params->transData.smbusWordData.bWrite = NV_TRUE; + } + else + { + params->transData.smbusByteData.bWrite = NV_TRUE; + } /* fall through*/ case NV_I2C_CMD_SMBUS_READ: - params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; - params->transData.smbusByteData.message = pData[0]; - params->transData.smbusByteData.registerAddress = command; + if (len == 2) + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW; + params->transData.smbusWordData.message = pData[0] | ((NvU16)pData[1] << 8); + params->transData.smbusWordData.registerAddress = command; + } + else + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; + params->transData.smbusByteData.message = pData[0]; + params->transData.smbusByteData.registerAddress = command; + } break; case NV_I2C_CMD_SMBUS_BLOCK_WRITE: @@ -3408,7 +3427,15 @@ static NV_STATUS RmNonDPAuxI2CTransfer // if (rmStatus == NV_OK && type == NV_I2C_CMD_SMBUS_READ) { - pData[0] = params->transData.smbusByteData.message; + if (len == 2) + { + pData[0] = (params->transData.smbusWordData.message & 0xff); + pData[1] = params->transData.smbusWordData.message >> 8; + } + else + { + pData[0] = params->transData.smbusByteData.message; + } } portMemFree(params); diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 77eac6c14..304a65335 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -58,6 +58,7 @@ #include #include #include +#include #include @@ -637,6 +638,15 @@ osInitNvMapping( sysApplyLockingPolicy(pSys); pGpu->busInfo.IntLine = nv->interrupt_line; + + // + // Set the DMA address size as soon as we have the HAL to call to + // determine the precise number of physical address bits supported + // by the architecture. DMA allocations should not be made before + // this point. + // + nv_set_dma_address_size(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)); + pGpu->dmaStartAddress = (RmPhysAddr)nv_get_dma_start_address(nv); if (nv->fb != NULL) { @@ -725,15 +735,6 @@ osTeardownScalability( return clTeardownPcie(pGpu, pCl); } -static inline void -RmSetDeviceDmaAddressSize( - nv_state_t *nv, - NvU8 numDmaAddressBits -) -{ - nv_set_dma_address_size(nv, numDmaAddressBits); -} - static void populateDeviceAttributes( OBJGPU *pGpu, @@ -883,8 +884,6 @@ RmInitNvDevice( return; } - RmSetDeviceDmaAddressSize(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)); - os_disable_console_access(); status->rmStatus = gpumgrStateInitGpu(pGpu); @@ -1188,7 +1187,7 @@ NvBool RmInitPrivateState( // Set up a reasonable default DMA address size, based on the minimum // possible on currently supported GPUs. // - RmSetDeviceDmaAddressSize(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + nv_set_dma_address_size(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); os_mem_set(nvp, 0, sizeof(*nvp)); nvp->status = NV_ERR_INVALID_STATE; @@ -1582,7 +1581,7 @@ NvBool RmInitAdapter( // if (nv->request_firmware) { - RmSetDeviceDmaAddressSize(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_GSP, &gspFw.pBuf, @@ -1655,6 +1654,17 @@ NvBool RmInitAdapter( goto shutdown; } + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + if ((pKernelFsp != NULL) && !IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu)) + { + status.rmStatus = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n"); + goto shutdown; + } + } + RmSetConsolePreservationParams(pGpu); // @@ -1830,7 +1840,7 @@ NvBool RmInitAdapter( RmInitS0ixPowerManagement(nv); RmInitDeferredDynamicPowerManagement(nv); - if (!NV_IS_SOC_DISPLAY_DEVICE(nv)) + if (!NV_IS_SOC_DISPLAY_DEVICE(nv) && !NV_IS_SOC_IGPU_DEVICE(nv)) { status.rmStatus = RmRegisterGpudb(pGpu); if (status.rmStatus != NV_OK) diff --git a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c index 1f41a7637..2d597a149 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c +++ b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c @@ -534,6 +534,27 @@ static void NV_API_CALL rm_nvlink_ops_training_complete NV_EXIT_RM_RUNTIME(sp, fp); } +static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK * pLink = link->link_info; + nvidia_stack_t * sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreAliTrainingCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + return status; +} + #endif /* defined(INCLUDE_NVLINK_LIB) */ const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) @@ -560,6 +581,7 @@ const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) .read_discovery_token = rm_nvlink_ops_read_link_discovery_token, .training_complete = rm_nvlink_ops_training_complete, .get_uphy_load = rm_nvlink_get_uphy_load, + .ali_training = rm_nvlink_ops_ali_training, }; return &rm_nvlink_link_ops; @@ -647,7 +669,7 @@ osGetPlatformNvlinkLinerate ) { #if defined(NVCPU_PPC64LE) - nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); if (!pKernelNvlink) diff --git a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c index f350bd1eb..d542393dc 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c +++ b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -396,12 +396,13 @@ NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *sp, gpuAddressSpaceHandle srcVaSpace, NvU64 srcAddress, gpuAddressSpaceHandle dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress) { NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstAddress); + rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstVaAlignment, dstAddress); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; } diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 69da2d394..b05249ba1 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -339,6 +339,7 @@ void osEnableInterrupts(OBJGPU *pGpu) intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); } } + } } diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 608e490ec..9f60568d5 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -31,7 +31,6 @@ * */ - #if defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) #include // NV01_ROOT @@ -75,14 +74,17 @@ #include // VOLTA_CHANNEL_GPFIFO_A #include // TURING_CHANNEL_GPFIFO_A #include // AMPERE_CHANNEL_GPFIFO_A +#include // HOPPER_CHANNEL_GPFIFO_A #include // NV04_SOFTWARE_TEST #include // VOLTA_USERMODE_A #include // TURING_USERMODE_A #include // AMPERE_USERMODE_A +#include // HOPPER_USERMODE_A #include // NVC371_DISP_SF_USER #include // NVC372_DISPLAY_SW #include // NVC573_DISP_CAPABILITIES #include // NVC673_DISP_CAPABILITIES +#include // NVC773_DISP_CAPABILITIES #include // NV04_DISPLAY_COMMON #include // NV50_DEFERRED_API_CLASS #include // MPS_COMPUTE @@ -97,6 +99,9 @@ #include // NVC67B_WINDOW_IMM_CHANNEL_DMA #include // NVC67D_CORE_CHANNEL_DMA #include // NVC67E_WINDOW_CHANNEL_DMA +#include // NVC770_DISPLAY +#include // NVC771_DISP_SF_USER +#include // NVC77D_CORE_CHANNEL_DMA #include // NV9010_VBLANK_CALLBACK #include // GF100_PROFILER #include // MAXWELL_PROFILER @@ -112,15 +117,22 @@ #include // FERMI_TWOD_A #include // FERMI_VASPACE_A #include // GF100_HDACODEC +#include // NVB8B0_VIDEO_DECODER #include // NVC4B0_VIDEO_DECODER #include // NVC6B0_VIDEO_DECODER #include // NVC7B0_VIDEO_DECODER +#include // NVC9B0_VIDEO_DECODER #include // NVC4B7_VIDEO_ENCODER #include // NVB4B7_VIDEO_ENCODER #include // NVC7B7_VIDEO_ENCODER +#include // NVC9B7_VIDEO_ENCODER +#include // NVB8D1_VIDEO_NVJPG #include // NVC4D1_VIDEO_NVJPG +#include // NVC9D1_VIDEO_NVJPG +#include // NVB8FA_VIDEO_OFA #include // NVC6FA_VIDEO_OFA #include // NVC7FA_VIDEO_OFA +#include // NVC9FA_VIDEO_OFA #include // KEPLER_INLINE_TO_MEMORY_B #include // FERMI_CONTEXT_SHARE_A #include // KEPLER_CHANNEL_GROUP_A @@ -128,6 +140,7 @@ #include // TURING_DMA_COPY_A #include // AMPERE_DMA_COPY_A #include // AMPERE_DMA_COPY_B +#include // HOPPER_DMA_COPY_A #include // MAXWELL_DMA_COPY_A #include // ACCESS_COUNTER_NOTIFY_BUFFER #include // MMU_FAULT_BUFFER @@ -137,20 +150,27 @@ #include // AMPERE_COMPUTE_A #include // AMPERE_B #include // AMPERE_COMPUTE_B +#include // ADA_A +#include // ADA_COMPUTE_A #include // AMPERE_SMC_PARTITION_REF #include // AMPERE_SMC_EXEC_PARTITION_REF #include // AMPERE_SMC_CONFIG_SESSION #include // NV0092_RG_LINE_CALLBACK #include // AMPERE_SMC_MONITOR_SESSION +#include // HOPPER_A +#include // HOPPER_COMPUTE_A #include // NV40_DEBUG_BUFFER #include // GT200_DEBUGGER #include // NV40_I2C #include // NV0060_SYNC_GPU_BOOST #include // GP100_UVM_SW #include // NV_EVENT_BUFFER +#include // NV_COUNTER_COLLECTION_UNIT + #else // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) + #ifndef NV01_ROOT #define NV01_ROOT (0x00000000) #endif @@ -378,6 +398,10 @@ #define AMPERE_CHANNEL_GPFIFO_A (0x0000c56f) #endif +#ifndef HOPPER_CHANNEL_GPFIFO_A +#define HOPPER_CHANNEL_GPFIFO_A (0x0000c86f) +#endif + #ifndef NV04_SOFTWARE_TEST #define NV04_SOFTWARE_TEST (0x0000007d) #endif @@ -397,6 +421,10 @@ #define AMPERE_USERMODE_A (0x0000c561) #endif +#ifndef HOPPER_USERMODE_A +#define HOPPER_USERMODE_A (0x0000c661) +#endif + #ifndef NVC371_DISP_SF_USER #define NVC371_DISP_SF_USER (0x0000c371) #endif @@ -413,6 +441,10 @@ #define NVC673_DISP_CAPABILITIES (0x0000c673) #endif +#ifndef NVC773_DISP_CAPABILITIES +#define NVC773_DISP_CAPABILITIES (0x0000c773) +#endif + #ifndef NV04_DISPLAY_COMMON #define NV04_DISPLAY_COMMON (0x00000073) #endif @@ -469,6 +501,18 @@ #define NVC67E_WINDOW_CHANNEL_DMA (0x0000c67e) #endif +#ifndef NVC770_DISPLAY +#define NVC770_DISPLAY (0x0000c770) +#endif + +#ifndef NVC771_DISP_SF_USER +#define NVC771_DISP_SF_USER (0x0000c771) +#endif + +#ifndef NVC77D_CORE_CHANNEL_DMA +#define NVC77D_CORE_CHANNEL_DMA (0x0000c77d) +#endif + #ifndef NV9010_VBLANK_CALLBACK #define NV9010_VBLANK_CALLBACK (0x00009010) #endif @@ -529,6 +573,10 @@ #define GF100_HDACODEC (0x000090ec) #endif +#ifndef NVB8B0_VIDEO_DECODER +#define NVB8B0_VIDEO_DECODER (0x0000b8b0) +#endif + #ifndef NVC4B0_VIDEO_DECODER #define NVC4B0_VIDEO_DECODER (0x0000c4b0) #endif @@ -541,6 +589,10 @@ #define NVC7B0_VIDEO_DECODER (0x0000c7b0) #endif +#ifndef NVC9B0_VIDEO_DECODER +#define NVC9B0_VIDEO_DECODER (0x0000c9b0) +#endif + #ifndef NVC4B7_VIDEO_ENCODER #define NVC4B7_VIDEO_ENCODER (0x0000c4b7) #endif @@ -553,10 +605,26 @@ #define NVC7B7_VIDEO_ENCODER (0x0000c7b7) #endif +#ifndef NVC9B7_VIDEO_ENCODER +#define NVC9B7_VIDEO_ENCODER (0x0000c9b7) +#endif + +#ifndef NVB8D1_VIDEO_NVJPG +#define NVB8D1_VIDEO_NVJPG (0x0000b8d1) +#endif + #ifndef NVC4D1_VIDEO_NVJPG #define NVC4D1_VIDEO_NVJPG (0x0000c4d1) #endif +#ifndef NVC9D1_VIDEO_NVJPG +#define NVC9D1_VIDEO_NVJPG (0x0000c9d1) +#endif + +#ifndef NVB8FA_VIDEO_OFA +#define NVB8FA_VIDEO_OFA (0x0000b8fa) +#endif + #ifndef NVC6FA_VIDEO_OFA #define NVC6FA_VIDEO_OFA (0x0000c6fa) #endif @@ -565,6 +633,10 @@ #define NVC7FA_VIDEO_OFA (0x0000c7fa) #endif +#ifndef NVC9FA_VIDEO_OFA +#define NVC9FA_VIDEO_OFA (0x0000c9fa) +#endif + #ifndef KEPLER_INLINE_TO_MEMORY_B #define KEPLER_INLINE_TO_MEMORY_B (0x0000a140) #endif @@ -593,6 +665,10 @@ #define AMPERE_DMA_COPY_B (0x0000c7b5) #endif +#ifndef HOPPER_DMA_COPY_A +#define HOPPER_DMA_COPY_A (0x0000c8b5) +#endif + #ifndef MAXWELL_DMA_COPY_A #define MAXWELL_DMA_COPY_A (0x0000b0b5) #endif @@ -629,6 +705,14 @@ #define AMPERE_COMPUTE_B (0x0000c7c0) #endif +#ifndef ADA_A +#define ADA_A (0x0000c997) +#endif + +#ifndef ADA_COMPUTE_A +#define ADA_COMPUTE_A (0x0000c9c0) +#endif + #ifndef AMPERE_SMC_PARTITION_REF #define AMPERE_SMC_PARTITION_REF (0x0000c637) #endif @@ -649,6 +733,14 @@ #define AMPERE_SMC_MONITOR_SESSION (0x0000c640) #endif +#ifndef HOPPER_A +#define HOPPER_A (0x0000cb97) +#endif + +#ifndef HOPPER_COMPUTE_A +#define HOPPER_COMPUTE_A (0x0000cbc0) +#endif + #ifndef NV40_DEBUG_BUFFER #define NV40_DEBUG_BUFFER (0x000000db) #endif @@ -673,4 +765,9 @@ #define NV_EVENT_BUFFER (0x000090cd) #endif +#ifndef NV_COUNTER_COLLECTION_UNIT +#define NV_COUNTER_COLLECTION_UNIT (0x0000cbca) +#endif + + #endif // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index dac58964e..adc1a985d 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -54,14 +54,20 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" #undef BINDATA_INCLUDE_STORAGE_PVT_DECL @@ -76,14 +82,20 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" #undef BINDATA_INCLUDE_DATA @@ -96,14 +108,20 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt = #include "g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" #undef BINDATA_INCLUDE_STORAGE_PVT_DEFN @@ -119,14 +137,20 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE #include "g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" +#include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" +#include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" #undef BINDATA_INCLUDE_FUNCTION diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c new file mode 100644 index 000000000..ca422b91b --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -0,0 +1,3242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("image_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_dbg.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_data_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 33024 +// COMPRESSED SIZE (bytes): 22004 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = +{ + 0xed, 0xdc, 0x73, 0xac, 0xac, 0xcd, 0x03, 0x27, 0xf8, 0x63, 0xdb, 0xbe, 0xc7, 0xb6, 0x6d, 0xdb, + 0xb6, 0x6d, 0xdb, 0xb6, 0xcf, 0x3d, 0xb6, 0x6d, 0xdb, 0xb6, 0xee, 0xb1, 0x6d, 0x6b, 0xde, 0x99, + 0xf9, 0x4d, 0x66, 0xf2, 0xee, 0xce, 0x3f, 0xbb, 0x9b, 0x6c, 0xb2, 0x7b, 0x3f, 0xc9, 0xb7, 0xeb, + 0xa9, 0xea, 0x4a, 0xaa, 0xbb, 0xba, 0xeb, 0x49, 0x9e, 0xee, 0xea, 0x06, 0x00, 0xf8, 0xff, 0x37, + 0x6b, 0x0c, 0xb6, 0x91, 0xc6, 0x4f, 0x81, 0xe6, 0x55, 0x10, 0xbe, 0x4d, 0xe4, 0x8e, 0x90, 0xbd, + 0x1c, 0x3c, 0x16, 0xa1, 0xe3, 0xfb, 0x3f, 0x62, 0x58, 0x45, 0x4e, 0x8c, 0x04, 0x9b, 0x12, 0xe6, + 0x5c, 0x04, 0xd9, 0xe3, 0x35, 0x3e, 0x4e, 0xd1, 0x21, 0xb6, 0xe1, 0xca, 0xb1, 0x92, 0xb7, 0xed, + 0xfe, 0x85, 0x8f, 0xf6, 0x78, 0x9d, 0xbe, 0x54, 0x97, 0x86, 0x03, 0x62, 0xaf, 0x99, 0x6f, 0x9d, + 0xc7, 0x9d, 0x29, 0xa3, 0x31, 0x54, 0x21, 0xed, 0x90, 0x55, 0xde, 0xa9, 0xd6, 0x57, 0xe4, 0x1b, + 0xad, 0x1b, 0x42, 0x16, 0xd8, 0x49, 0xcc, 0x01, 0x90, 0x75, 0xa1, 0xbc, 0xf5, 0xd5, 0xd8, 0x9e, + 0xeb, 0xa5, 0x05, 0x0a, 0xe7, 0x43, 0x55, 0xc7, 0x07, 0x97, 0xda, 0x42, 0x5c, 0x89, 0xe8, 0x7a, + 0x56, 0xc3, 0x9d, 0xc7, 0x90, 0x1a, 0xb7, 0x02, 0x60, 0x1c, 0xd2, 0x03, 0x91, 0xb3, 0x8b, 0xbe, + 0xb2, 0xfb, 0xc4, 0xf0, 0x22, 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0xb5, 0x78, 0xe4, 0xd6, 0x36, 0x58, 0x91, 0x65, 0x6a, 0x4b, 0x48, 0x07, 0x1f, 0x94, 0xe4, + 0xf3, 0x09, 0x06, 0xbf, 0x3b, 0x30, 0x4c, 0x45, 0xf5, 0xc6, 0x20, 0xb7, 0xff, 0xaf, 0xd7, 0xff, + 0xdf, 0xfe, 0xff, 0xd9, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, + 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, + 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, 0xaf, 0xbf, 0xfe, 0xfa, 0xeb, + 0xaf, 0xbf, 0xfe, 0xfa, 0xbf, 0xa2, 0x8b, 0x1c, 0x00, 0x00, 0xe8, 0x9f, 0x12, 0xf0, 0x3f, 0x19, + 0x20, 0xff, 0x9f, 0xc7, 0xff, 0x35, 0x23, 0xe4, 0xff, 0xbd, 0xdf, 0xff, 0xa8, 0x03, 0x20, 0x79, + 0xfe, 0xb7, 0x52, 0x56, 0x55, 0x51, 0x56, 0x0c, 0xdf, 0xc4, 0xd6, 0xcc, 0xc2, 0xd6, 0xe4, 0x9f, + 0x8a, 0xbc, 0x94, 0xc0, 0x7f, 0x2a, 0xf8, 0x5a, 0x8a, 0x4a, 0x02, 0xf8, 0x36, 0x76, 0xc6, 0x26, + 0x3a, 0xff, 0x6a, 0x17, 0x11, 0x12, 0xfa, 0x4f, 0xfb, 0x3f, 0xd8, 0xc9, 0xfe, 0xb9, 0xf9, 0x27, + 0x0c, 0xff, 0x14, 0xf8, 0xff, 0x0f, 0x3f, 0x27, 0x98, 0x7f, 0x82, 0xfe, 0x4f, 0x08, 0xfe, 0x89, + 0xc8, 0x3f, 0x63, 0x20, 0xfc, 0x13, 0xfa, 0x7f, 0x8e, 0x81, 0x00, 0xff, 0xcf, 0xfb, 0x53, 0xfe, + 0xdf, 0x18, 0x0b, 0x0d, 0xe0, 0xbf, 0x3f, 0x7e, 0x9d, 0xff, 0x65, 0x1c, 0x10, 0x88, 0xff, 0x7d, + 0xff, 0xb4, 0xff, 0xe5, 0x38, 0xfd, 0x9f, 0x64, 0xfc, 0x13, 0xb1, 0x7f, 0x22, 0xfe, 0x4f, 0x24, + 0xfe, 0x89, 0xe4, 0x7f, 0xee, 0x93, 0xfe, 0x4f, 0x29, 0xf3, 0xaf, 0x71, 0xf0, 0xff, 0x33, 0xce, + 0x7f, 0x9d, 0xbb, 0xff, 0xf6, 0x1a, 0x00, 0xfc, 0x33, 0xc5, 0x00, 0x4a, 0x22, 0xf4, 0x00, 0x42, + 0xff, 0x4c, 0xaf, 0x81, 0xa3, 0x85, 0xb3, 0xb9, 0x8d, 0x89, 0xb3, 0x85, 0x11, 0xbe, 0x89, 0xa3, + 0xa3, 0x9d, 0x23, 0xd4, 0xff, 0xa6, 0xf5, 0xaf, 0xff, 0xe1, 0xbf, 0x00, 0x1c, 0x01, 0x52, 0x4f, + 0x00, 0x81, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 33024, // uncompressed data size (bytes) + 22004, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("header_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_dbg.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_header_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("image_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_prod.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_data_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 33024 +// COMPRESSED SIZE (bytes): 22000 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_prod_data[] = +{ + 0xed, 0xfc, 0x73, 0xac, 0xec, 0x41, 0xc3, 0x07, 0x78, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, + 0x7b, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x3d, 0xb6, 0xe7, 0x99, 0x99, 0x77, + 0x32, 0x93, 0x67, 0x77, 0xfe, 0xd9, 0xdd, 0x64, 0x93, 0xdd, 0xfb, 0x49, 0xbe, 0x5d, 0xe8, 0x4a, + 0xaa, 0xbb, 0x3a, 0xbf, 0x4a, 0xba, 0xbb, 0xba, 0x01, 0x00, 0xfe, 0xff, 0x9b, 0xf0, 0xc5, 0x07, + 0x5c, 0x24, 0x76, 0xe4, 0xac, 0x50, 0x78, 0x29, 0x30, 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0xb4, 0xff, 0x4b, 0x3d, 0xfd, + 0x3f, 0xc9, 0xf8, 0x4f, 0xc4, 0xff, 0x13, 0x89, 0xff, 0x44, 0xf2, 0x3f, 0x91, 0xfa, 0x9f, 0xfb, + 0x64, 0xfe, 0xa7, 0x94, 0xfd, 0xaf, 0x79, 0x08, 0xfe, 0x67, 0x9e, 0xff, 0x75, 0xed, 0xfe, 0xb7, + 0xd7, 0x00, 0xe0, 0x3f, 0x4b, 0x0c, 0xa0, 0x2c, 0xca, 0x00, 0x20, 0xfc, 0x9f, 0xe5, 0x35, 0x70, + 0xb4, 0x70, 0x36, 0xb7, 0x31, 0x71, 0xb6, 0x30, 0x22, 0x30, 0x71, 0x74, 0xb4, 0x73, 0x84, 0xfa, + 0xbf, 0xe9, 0xfd, 0xe7, 0xff, 0xf0, 0xbf, 0x00, 0xff, 0xbb, 0x69, 0x24, 0x00, 0x81, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 33024, // uncompressed data size (bytes) + 22000, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("header_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_prod.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_header_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_prod_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_header_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("sig_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_load_sig_dbg_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x6c, 0x0e, 0x43, 0x32, 0x75, 0x20, 0x86, 0x2c, 0x6c, 0xe5, 0x3a, + 0xeb, 0xc9, 0x91, 0x96, 0xd9, 0x07, 0x15, 0x0b, 0xd1, 0xea, 0xb6, 0xce, 0xa1, 0xf1, 0xb5, 0x86, + 0xa3, 0xed, 0x0f, 0x98, 0x17, 0x94, 0x87, 0x76, 0x53, 0x4d, 0x75, 0x04, 0x00, 0xb3, 0xa7, 0x66, + 0xfe, 0x50, 0x95, 0xdb, 0x32, 0xed, 0x05, 0x04, 0x50, 0xa1, 0x47, 0x84, 0xfc, 0xd7, 0xa7, 0xea, + 0x69, 0xa3, 0xcf, 0xca, 0x0b, 0xea, 0x2a, 0xfc, 0x3b, 0x4a, 0xb9, 0xca, 0xbd, 0xa7, 0xa8, 0x1b, + 0x16, 0xcf, 0x6f, 0x4b, 0xd5, 0x4e, 0x89, 0x25, 0xb2, 0x20, 0xfb, 0xad, 0x29, 0x35, 0xd3, 0xcb, + 0xb6, 0x73, 0x6d, 0x96, 0xb3, 0x83, 0xc9, 0x9a, 0x62, 0x3f, 0xe5, 0x1e, 0x70, 0xf2, 0x9f, 0xdb, + 0xb3, 0x56, 0x1c, 0x25, 0x7f, 0xde, 0xf4, 0x05, 0xc5, 0xa3, 0x4f, 0x18, 0x64, 0x8e, 0xdf, 0xcd, + 0x7f, 0x2d, 0x44, 0x55, 0x10, 0x44, 0x27, 0x05, 0x9b, 0x0a, 0xa7, 0x64, 0x40, 0x29, 0xa5, 0xb7, + 0xff, 0x21, 0xe1, 0x83, 0xfd, 0x9b, 0xc9, 0xbf, 0x15, 0xe5, 0xdb, 0xf4, 0xdb, 0x5e, 0x32, 0xc7, + 0xff, 0x57, 0x37, 0x0d, 0x19, 0xd1, 0xa7, 0x15, 0xee, 0x72, 0x10, 0xca, 0x90, 0x71, 0xf0, 0xa8, + 0x96, 0x5c, 0x0d, 0xb5, 0xdc, 0x42, 0x76, 0x2b, 0xb0, 0x86, 0x2c, 0xba, 0x58, 0x80, 0xb3, 0xcf, + 0x30, 0xfd, 0x0a, 0x8a, 0xea, 0x55, 0xef, 0xac, 0x2b, 0xd7, 0x6f, 0x73, 0xd5, 0xaa, 0x71, 0x2e, + 0xcb, 0x24, 0x27, 0x31, 0x4e, 0xfd, 0xbb, 0xf5, 0x4c, 0xa2, 0x15, 0x53, 0x9b, 0x54, 0x19, 0x95, + 0x4e, 0x86, 0x0c, 0xf5, 0x95, 0x3f, 0x24, 0x95, 0xd2, 0x5e, 0xc2, 0xed, 0x7e, 0xab, 0x0f, 0x8e, + 0xc4, 0x87, 0xbf, 0x77, 0x33, 0xfa, 0x95, 0x05, 0x9b, 0x2f, 0x05, 0xcd, 0xe0, 0xf8, 0xf3, 0x8f, + 0x1a, 0xf4, 0xe3, 0x80, 0x32, 0x3e, 0x20, 0xbc, 0x61, 0x67, 0xb1, 0xf7, 0x77, 0xe3, 0x66, 0xf5, + 0xac, 0x99, 0xf4, 0xb6, 0x20, 0x66, 0x82, 0x99, 0x74, 0x79, 0x1a, 0xe8, 0x80, 0xac, 0xe5, 0x66, + 0x43, 0x3c, 0x6a, 0xb2, 0xea, 0xcb, 0xe0, 0xf7, 0x76, 0xa4, 0x15, 0xba, 0x28, 0x88, 0x74, 0xd1, + 0xa7, 0xea, 0xf5, 0x56, 0x60, 0x8a, 0xdb, 0xe4, 0x31, 0xae, 0xb1, 0xff, 0x40, 0x1a, 0xf4, 0x7a, + 0xf0, 0x2c, 0x33, 0x83, 0x35, 0x23, 0x8c, 0x73, 0xb4, 0x24, 0xb2, 0x0a, 0x35, 0xec, 0xc3, 0x9a, + 0x9f, 0x06, 0x7c, 0xf6, 0x49, 0x9a, 0x6b, 0xbc, 0x31, 0xa5, 0x3c, 0xc8, 0x4e, 0x3b, 0x18, 0x93, + 0x2a, 0x3d, 0xd1, 0x5e, 0x52, 0x96, 0x22, 0x4e, 0x73, 0xc3, 0x1b, 0x56, 0xb6, 0x8d, 0x1d, 0xcf, + 0x78, 0xd5, 0x21, 0x32, 0x94, 0x19, 0x6f, 0xeb, 0x71, 0x69, 0x24, 0x93, 0xc6, 0xeb, 0x1c, 0x45, + 0x8d, 0xf8, 0x06, 0xd2, 0x1a, 0xbb, 0x4a, 0x4e, 0x3b, 0xb0, 0x66, 0x44, 0xb3, 0x0b, 0xf3, 0xaf, + 0xa9, 0x3e, 0xd7, 0x8a, 0xe8, 0xd4, 0x55, 0xee, 0xec, 0x72, 0x2b, 0x0f, 0x7d, 0xc5, 0x27, 0xd8, + 0x4f, 0xe4, 0xf2, 0x1a, 0xc4, 0xe3, 0xc2, 0x73, 0x91, 0x32, 0x23, 0xe4, 0x83, 0xae, 0x1e, 0xbc, + 0x66, 0x72, 0x94, 0xfc, 0x60, 0x6f, 0xf8, 0x6a, 0x54, 0x37, 0xac, 0xe1, 0x80, 0x18, 0xc6, 0x9b, + 0x01, 0x11, 0xc1, 0x75, 0xde, 0xe3, 0xce, 0xae, 0x69, 0x9f, 0x33, 0x61, 0x06, 0xe5, 0x4c, 0xc2, + 0x83, 0xf0, 0x54, 0xb1, 0x42, 0x16, 0x82, 0x2d, 0xb6, 0x89, 0x2d, 0x81, 0x00, 0x23, 0xe6, 0xaf, + 0xff, 0xa6, 0x5c, 0xa8, 0xff, 0xd8, 0x4f, 0x40, 0x49, 0xe6, 0x3a, 0x3c, 0x3a, 0x5e, 0xf8, 0xe9, + 0x77, 0x09, 0x2e, 0x2b, 0x23, 0xcb, 0xf8, 0x3d, 0x90, 0x38, 0xbb, 0x7f, 0x76, 0x97, 0x09, 0x12, + 0xb2, 0xdf, 0x19, 0x60, 0xbb, 0xb9, 0xba, 0x69, 0xdb, 0x46, 0x06, 0x7e, 0xc9, 0xa6, 0x14, 0x10, + 0x44, 0x78, 0x98, 0x48, 0x8b, 0x51, 0x2d, 0x22, 0xe1, 0xa8, 0x11, 0xd7, 0xc2, 0x9c, 0x51, 0xf4, + 0xf6, 0xac, 0x96, 0xd2, 0xd5, 0xe0, 0xad, 0x6c, 0x99, 0xab, 0xbf, 0x58, 0xdd, 0xc7, 0xd7, 0xab, + 0xc6, 0xc4, 0x9d, 0x62, 0xb6, 0xee, 0x9e, 0x63, 0xba, 0x19, 0xec, 0xc7, 0x88, 0x6b, 0x3d, 0xa8, + 0xd9, 0xd5, 0xb7, 0x27, 0x45, 0x91, 0x5c, 0x1f, 0xa1, 0xf6, 0x32, 0x3b, 0xd6, 0x67, 0x97, 0x4c, + 0xdc, 0xd3, 0x49, 0x98, 0x22, 0xa8, 0x91, 0x5f, 0xf8, 0x45, 0xf8, 0xef, 0x7e, 0xba, 0xb1, 0x45, + 0xe7, 0xb2, 0x6a, 0x7b, 0x45, 0xd8, 0xde, 0xaa, 0x88, 0x7a, 0x01, 0x30, 0x15, 0x64, 0x15, 0x3d, + 0x7a, 0xfb, 0x9b, 0xf6, 0x37, 0x69, 0xbe, 0x4d, 0x3b, 0x77, 0x76, 0xb6, 0xb4, 0xc3, 0x83, 0x21, + 0xa4, 0x15, 0xf3, 0x11, 0xa4, 0xf2, 0xf9, 0xae, 0x91, 0x4e, 0xce, 0x99, 0x59, 0x49, 0xe5, 0xc1, + 0xa5, 0x69, 0x14, 0x48, 0x47, 0xa4, 0xf3, 0x5e, 0x76, 0xee, 0x65, 0x02, 0xb6, 0x9f, 0x59, 0xc9, + 0x37, 0x17, 0xf4, 0xd3, 0xfe, 0xe4, 0x9f, 0xdd, 0x25, 0x1f, 0xc8, 0x3a, 0x15, 0xd6, 0xe6, 0xd8, + 0x05, 0xda, 0x65, 0xc9, 0x20, 0x68, 0x6a, 0x7d, 0x93, 0x29, 0xe1, 0xaf, 0xad, 0x52, 0x20, 0x3a, + 0x88, 0xdc, 0x4b, 0xf7, 0x23, 0x7f, 0x41, 0xae, 0x09, 0x1e, 0xcd, 0xd2, 0x1b, 0x1e, 0x73, 0xfb, + 0x22, 0xbe, 0xa9, 0x42, 0x78, 0x6b, 0x18, 0xc3, 0x3b, 0x3e, 0x3b, 0x2f, 0x10, 0x40, 0x56, 0x0c, + 0x31, 0xb9, 0x29, 0xcd, 0xda, 0xab, 0x6a, 0xbe, 0x92, 0xca, 0xac, 0x24, 0x80, 0x79, 0xec, 0x4d, + 0x3d, 0xc5, 0xcd, 0x64, 0x5c, 0xe3, 0xce, 0xe5, 0x4b, 0x7d, 0x38, 0xdf, 0x74, 0x9c, 0xe1, 0x98, + 0xf7, 0x2f, 0x0a, 0x69, 0x63, 0xf4, 0x56, 0x8d, 0x9e, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("sig_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_load_sig_prod_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x42, 0x8e, 0xfe, 0xf5, 0x06, 0x4e, 0x98, 0x04, 0x7e, 0xc3, 0x2b, + 0x83, 0x4d, 0x9a, 0x9a, 0xfc, 0x98, 0x38, 0x19, 0x41, 0xa2, 0xe1, 0xb4, 0x9d, 0x76, 0xf9, 0x77, + 0x55, 0xf5, 0x76, 0x2d, 0x31, 0xdd, 0xd6, 0xff, 0xf8, 0x06, 0xf5, 0xe2, 0xc2, 0xb1, 0xb7, 0x3b, + 0xc7, 0x78, 0x7f, 0x99, 0x52, 0xfb, 0x94, 0x6d, 0x20, 0x6a, 0x21, 0x36, 0x67, 0x7c, 0x0e, 0x16, + 0xb3, 0x8e, 0x7d, 0x49, 0xf8, 0x18, 0x07, 0x82, 0x4b, 0x9a, 0xf4, 0x3a, 0xa1, 0x44, 0x1c, 0x00, + 0x66, 0x14, 0x93, 0x68, 0xc0, 0x29, 0x7f, 0x43, 0x3c, 0xa8, 0x0e, 0x81, 0xba, 0x79, 0xda, 0x91, + 0x4f, 0x59, 0x42, 0xec, 0x10, 0xcd, 0xd1, 0x3a, 0x4d, 0x5d, 0xd7, 0xdb, 0x37, 0x82, 0x78, 0x01, + 0x1b, 0xb3, 0xcc, 0x85, 0xff, 0x75, 0x92, 0xb3, 0x52, 0xa3, 0x53, 0xa5, 0x62, 0x52, 0x38, 0x55, + 0xec, 0x63, 0x27, 0x10, 0x0d, 0xf4, 0xed, 0x0b, 0x0c, 0xf1, 0x9b, 0x2b, 0xee, 0xb3, 0x81, 0x42, + 0x80, 0x2b, 0xd4, 0xd9, 0x3c, 0xdf, 0x6b, 0x72, 0x7c, 0xaf, 0xf8, 0xfa, 0x84, 0xdd, 0x6a, 0xc5, + 0xed, 0x0f, 0x16, 0x66, 0xe5, 0x53, 0xc8, 0x31, 0xd3, 0xa6, 0xa8, 0x4d, 0xd1, 0xa1, 0x6b, 0xf4, + 0x43, 0xae, 0x72, 0x5f, 0x99, 0x64, 0xde, 0x07, 0x78, 0xcc, 0x5e, 0xb6, 0x32, 0x24, 0x90, 0xf6, + 0xff, 0x1b, 0x2f, 0x10, 0x1c, 0x72, 0x0d, 0x60, 0x72, 0xde, 0x7d, 0xbd, 0x42, 0x82, 0x24, 0x77, + 0x58, 0x36, 0x68, 0xa2, 0x46, 0x2c, 0x35, 0x5c, 0x8f, 0x40, 0x2c, 0xb2, 0x15, 0xd8, 0xf5, 0xef, + 0x4b, 0xe3, 0xd7, 0x8d, 0x4b, 0xf2, 0xe7, 0x42, 0xb2, 0x87, 0xfc, 0x58, 0x0f, 0x13, 0xf7, 0xc3, + 0x26, 0x5b, 0x2a, 0xfc, 0x36, 0x6c, 0xca, 0xbc, 0x20, 0xa7, 0x75, 0x50, 0x3e, 0xce, 0x07, 0x2a, + 0xeb, 0x53, 0xf7, 0x66, 0x2e, 0xdc, 0xb3, 0xc0, 0xd3, 0x85, 0x10, 0xe2, 0x84, 0x1e, 0x77, 0x82, + 0x9a, 0xe2, 0x61, 0x28, 0xa3, 0x5d, 0xdc, 0x79, 0x3a, 0x4c, 0x6f, 0x11, 0xf1, 0x40, 0x19, 0xba, + 0xa1, 0x94, 0xda, 0x38, 0xaa, 0x51, 0xf8, 0x4a, 0xb7, 0xfd, 0x43, 0x47, 0x14, 0x4f, 0xc2, 0xa5, + 0xe3, 0xe0, 0x73, 0x76, 0xb8, 0x40, 0x4a, 0x65, 0x0f, 0x5e, 0x0e, 0x19, 0xaa, 0xde, 0xed, 0xcb, + 0xaa, 0x7d, 0x41, 0x19, 0xfb, 0x7d, 0x72, 0xd3, 0x7e, 0x3e, 0x9a, 0x76, 0x98, 0x2e, 0xac, 0xdc, + 0x0b, 0x35, 0x3a, 0xd5, 0x42, 0xa5, 0x00, 0xc4, 0x8d, 0x42, 0x1b, 0xb0, 0xb1, 0x54, 0x50, 0x83, + 0x71, 0xc5, 0x94, 0x07, 0xd6, 0x0a, 0xa1, 0x43, 0xff, 0x2f, 0x1e, 0x21, 0x5e, 0x06, 0x46, 0x41, + 0x24, 0x54, 0xd5, 0x20, 0x11, 0xaf, 0x45, 0x4a, 0x4d, 0xc1, 0x4a, 0xbb, 0x02, 0x6f, 0x9b, 0xc4, + 0x36, 0xc0, 0xe6, 0xf7, 0x25, 0x65, 0x97, 0x4d, 0x2e, 0x7f, 0x83, 0x65, 0x52, 0x4c, 0x85, 0xe5, + 0x7a, 0xe6, 0x67, 0x63, 0x2c, 0x20, 0x56, 0x9c, 0xb3, 0x40, 0x95, 0x7c, 0x5e, 0xb3, 0xfe, 0xf3, + 0x05, 0x48, 0xd1, 0x50, 0x30, 0xa6, 0x82, 0x79, 0xe6, 0xb8, 0xca, 0x76, 0x7b, 0x66, 0xcd, 0x4a, + 0xd6, 0xb0, 0x24, 0xe4, 0x46, 0xcd, 0xd1, 0x75, 0x6a, 0x03, 0x9e, 0xa4, 0x0d, 0x68, 0x47, 0x3e, + 0xe4, 0xe6, 0x97, 0x5c, 0x0c, 0xba, 0x98, 0xdd, 0x70, 0xd3, 0xc9, 0xe5, 0xc5, 0xf4, 0x2d, 0xf0, + 0xff, 0xc0, 0x6e, 0x10, 0x9f, 0x4b, 0x8c, 0x80, 0xd5, 0x5c, 0x01, 0x35, 0x6f, 0x1e, 0x04, 0x83, + 0x01, 0x5f, 0x1f, 0x44, 0xcb, 0x44, 0xd6, 0x8d, 0xe1, 0xb7, 0x91, 0xd0, 0x63, 0x89, 0x94, 0x3a, + 0xcb, 0x7a, 0x6b, 0xc4, 0xf1, 0x57, 0x26, 0xbb, 0xa6, 0xf2, 0x2d, 0x3a, 0x3f, 0xb9, 0xe6, 0x98, + 0x84, 0x08, 0x8b, 0xa1, 0xc2, 0xb3, 0x16, 0x55, 0x0f, 0x0f, 0xdf, 0x82, 0x98, 0xcb, 0x31, 0x23, + 0x8f, 0x99, 0x94, 0x6b, 0x52, 0x71, 0x5d, 0xf0, 0xde, 0xeb, 0x56, 0x59, 0x6b, 0x0e, 0xab, 0x02, + 0xe8, 0x52, 0x1f, 0x60, 0x2b, 0x9b, 0x64, 0x2c, 0x1d, 0x0d, 0x25, 0x14, 0x2b, 0x21, 0x23, 0x95, + 0x53, 0x39, 0xc6, 0x63, 0xdd, 0x24, 0x55, 0xd0, 0x01, 0x9c, 0xc8, 0xf7, 0x3e, 0x9d, 0x26, 0x84, + 0xe3, 0x63, 0x70, 0x05, 0x42, 0xd7, 0x0b, 0xd0, 0xa3, 0xfc, 0xa1, 0xea, 0xe6, 0x2f, 0xa1, 0x73, + 0x1b, 0x32, 0x73, 0xfb, 0x96, 0xde, 0x31, 0xc2, 0xbe, 0x30, 0x13, 0x58, 0x8f, 0xac, 0x66, 0x56, + 0xac, 0x29, 0x3d, 0x22, 0x45, 0xea, 0xf2, 0x39, 0xb9, 0xc0, 0xee, 0xb7, 0x5a, 0x70, 0x30, 0xa6, + 0x57, 0xe5, 0x99, 0xe0, 0x2f, 0x16, 0xa4, 0x90, 0xe6, 0xbd, 0xfb, 0x37, 0xd1, 0x21, 0xa2, 0x0e, + 0x8b, 0xfc, 0x6c, 0xe6, 0x77, 0x95, 0x37, 0x68, 0x28, 0x72, 0xb3, 0x7f, 0x7b, 0x0a, 0x18, 0x1f, + 0xa4, 0x4b, 0x2f, 0xaf, 0xbc, 0xf8, 0x9b, 0xe2, 0xf0, 0xdf, 0xc9, 0xb9, 0x6e, 0x65, 0x02, 0x87, + 0xf3, 0x20, 0x4d, 0xd0, 0xc5, 0x48, 0x1d, 0xf3, 0xb6, 0x2c, 0xe0, 0x61, 0x1e, 0xad, 0x24, 0xab, + 0x21, 0x95, 0x2c, 0xf3, 0x4f, 0x62, 0x1f, 0xd3, 0x4c, 0xa4, 0x64, 0x4f, 0xb1, 0xfa, 0x89, 0x2a, + 0xb1, 0x09, 0x9b, 0xed, 0x0d, 0xae, 0xac, 0xf2, 0x97, 0xde, 0x84, 0x1f, 0x20, 0x57, 0xd3, 0xe5, + 0xfa, 0x2a, 0x86, 0xf1, 0xb2, 0x91, 0xaf, 0x75, 0x18, 0xd1, 0x61, 0xee, 0xb3, 0x8f, 0x34, 0x39, + 0x3b, 0x79, 0xc5, 0x96, 0x99, 0x76, 0x16, 0x2a, 0x90, 0xbd, 0x72, 0xb8, 0x0a, 0xc5, 0x56, 0xd0, + 0xec, 0xf6, 0x74, 0x19, 0x78, 0xf5, 0xc0, 0x41, 0xc6, 0x00, 0xa9, 0x6a, 0x6b, 0x8e, 0xa8, 0x61, + 0xa8, 0xc6, 0x33, 0xb4, 0x1e, 0x67, 0x67, 0x63, 0x7b, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("patch_loc") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_load_sig_ad10x_patch_location +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data[] = +{ + 0x10, 0x57, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_patch_loc_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("patch_sig") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_load_sig_ad10x_patch_signature +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_sig_data[] = +{ + 0x00, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_patch_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_patch_sig_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("patch_meta") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_load_sig_ad10x_patch_meta_data +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 12 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_meta_data[] = +{ + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_patch_meta_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 12, // uncompressed data size (bytes) + 12, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_patch_meta_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterLoadUcode_AD102("num_sigs") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: num_sigs_per_ucode +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_num_sigs_data[] = +{ + 0x02, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_num_sigs_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterLoadUcode_AD102_num_sigs_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterLoadUcode_AD102 = +{ + 10, // entryNum + { + // entries[] : { "name", pBinStorage } + { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt }, + { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt }, + { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt }, + { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt }, + { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt }, + { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt }, + { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_patch_loc_storage_pvt }, + { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_patch_sig_storage_pvt }, + { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_patch_meta_storage_pvt }, + { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterLoadUcode_AD102_num_sigs_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_AD102(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveBooterLoadUcode_AD102; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index 75711b7b7..d8a6e50d3 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -55,7 +55,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0xfa, 0x7f, 0xf7, 0x81, 0xfd, 0x5f, 0xed, 0x7f, 0xc3, 0x02, 0x25, 0xc3, 0x43, 0xec, 0xfc, 0xdf, 0x14, 0xbe, 0xdf, 0x41, 0xc3, 0x01, 0xf4, 0x00, 0xbe, 0x73, 0x40, 0x3a, 0xe3, 0x80, 0x5a, 0x92, 0x10, 0xfe, 0xd7, 0xfe, 0xf9, 0x00, 0xf0, 0xf9, 0xdf, 0xc4, 0xde, 0x80, 0xba, 0x8b, 0x3e, 0x01, - 0x63, 0xab, 0x77, 0x00, 0xc3, 0x09, 0x68, 0x01, 0xf2, 0x72, 0xdf, 0x00, 0x62, 0xff, 0x57, 0xf6, + 0x63, 0x67, 0x46, 0x21, 0xc2, 0x09, 0x68, 0x01, 0xf2, 0x72, 0xdf, 0x00, 0x62, 0xff, 0x57, 0xf6, 0xfe, 0x3e, 0x31, 0x7c, 0xfd, 0x48, 0x00, 0xe6, 0xe5, 0xf2, 0xbe, 0x03, 0xfc, 0x1f, 0x74, 0x90, 0xcb, 0x5b, 0xec, 0x2f, 0xe8, 0xb8, 0x9f, 0x49, 0xf1, 0x43, 0xb4, 0x1c, 0x66, 0x05, 0xbf, 0xc2, 0x27, 0x3b, 0xbc, 0x4e, 0x1f, 0xea, 0x2b, 0x83, 0x01, 0xb1, 0xb7, 0xcc, 0xf7, 0xce, 0x93, 0xce, @@ -595,8 +595,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0xd5, 0x12, 0x94, 0x7e, 0x89, 0xc9, 0xd0, 0x69, 0x2e, 0x99, 0xd5, 0x55, 0x5a, 0x20, 0x84, 0x13, 0xa7, 0x85, 0x61, 0x46, 0x3a, 0x28, 0x62, 0xc9, 0x5f, 0x4f, 0xa2, 0x98, 0x28, 0xff, 0x68, 0x4c, 0xbc, 0x6c, 0x2f, 0xf7, 0x85, 0xe6, 0x43, 0xa4, 0xe5, 0x6f, 0x22, 0x31, 0x93, 0xd5, 0xae, 0xac, - 0x38, 0x78, 0x76, 0x47, 0x7d, 0x99, 0x22, 0x76, 0x6f, 0xb2, 0xf5, 0x8b, 0x30, 0xab, 0x71, 0x92, - 0xf7, 0x72, 0x6f, 0x53, 0x85, 0x83, 0xcd, 0xcd, 0x5f, 0xd9, 0x72, 0x42, 0x7c, 0x06, 0xf7, 0x01, + 0x38, 0x78, 0x76, 0x47, 0x7d, 0x99, 0x22, 0x76, 0x6f, 0xb2, 0xdd, 0x22, 0xfd, 0x44, 0x5a, 0x0f, + 0x4f, 0x2a, 0x44, 0x77, 0x3b, 0xde, 0x7f, 0x8c, 0x3f, 0xea, 0x74, 0x42, 0x7c, 0x06, 0xf7, 0x01, 0xfe, 0x66, 0x2d, 0x7f, 0x6f, 0x52, 0x89, 0xff, 0xf0, 0x9e, 0xfe, 0xf3, 0x7b, 0xc7, 0xf4, 0x75, 0x9c, 0xf0, 0xd9, 0x2a, 0xa2, 0x61, 0xc5, 0x3a, 0xca, 0xf1, 0x9a, 0xe5, 0xeb, 0xb2, 0x81, 0x98, 0x7d, 0xf3, 0xe7, 0x9d, 0x57, 0x20, 0x94, 0xd2, 0x56, 0x2d, 0x37, 0xb2, 0x75, 0xa1, 0x42, 0x7b, @@ -624,8 +624,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x00, 0x90, 0x8f, 0xab, 0xf0, 0x40, 0x3e, 0x3e, 0x06, 0x4c, 0x35, 0xe0, 0xbb, 0xa0, 0x03, 0x59, 0x0e, 0xe5, 0x60, 0x40, 0x99, 0x11, 0xa2, 0xe6, 0x5f, 0xa3, 0xcb, 0xec, 0x78, 0x15, 0x89, 0xb0, 0xd9, 0xf3, 0x07, 0xb7, 0xa0, 0xa4, 0x55, 0x4c, 0xb5, 0xab, 0x17, 0x7b, 0x8b, 0x43, 0x72, 0x5a, - 0x47, 0x7b, 0x7e, 0x9b, 0x61, 0x90, 0x84, 0xea, 0x9d, 0xbc, 0x72, 0xd3, 0x50, 0x1a, 0xee, 0x44, - 0x10, 0x16, 0x05, 0x5c, 0xda, 0xaf, 0x98, 0x4d, 0x47, 0x76, 0xce, 0xc3, 0x0f, 0xa3, 0x24, 0x0d, + 0x47, 0x7b, 0x7e, 0x9b, 0x61, 0x90, 0x84, 0xea, 0x9d, 0xbc, 0xf2, 0xcf, 0x1d, 0xad, 0x2b, 0xc3, + 0x88, 0x86, 0x4e, 0xcb, 0x9b, 0x3b, 0x46, 0x62, 0xb7, 0x26, 0xb2, 0xc3, 0x0f, 0xa3, 0x24, 0x0d, 0xd0, 0x4d, 0x85, 0xb6, 0x1f, 0x10, 0x4b, 0x38, 0xb6, 0x88, 0x87, 0x15, 0x89, 0xd9, 0xea, 0x63, 0xdc, 0xf5, 0xb8, 0x0c, 0xac, 0x08, 0xb0, 0xca, 0x85, 0x8e, 0xf9, 0xeb, 0x58, 0x83, 0x35, 0x87, 0xdd, 0x4d, 0x57, 0xe9, 0x69, 0x5e, 0x6c, 0xbe, 0x61, 0x81, 0x87, 0x3e, 0x7a, 0x5a, 0x57, 0x75, @@ -662,8 +662,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x84, 0x5a, 0x14, 0x44, 0x75, 0x4e, 0x1b, 0xcc, 0x35, 0x83, 0x23, 0xed, 0xaa, 0xfc, 0x2c, 0x1b, 0x0d, 0xb9, 0x3a, 0x49, 0x64, 0x51, 0x93, 0xdb, 0x14, 0x49, 0x27, 0x44, 0x81, 0x3b, 0x0a, 0x2a, 0xa3, 0xcc, 0x09, 0xb3, 0x96, 0x1b, 0x5b, 0x3b, 0xbc, 0x17, 0xa6, 0x69, 0x6a, 0x23, 0xea, 0x8a, - 0xc3, 0x00, 0xd4, 0x15, 0x75, 0xe2, 0xfd, 0x56, 0xbe, 0xbf, 0x01, 0x6f, 0x20, 0xec, 0xe7, 0x71, - 0x98, 0xe3, 0x53, 0xd3, 0x7e, 0x85, 0x45, 0x64, 0xee, 0x6f, 0x05, 0xac, 0x55, 0x33, 0x83, 0x24, + 0xc3, 0x00, 0xd4, 0x15, 0x75, 0xe2, 0xfd, 0x56, 0xbe, 0xbf, 0x01, 0x6f, 0xb7, 0x03, 0x21, 0x29, + 0xbb, 0x4f, 0xdf, 0x44, 0x91, 0x04, 0x7f, 0x79, 0x15, 0x35, 0xd3, 0xad, 0x55, 0x33, 0x83, 0x24, 0xac, 0x1a, 0xb4, 0x79, 0x4d, 0x8b, 0x05, 0x56, 0x51, 0x66, 0x70, 0x05, 0x63, 0x91, 0xd2, 0x5d, 0xc9, 0x8e, 0xdc, 0xad, 0xd8, 0x73, 0xb7, 0xbd, 0x22, 0x33, 0x73, 0x8c, 0x23, 0xab, 0xed, 0x74, 0x9a, 0xbe, 0xc7, 0x23, 0xdf, 0xb8, 0x46, 0xc6, 0x8b, 0xda, 0xb8, 0x80, 0x2f, 0x39, 0xa6, 0x74, @@ -691,9 +691,9 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x97, 0xe4, 0xee, 0x89, 0x24, 0x22, 0xf8, 0x95, 0x90, 0xe6, 0xed, 0xdf, 0xfc, 0xba, 0x82, 0x87, 0x4c, 0x1f, 0x53, 0x05, 0xc9, 0x88, 0x0b, 0xa1, 0xe7, 0xc0, 0xdc, 0x83, 0xf2, 0x7d, 0x2f, 0x45, 0xee, 0xb1, 0xb7, 0x84, 0x48, 0x1a, 0xe9, 0x96, 0xa5, 0x12, 0x96, 0xbf, 0xe5, 0x0e, 0xe9, 0xd3, - 0x5e, 0x0a, 0xab, 0xad, 0xf9, 0x91, 0xb0, 0xaa, 0x1e, 0x1a, 0x88, 0xa7, 0x04, 0xe8, 0x09, 0x35, - 0x16, 0x1d, 0x32, 0x21, 0x35, 0x50, 0xb5, 0x11, 0x4b, 0x5f, 0x05, 0x42, 0x46, 0x79, 0x10, 0x96, - 0x26, 0xf1, 0xdb, 0xbd, 0x58, 0x6a, 0x0f, 0x3a, 0xc6, 0xb7, 0x96, 0x98, 0x86, 0xe2, 0xb7, 0x0e, + 0x5e, 0x0a, 0xab, 0xad, 0xf9, 0x91, 0xb0, 0xaa, 0x1e, 0x1a, 0x88, 0x0f, 0x95, 0x66, 0x12, 0x70, + 0x55, 0x3e, 0xcf, 0xfe, 0x7d, 0xad, 0x88, 0x47, 0xe1, 0xc2, 0xc1, 0xf8, 0xbd, 0x2b, 0xc2, 0x15, + 0x54, 0xb9, 0xd4, 0xb2, 0x01, 0xb2, 0x6d, 0x16, 0xeb, 0xf7, 0x59, 0x9e, 0x86, 0xe2, 0xb7, 0x0e, 0x1a, 0x0d, 0x9b, 0x92, 0xd3, 0xa4, 0x1c, 0x15, 0xe5, 0x5f, 0x9b, 0xbc, 0x54, 0xbc, 0xec, 0x99, 0x54, 0x3a, 0x10, 0xc8, 0x28, 0x54, 0xba, 0xb9, 0xc0, 0xa0, 0xaa, 0x01, 0x06, 0x29, 0xcb, 0xb3, 0x27, 0x06, 0xd2, 0x28, 0x70, 0x56, 0x96, 0xd5, 0xa2, 0x33, 0x9d, 0x4c, 0x4f, 0x6f, 0x57, 0x28, @@ -1083,8 +1083,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x6b, 0xac, 0x4f, 0x45, 0xc0, 0x51, 0x9d, 0x45, 0xc6, 0xc3, 0x95, 0xfa, 0x32, 0xcb, 0x2d, 0x20, 0xf8, 0x34, 0xc5, 0xc0, 0xf8, 0xfa, 0x09, 0x9b, 0x88, 0x0d, 0x35, 0x2c, 0xeb, 0xc9, 0x7b, 0x2d, 0x5f, 0x12, 0xf1, 0x7d, 0x78, 0x2a, 0x8b, 0x77, 0xf5, 0xf5, 0xed, 0x8b, 0xe0, 0x88, 0xed, 0x2a, - 0x96, 0x15, 0x78, 0x4e, 0xf4, 0x94, 0x41, 0xf7, 0xf8, 0x69, 0xfd, 0x2d, 0x79, 0x40, 0xe0, 0xe8, - 0xb4, 0x4d, 0xc7, 0x15, 0xd7, 0xad, 0x36, 0x10, 0x9b, 0x23, 0x34, 0xa5, 0x3f, 0x33, 0xd6, 0x0a, + 0x96, 0x15, 0xf8, 0x2a, 0xc3, 0x04, 0xbe, 0xde, 0x37, 0x9b, 0x39, 0xce, 0x96, 0x88, 0x69, 0x80, + 0x56, 0x63, 0xe3, 0x15, 0xd7, 0xad, 0x36, 0x10, 0x9b, 0x23, 0x34, 0xa5, 0x3f, 0x33, 0xd6, 0x0a, 0xed, 0x01, 0x9c, 0x95, 0x1a, 0x86, 0xb9, 0xf2, 0x33, 0x67, 0x1b, 0xab, 0x93, 0x49, 0x97, 0xa8, 0x25, 0x76, 0x7f, 0x10, 0x8c, 0x2c, 0xe2, 0xa7, 0x2e, 0xfb, 0x83, 0xd2, 0xa3, 0x19, 0x16, 0xdb, 0x67, 0xcb, 0xf9, 0x10, 0x30, 0x0d, 0xf3, 0x93, 0x45, 0xeb, 0xa2, 0x36, 0x54, 0x66, 0x97, 0xd6, @@ -1135,8 +1135,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x94, 0x23, 0x3c, 0xd6, 0x04, 0x7d, 0xb3, 0xee, 0xa6, 0xe8, 0xe6, 0xc7, 0x58, 0x19, 0x57, 0x34, 0xda, 0x60, 0xea, 0x46, 0x9d, 0xd1, 0x69, 0xc3, 0x7b, 0xa6, 0x98, 0x96, 0xb7, 0xac, 0x9c, 0x71, 0x06, 0x82, 0x08, 0x02, 0xec, 0x2e, 0x68, 0x75, 0xce, 0x21, 0x84, 0xa9, 0x4b, 0xc5, 0xfd, 0x81, - 0xb6, 0x79, 0x69, 0xe2, 0x1b, 0x47, 0x40, 0xbc, 0x5f, 0xb6, 0x4b, 0xa2, 0x7e, 0x17, 0xc1, 0xab, - 0x20, 0x2f, 0xa1, 0x44, 0xa3, 0x2e, 0x4a, 0xe0, 0x9c, 0xf1, 0x04, 0xb3, 0xed, 0x14, 0x33, 0xbe, + 0xb6, 0x79, 0x69, 0xe2, 0x93, 0x01, 0x36, 0x03, 0x88, 0x34, 0x81, 0xb5, 0x7c, 0xce, 0x82, 0xbb, + 0x81, 0x63, 0xe8, 0xa0, 0xa7, 0x2e, 0x4a, 0xe0, 0x9c, 0xf1, 0x04, 0xb3, 0xed, 0x14, 0x33, 0xbe, 0x1a, 0xe6, 0x4d, 0x7e, 0xa0, 0xce, 0xd9, 0x3b, 0x18, 0xc9, 0xd5, 0xc9, 0xc5, 0x84, 0x2a, 0x39, 0x9e, 0xf9, 0x2b, 0x0a, 0x4e, 0x73, 0x41, 0x6b, 0xb9, 0x15, 0x59, 0xd3, 0xa1, 0x02, 0xb9, 0x14, 0xdb, 0x7c, 0x1f, 0x1a, 0x3d, 0x8c, 0x19, 0x6a, 0x2f, 0xc3, 0x78, 0x36, 0x9a, 0xb2, 0xcb, 0x8f, @@ -1182,8 +1182,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0xb2, 0x91, 0x9b, 0xe5, 0x22, 0x8b, 0xd8, 0x97, 0xca, 0xa0, 0x59, 0x4c, 0x6e, 0x51, 0x30, 0xda, 0x27, 0x86, 0xa2, 0xeb, 0xc8, 0x3c, 0x1c, 0xea, 0xc1, 0xe6, 0xda, 0xd0, 0xb8, 0xd0, 0xc4, 0x43, 0x98, 0xde, 0xaa, 0x82, 0x85, 0x5f, 0x43, 0x5e, 0x4c, 0xf2, 0x9d, 0xdb, 0x19, 0x02, 0x88, 0xdb, - 0xad, 0x44, 0xef, 0x54, 0x07, 0x41, 0xa9, 0x6a, 0x87, 0xf5, 0xca, 0xa7, 0xba, 0x9d, 0xca, 0x51, - 0x1c, 0x55, 0x00, 0x01, 0x6b, 0x45, 0x27, 0x56, 0x2e, 0x3e, 0xe4, 0x7d, 0xca, 0x5c, 0x17, 0xd0, + 0xad, 0x44, 0xef, 0x54, 0x07, 0x41, 0xa9, 0x6a, 0xdf, 0xd0, 0x58, 0x5d, 0x68, 0x1c, 0xff, 0xbd, + 0xfc, 0x45, 0xef, 0x49, 0x7a, 0x70, 0x94, 0xde, 0x2b, 0x3e, 0xe4, 0x7d, 0xca, 0x5c, 0x17, 0xd0, 0x04, 0x30, 0xf2, 0x94, 0x75, 0x65, 0x03, 0xee, 0x77, 0x14, 0xc6, 0x13, 0x24, 0x3a, 0x11, 0x5c, 0xf5, 0x5a, 0x13, 0x61, 0x6c, 0x82, 0xa1, 0x8b, 0x13, 0x5e, 0xd7, 0xd6, 0xb6, 0x77, 0xdf, 0x1a, 0xef, 0x6b, 0xdb, 0xaa, 0xb8, 0xd9, 0x02, 0xde, 0xff, 0x43, 0x54, 0xed, 0x63, 0x4c, 0x35, 0xf4, @@ -1528,7 +1528,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x27, 0xfc, 0x3f, - 0x72, 0x96, 0x6c, 0xeb, 0x00, 0x8e, 0x00, 0x00, + 0xd2, 0xe5, 0x3f, 0xaa, 0x00, 0x8e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1591,7 +1591,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 23829 +// COMPRESSED SIZE (bytes): 23828 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { @@ -1610,8 +1610,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] 0x1e, 0xb0, 0x3d, 0x13, 0x00, 0x17, 0xe8, 0xff, 0x7a, 0xc0, 0xff, 0xeb, 0x01, 0x02, 0xfd, 0xbf, 0xe6, 0xc0, 0xfe, 0xaf, 0xf7, 0xbf, 0xd7, 0x02, 0xa5, 0xc2, 0x43, 0xec, 0xfc, 0xdf, 0x12, 0xbe, 0xdf, 0x41, 0x23, 0x01, 0x0c, 0x00, 0xbe, 0x73, 0x41, 0xba, 0x12, 0x80, 0x5a, 0x53, 0x10, 0xfe, - 0x37, 0xfe, 0xf9, 0x00, 0xf0, 0xfb, 0xdf, 0xc2, 0xde, 0x80, 0x7a, 0x8a, 0x3f, 0x01, 0xe3, 0x6b, - 0x76, 0x00, 0x23, 0x09, 0x68, 0x01, 0xf2, 0xf3, 0xde, 0x00, 0xe2, 0xff, 0xd7, 0xf6, 0xfd, 0x3e, + 0x37, 0xfe, 0xf9, 0x00, 0xf0, 0xfb, 0xdf, 0xc2, 0xde, 0x80, 0x7a, 0x8a, 0x3f, 0x01, 0xe3, 0x67, + 0xc7, 0x20, 0x22, 0x09, 0x68, 0x01, 0xf2, 0xf3, 0xde, 0x00, 0xe2, 0xff, 0xd7, 0xf6, 0xfd, 0x3e, 0x31, 0x7c, 0xfd, 0x48, 0x02, 0xe6, 0xe7, 0xf1, 0xbd, 0x03, 0xfc, 0x9f, 0x9e, 0x07, 0x33, 0xf2, 0x7c, 0x50, 0xcf, 0xae, 0x82, 0x1e, 0x95, 0xd4, 0x4d, 0xf8, 0x44, 0x23, 0x81, 0x96, 0xd6, 0x65, 0x9c, 0x30, 0xa6, 0xc2, 0x6f, 0x98, 0x9f, 0xe4, 0xd2, 0x86, 0x61, 0xd1, 0x04, 0x3b, 0x6d, 0x07, @@ -2151,8 +2151,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] 0x60, 0x4d, 0x8d, 0xfb, 0x8e, 0xe4, 0xeb, 0x54, 0xcf, 0x33, 0x86, 0x9c, 0x38, 0x18, 0xb2, 0xe4, 0xc8, 0x83, 0x85, 0x25, 0xe1, 0x1d, 0xe0, 0xb7, 0x49, 0x68, 0xc1, 0xea, 0x3c, 0x58, 0xeb, 0x2c, 0xee, 0xa4, 0x6e, 0xff, 0xad, 0xa8, 0x62, 0xa8, 0xe8, 0x61, 0x6e, 0x5e, 0xce, 0x08, 0xe0, 0x1b, - 0xf9, 0xa5, 0xd5, 0x8e, 0xd5, 0x1e, 0x58, 0x7d, 0x5a, 0xe6, 0xa6, 0x51, 0xe4, 0x31, 0x86, 0x4f, - 0xa7, 0x48, 0xad, 0xbb, 0x38, 0xbf, 0xcf, 0x09, 0xdc, 0xe7, 0xd4, 0x1e, 0x94, 0xbc, 0x2e, 0xfb, + 0xf9, 0xa5, 0xd5, 0x8e, 0xd5, 0x1e, 0x58, 0x7d, 0xda, 0xf9, 0xe2, 0xdd, 0x04, 0xc7, 0x50, 0x77, + 0xcb, 0x2f, 0x6f, 0xa4, 0xdc, 0x6d, 0x73, 0xbb, 0xd8, 0xe7, 0xd4, 0x1e, 0x94, 0xbc, 0x2e, 0xfb, 0x5e, 0x94, 0x58, 0x49, 0x56, 0x8f, 0x34, 0xbe, 0x57, 0x81, 0xef, 0xe9, 0x34, 0x91, 0x55, 0x69, 0x78, 0x1d, 0xe3, 0x6e, 0xba, 0x46, 0x30, 0x12, 0x35, 0x08, 0xe8, 0xea, 0x0f, 0xdb, 0xd0, 0xcb, 0xa0, 0x03, 0x0b, 0xdc, 0x54, 0x00, 0xdc, 0x6a, 0xd6, 0x64, 0xd8, 0x55, 0xa7, 0x08, 0xa8, 0x8f, @@ -2180,8 +2180,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] 0xc7, 0x46, 0xbe, 0xee, 0xab, 0x81, 0xbe, 0xce, 0x5f, 0xac, 0xa8, 0xce, 0x83, 0x06, 0xa1, 0xcf, 0x5d, 0xe0, 0x52, 0x1e, 0x0c, 0x93, 0x1f, 0x0f, 0x94, 0xe4, 0xd3, 0x84, 0x20, 0x6f, 0xdc, 0x1c, 0xde, 0x32, 0x60, 0x57, 0x89, 0xd7, 0xf6, 0x48, 0x1d, 0x60, 0xf2, 0xda, 0x5e, 0x80, 0x41, 0x4b, - 0xfe, 0xb2, 0xe5, 0xd8, 0x52, 0xa5, 0x34, 0x65, 0x09, 0xd0, 0xcc, 0x68, 0x98, 0x92, 0x65, 0xc8, - 0xa7, 0xaf, 0x66, 0xcd, 0xe4, 0x29, 0x72, 0x9c, 0x65, 0xaf, 0x29, 0x07, 0xc0, 0x81, 0x96, 0xe3, + 0xfe, 0xb2, 0xe5, 0xd8, 0x52, 0xa5, 0x34, 0x65, 0x89, 0x37, 0x65, 0x2c, 0x46, 0xaa, 0x07, 0x50, + 0x28, 0x8e, 0xb3, 0x4f, 0xc8, 0xd3, 0xfe, 0xed, 0x59, 0xaf, 0x29, 0x07, 0xc0, 0x81, 0x96, 0xe3, 0xbd, 0x3f, 0xe8, 0x7b, 0x1e, 0xef, 0x57, 0x4d, 0xe7, 0xd4, 0x35, 0xe4, 0xdd, 0x44, 0xaf, 0x32, 0x88, 0x7e, 0x91, 0xde, 0x31, 0x30, 0x9d, 0x34, 0x5a, 0xef, 0x3c, 0xa7, 0x0c, 0x18, 0xb4, 0x97, 0x9f, 0xf7, 0x11, 0xbf, 0xd2, 0x4c, 0x41, 0x62, 0xe0, 0xad, 0x1a, 0x71, 0x11, 0x77, 0x23, 0xc1, @@ -2218,8 +2218,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] 0xbf, 0x59, 0x3a, 0x70, 0x1b, 0x2a, 0x5c, 0x0d, 0x4a, 0xf2, 0x89, 0x43, 0x7b, 0x9b, 0xc1, 0xdb, 0x13, 0xb1, 0x2d, 0x3d, 0xd6, 0x3b, 0xe6, 0x47, 0xaa, 0x54, 0x15, 0xd7, 0x22, 0x0c, 0xf6, 0x43, 0xb4, 0xb1, 0x92, 0xb6, 0xbd, 0x42, 0x7e, 0xe6, 0x9c, 0xa1, 0x39, 0x1e, 0x9f, 0xa2, 0x92, 0xf9, - 0xdc, 0x42, 0x1a, 0x6e, 0xeb, 0xc1, 0xff, 0xc0, 0x4a, 0x10, 0xd1, 0xdf, 0x90, 0x30, 0x20, 0xd5, - 0x43, 0x0d, 0x35, 0x09, 0x91, 0x44, 0xec, 0xdb, 0x40, 0x51, 0xf3, 0x4b, 0x55, 0x7f, 0xca, 0x79, + 0xdc, 0x42, 0x1a, 0x6e, 0xeb, 0xc1, 0xff, 0xc0, 0x4a, 0x40, 0xa9, 0x7c, 0x38, 0x78, 0x9b, 0xef, + 0xbd, 0xa5, 0xce, 0xd0, 0xa4, 0x15, 0x24, 0x0d, 0x9a, 0x50, 0xf3, 0x4b, 0x55, 0x7f, 0xca, 0x79, 0xf5, 0xc0, 0x48, 0xbe, 0xf8, 0xbd, 0xbd, 0x5f, 0x52, 0xee, 0xd6, 0x31, 0x79, 0x35, 0x0c, 0x57, 0xf4, 0xc0, 0xde, 0x34, 0xa3, 0x84, 0xf6, 0x56, 0x7c, 0xfd, 0xe8, 0xfe, 0x61, 0xb3, 0x0e, 0xbb, 0xb7, 0x18, 0xe0, 0xcd, 0x36, 0x51, 0x2a, 0xfd, 0x5c, 0x29, 0xeb, 0xa1, 0x5e, 0x7c, 0x47, 0xcb, @@ -2247,844 +2247,844 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] 0xb7, 0x25, 0x0b, 0x27, 0x97, 0xc0, 0x18, 0x74, 0xc8, 0x36, 0xf9, 0x42, 0x44, 0xb8, 0x8a, 0xc7, 0x10, 0x0b, 0xf7, 0xd2, 0x30, 0x85, 0x92, 0xd2, 0x6a, 0x84, 0x44, 0x10, 0xb0, 0x88, 0xb4, 0xe9, 0x8e, 0xa0, 0xa9, 0xc2, 0xb9, 0x86, 0x8b, 0x83, 0xb1, 0x5c, 0x00, 0x62, 0x21, 0x6d, 0x88, 0x66, - 0xac, 0x92, 0x10, 0x56, 0xc8, 0x21, 0xba, 0x7c, 0x5a, 0x59, 0xe3, 0xcc, 0xaf, 0xab, 0x11, 0x0d, - 0xe9, 0x91, 0x52, 0x07, 0xfa, 0x03, 0x92, 0x18, 0x18, 0x97, 0x2f, 0xf3, 0x2e, 0xed, 0x31, 0xc4, - 0x80, 0xf1, 0x14, 0x25, 0x78, 0x87, 0x65, 0x58, 0xaf, 0xb9, 0xfa, 0x5d, 0x6e, 0x8d, 0xe0, 0x41, - 0xb6, 0x59, 0x65, 0x91, 0x1e, 0x9c, 0xcd, 0xa3, 0x83, 0xf2, 0x77, 0xfd, 0x31, 0xbe, 0xab, 0xf3, - 0x16, 0x68, 0x47, 0xf8, 0xf4, 0xfc, 0x3e, 0x12, 0x41, 0x0a, 0x19, 0x9a, 0x0e, 0x24, 0xc9, 0x17, - 0x5e, 0x4a, 0x59, 0xbb, 0x24, 0xf0, 0x9c, 0x34, 0xa2, 0x47, 0x6f, 0xbb, 0x44, 0x87, 0x60, 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0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, - 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, - 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x27, 0xfc, 0x3f, 0x00, 0xd8, 0xe2, 0x6e, - 0x15, 0x00, 0x8e, 0x00, 0x00, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xff, 0x09, 0xff, 0x0f, 0x4b, 0xb0, 0xaf, 0xce, + 0x00, 0x8e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3095,7 +3095,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 36352, // uncompressed data size (bytes) - 23829, // compressed data size (bytes) + 23828, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3151,31 +3151,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xe1, 0x90, 0xee, 0x5b, 0xc4, 0x0a, 0x9f, 0xff, 0x65, 0xaa, 0xee, - 0x83, 0x6c, 0xcc, 0x4d, 0x4b, 0xc0, 0xc3, 0x34, 0x81, 0x9b, 0x35, 0xbf, 0x5f, 0x0b, 0x47, 0x21, - 0xfd, 0xe5, 0x04, 0x56, 0x57, 0x3f, 0xbb, 0xa0, 0x2d, 0x23, 0x7a, 0x9c, 0xcc, 0x97, 0x67, 0x10, - 0x35, 0x70, 0x4d, 0x9a, 0xe2, 0x0c, 0x9c, 0x25, 0xc9, 0xe2, 0x94, 0xef, 0x9c, 0x97, 0x6b, 0xa3, - 0x19, 0xf8, 0x36, 0xbf, 0x21, 0xae, 0x2d, 0x4e, 0x02, 0xff, 0x26, 0xe9, 0xe9, 0x0d, 0x75, 0x1c, - 0xa8, 0xdb, 0x1e, 0xa1, 0xaa, 0x01, 0x0c, 0x05, 0x27, 0x69, 0x84, 0x21, 0xaa, 0xa9, 0x80, 0x96, - 0x1b, 0x25, 0x35, 0x3b, 0x21, 0x6f, 0x20, 0x56, 0xd7, 0xb9, 0xdb, 0xa4, 0x0a, 0x61, 0x2f, 0x07, - 0xaf, 0x25, 0x6e, 0xd1, 0xa9, 0x21, 0xfc, 0x6b, 0x25, 0xfb, 0x3f, 0x36, 0x8f, 0xc5, 0xae, 0x04, - 0xb0, 0xc2, 0x8a, 0x86, 0x8b, 0x23, 0x45, 0x9d, 0xc0, 0x71, 0x33, 0xf2, 0x4b, 0xd1, 0x91, 0x1c, - 0x79, 0x36, 0xcf, 0x64, 0x53, 0x4a, 0x5a, 0xdb, 0xd6, 0x83, 0x94, 0xcb, 0x16, 0xb3, 0x1e, 0xf6, - 0xe5, 0x8a, 0xf3, 0x67, 0xc9, 0x0d, 0xa9, 0x84, 0xd9, 0x69, 0x9d, 0x1b, 0xf1, 0x71, 0xc4, 0x8d, - 0xf6, 0x2f, 0x2c, 0x79, 0x16, 0xcb, 0x93, 0x97, 0xfe, 0x7b, 0xec, 0x7c, 0x16, 0xbd, 0x95, 0xec, - 0x4e, 0xdc, 0x09, 0x13, 0xaa, 0x2c, 0xf9, 0xac, 0x81, 0xa4, 0x25, 0x77, 0xa3, 0x60, 0x4c, 0x7b, - 0xe5, 0x37, 0xc9, 0x71, 0x3e, 0x6e, 0xc0, 0x7f, 0xa1, 0x96, 0xf4, 0xb8, 0xa5, 0xec, 0x56, 0x8a, - 0x75, 0x90, 0x00, 0x4b, 0x21, 0x54, 0xba, 0x62, 0x73, 0x3e, 0x4c, 0xd5, 0x17, 0xc1, 0x81, 0x11, - 0xfd, 0xb4, 0x1e, 0xfd, 0x51, 0xc7, 0x33, 0x18, 0x8c, 0x61, 0xd2, 0x46, 0xa4, 0x2b, 0xb3, 0x36, - 0x89, 0x45, 0x73, 0x8a, 0xbd, 0x9c, 0xfb, 0x3b, 0x1d, 0xf0, 0x9a, 0x64, 0xd0, 0x73, 0xf6, 0xfd, - 0xaa, 0xec, 0xd9, 0x71, 0x3f, 0x41, 0x76, 0x66, 0x47, 0xe4, 0x33, 0xd8, 0xa8, 0x55, 0x3b, 0xea, - 0x40, 0xce, 0xe2, 0xeb, 0x04, 0x87, 0x54, 0x9a, 0x76, 0x4e, 0xa0, 0x0e, 0xc2, 0xa8, 0xa8, 0x80, - 0x26, 0x5e, 0xf8, 0xed, 0xcc, 0x40, 0x99, 0xfe, 0x27, 0xbf, 0xfa, 0xa9, 0x40, 0xf4, 0xec, 0xe3, - 0xa6, 0xff, 0xa8, 0x0e, 0x04, 0xee, 0x5a, 0x70, 0x9d, 0x79, 0xb8, 0x9e, 0xfc, 0xb1, 0x89, 0x0c, - 0x68, 0xb5, 0xfc, 0x8a, 0xcd, 0x3f, 0xac, 0xb1, 0xb9, 0xa8, 0x2f, 0x22, 0xae, 0x64, 0xd0, 0x01, - 0x21, 0xe7, 0xc1, 0x36, 0xc9, 0x07, 0xd9, 0x52, 0x88, 0x1f, 0x76, 0x10, 0x09, 0xcc, 0x5c, 0xbf, - 0xd8, 0x29, 0xff, 0xd9, 0x41, 0xb8, 0x4d, 0x44, 0x98, 0x68, 0xd8, 0x72, 0x40, 0x9b, 0x02, 0x14, - 0x0c, 0x3e, 0xaf, 0xe0, 0x03, 0xf5, 0x2d, 0xca, 0xff, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x40, 0x07, 0xac, 0x9b, 0x5d, 0xf4, 0x1d, 0xdd, 0x6b, 0xd5, 0x5a, + 0xf1, 0xef, 0x4c, 0x4b, 0x38, 0x51, 0x2c, 0x5e, 0x3e, 0xed, 0x96, 0x68, 0xad, 0xda, 0x7e, 0xf0, + 0x11, 0xa2, 0x77, 0x1a, 0xf0, 0xe6, 0x27, 0x8e, 0xaf, 0xd1, 0xa3, 0x5c, 0x1b, 0xbb, 0x3b, 0x7e, + 0xf7, 0xd7, 0x80, 0x80, 0x71, 0x9d, 0x4b, 0xa5, 0xdf, 0x9e, 0x82, 0x18, 0xa1, 0x1a, 0x5b, 0x6c, + 0xc8, 0x7c, 0x07, 0x09, 0xa8, 0xfd, 0xc6, 0x46, 0x6d, 0x00, 0xeb, 0xc3, 0x82, 0x94, 0xb5, 0x54, + 0x6f, 0xbc, 0x65, 0xbd, 0xb8, 0xcc, 0x4a, 0xde, 0xca, 0x33, 0xf9, 0xfd, 0x47, 0xb6, 0x77, 0x54, + 0xf4, 0xec, 0xfc, 0x3a, 0xa2, 0xf9, 0x2d, 0x9c, 0xd5, 0x89, 0x90, 0x79, 0xb7, 0x52, 0xc2, 0x61, + 0x8f, 0x07, 0x41, 0xc7, 0x1f, 0x2e, 0x5c, 0xf2, 0xe5, 0xd3, 0x80, 0x9d, 0x28, 0x89, 0x37, 0xab, + 0xdd, 0xc0, 0x63, 0xc6, 0x21, 0x29, 0x84, 0x7a, 0x71, 0x23, 0x82, 0x92, 0x81, 0xb2, 0x38, 0x36, + 0xa7, 0xe9, 0xef, 0xa9, 0x60, 0x09, 0x32, 0x8a, 0x68, 0xac, 0x5e, 0x20, 0x7d, 0x9c, 0xe8, 0x0c, + 0xea, 0xb9, 0x6c, 0x17, 0x10, 0xae, 0x75, 0x0f, 0x8e, 0xd1, 0x5c, 0xe4, 0x98, 0x34, 0xf5, 0x40, + 0xdb, 0x1c, 0x9e, 0xe7, 0x19, 0xd6, 0x2f, 0x8e, 0x88, 0xfc, 0x51, 0x12, 0x80, 0x57, 0x83, 0xca, + 0x56, 0x83, 0xc7, 0x68, 0xf5, 0xe4, 0x63, 0xcb, 0x98, 0xc3, 0x4d, 0x29, 0x56, 0x68, 0x7f, 0xad, + 0xa5, 0xe6, 0x01, 0x5a, 0x03, 0xdb, 0x95, 0xaa, 0xec, 0x32, 0x78, 0x3a, 0xeb, 0x24, 0x6d, 0x41, + 0x61, 0xd5, 0x3d, 0x7f, 0x56, 0xe6, 0x37, 0x8a, 0x00, 0x9e, 0x62, 0x18, 0x1d, 0xca, 0x0b, 0x7e, + 0x9a, 0x15, 0xcf, 0x6a, 0xf2, 0xb1, 0x6b, 0x4d, 0xf4, 0xdb, 0xf7, 0xe0, 0x96, 0xa6, 0xbf, 0x1d, + 0x31, 0x7d, 0x21, 0xdc, 0xbb, 0x1a, 0xe4, 0x45, 0xf8, 0xa1, 0xaa, 0x91, 0xfb, 0xc8, 0x07, 0x4d, + 0xb4, 0x36, 0x7d, 0xaa, 0x2a, 0x3e, 0x19, 0xdf, 0x59, 0x77, 0xab, 0xbc, 0xf7, 0x44, 0x89, 0xcc, + 0xe4, 0x4d, 0x3f, 0xc6, 0x5f, 0x82, 0xf0, 0xde, 0x6b, 0x83, 0xdd, 0x5b, 0xe9, 0x15, 0x89, 0x0d, + 0x56, 0x1f, 0x83, 0xc4, 0x10, 0xc5, 0xe6, 0xbe, 0xcb, 0x24, 0x6d, 0x66, 0x2b, 0xdd, 0xdf, 0xc5, + 0xa6, 0x03, 0x90, 0xe4, 0xb7, 0xc3, 0x33, 0x28, 0x59, 0xa6, 0x62, 0x45, 0xf3, 0x97, 0xbd, 0xd2, + 0x99, 0x3f, 0x82, 0x69, 0xa2, 0xcb, 0xe7, 0x2a, 0xe9, 0x51, 0xe7, 0x3d, 0x41, 0x52, 0x74, 0x7b, + 0xfd, 0x02, 0x0f, 0x74, 0xa0, 0xfe, 0xc5, 0x37, 0x51, 0x97, 0xe7, 0x1d, 0xd4, 0x9d, 0xe1, 0xe2, + 0x1e, 0xb1, 0x24, 0x88, 0xe1, 0xd6, 0x29, 0x14, 0xaf, 0xba, 0x9f, 0xd3, 0x93, 0x4a, 0x97, 0x79, + 0x82, 0xaf, 0x03, 0xa7, 0x12, 0xa2, 0x10, 0xd8, 0x8b, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3208,31 +3208,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x5e, 0x0d, 0x4b, 0x7c, 0x9d, 0x68, 0x4f, 0x49, 0x2a, 0x62, 0xd5, - 0x70, 0x54, 0x8c, 0xa4, 0x23, 0xc6, 0x6f, 0x7c, 0x84, 0x29, 0x6d, 0x91, 0x04, 0x14, 0x15, 0xb3, - 0x0e, 0x71, 0xbd, 0x62, 0x7a, 0x6f, 0x9d, 0xd7, 0x7c, 0x4c, 0xf4, 0xc6, 0xbd, 0x59, 0xed, 0x53, - 0xb4, 0xb5, 0x1b, 0x2d, 0x47, 0x21, 0x55, 0xc4, 0x56, 0xb1, 0x17, 0xb7, 0x19, 0xdb, 0x11, 0xb6, - 0x5d, 0xb3, 0x12, 0xdf, 0x5e, 0xac, 0x98, 0xdb, 0x0c, 0x03, 0xc3, 0x88, 0x81, 0xbc, 0xde, 0xf3, - 0x4c, 0x4b, 0x9b, 0xde, 0x04, 0x52, 0x4c, 0xfa, 0xe6, 0xe5, 0x36, 0x53, 0xe4, 0xa9, 0x85, 0xa1, - 0xf2, 0x99, 0x46, 0x78, 0x94, 0xb7, 0x88, 0xe0, 0xfb, 0x2d, 0xf7, 0x3f, 0x83, 0x20, 0x60, 0xd2, - 0x52, 0x4e, 0xf0, 0xc5, 0xbc, 0xf5, 0xcc, 0xd8, 0x42, 0xaf, 0xce, 0x3d, 0x46, 0xe3, 0x7f, 0xc5, - 0x8f, 0x2e, 0x9c, 0x6f, 0x3a, 0x89, 0xd3, 0x0a, 0x3a, 0x27, 0x7f, 0x9e, 0xb9, 0x9e, 0x83, 0x1f, - 0xb3, 0x50, 0xb8, 0x52, 0x21, 0x24, 0xa0, 0xe6, 0x4a, 0x8d, 0xa4, 0x91, 0x75, 0xb9, 0x76, 0x2f, - 0xd5, 0xba, 0x87, 0xf4, 0xf2, 0x65, 0x9f, 0x48, 0xa0, 0xb1, 0x56, 0x29, 0xd9, 0x18, 0x18, 0xb8, - 0xbc, 0xaf, 0xe1, 0x40, 0x35, 0xb0, 0x97, 0x1a, 0x77, 0x6b, 0x33, 0x60, 0x44, 0xc7, 0xd3, 0xb7, - 0xab, 0x19, 0x4f, 0xc4, 0xd4, 0xe0, 0x92, 0x7c, 0x7e, 0x85, 0xc4, 0xf0, 0x95, 0x04, 0xe7, 0xbb, - 0x9d, 0x8d, 0x7b, 0x9e, 0xf2, 0x0c, 0xc9, 0xc6, 0x2c, 0x13, 0xf6, 0xb7, 0xc1, 0x40, 0x5b, 0x4d, - 0xc9, 0x0e, 0xa2, 0x42, 0x72, 0x47, 0x7d, 0xe9, 0xd5, 0x97, 0xb0, 0x5a, 0xbf, 0x46, 0x8f, 0x1d, - 0x77, 0x28, 0x22, 0x39, 0x31, 0x6c, 0x80, 0xc6, 0x2f, 0x56, 0x0b, 0xd1, 0x93, 0x47, 0xcb, 0x93, - 0xc0, 0xd7, 0xbe, 0xfe, 0x21, 0xfd, 0xf2, 0x11, 0x78, 0x6a, 0x5d, 0x4e, 0x44, 0x7f, 0x99, 0x2a, - 0x50, 0x8a, 0x5b, 0x9c, 0x34, 0x50, 0xe1, 0x77, 0xfe, 0xe9, 0x4f, 0xce, 0xc3, 0xf5, 0xb4, 0x4f, - 0xa6, 0x3e, 0x0e, 0x72, 0xc7, 0x51, 0xd9, 0x02, 0xb7, 0x28, 0x7f, 0x27, 0x98, 0xad, 0x14, 0xdd, - 0x3f, 0xbc, 0x01, 0x86, 0xd3, 0xe4, 0x7b, 0x79, 0x9c, 0xa7, 0x08, 0x29, 0xc1, 0x09, 0x62, 0x18, - 0xc8, 0x5e, 0xa1, 0x34, 0xf0, 0xf2, 0x48, 0x9b, 0xc2, 0x43, 0xa9, 0xb6, 0x34, 0xa4, 0x2e, 0x21, - 0xed, 0x94, 0xaa, 0xbb, 0x66, 0x50, 0x5a, 0x45, 0x07, 0x70, 0xd8, 0x46, 0xd7, 0x0e, 0xe3, 0x12, - 0xee, 0x19, 0xad, 0x3e, 0x33, 0x9e, 0xbd, 0x39, 0x61, 0x0c, 0xc7, 0x39, 0x0c, 0x71, 0x01, 0xe3, - 0x4a, 0x8d, 0xd7, 0x6c, 0xa0, 0x34, 0xb0, 0x74, 0x05, 0x0f, 0xcb, 0x02, 0x33, 0x3f, 0x80, 0x71, - 0xe0, 0xf4, 0x09, 0x2b, 0x0d, 0x86, 0xd6, 0xd1, 0xb5, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xab, 0xf2, 0xff, 0xd7, 0x03, 0x58, 0xb3, 0xc7, 0xdb, 0xb5, 0xc8, + 0xcf, 0xde, 0xf4, 0x3d, 0xe1, 0x67, 0x8a, 0x76, 0x59, 0x3b, 0xa2, 0x10, 0x91, 0x47, 0xa6, 0x27, + 0x0c, 0xbb, 0xb3, 0x7f, 0x16, 0xc0, 0xa8, 0x89, 0x4b, 0x32, 0xdc, 0xe9, 0x85, 0x24, 0xde, 0x32, + 0x79, 0x68, 0x16, 0xf6, 0xb3, 0xbd, 0xbe, 0x9f, 0xc5, 0x2b, 0xd7, 0x57, 0xaf, 0x35, 0x5d, 0x37, + 0xda, 0x5a, 0xe1, 0x04, 0xa4, 0xac, 0x6c, 0x7b, 0x12, 0x09, 0x29, 0xaf, 0x70, 0x2f, 0xbb, 0x41, + 0x13, 0x91, 0xe3, 0xaf, 0x8c, 0xd5, 0xa3, 0x38, 0x0a, 0xb0, 0x7d, 0x15, 0x00, 0xd9, 0x07, 0x69, + 0x3c, 0xe9, 0x9d, 0xad, 0xc6, 0x34, 0x4b, 0x63, 0xfb, 0x91, 0x1d, 0x93, 0xd9, 0x6d, 0x44, 0x89, + 0xa1, 0xc5, 0x9c, 0x50, 0x0a, 0xdc, 0xd1, 0x02, 0xc3, 0x9a, 0x0a, 0x53, 0xf2, 0x2e, 0x40, 0xc8, + 0xdb, 0x75, 0xc8, 0xf4, 0xa9, 0x16, 0xee, 0x81, 0x03, 0x7f, 0x62, 0xfe, 0x98, 0x5f, 0x87, 0x0c, + 0xed, 0xa9, 0xd5, 0x04, 0x7e, 0xa7, 0x33, 0x28, 0x4c, 0xe4, 0xfc, 0x2d, 0x35, 0x76, 0x85, 0xc1, + 0xb2, 0x54, 0xb7, 0xbd, 0x5d, 0xde, 0x9c, 0xc0, 0x44, 0xc8, 0xbc, 0xa2, 0xb7, 0x6a, 0xa1, 0x42, + 0x71, 0x4a, 0x09, 0x9b, 0x19, 0x80, 0x44, 0xe3, 0x82, 0x38, 0xc0, 0xc8, 0x95, 0xd8, 0x80, 0xe5, + 0x47, 0xf2, 0xd4, 0x1b, 0xc7, 0x74, 0xb7, 0x67, 0xa5, 0x07, 0x19, 0x65, 0xb2, 0x2f, 0xaa, 0x62, + 0x99, 0xfc, 0x74, 0xc6, 0x83, 0x91, 0x9a, 0x49, 0x0a, 0x64, 0x84, 0xc7, 0x06, 0x5e, 0xe3, 0xde, + 0x32, 0xbe, 0xd4, 0x6d, 0x8e, 0x71, 0x0f, 0x57, 0xd8, 0x51, 0xda, 0xc0, 0x69, 0xa7, 0x90, 0x9e, + 0xfd, 0x32, 0xea, 0x85, 0x3d, 0x07, 0x60, 0xe3, 0x2a, 0x60, 0x0f, 0xe1, 0x77, 0x38, 0xa7, 0x45, + 0x05, 0x70, 0x23, 0x44, 0xae, 0x89, 0x02, 0x87, 0xd9, 0x54, 0x0b, 0xd6, 0x97, 0xb5, 0x0d, 0xc5, + 0x12, 0xd3, 0x91, 0x52, 0x9f, 0x37, 0xcf, 0xdf, 0x7e, 0x08, 0x79, 0x35, 0xad, 0x4a, 0xfa, 0xa5, + 0x2b, 0x34, 0xad, 0x87, 0x8a, 0xa8, 0x0b, 0x34, 0x47, 0x12, 0x1b, 0x78, 0xc3, 0x55, 0x91, 0x5a, + 0xb2, 0xdd, 0x9e, 0xc0, 0x25, 0xe7, 0x86, 0x93, 0x1a, 0xdb, 0x71, 0xea, 0xf6, 0xb8, 0xcf, 0x79, + 0x12, 0x1c, 0xf5, 0xbd, 0x5b, 0xa5, 0x0f, 0x84, 0x33, 0xba, 0x18, 0xa2, 0xdb, 0x74, 0xad, 0x3e, + 0x39, 0xe9, 0x89, 0xd7, 0xb9, 0xdf, 0x8c, 0xba, 0x3d, 0x55, 0xb6, 0x32, 0xb3, 0x8b, 0x23, 0x8c, + 0x52, 0x57, 0x66, 0x26, 0x56, 0xbf, 0x8f, 0xae, 0xf9, 0x90, 0xfd, 0xf4, 0xc3, 0x1a, 0x38, 0x77, + 0x6c, 0xf1, 0xc3, 0x61, 0xd5, 0x73, 0x11, 0x7d, 0x9c, 0x38, 0xdb, 0x75, 0x98, 0x37, 0x06, 0x99, + 0xee, 0x33, 0xfe, 0xd0, 0x9b, 0x7f, 0x80, 0x20, 0xcf, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index c66c9a3aa..f654ded1a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -35,1585 +35,1585 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 36864 -// COMPRESSED SIZE (bytes): 25192 +// COMPRESSED SIZE (bytes): 25193 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { 0xed, 0xfd, 0x43, 0xb0, 0x30, 0x4b, 0xd7, 0x00, 0x6a, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0xbb, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xbb, 0xff, 0xf1, 0x37, 0xe9, - 0x8e, 0xe8, 0xc1, 0x1d, 0xdc, 0xf3, 0xcc, 0x6a, 0x94, 0x91, 0x55, 0x91, 0x58, 0xab, 0x12, 0x00, - 0x00, 0xff, 0xef, 0x66, 0x83, 0xc1, 0x3e, 0xda, 0xf4, 0x2d, 0xd8, 0xb2, 0x06, 0xc2, 0xbf, 0x85, - 0xdc, 0x19, 0x72, 0x90, 0x8b, 0xc7, 0x2a, 0x7c, 0xfa, 0xb8, 0x2d, 0x8e, 0x55, 0xec, 0xcc, 0x44, - 0xb8, 0x25, 0x69, 0xc1, 0x4d, 0x98, 0x33, 0x51, 0xeb, 0xeb, 0x1c, 0x1d, 0x62, 0x17, 0xae, 0x12, - 0x2b, 0x75, 0xdf, 0xe1, 0x5f, 0xf4, 0xec, 0x80, 0xd7, 0xe5, 0x47, 0x7d, 0x6d, 0x34, 0x28, 0xfe, - 0x9e, 0xf5, 0xd1, 0x75, 0xda, 0x95, 0x32, 0x16, 0x43, 0x1d, 0xd2, 0x01, 0x59, 0xed, 0x93, 0x6a, - 0x73, 0x43, 0xb1, 0xd9, 0xb6, 0x29, 0x6c, 0x89, 0x9d, 0xc4, 0x12, 0x00, 0x59, 0x1f, 0xca, 0xd7, - 0x50, 0x83, 0xed, 0xb5, 0x51, 0x56, 0xa8, 0x78, 0x39, 0x5c, 0x7d, 0x7a, 0x74, 0xad, 0x23, 0xcc, - 0x9d, 0x88, 0xae, 0x6f, 0x3d, 0xd2, 0x75, 0x0a, 0xa9, 0x79, 0x2f, 0x08, 0xc6, 0x29, 0x33, 0x18, - 0x39, 0xb7, 0xe4, 0x27, 0x77, 0x48, 0x02, 0x2f, 0xea, 0x06, 0x45, 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0xb9, 0x5d, 0xbb, 0xfe, 0x07, 0x36, 0x33, 0x24, 0x13, 0xb8, + 0x77, 0xc0, 0x59, 0xb9, 0x12, 0xcd, 0x0d, 0xd4, 0xe4, 0x0b, 0x41, 0x31, 0xc5, 0xf5, 0x6e, 0x2e, + 0x69, 0x8f, 0x0f, 0x34, 0x0d, 0x77, 0x40, 0xd0, 0x16, 0xcc, 0xc3, 0x84, 0x32, 0xbd, 0x3f, 0xd7, + 0x4b, 0x51, 0x4d, 0x3a, 0x04, 0x98, 0x78, 0x0e, 0x0f, 0xfe, 0x16, 0x57, 0x28, 0x21, 0x7a, 0xb2, + 0xa3, 0xd1, 0x55, 0x57, 0xad, 0x52, 0x28, 0xe2, 0xa5, 0xa0, 0x62, 0x0d, 0xa9, 0x76, 0xff, 0x60, + 0xf2, 0xd1, 0x56, 0x17, 0x86, 0x34, 0xbd, 0xed, 0xd6, 0x52, 0x9a, 0x95, 0x5c, 0xea, 0x1c, 0x73, + 0xc7, 0x3f, 0x06, 0x38, 0xc1, 0x73, 0x0b, 0xb3, 0xb8, 0x83, 0xf1, 0x3c, 0xce, 0xc6, 0x60, 0xdf, + 0xa3, 0xe8, 0x3d, 0x98, 0x8d, 0x3a, 0x97, 0xe2, 0xab, 0x70, 0x2e, 0xfd, 0x30, 0x1b, 0xb2, 0x6f, + 0x9f, 0xcf, 0x6c, 0xd3, 0xe5, 0xe0, 0x1a, 0x5a, 0x3d, 0x5a, 0xd7, 0x5b, 0x1b, 0x12, 0xee, 0x39, + 0x92, 0x5b, 0x9c, 0xd6, 0xe7, 0x99, 0x69, 0xa6, 0x4c, 0x1d, 0x73, 0xd8, 0x8b, 0x0f, 0xb3, 0x41, + 0xdc, 0x7f, 0x09, 0x70, 0x0a, 0x1b, 0xe4, 0x6d, 0x36, 0x88, 0xc5, 0x30, 0x34, 0xf7, 0x2a, 0x73, + 0x83, 0x97, 0x53, 0x1d, 0x6f, 0xff, 0xaf, 0x92, 0x2c, 0x92, 0xeb, 0xc1, 0x7a, 0x98, 0x93, 0x0d, + 0xe4, 0x0e, 0x93, 0xaa, 0x7f, 0x7b, 0x52, 0x53, 0x6a, 0x77, 0x0c, 0x5b, 0x33, 0x17, 0xec, 0x43, + 0xbb, 0xfc, 0x97, 0x30, 0x38, 0x2b, 0xc3, 0x01, 0x1b, 0x61, 0x3a, 0x99, 0x1c, 0xd2, 0x82, 0xba, + 0xa1, 0xd9, 0x6d, 0x14, 0xc1, 0x06, 0xa3, 0x8f, 0xb6, 0x92, 0x6a, 0xc6, 0x4d, 0x64, 0x88, 0x19, + 0xde, 0x80, 0xf6, 0x39, 0x1e, 0xe7, 0xee, 0x7f, 0xaf, 0xbf, 0xf3, 0x49, 0x0e, 0x05, 0xfb, 0x05, + 0x61, 0x4d, 0xd8, 0xd7, 0x97, 0xcb, 0x0e, 0x7d, 0x3e, 0xd9, 0x2c, 0xf3, 0x68, 0xba, 0x97, 0x00, + 0x7e, 0x70, 0x43, 0xd4, 0x71, 0x44, 0x5e, 0x59, 0xe0, 0x8d, 0x01, 0x92, 0xc7, 0xba, 0x35, 0xd2, + 0x46, 0x17, 0x5c, 0x7e, 0xb9, 0x52, 0x5e, 0xf0, 0x60, 0x89, 0x2e, 0xae, 0x54, 0x13, 0x53, 0xd6, + 0xf7, 0xdd, 0xd6, 0xf3, 0x47, 0xcd, 0x46, 0x57, 0xf8, 0xd5, 0x44, 0x30, 0xc4, 0x26, 0xee, 0xf0, + 0x17, 0x97, 0x99, 0x1a, 0x32, 0xf9, 0xf3, 0x11, 0xb1, 0xf6, 0xf5, 0xed, 0x98, 0x67, 0x1b, 0xd0, + 0x94, 0xee, 0x4e, 0x53, 0x73, 0xf5, 0xfd, 0x07, 0x3d, 0x18, 0x38, 0xe0, 0x52, 0xe4, 0x0e, 0xfc, + 0xf2, 0x77, 0x43, 0x9d, 0x63, 0x0f, 0xe2, 0xb3, 0x77, 0xe5, 0xe8, 0x8b, 0x92, 0x7c, 0x39, 0xc9, + 0xf8, 0xef, 0x01, 0x0c, 0x53, 0x49, 0xa3, 0x29, 0xc8, 0xfd, 0xff, 0xdf, 0xf6, 0xff, 0xd3, 0xe7, + 0x6f, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, + 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, + 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, + 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xff, 0xdd, 0xff, + 0x07, 0x50, 0x15, 0x4e, 0x6d, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1624,7 +1624,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 36864, // uncompressed data size (bytes) - 25192, // compressed data size (bytes) + 25193, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2239,8 +2239,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0xd1, 0xdf, 0x2f, 0x96, 0xa8, 0x17, 0xfc, 0xea, 0x7f, 0x2b, 0x42, 0xb2, 0xbf, 0xcf, 0x68, 0x7c, 0xb7, 0x5b, 0xec, 0x38, 0x09, 0x89, 0xeb, 0x7c, 0xad, 0xa7, 0xc2, 0x15, 0x04, 0xfe, 0xac, 0x45, 0xe3, 0xd1, 0xff, 0x89, 0xb0, 0x46, 0x68, 0xfc, 0x48, 0xe0, 0x23, 0x45, 0x3d, 0xfd, 0xb3, 0xc6, - 0xbe, 0x63, 0xc4, 0x91, 0xa0, 0xd5, 0x95, 0x98, 0xca, 0xa8, 0xa5, 0x13, 0x06, 0x0d, 0x37, 0xea, - 0x46, 0xdd, 0xc8, 0xd0, 0xe9, 0x11, 0x0d, 0xe2, 0xa5, 0xed, 0xec, 0x39, 0x67, 0x4e, 0x20, 0xe0, + 0xbe, 0xcb, 0x27, 0x72, 0x07, 0x76, 0x59, 0x28, 0x09, 0x63, 0x48, 0xa7, 0x59, 0x83, 0x32, 0x9a, + 0x0e, 0xd9, 0xc8, 0xd0, 0xe9, 0x11, 0x0d, 0xe2, 0xa5, 0xed, 0xec, 0x39, 0x67, 0x4e, 0x20, 0xe0, 0xbe, 0x9b, 0x00, 0x24, 0x7e, 0x9b, 0xaa, 0xb3, 0xfd, 0x21, 0x34, 0xaf, 0xb8, 0x1f, 0x4f, 0x4f, 0x78, 0xd7, 0x47, 0x09, 0x3d, 0x49, 0xb9, 0x99, 0x2c, 0x2f, 0xce, 0x00, 0xe7, 0xd9, 0x1f, 0x14, 0x5a, 0xca, 0x1f, 0xcc, 0x14, 0xf0, 0xf6, 0x35, 0x6a, 0xa2, 0x26, 0x6a, 0x2c, 0x03, 0x3d, 0xfe, @@ -2268,8 +2268,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0xe4, 0xb7, 0x4f, 0xb9, 0x4a, 0xf8, 0x49, 0x51, 0x11, 0x5d, 0xbf, 0xcf, 0x48, 0x50, 0x0f, 0xa6, 0x48, 0x21, 0xf5, 0x8f, 0xcf, 0xa4, 0xbf, 0xbe, 0xcf, 0xf9, 0x65, 0x70, 0x54, 0xfe, 0x78, 0x6c, 0x5e, 0xde, 0x55, 0x66, 0x22, 0xd7, 0xfb, 0x04, 0x72, 0x19, 0xa5, 0x27, 0xf0, 0x83, 0xc6, 0x12, - 0x47, 0xa8, 0x88, 0xe6, 0xa9, 0x44, 0x87, 0x87, 0x23, 0x3c, 0xcc, 0xce, 0x1a, 0x31, 0xf8, 0x40, - 0x47, 0x58, 0xe4, 0x34, 0x0f, 0xd1, 0x39, 0x66, 0xb4, 0x38, 0x9b, 0xff, 0xf9, 0x9a, 0xa0, 0x82, + 0x47, 0xa8, 0x10, 0x79, 0x95, 0xc5, 0x95, 0xe2, 0x4b, 0x72, 0x46, 0xba, 0x52, 0x8d, 0xdc, 0xd5, + 0xe2, 0x46, 0xe4, 0x34, 0x0f, 0xd1, 0x39, 0x66, 0xb4, 0x38, 0x9b, 0xff, 0xf9, 0x9a, 0xa0, 0x82, 0x51, 0x70, 0xfc, 0x30, 0xf1, 0xfb, 0x61, 0x32, 0xa7, 0xf7, 0xb4, 0x0a, 0xee, 0x25, 0xc1, 0x92, 0x56, 0x06, 0x74, 0xca, 0x5d, 0x69, 0x37, 0x71, 0x32, 0x5b, 0xd1, 0xf9, 0x20, 0xc0, 0x99, 0x81, 0xef, 0x28, 0x0e, 0xae, 0x29, 0x16, 0x64, 0xdd, 0x3e, 0x8f, 0x13, 0x6f, 0xa7, 0x64, 0x58, 0x81, @@ -2306,8 +2306,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0xd2, 0xea, 0x8e, 0x44, 0x3e, 0x04, 0xbe, 0xee, 0x22, 0xc0, 0x0e, 0xbf, 0xba, 0x6d, 0x7e, 0x5b, 0x1b, 0x4f, 0xe2, 0x65, 0xea, 0xa9, 0xbe, 0x2f, 0xc5, 0x14, 0xa4, 0x9f, 0xcd, 0x5e, 0x21, 0x44, 0xa6, 0xe7, 0x63, 0x3d, 0x0a, 0xd7, 0xb3, 0x5e, 0x8f, 0x79, 0xdc, 0x93, 0x1e, 0x38, 0xd7, 0x86, - 0x5a, 0x20, 0x4c, 0x15, 0x97, 0xe2, 0x8e, 0x2d, 0x74, 0x08, 0x73, 0xfa, 0x5f, 0x7a, 0x8a, 0xeb, - 0xcb, 0xbe, 0x57, 0xf2, 0x3f, 0x69, 0x7b, 0xdb, 0x41, 0xad, 0xdf, 0x97, 0x68, 0xba, 0x62, 0xd9, + 0x5a, 0x20, 0x36, 0xdc, 0xe4, 0x64, 0x21, 0xee, 0xb4, 0x18, 0x08, 0x13, 0x4c, 0x4d, 0xc3, 0xf3, + 0x29, 0xd9, 0x57, 0xf2, 0x3f, 0x69, 0x7b, 0xdb, 0x41, 0xad, 0xdf, 0x97, 0x68, 0xba, 0x62, 0xd9, 0x06, 0xdc, 0xe2, 0x5a, 0xc0, 0x5e, 0x06, 0xa1, 0x36, 0x04, 0xce, 0x44, 0xe2, 0x6b, 0x28, 0xd1, 0x46, 0x7f, 0x87, 0x34, 0x3d, 0x9c, 0xfe, 0xb8, 0x5e, 0x1c, 0x52, 0x71, 0xb3, 0xb6, 0x36, 0xa4, 0x49, 0xc7, 0xb4, 0x1a, 0xef, 0x9f, 0x8c, 0xf5, 0x00, 0x61, 0xb2, 0x69, 0x86, 0x12, 0xea, 0x7a, @@ -2336,8 +2336,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0x19, 0x7b, 0x49, 0xe8, 0xd8, 0xa4, 0x20, 0x8b, 0xae, 0x1b, 0x4d, 0xd5, 0x24, 0xed, 0x65, 0x23, 0x19, 0xc8, 0x1e, 0x84, 0x0b, 0xa7, 0xf3, 0x68, 0x6b, 0xd8, 0x6b, 0x6e, 0x65, 0x3a, 0xd2, 0x4f, 0x1d, 0x47, 0x83, 0x18, 0xb3, 0x91, 0x17, 0xf0, 0xc2, 0x65, 0xfd, 0x3e, 0xf1, 0xab, 0xa3, 0x49, - 0xf5, 0xab, 0xe5, 0x3d, 0x92, 0x88, 0x4e, 0xad, 0x5a, 0xcf, 0xc9, 0x5d, 0x67, 0xdf, 0xf3, 0xf7, - 0xdc, 0xd4, 0x22, 0xa2, 0x95, 0x20, 0x62, 0xcc, 0x9a, 0x3d, 0x3d, 0x19, 0x1d, 0xa8, 0x09, 0xfb, + 0xf5, 0xab, 0xa7, 0x00, 0x73, 0x4e, 0x89, 0xe8, 0x8c, 0xe6, 0x4a, 0x33, 0x7d, 0xb8, 0x90, 0xaf, + 0x7c, 0xb6, 0x22, 0xa2, 0x95, 0x20, 0x62, 0xcc, 0x9a, 0x3d, 0x3d, 0x19, 0x1d, 0xa8, 0x09, 0xfb, 0xd7, 0xf2, 0x08, 0xdf, 0xdc, 0x11, 0xbb, 0x2a, 0x30, 0x9b, 0xb0, 0x88, 0x97, 0x00, 0x47, 0xe0, 0xe0, 0x95, 0x03, 0x24, 0x43, 0xc3, 0x9b, 0x67, 0x8a, 0x1a, 0x56, 0xe2, 0xd0, 0x03, 0x5a, 0xa1, 0x38, 0xa9, 0xee, 0x2f, 0xd4, 0xd5, 0x06, 0xfe, 0x50, 0x63, 0x3f, 0x97, 0x1f, 0xe7, 0x3f, 0xe3, @@ -2731,8 +2731,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0x8b, 0xe2, 0xda, 0x71, 0x32, 0x26, 0x86, 0x6d, 0xd8, 0x01, 0x35, 0x7d, 0x15, 0x4c, 0xb8, 0x56, 0x07, 0x41, 0x87, 0xa3, 0x33, 0xc8, 0x8e, 0x63, 0x7e, 0x89, 0x3f, 0x10, 0x14, 0x84, 0xa8, 0xbc, 0xe5, 0xab, 0xed, 0xe8, 0x3d, 0x86, 0xd1, 0xda, 0x3d, 0xb3, 0x52, 0xfe, 0x45, 0x19, 0xed, 0xf6, - 0xcc, 0xb7, 0x3f, 0x40, 0xa2, 0xe2, 0x25, 0x3f, 0x7e, 0x16, 0x89, 0x15, 0x23, 0x8a, 0xdf, 0xa0, - 0x07, 0xe0, 0x84, 0xfc, 0xb3, 0x9e, 0xaa, 0xb3, 0x60, 0x80, 0x3e, 0x75, 0x68, 0x58, 0xaf, 0x33, + 0xcc, 0x37, 0xff, 0x30, 0x21, 0x1e, 0x06, 0xfc, 0x98, 0xdc, 0x20, 0x48, 0x99, 0x72, 0x6c, 0xa5, + 0x6d, 0xca, 0x84, 0xfc, 0xb3, 0x9e, 0xaa, 0xb3, 0x60, 0x80, 0x3e, 0x75, 0x68, 0x58, 0xaf, 0x33, 0x6c, 0xf4, 0xfd, 0x68, 0x77, 0xd9, 0xd7, 0x4a, 0x21, 0x08, 0x98, 0xe0, 0xc6, 0xcd, 0xd5, 0xb9, 0x1d, 0x30, 0xdb, 0x1b, 0x58, 0x80, 0x5e, 0x31, 0x69, 0x4d, 0xf8, 0x24, 0xf0, 0x8f, 0x16, 0xe5, 0x68, 0xfd, 0x37, 0xf5, 0x92, 0xdf, 0x44, 0x81, 0xe2, 0x67, 0x27, 0x9d, 0x16, 0xbf, 0x35, 0xb9, @@ -2783,8 +2783,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0x31, 0xf9, 0x15, 0x3c, 0x0b, 0xc1, 0xe6, 0x9c, 0xd0, 0x04, 0x4d, 0xb4, 0x02, 0x07, 0xe9, 0xbf, 0x54, 0x5c, 0x00, 0x47, 0x3a, 0x58, 0xf5, 0x6c, 0xbd, 0x89, 0xee, 0x42, 0xc1, 0x44, 0xc5, 0x19, 0x4e, 0x71, 0xb8, 0x4b, 0x5b, 0xbe, 0x17, 0x48, 0xd4, 0xab, 0xf8, 0xd4, 0x5d, 0x41, 0x5c, 0x52, - 0xab, 0xa2, 0xf0, 0x5f, 0xf9, 0x90, 0x64, 0x07, 0x88, 0xe1, 0xf5, 0x7a, 0x97, 0x1b, 0xdc, 0x40, - 0xc6, 0x8e, 0xa8, 0xd0, 0xa4, 0x05, 0xb4, 0x11, 0x7d, 0xdc, 0xd5, 0xf6, 0xd4, 0x13, 0x30, 0xc3, + 0xab, 0xa2, 0x30, 0x92, 0xb1, 0xcd, 0x9a, 0xfe, 0x59, 0xd7, 0x83, 0xc1, 0x1f, 0x31, 0x33, 0xd9, + 0xd8, 0x79, 0xa9, 0xd0, 0xa4, 0x05, 0xb4, 0x11, 0x7d, 0xdc, 0xd5, 0xf6, 0xd4, 0x13, 0x30, 0xc3, 0x68, 0x03, 0x9a, 0x3b, 0x24, 0xfe, 0x0b, 0x60, 0xbf, 0x52, 0xdf, 0x30, 0xde, 0x96, 0x43, 0x9c, 0x45, 0x3d, 0xa2, 0x90, 0x7d, 0x04, 0xb9, 0xca, 0xe5, 0xdd, 0x0f, 0x3f, 0xda, 0xa1, 0xa6, 0xb9, 0x32, 0xdf, 0x3e, 0x77, 0x1a, 0x64, 0x9d, 0x5b, 0x03, 0x82, 0xa9, 0xac, 0x4f, 0x78, 0x08, 0xc6, @@ -2829,9 +2829,9 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0x67, 0x6d, 0xda, 0xc8, 0x0c, 0xcc, 0xd6, 0x8b, 0x71, 0xed, 0x69, 0x7a, 0x9d, 0x35, 0xa5, 0x04, 0xc3, 0x17, 0x26, 0xba, 0x89, 0xe6, 0x6a, 0xcb, 0xe9, 0x48, 0x73, 0xa1, 0x22, 0x24, 0x08, 0x62, 0xa7, 0x39, 0xdb, 0x2b, 0x86, 0x3c, 0x1f, 0x62, 0xe6, 0x43, 0xb3, 0x7b, 0x6b, 0xa7, 0x0e, 0x5e, - 0xaa, 0x57, 0x05, 0xba, 0xe5, 0xd2, 0x60, 0x3d, 0x1a, 0x71, 0xba, 0xe3, 0x75, 0xee, 0x9d, 0xfc, - 0x10, 0x94, 0x33, 0x51, 0x45, 0x1e, 0x12, 0x62, 0xd5, 0xdc, 0x62, 0x68, 0x0b, 0xdf, 0xef, 0x60, - 0xf8, 0x3f, 0x94, 0x6b, 0x3d, 0xa6, 0xff, 0xbb, 0x5e, 0xf0, 0xf6, 0xef, 0x59, 0x77, 0x53, 0xa4, + 0xaa, 0x57, 0x05, 0xba, 0xe5, 0xd2, 0x35, 0x67, 0xd3, 0xa7, 0x87, 0x95, 0x26, 0x46, 0x4b, 0xb9, + 0x47, 0x9e, 0xac, 0x66, 0x0b, 0x4e, 0x98, 0xfa, 0xdc, 0xc3, 0xc9, 0xeb, 0x68, 0x56, 0x96, 0x5c, + 0x0b, 0x03, 0x9b, 0x3e, 0xa5, 0x3b, 0xff, 0xbb, 0x5e, 0xf0, 0xf6, 0xef, 0x59, 0x77, 0x53, 0xa4, 0x75, 0x3a, 0x9e, 0xc9, 0xa2, 0x99, 0x0f, 0x9f, 0x16, 0x0b, 0x58, 0x40, 0xb9, 0x50, 0x49, 0x1b, 0x1c, 0x9e, 0x80, 0xfb, 0x7b, 0xb0, 0x9b, 0xa9, 0xc4, 0xab, 0x13, 0x5f, 0xb0, 0x88, 0x04, 0x13, 0x64, 0x3c, 0x0a, 0x2f, 0x1c, 0x9b, 0x5e, 0x8f, 0x5a, 0x66, 0x6b, 0x36, 0xaa, 0x62, 0x37, 0xa5, @@ -3253,7 +3253,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, - 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xdf, 0xf7, 0x7f, 0x01, 0x8e, 0x22, 0x30, 0x2a, + 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xdf, 0xf7, 0x7f, 0x01, 0x5a, 0xfd, 0x31, 0xbd, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3321,55 +3321,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xd2, 0x1b, 0x50, 0xcd, 0xb8, 0xb5, 0xe7, 0x98, 0xd9, 0x8d, 0x3e, - 0x75, 0x5c, 0x30, 0x3d, 0x12, 0x2b, 0x80, 0x0f, 0xe3, 0x4b, 0x02, 0x94, 0x84, 0x47, 0xb9, 0x93, - 0x80, 0x13, 0x29, 0xcf, 0x18, 0xb1, 0x10, 0xae, 0xe6, 0x00, 0xc7, 0xa6, 0x97, 0xd2, 0x96, 0x5f, - 0x49, 0x7b, 0xb8, 0x65, 0xe2, 0xfe, 0x2f, 0xab, 0x61, 0x6a, 0xf2, 0xa2, 0x31, 0x72, 0x37, 0xb3, - 0x32, 0x02, 0x34, 0x17, 0xf9, 0xf2, 0x79, 0xdc, 0x72, 0x46, 0x1a, 0x22, 0xb0, 0x52, 0xf7, 0xbd, - 0xb5, 0xb7, 0xf7, 0xf0, 0x2a, 0xd6, 0xc9, 0xa7, 0xe5, 0x6e, 0xf9, 0x93, 0x94, 0x1b, 0xe9, 0xd0, - 0x75, 0xff, 0x84, 0xb6, 0xf4, 0x53, 0xf4, 0x9f, 0x84, 0xad, 0xc5, 0x2f, 0x9f, 0x6e, 0x89, 0xcf, - 0x1f, 0x99, 0x69, 0x14, 0x42, 0x4d, 0x07, 0x8c, 0xa6, 0xfe, 0x6d, 0xe7, 0xea, 0xac, 0x85, 0xc1, - 0x33, 0x64, 0x5c, 0xe9, 0x89, 0xd9, 0x6c, 0x43, 0xd1, 0x33, 0x7f, 0x30, 0xce, 0xab, 0xc1, 0x6f, - 0x14, 0x0d, 0xab, 0x45, 0x8f, 0x76, 0x9f, 0xb5, 0xa7, 0x52, 0x41, 0xc8, 0xe3, 0x2b, 0xc9, 0xa9, - 0x87, 0x34, 0x8e, 0x99, 0x79, 0x77, 0x8a, 0x64, 0x11, 0xbc, 0x5a, 0x26, 0x92, 0x2b, 0x6f, 0xa5, - 0x02, 0xe7, 0xfa, 0xce, 0x24, 0xe9, 0x07, 0x64, 0xcb, 0xed, 0x8a, 0xc2, 0xe9, 0x7a, 0x2a, 0x4b, - 0xca, 0xb0, 0xb6, 0xb9, 0xc8, 0xcb, 0x6c, 0x39, 0x2c, 0xc3, 0x17, 0x55, 0x63, 0xb9, 0xdd, 0x30, - 0x15, 0x8c, 0x96, 0x83, 0xff, 0x9a, 0x97, 0xf3, 0x82, 0xb3, 0x39, 0x6a, 0x63, 0x24, 0x6e, 0x7d, - 0xdb, 0xcb, 0xbc, 0x0a, 0x4a, 0x00, 0xa9, 0x70, 0xc1, 0x23, 0xf1, 0xf8, 0x0b, 0xde, 0xdb, 0xd8, - 0xf0, 0x48, 0xd0, 0x3a, 0xb9, 0xd2, 0x9c, 0x7a, 0xdc, 0x5f, 0x52, 0xae, 0x96, 0x68, 0x2b, 0x71, - 0xff, 0x26, 0x8e, 0x18, 0x9d, 0xf8, 0x7a, 0x69, 0x01, 0x3e, 0xa3, 0xbd, 0xb8, 0xcf, 0x12, 0xc4, - 0x6b, 0x21, 0x2c, 0x25, 0x22, 0x4f, 0x9f, 0x4c, 0x99, 0x06, 0x68, 0x23, 0x8c, 0x83, 0x9c, 0xed, - 0x1e, 0x64, 0x08, 0xc6, 0xdd, 0xf3, 0x26, 0x96, 0xb0, 0x57, 0x97, 0x47, 0x1a, 0xe5, 0x64, 0x63, - 0xf6, 0xd8, 0xfd, 0x26, 0x68, 0x47, 0x94, 0xd6, 0xc8, 0xc3, 0xcc, 0x57, 0x28, 0x01, 0xa2, 0x19, - 0xb1, 0x47, 0xcd, 0x47, 0x38, 0xa6, 0x09, 0xe5, 0xc3, 0x18, 0xf8, 0x10, 0xcd, 0x6d, 0xf5, 0x46, - 0xd8, 0xf5, 0x30, 0x3d, 0x72, 0x8e, 0x18, 0xd5, 0x18, 0x76, 0xf0, 0xdd, 0x86, 0x2c, 0x71, 0x0d, - 0x2d, 0xc6, 0x03, 0xfe, 0x9c, 0x07, 0x0b, 0x1a, 0xc7, 0x39, 0x72, 0x6b, 0xac, 0xc5, 0x35, 0xda, - 0x40, 0x02, 0xa5, 0x4b, 0x3c, 0xfe, 0xf8, 0x51, 0x44, 0x93, 0x6b, 0x0e, 0x98, 0x38, 0x50, 0x35, - 0xc2, 0x59, 0xe4, 0xe5, 0x8e, 0x95, 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0xaa, 0xc5, 0x4a, 0x33, 0xf8, 0xc4, 0xad, 0x66, 0x5d, 0x8d, 0x94, 0xd7, 0x55, 0x81, + 0xbb, 0x48, 0xa3, 0x9a, 0x39, 0x1a, 0xc6, 0xa3, 0x5f, 0xb7, 0x6a, 0x56, 0x4a, 0x84, 0x8c, 0x0b, + 0x01, 0x9f, 0x14, 0xbc, 0x32, 0x13, 0x82, 0xa8, 0x47, 0xa8, 0x34, 0xde, 0xa3, 0x32, 0xeb, 0xb9, + 0x3a, 0xc0, 0x16, 0xe7, 0xd3, 0x17, 0xb8, 0xeb, 0x1d, 0x8a, 0x53, 0x62, 0x97, 0x46, 0x10, 0xba, + 0x35, 0x9d, 0x92, 0xdc, 0xa7, 0xfe, 0xf7, 0x16, 0x26, 0x3a, 0x4d, 0x24, 0x03, 0x57, 0x99, 0x0e, + 0x14, 0x3e, 0xd7, 0x48, 0x1a, 0xdc, 0x80, 0xe0, 0x26, 0xe0, 0x2f, 0x87, 0xd4, 0x13, 0xe3, 0x14, + 0xd6, 0x3c, 0xeb, 0x59, 0x90, 0xcd, 0x1c, 0x31, 0xcc, 0x60, 0x38, 0x13, 0x43, 0x76, 0xe5, 0xe1, + 0xc4, 0xb6, 0xbb, 0xe3, 0x7b, 0x06, 0xde, 0x6d, 0xf0, 0xbb, 0xde, 0xaa, 0x30, 0x17, 0x8b, 0x3c, + 0x94, 0x95, 0x8e, 0xac, 0xb2, 0x41, 0x29, 0x84, 0xe6, 0xee, 0x9f, 0x5e, 0xdf, 0x73, 0xc8, 0xce, + 0xca, 0xb9, 0x1f, 0x2b, 0xf7, 0x2d, 0xf1, 0x8d, 0xfe, 0xeb, 0x51, 0x6e, 0xe2, 0xda, 0x4e, 0xba, + 0xb0, 0x37, 0x8f, 0xf1, 0x71, 0x38, 0x97, 0xb3, 0x23, 0x65, 0xfd, 0xf5, 0xf9, 0xb5, 0xb5, 0xd0, + 0xf0, 0x85, 0x1c, 0x94, 0x97, 0xbe, 0x2c, 0xd4, 0x05, 0xee, 0xcf, 0xc8, 0xa6, 0xaf, 0xcc, 0x77, + 0xac, 0x5e, 0x01, 0x4f, 0x10, 0xd1, 0x21, 0x53, 0x15, 0xa3, 0x76, 0x82, 0x31, 0x69, 0x63, 0x95, + 0x7c, 0x8d, 0xf6, 0x7e, 0x9b, 0x9e, 0x15, 0xfd, 0xb7, 0x3c, 0xc9, 0xb5, 0xc1, 0xaa, 0xfe, 0x27, + 0xb7, 0x4f, 0xf9, 0xf2, 0x08, 0x36, 0x0b, 0x14, 0x62, 0x8f, 0xe0, 0x47, 0xb9, 0xf0, 0x80, 0x79, + 0x54, 0x10, 0x09, 0x5e, 0x9f, 0xd1, 0x46, 0x32, 0xca, 0xe5, 0x6e, 0x4d, 0xf8, 0x92, 0x0b, 0xd9, + 0x4d, 0xe2, 0x71, 0xac, 0xd6, 0x63, 0x34, 0x69, 0x57, 0x93, 0xf5, 0xfd, 0x6a, 0x98, 0xe5, 0xb4, + 0xa2, 0xee, 0xa7, 0xd1, 0x86, 0x69, 0x0c, 0x9c, 0xc6, 0xd7, 0x04, 0x82, 0x3a, 0x9f, 0x41, 0x0c, + 0xaf, 0x1d, 0xa8, 0x7c, 0x07, 0x60, 0x2f, 0x80, 0x40, 0xc2, 0x6b, 0xc6, 0x33, 0x35, 0x6f, 0xa5, + 0x94, 0xdd, 0xd8, 0xae, 0x58, 0x98, 0xaa, 0x53, 0x29, 0xe3, 0x1e, 0x37, 0x52, 0xc5, 0x63, 0x1d, + 0xe3, 0x81, 0x5b, 0x80, 0x0c, 0x45, 0x27, 0x85, 0x9f, 0xb3, 0x87, 0x62, 0xb9, 0x7b, 0xc7, 0x40, + 0xe2, 0x45, 0xf0, 0xc2, 0xaf, 0x3f, 0x19, 0x6b, 0xf0, 0x31, 0xf3, 0x24, 0x5e, 0xab, 0x6f, 0x8f, + 0xea, 0x9b, 0x61, 0x89, 0xba, 0x2f, 0x51, 0xad, 0x89, 0xc7, 0x1b, 0x3e, 0x6a, 0x87, 0xb4, 0xd8, + 0x70, 0x09, 0x34, 0xc6, 0x6c, 0xb4, 0x95, 0x27, 0x81, 0xa3, 0xd3, 0xd3, 0xcf, 0x6a, 0xc7, 0x1f, + 0xa3, 0xd8, 0xc7, 0x6c, 0x18, 0xe5, 0x65, 0xfa, 0x0d, 0x43, 0xcb, 0x74, 0xce, 0x59, 0x2d, 0x58, + 0xfa, 0x02, 0x99, 0xdd, 0x63, 0x1b, 0x1f, 0x48, 0x8f, 0xd8, 0x22, 0xb1, 0x6d, 0xea, 0x79, 0xa9, + 0x6a, 0xbc, 0xdd, 0xe3, 0xc5, 0x82, 0xaa, 0x92, 0x75, 0xb9, 0x0e, 0x6a, 0xf1, 0xd9, 0xbe, 0x80, + 0xae, 0xc9, 0x03, 0x13, 0x18, 0xf1, 0x13, 0xc0, 0x77, 0x01, 0xc3, 0x32, 0x17, 0xcc, 0xab, 0xcf, + 0x0d, 0xca, 0x45, 0x07, 0x47, 0xe4, 0xb8, 0xf4, 0x95, 0x9b, 0xec, 0xca, 0x6a, 0x62, 0x79, 0x64, + 0xd6, 0xdd, 0x01, 0x5a, 0x19, 0xbc, 0x86, 0xb3, 0x90, 0x88, 0x68, 0xcc, 0xdc, 0x21, 0x1c, 0xb2, + 0xd0, 0x87, 0x1e, 0x1d, 0x98, 0xaf, 0x94, 0x3b, 0xbb, 0xc5, 0x9e, 0x6e, 0xe4, 0x00, 0xf7, 0x72, + 0x63, 0x74, 0xf1, 0x45, 0xee, 0x4a, 0x9c, 0x0a, 0x8e, 0x44, 0x5a, 0x9c, 0x77, 0x92, 0x51, 0x05, + 0xf7, 0x1c, 0xb0, 0x7d, 0x8d, 0x38, 0xf6, 0x7c, 0xe7, 0x57, 0xba, 0x60, 0xf6, 0xf7, 0xec, 0x81, + 0xb2, 0x1d, 0xe7, 0x55, 0x62, 0x6a, 0xd9, 0x5b, 0x7a, 0xd5, 0x4f, 0xc8, 0x2c, 0x9d, 0x36, 0x8a, + 0xfb, 0xcc, 0x4e, 0xad, 0x32, 0xbc, 0xa7, 0x60, 0x7b, 0x4f, 0x8c, 0x57, 0xf5, 0xa2, 0x72, 0x48, + 0x9b, 0x45, 0x8f, 0xd6, 0x55, 0x0f, 0xdb, 0x7f, 0x6e, 0x1d, 0xc2, 0x20, 0x7d, 0x78, 0xd4, 0xde, + 0xff, 0x6a, 0x31, 0x75, 0xa0, 0x36, 0x39, 0xd4, 0x6f, 0xd7, 0xa5, 0x1d, 0x7d, 0xb9, 0xa2, 0x23, + 0xff, 0xb8, 0x8e, 0x75, 0x62, 0x2e, 0x8d, 0x55, 0xb1, 0xf1, 0x02, 0x66, 0x1a, 0xcd, 0xc6, 0xcf, + 0x06, 0xf0, 0xca, 0xcd, 0x76, 0x36, 0xb7, 0xbb, 0xfc, 0xe1, 0x1e, 0x42, 0x32, 0x91, 0x79, 0x9a, + 0x36, 0xa0, 0x2a, 0x69, 0xd3, 0x86, 0x7d, 0x14, 0x09, 0xb0, 0x0a, 0xba, 0x5d, 0xa9, 0x05, 0x13, + 0xb5, 0x58, 0x44, 0x0f, 0x70, 0x75, 0x8f, 0x74, 0x93, 0xb0, 0x20, 0xc7, 0xda, 0xa2, 0x6d, 0xb2, + 0x47, 0x91, 0x96, 0x64, 0xf1, 0x30, 0x07, 0x06, 0xe1, 0xdd, 0xe9, 0x50, 0xe7, 0x52, 0x4a, 0x1b, + 0x69, 0xdf, 0xf1, 0x5e, 0x66, 0x44, 0x75, 0xbd, 0xbd, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3398,37 +3398,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 420 +// COMPRESSED SIZE (bytes): 419 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data[] = { - 0xfb, 0xc9, 0xfb, 0xe8, 0xce, 0xa9, 0x08, 0xbd, 0xdb, 0x77, 0x56, 0x98, 0x33, 0x6f, 0xcb, 0x88, - 0x3d, 0x6f, 0x73, 0x3e, 0x7a, 0xb6, 0x4d, 0xc1, 0xeb, 0xa3, 0xc2, 0xba, 0x41, 0x95, 0xf3, 0x3d, - 0x99, 0x64, 0x92, 0x0e, 0xed, 0xdf, 0xd1, 0x36, 0xf3, 0x5d, 0xc8, 0xb2, 0x49, 0x61, 0x6a, 0x2b, - 0xde, 0xf7, 0x2f, 0x3a, 0x7f, 0x4a, 0x5c, 0x20, 0xcc, 0xe3, 0xbe, 0xc4, 0x0c, 0x6f, 0xfe, 0xea, - 0xbc, 0x0b, 0xfa, 0xcb, 0xff, 0x7b, 0xad, 0x7d, 0x52, 0x6a, 0xbf, 0x3c, 0xd0, 0x40, 0xa7, 0x73, - 0xca, 0xc2, 0x0d, 0x7b, 0xf4, 0x1d, 0x83, 0x2a, 0xfd, 0x34, 0x9f, 0x5e, 0x3e, 0x55, 0x7a, 0x66, - 0xb7, 0x95, 0x6d, 0xdb, 0x0e, 0xb7, 0xdc, 0x65, 0xd7, 0xa7, 0x48, 0xae, 0x97, 0xb2, 0x3f, 0xbd, - 0x61, 0x4a, 0xa9, 0xba, 0xfa, 0x53, 0xd5, 0x35, 0x2b, 0x6b, 0x5e, 0x79, 0x1e, 0xfe, 0x3b, 0x21, - 0x77, 0x52, 0xcf, 0x84, 0xbe, 0x4b, 0x0d, 0xdb, 0x93, 0xdd, 0x02, 0xa5, 0x2e, 0x1b, 0x9f, 0x11, - 0x79, 0x72, 0xa9, 0x98, 0x67, 0xe9, 0xa6, 0xf2, 0x1f, 0x4f, 0x92, 0x8e, 0x72, 0x5d, 0x74, 0x71, - 0x79, 0x67, 0xab, 0xbc, 0x51, 0xb0, 0x88, 0xed, 0xd0, 0x4d, 0xf3, 0xef, 0x2b, 0xff, 0xac, 0x9c, - 0xfd, 0x2e, 0xc5, 0x4d, 0xf8, 0xe8, 0xa3, 0xf9, 0x9f, 0x8f, 0xdd, 0xac, 0x30, 0x4e, 0x79, 0xdb, - 0xad, 0x61, 0xb1, 0xa1, 0x64, 0xef, 0xd3, 0x6e, 0x81, 0xdf, 0x59, 0x5b, 0xff, 0x9f, 0x0c, 0xff, - 0x71, 0x7c, 0x4f, 0x81, 0x10, 0xdb, 0xed, 0x2f, 0xdf, 0xda, 0x85, 0xd3, 0x36, 0xde, 0xdc, 0xb3, - 0x3b, 0xd9, 0x22, 0x85, 0x6f, 0xde, 0x14, 0x36, 0xf7, 0x42, 0xbf, 0x1f, 0x6f, 0xd2, 0x5e, 0x2f, - 0x2d, 0x36, 0x28, 0xb1, 0x66, 0x49, 0x73, 0xba, 0xdb, 0x1f, 0xe8, 0xa7, 0xa1, 0x75, 0xfb, 0xe5, - 0xd1, 0xeb, 0x19, 0xd5, 0x59, 0x87, 0xdf, 0x3e, 0x59, 0xfd, 0x70, 0x6e, 0x67, 0xe3, 0x85, 0x18, - 0xc3, 0x3f, 0xb6, 0x21, 0xc6, 0xa9, 0x96, 0x65, 0x6a, 0x8d, 0x4c, 0x51, 0x22, 0x3b, 0x56, 0x4c, - 0x5a, 0xed, 0xff, 0x54, 0x65, 0xc6, 0x33, 0x29, 0xe5, 0xcf, 0x9f, 0xb6, 0x9f, 0xdf, 0x31, 0xd1, - 0x87, 0x67, 0x97, 0xa0, 0x4e, 0x69, 0x77, 0x48, 0xdd, 0xbd, 0xc4, 0x94, 0x6c, 0x2e, 0xfb, 0xd9, - 0x05, 0x7b, 0xd8, 0x4b, 0x36, 0xcc, 0x2d, 0x8d, 0x95, 0x9e, 0x7c, 0x94, 0x41, 0x3e, 0x63, 0xc1, - 0xf5, 0x0b, 0x8f, 0xf2, 0x0a, 0xbd, 0x8f, 0x47, 0x05, 0x7a, 0xea, 0xf4, 0x72, 0xbb, 0xaf, 0x64, - 0xf8, 0x69, 0x11, 0x79, 0x72, 0xbb, 0x97, 0x6e, 0x17, 0xc3, 0xf3, 0x9a, 0xc4, 0x3a, 0xd6, 0x9c, - 0xe3, 0x29, 0x4d, 0x1b, 0xa6, 0x9e, 0xff, 0x66, 0xd1, 0xf5, 0x79, 0x81, 0x7a, 0x8e, 0xd2, 0x84, - 0x74, 0x05, 0xb7, 0x96, 0xf8, 0x05, 0x16, 0x13, 0xf3, 0xe6, 0x6e, 0x51, 0xfd, 0x7e, 0x60, 0x0a, - 0xff, 0xdc, 0xc9, 0x7f, 0xb4, 0xab, 0x18, 0x46, 0xc1, 0x80, 0x02, 0x00, 0x3e, 0xdf, 0xdd, 0xd9, - 0x00, 0x03, 0x00, 0x00, + 0xfb, 0xa7, 0x7c, 0xf3, 0xdb, 0xf4, 0xff, 0xcc, 0x0b, 0x6f, 0x7d, 0x9b, 0x6d, 0xcd, 0xb5, 0x6e, + 0x5b, 0xfe, 0xe5, 0xc0, 0xff, 0xd7, 0xea, 0xc2, 0xb7, 0x76, 0x88, 0x6d, 0xae, 0xcc, 0xda, 0xbe, + 0x77, 0xe9, 0xcb, 0xe5, 0xdf, 0x02, 0x05, 0xf7, 0xff, 0x9f, 0x11, 0x24, 0x19, 0x5a, 0xe5, 0xd8, + 0x37, 0x57, 0xc4, 0x53, 0xe9, 0xe2, 0x83, 0x44, 0xd1, 0x15, 0x8f, 0x0e, 0xeb, 0x4b, 0xbc, 0x28, + 0xde, 0xd1, 0x7f, 0x75, 0xab, 0x48, 0xae, 0x47, 0xc9, 0x2e, 0x01, 0x19, 0xaf, 0xd7, 0xf9, 0x47, + 0x14, 0x5e, 0x73, 0x9e, 0x59, 0xb6, 0xf9, 0xe2, 0xfc, 0x9f, 0x2e, 0x1a, 0x85, 0x6c, 0x6a, 0xdb, + 0xc4, 0xa7, 0x1b, 0xcf, 0xde, 0xfc, 0x6c, 0xde, 0x51, 0x2b, 0xfd, 0xe6, 0xc6, 0x92, 0xdf, 0xde, + 0x9e, 0xe9, 0x29, 0xba, 0x2c, 0x45, 0xd7, 0xbd, 0x5a, 0x8f, 0x5b, 0x3d, 0xf1, 0xb7, 0x34, 0x59, + 0x57, 0x2f, 0xd6, 0x74, 0xdf, 0x53, 0x52, 0x7c, 0xe1, 0x1c, 0xa6, 0xbb, 0x2c, 0xf9, 0xb9, 0x97, + 0x4f, 0xc4, 0xa6, 0x17, 0xcf, 0xca, 0xf9, 0x68, 0x9d, 0xeb, 0x37, 0xf1, 0xb0, 0xcf, 0xd5, 0x24, + 0xa9, 0xe2, 0x5b, 0xbc, 0x65, 0x57, 0x5f, 0xc6, 0x7d, 0xd8, 0x76, 0x6a, 0x33, 0xb7, 0x6a, 0xeb, + 0x8d, 0x14, 0xcf, 0xf4, 0x32, 0x5b, 0x81, 0xf0, 0xb8, 0xcc, 0xdc, 0xe3, 0x45, 0xd9, 0x4b, 0x6f, + 0xce, 0x9c, 0x7b, 0xcc, 0xb8, 0x68, 0x55, 0xd8, 0x1f, 0xab, 0xe3, 0x89, 0x7f, 0x83, 0xc4, 0xcd, + 0x77, 0xad, 0x72, 0x11, 0x91, 0xae, 0x0f, 0x3a, 0xac, 0x7d, 0x26, 0x61, 0xc5, 0xf7, 0xef, 0xda, + 0xfa, 0x57, 0xee, 0x99, 0xc4, 0x4e, 0x9a, 0xfa, 0x2c, 0x40, 0xad, 0xf1, 0xff, 0x64, 0x9b, 0xbd, + 0x85, 0xe6, 0xf6, 0xe6, 0x8b, 0x9e, 0x0b, 0xd4, 0xfc, 0x10, 0xe2, 0xd9, 0x5d, 0x10, 0x2b, 0x9e, + 0xb4, 0xe6, 0x94, 0xf3, 0x5c, 0x39, 0xbb, 0x6b, 0x3c, 0xc5, 0x91, 0xa5, 0xcf, 0xbf, 0xbc, 0x99, + 0x7f, 0x3a, 0xef, 0xfb, 0x71, 0x5f, 0x71, 0xe6, 0xf3, 0xd6, 0xac, 0x71, 0xbb, 0x5e, 0x5f, 0xfe, + 0xe8, 0x2f, 0xae, 0x24, 0xbb, 0xc8, 0x98, 0xbf, 0xb9, 0x40, 0x27, 0x70, 0xc5, 0x87, 0xfe, 0x63, + 0x1e, 0xa5, 0x0f, 0x3f, 0xd8, 0xec, 0xd6, 0x68, 0x4d, 0xce, 0x0d, 0x9f, 0x71, 0x85, 0x7b, 0xa2, + 0xc9, 0x05, 0x8d, 0xf6, 0xe4, 0x8b, 0x9d, 0x8d, 0xd1, 0x61, 0x42, 0x1f, 0xf5, 0xda, 0x83, 0x8f, + 0x36, 0x4c, 0xab, 0xab, 0x9b, 0xd5, 0xe0, 0xcc, 0xdb, 0x77, 0x3a, 0xe8, 0x6b, 0xb3, 0xa8, 0xe0, + 0x3b, 0x11, 0xcb, 0x3d, 0xb3, 0xd5, 0x1f, 0xf8, 0xcd, 0xf5, 0xf8, 0x1c, 0xc0, 0x76, 0xec, 0xca, + 0xcf, 0xbd, 0x6f, 0xaf, 0x64, 0xfd, 0x5c, 0xf9, 0xd7, 0xd1, 0x3c, 0xa3, 0xd4, 0x33, 0x39, 0x44, + 0x61, 0xfd, 0x15, 0xad, 0x1b, 0xca, 0x27, 0xeb, 0x82, 0x43, 0x2d, 0x2c, 0x9a, 0x32, 0x2e, 0xaf, + 0x76, 0xd0, 0x29, 0xd8, 0xce, 0x30, 0x0a, 0x06, 0x14, 0x00, 0x00, 0xaa, 0xd8, 0x3f, 0xfe, 0x00, + 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3439,7 +3439,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 420, // compressed data size (bytes) + 419, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index 85a74b510..919a574e7 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -54,8 +54,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = 0x78, 0x80, 0x62, 0x01, 0x00, 0xc0, 0xc2, 0xff, 0x17, 0xea, 0x3b, 0x17, 0xb4, 0xfb, 0xe9, 0xe3, 0x1d, 0xec, 0x0d, 0xf8, 0x7f, 0x4f, 0x03, 0x4a, 0x86, 0x87, 0xd8, 0xf9, 0xbf, 0x91, 0xbf, 0xdf, 0x41, 0xc3, 0x01, 0xf4, 0x00, 0xbe, 0x73, 0x40, 0x3a, 0xe3, 0x80, 0x5a, 0x92, 0x10, 0xfe, 0xb7, - 0xfe, 0xf9, 0x00, 0xf0, 0xf9, 0xdf, 0x7e, 0xde, 0x80, 0xba, 0x8b, 0x3e, 0x01, 0x63, 0x6d, 0x4a, - 0xe1, 0xc3, 0x09, 0xa8, 0x01, 0xf2, 0x72, 0xdf, 0x00, 0x62, 0xff, 0x37, 0xf6, 0xfe, 0x3e, 0x31, + 0xfe, 0xf9, 0x00, 0xf0, 0xf9, 0xdf, 0x7e, 0xde, 0x80, 0xba, 0x8b, 0x3e, 0x01, 0x63, 0xb9, 0x98, + 0xc0, 0xc2, 0x09, 0xa8, 0x01, 0xf2, 0x72, 0xdf, 0x00, 0x62, 0xff, 0x37, 0xf6, 0xfe, 0x3e, 0x31, 0x7c, 0xfd, 0x48, 0x00, 0xe6, 0xe5, 0xf2, 0xdd, 0x01, 0xfc, 0xbf, 0x40, 0xae, 0xe9, 0x90, 0x2d, 0x8e, 0x16, 0x97, 0x25, 0xac, 0xab, 0xb0, 0x5f, 0x93, 0x89, 0xe2, 0xe6, 0x08, 0x68, 0xb5, 0xe8, 0x4a, 0xe8, 0x97, 0xda, 0x46, 0x9e, 0x60, 0x1f, 0x12, 0x9a, 0xe6, 0xff, 0x38, 0xab, 0xcf, 0x79, @@ -142,9 +142,9 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = 0xb3, 0x68, 0xa7, 0x00, 0x1c, 0xbe, 0xdc, 0xde, 0xf1, 0x1c, 0xb9, 0xa7, 0xbf, 0xf1, 0xd0, 0xb4, 0xfd, 0xf5, 0x69, 0x7b, 0xf0, 0xc3, 0x6f, 0x58, 0x09, 0x92, 0xa0, 0x30, 0xe0, 0x35, 0x04, 0x79, 0x80, 0x99, 0x3b, 0xf7, 0xee, 0x9b, 0x95, 0xda, 0xf1, 0x80, 0x4e, 0x36, 0x0f, 0xdf, 0xb6, 0x7a, - 0x35, 0x55, 0x75, 0xc0, 0x31, 0x95, 0xd8, 0x18, 0x29, 0x61, 0x4c, 0x88, 0x7e, 0x4b, 0x0a, 0x02, - 0xa4, 0xb6, 0xc9, 0x3f, 0xb4, 0x64, 0xb0, 0xc9, 0x01, 0x59, 0x02, 0x3f, 0xe4, 0xd1, 0xc5, 0x56, - 0x10, 0xdc, 0x99, 0x0f, 0x21, 0xbf, 0x35, 0x2b, 0x26, 0x22, 0x4b, 0xee, 0x13, 0x47, 0xc0, 0xcf, + 0x35, 0x55, 0x75, 0xc0, 0x31, 0x95, 0xd8, 0x18, 0x29, 0x61, 0x4c, 0x88, 0xc1, 0x36, 0xa0, 0x28, + 0x68, 0x06, 0x9c, 0x02, 0xf8, 0xc6, 0x76, 0xf0, 0x92, 0x4b, 0x83, 0x62, 0xbe, 0x3c, 0xef, 0x90, + 0x32, 0x29, 0xa3, 0x74, 0xd2, 0xbb, 0x5b, 0xd3, 0x0f, 0x2d, 0xdf, 0x84, 0x13, 0x47, 0xc0, 0xcf, 0x9d, 0x61, 0x62, 0x99, 0xcb, 0xe7, 0x74, 0x15, 0x7f, 0xfc, 0xed, 0xbc, 0xf4, 0x91, 0xe1, 0xe7, 0x48, 0x48, 0xc5, 0xdc, 0x7e, 0x4c, 0xf0, 0x76, 0xcd, 0xdf, 0x58, 0xfd, 0x44, 0x6b, 0x2d, 0x16, 0x94, 0xa1, 0x75, 0x6b, 0x00, 0x38, 0x6a, 0x88, 0xa6, 0x6e, 0xee, 0x5e, 0x29, 0x4f, 0x05, 0xf5, @@ -631,928 +631,928 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = 0x58, 0x05, 0x0d, 0xe9, 0xa0, 0x85, 0xbf, 0xe3, 0x82, 0x5e, 0xc9, 0x6a, 0xf8, 0xf6, 0xba, 0xab, 0xf2, 0xee, 0xed, 0x0a, 0x83, 0x36, 0xf1, 0x40, 0x85, 0xbb, 0x49, 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0x02, 0x97, 0xfa, 0x04, 0x76, 0x97, 0x85, 0x3f, + 0x5d, 0x07, 0x8e, 0x04, 0xd6, 0xf8, 0xa6, 0xc1, 0x4f, 0x4c, 0xa9, 0xdd, 0xac, 0xff, 0x8d, 0xff, + 0xa4, 0xe7, 0xaf, 0x88, 0xc5, 0xf3, 0xe0, 0xbd, 0xf8, 0xf0, 0xb3, 0x60, 0xee, 0x7d, 0xf1, 0xa8, + 0x5c, 0x9a, 0xf9, 0xab, 0x1a, 0xe2, 0xd6, 0x18, 0x41, 0xa4, 0x97, 0x62, 0x35, 0x8a, 0x8e, 0xa7, + 0xba, 0xf8, 0xb4, 0xd0, 0x46, 0x54, 0x4d, 0x40, 0xe2, 0x65, 0x1a, 0x84, 0x46, 0xb8, 0xce, 0xdc, + 0x07, 0xf2, 0x84, 0xe4, 0x3b, 0x7e, 0x3a, 0x93, 0x48, 0xb1, 0x77, 0x59, 0xe1, 0x36, 0x68, 0x90, + 0xc1, 0x28, 0x45, 0x01, 0x71, 0xbd, 0xa9, 0x8b, 0xb3, 0x99, 0x1a, 0xf9, 0x0a, 0x76, 0x18, 0x6b, + 0xbe, 0x44, 0xf4, 0x15, 0x0b, 0x0f, 0x24, 0xf4, 0x4c, 0x89, 0xaf, 0xf8, 0x73, 0xab, 0xf0, 0x7e, + 0x04, 0x2b, 0x4f, 0x13, 0xd1, 0x2e, 0x73, 0xaf, 0xfc, 0x6e, 0xc9, 0xd7, 0xbd, 0x71, 0x64, 0xd5, + 0x56, 0x45, 0xcd, 0x6f, 0x71, 0x26, 0x7f, 0x08, 0x89, 0x6c, 0xbf, 0xba, 0x2e, 0xef, 0x04, 0x07, + 0xf0, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, - 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xbf, 0xf1, 0xff, 0x00, 0x36, 0x68, 0x17, 0x1f, 0x00, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xff, 0xc6, 0xff, 0x03, 0x8a, 0xb4, 0x4b, 0x06, 0x00, 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3201,7 +3201,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0xc5, 0x93, 0x0d, 0xa9, 0xd2, 0x70, 0x67, 0x4d, 0x95, 0xba, 0x6b, 0x89, 0xcf, 0xd5, 0xbb, 0x09, + 0xdc, 0x0b, 0xc1, 0x59, 0x91, 0xe1, 0x5d, 0xf2, 0x54, 0x06, 0x0d, 0xa3, 0x71, 0xb0, 0xc7, 0x52, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3234,7 +3234,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0xb7, 0xa4, 0x87, 0x23, 0xda, 0x77, 0x45, 0x37, 0x33, 0xd3, 0xc5, 0x34, 0xa5, 0x94, 0xd3, 0xaf, + 0xcc, 0x26, 0x2d, 0xb0, 0xb0, 0x5c, 0x1f, 0xb1, 0x57, 0x5e, 0x05, 0x8a, 0xa1, 0x2d, 0x2b, 0x6c, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index 869417bc1..33f6f3531 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -55,7 +55,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x7d, 0xbc, 0x83, 0xbd, 0x01, 0xff, 0xef, 0x6c, 0x40, 0x29, 0xf0, 0x10, 0x3b, 0xff, 0x27, 0xf2, 0xf7, 0x3b, 0x68, 0x04, 0x80, 0x3e, 0xc0, 0x77, 0x2e, 0x48, 0x67, 0x3c, 0x50, 0x4b, 0x32, 0xc2, 0xff, 0xea, 0x3f, 0x1f, 0x00, 0xbe, 0xff, 0xbb, 0x9e, 0x37, 0xa0, 0xee, 0xe2, 0x4f, 0xc0, 0xb8, - 0xf2, 0x39, 0x98, 0x08, 0x02, 0x6a, 0x80, 0xfc, 0xbc, 0x37, 0x80, 0xb8, 0xff, 0x95, 0xbd, 0xbf, + 0xdb, 0x6e, 0x88, 0x08, 0x02, 0x6a, 0x80, 0xfc, 0xbc, 0x37, 0x80, 0xb8, 0xff, 0x95, 0xbd, 0xbf, 0x4f, 0x0c, 0x5f, 0x3f, 0x92, 0x80, 0xf9, 0x79, 0x7c, 0x77, 0x00, 0xff, 0x0f, 0x90, 0x6b, 0xba, 0x64, 0x8b, 0xa3, 0x25, 0xe5, 0x89, 0xeb, 0xaa, 0xec, 0xd7, 0x64, 0xa2, 0xb8, 0xb9, 0x02, 0xda, 0x2d, 0x7a, 0x92, 0x06, 0x65, 0xb6, 0x51, 0x27, 0xd8, 0x87, 0x84, 0xa6, 0x05, 0x3f, 0x2e, 0x1a, @@ -142,564 +142,564 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x25, 0x33, 0x8b, 0x71, 0x0e, 0xc4, 0xe1, 0xcb, 0xeb, 0x1d, 0xcf, 0x95, 0x7f, 0x72, 0x4c, 0x80, 0xa6, 0xed, 0xff, 0x9b, 0xbe, 0x07, 0x3f, 0xfc, 0x86, 0x95, 0x28, 0x05, 0x0a, 0x03, 0x5e, 0x4b, 0x90, 0x0f, 0x98, 0xb5, 0x73, 0xef, 0xb1, 0x59, 0xa5, 0x93, 0x00, 0xe8, 0x6c, 0xf3, 0xf0, 0x6d, - 0xab, 0x5f, 0x5b, 0x5d, 0x0f, 0x1c, 0x5b, 0x85, 0x8d, 0x91, 0x1a, 0xce, 0x84, 0xe8, 0xbf, 0xa4, - 0x28, 0x40, 0x6a, 0x9b, 0xf2, 0x43, 0x4b, 0x06, 0x9b, 0x12, 0x98, 0x2d, 0xf0, 0x43, 0x1e, 0x53, - 0x62, 0x05, 0xc1, 0x9d, 0xf5, 0x10, 0xfa, 0x5b, 0xbb, 0xf2, 0x47, 0x64, 0xc9, 0x63, 0xe2, 0x08, - 0xf8, 0xb9, 0x33, 0x5c, 0x2c, 0x6b, 0xf9, 0x9c, 0xae, 0x52, 0x22, 0xc0, 0xce, 0xdb, 0x00, 0x19, - 0x7e, 0x8e, 0x84, 0x54, 0xcc, 0xfd, 0xe7, 0x0f, 0xde, 0xae, 0xf9, 0x1b, 0xab, 0xbf, 0x68, 0x9d, - 0xc5, 0x82, 0x0a, 0xb4, 0x5e, 0x2d, 0x00, 0x47, 0x2d, 0xd1, 0xd4, 0xcd, 0xdd, 0x2b, 0xe5, 0xa9, - 0xa0, 0xfe, 0x2b, 0xc0, 0x00, 0x9c, 0x57, 0x16, 0x0c, 0x54, 0x8b, 0xb1, 0x1f, 0xee, 0xce, 0x72, - 0x2f, 0x66, 0x11, 0x23, 0xcb, 0xfe, 0x24, 0xaf, 0xab, 0x71, 0x3d, 0xce, 0xe4, 0x6d, 0x5a, 0x13, - 0xd9, 0x33, 0x31, 0x14, 0x1f, 0xaf, 0x60, 0xa4, 0xd0, 0x6b, 0xb2, 0x0d, 0x9b, 0x0e, 0x3e, 0x12, - 0x15, 0x7d, 0xa0, 0xda, 0xb5, 0x73, 0x66, 0x0e, 0x17, 0x33, 0xa1, 0xe9, 0xb9, 0x74, 0xc8, 0x8d, - 0x91, 0x65, 0x09, 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0x74, 0xf4, 0x71, 0x75, 0xd2, 0x9f, 0xf9, 0x4f, 0x51, + 0x44, 0x7d, 0x01, 0x97, 0xd2, 0xb2, 0xc5, 0x85, 0xc8, 0xab, 0x78, 0x02, 0x58, 0xdd, 0xf7, 0x59, + 0x6c, 0x00, 0xad, 0x75, 0xc2, 0xcf, 0xd0, 0x2b, 0x29, 0xed, 0x04, 0xd9, 0x75, 0xf3, 0x55, 0x53, + 0x61, 0xd8, 0x06, 0xc1, 0xee, 0x88, 0x64, 0x3d, 0xc6, 0x77, 0xcd, 0x24, 0x76, 0x3d, 0x6d, 0x16, + 0x0b, 0x60, 0x30, 0x5c, 0xca, 0xb9, 0x40, 0x03, 0x05, 0x8a, 0x61, 0x5f, 0x86, 0x85, 0xd9, 0x4d, + 0xe7, 0xe8, 0x6e, 0xc6, 0x90, 0x3f, 0x07, 0x64, 0x45, 0x90, 0x94, 0x0f, 0xe6, 0x7c, 0x81, 0x33, 0x93, 0xf1, 0x14, 0x9f, 0x4c, 0xf1, 0xcd, 0x68, 0x69, 0xad, 0x99, 0x4e, 0xb0, 0x17, 0xa2, 0xc7, 0x51, 0xdb, 0x6d, 0xca, 0xad, 0x90, 0x3d, 0x28, 0xbc, 0x76, 0xad, 0x3f, 0x94, 0xef, 0x8a, 0xa5, 0x02, 0x25, 0x37, 0xed, 0x7d, 0x80, 0x5b, 0xd9, 0xa6, 0x16, 0xeb, 0x22, 0x76, 0x71, 0x53, 0xbc, @@ -729,7 +729,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x47, 0x75, 0x87, 0x59, 0x35, 0x44, 0x37, 0xde, 0xc8, 0xbf, 0x21, 0xd8, 0x25, 0xfd, 0xd9, 0x07, 0xd4, 0x82, 0xa6, 0x4b, 0xd8, 0xd3, 0x97, 0x95, 0xe4, 0x10, 0xa9, 0x4d, 0x26, 0x62, 0x8b, 0x22, 0xcc, 0x61, 0x13, 0x68, 0x86, 0xf6, 0x2f, 0x4a, 0x3e, 0xe9, 0xbc, 0x55, 0x32, 0x27, 0xca, 0x62, - 0xda, 0xa8, 0x18, 0x4b, 0xdf, 0xbb, 0xc9, 0xb7, 0x8f, 0x93, 0x8d, 0xa2, 0xd6, 0x91, 0x8f, 0x46, + 0x12, 0xa0, 0xd3, 0x01, 0xd6, 0x5b, 0xcc, 0x94, 0x46, 0xd5, 0x21, 0x5c, 0xb5, 0x8b, 0x2e, 0x84, 0x71, 0xda, 0x09, 0xaf, 0x31, 0x43, 0x04, 0x60, 0x7a, 0xc1, 0x74, 0xd0, 0x26, 0xe5, 0x0c, 0x9a, 0x7c, 0xca, 0x0d, 0xbe, 0xcf, 0x9a, 0xe6, 0xc0, 0x80, 0x49, 0x0a, 0xe0, 0x4a, 0xf0, 0x09, 0x4f, 0xca, 0x6c, 0xed, 0x0b, 0x95, 0xf7, 0x2a, 0xb6, 0xbe, 0xf6, 0x9d, 0xc4, 0xf0, 0xa4, 0xd3, 0x4e, @@ -1113,17 +1113,17 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x5b, 0x45, 0xae, 0x42, 0xdf, 0x11, 0x2c, 0x2c, 0x85, 0x1a, 0x27, 0x20, 0x86, 0x35, 0x3c, 0x73, 0xdd, 0xc6, 0x70, 0x3a, 0x35, 0xd8, 0x1b, 0xaf, 0x60, 0xa6, 0xd7, 0x98, 0xec, 0x56, 0x34, 0xa4, 0xeb, 0xd8, 0xe9, 0xdd, 0x0d, 0x83, 0xc5, 0x84, 0x63, 0xea, 0x1b, 0x0a, 0x84, 0x63, 0x0c, 0x53, - 0xe8, 0xc2, 0xb3, 0x0c, 0x7a, 0x05, 0xc8, 0x32, 0x4b, 0x98, 0xa4, 0xfa, 0xe7, 0x0c, 0xe4, 0x94, - 0xbd, 0xea, 0x2d, 0x65, 0xdc, 0x62, 0xa5, 0x1b, 0x66, 0xdc, 0x48, 0x23, 0xa6, 0xc6, 0x36, 0x6c, - 0xe0, 0xac, 0xd0, 0x6a, 0x70, 0x65, 0x90, 0x30, 0xcc, 0xc5, 0x5e, 0x8c, 0xa0, 0x20, 0xf8, 0xe1, + 0xe8, 0x82, 0xbe, 0xd6, 0x83, 0xaa, 0x4c, 0xd3, 0xea, 0x3e, 0xc7, 0xb3, 0x03, 0x67, 0xac, 0x72, + 0xf1, 0x87, 0x10, 0x55, 0x0c, 0x4c, 0x9e, 0x55, 0xb0, 0x42, 0x8f, 0x2b, 0xe9, 0x54, 0x62, 0x14, + 0x72, 0xb8, 0xd0, 0x6a, 0x70, 0x65, 0x90, 0x30, 0xcc, 0xc5, 0x5e, 0x8c, 0xa0, 0x20, 0xf8, 0xe1, 0xbe, 0xbc, 0x66, 0x9f, 0xf5, 0x9b, 0x10, 0xd5, 0x35, 0x3e, 0x19, 0xc0, 0xa2, 0x5a, 0xef, 0xfb, 0x55, 0x10, 0xf1, 0xfc, 0xaf, 0x9d, 0x6a, 0x49, 0xd2, 0x07, 0x15, 0x96, 0x4e, 0x9c, 0x1f, 0xfa, 0x5c, 0x44, 0x9d, 0xef, 0xef, 0x1b, 0xc6, 0xbb, 0x50, 0x57, 0x56, 0x5f, 0xb1, 0x60, 0x84, 0x64, 0xd3, 0x2f, 0xd6, 0x52, 0x43, 0x99, 0xc8, 0xb9, 0xa8, 0xa6, 0xb3, 0xa1, 0x59, 0x71, 0x0a, 0x11, 0x1e, 0x91, 0x6f, 0x57, 0x3c, 0x7c, 0x69, 0xe2, 0x76, 0xd5, 0x60, 0x3c, 0xcb, 0x0f, 0x7d, 0xb4, 0x7b, 0x0d, 0x27, 0xf5, 0xd7, 0x26, 0x5b, 0xc7, 0x24, 0x79, 0x6a, 0x61, 0xe5, 0xa0, 0x8a, 0x6f, - 0x1b, 0x9f, 0x37, 0x09, 0xfe, 0x1b, 0x39, 0xb1, 0xc6, 0x47, 0xde, 0x6a, 0x5b, 0xe2, 0xaa, 0xfe, - 0xc9, 0x08, 0x37, 0x88, 0x0d, 0xd6, 0xca, 0xd3, 0x5d, 0x1a, 0x21, 0x51, 0xdc, 0xfe, 0x18, 0x4c, + 0x1b, 0x9f, 0xae, 0x3d, 0x1f, 0x5e, 0x72, 0xe5, 0x72, 0xdd, 0xc8, 0x29, 0x89, 0xf1, 0xae, 0xd6, + 0xbc, 0x29, 0x37, 0x88, 0x0d, 0xd6, 0xca, 0xd3, 0x5d, 0x1a, 0x21, 0x51, 0xdc, 0xfe, 0x18, 0x4c, 0xd8, 0x10, 0xe9, 0x73, 0xa7, 0x53, 0x0a, 0x01, 0x5e, 0x58, 0x67, 0xf4, 0xad, 0x2d, 0x84, 0xc8, 0x68, 0x25, 0x1a, 0xf7, 0x71, 0x17, 0x29, 0x05, 0x39, 0xf6, 0x8c, 0xe4, 0x93, 0x2d, 0xc7, 0x40, 0x32, 0xee, 0x08, 0x19, 0x73, 0x52, 0x31, 0xf2, 0x4a, 0x20, 0x6f, 0x5b, 0xf1, 0x4e, 0x1f, 0xd5, @@ -1174,8 +1174,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0xc4, 0x92, 0x80, 0x3d, 0x2e, 0x4c, 0x39, 0x85, 0x19, 0xff, 0x35, 0x4c, 0xef, 0x3f, 0xcf, 0x65, 0xd6, 0x74, 0x3c, 0x38, 0x69, 0x8b, 0xaf, 0xc6, 0xfd, 0x29, 0xc2, 0x3b, 0x58, 0xa8, 0xc3, 0xee, 0xa5, 0x24, 0xff, 0xb0, 0x8d, 0x92, 0xcd, 0x4f, 0x23, 0x02, 0x56, 0xdc, 0x3a, 0x50, 0x22, 0xee, - 0xf6, 0x62, 0x14, 0x9d, 0x4d, 0x08, 0x20, 0xf0, 0x0d, 0x29, 0xc4, 0x31, 0x24, 0xa0, 0xe7, 0xa4, - 0x24, 0x29, 0x30, 0x38, 0x4f, 0x58, 0x20, 0x90, 0xf1, 0x19, 0x62, 0x81, 0x00, 0x76, 0x1a, 0xb1, + 0xf6, 0x62, 0xd4, 0x50, 0x5c, 0xcb, 0xb2, 0x54, 0xbf, 0xfa, 0xa5, 0xdc, 0x1c, 0x1c, 0x63, 0x13, + 0x24, 0xa7, 0x31, 0x38, 0x4f, 0x58, 0x20, 0x90, 0xf1, 0x19, 0x62, 0x81, 0x00, 0x76, 0x1a, 0xb1, 0x6b, 0x9c, 0x74, 0x95, 0xa4, 0xad, 0xc8, 0xb3, 0xfa, 0x9e, 0x1f, 0xd3, 0x3a, 0x0d, 0x59, 0xcb, 0x02, 0x42, 0x77, 0x72, 0xd4, 0xc0, 0xf8, 0x71, 0x60, 0xa6, 0x58, 0xac, 0x52, 0xd1, 0x2d, 0x3c, 0xda, 0x3d, 0x90, 0xee, 0x8f, 0x09, 0x11, 0xd7, 0xda, 0x85, 0x57, 0x96, 0x66, 0x24, 0xb8, 0x23, @@ -1220,8 +1220,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x19, 0x91, 0x35, 0xaf, 0x95, 0xf2, 0xf0, 0x65, 0xd6, 0x2c, 0xbb, 0xd7, 0xf4, 0xcd, 0xe6, 0xb8, 0x18, 0x6d, 0x2c, 0x70, 0x96, 0xed, 0x19, 0x02, 0xe9, 0x83, 0xb8, 0xd1, 0xc2, 0x46, 0x62, 0x93, 0xba, 0x4e, 0xaf, 0xc3, 0x91, 0xcf, 0x17, 0x2e, 0x09, 0x42, 0x6e, 0xaa, 0x65, 0xdb, 0x5b, 0x37, - 0x92, 0x7e, 0x6b, 0x09, 0x00, 0x81, 0xb5, 0x22, 0x53, 0x6a, 0xbc, 0x70, 0x2d, 0x79, 0x39, 0xf9, - 0xdc, 0x34, 0xc2, 0x3b, 0x2a, 0xec, 0xdd, 0xa5, 0x47, 0x97, 0x3e, 0x28, 0x74, 0x6b, 0x45, 0xed, + 0x92, 0x7e, 0x6b, 0x09, 0x00, 0x81, 0xd5, 0x69, 0xca, 0xdb, 0x8f, 0x77, 0x36, 0xb2, 0xc9, 0xe7, + 0xcb, 0x42, 0xd3, 0xd8, 0xe8, 0x48, 0xdc, 0xa5, 0x47, 0x97, 0x3e, 0x28, 0x74, 0x6b, 0x45, 0xed, 0xd0, 0xdd, 0x84, 0xa6, 0xa4, 0x81, 0xcf, 0x05, 0x07, 0x96, 0x94, 0xc6, 0xf5, 0x17, 0x8d, 0xb7, 0xfe, 0x9d, 0x5d, 0x8e, 0xc4, 0x0c, 0x22, 0x8d, 0x25, 0x63, 0x6b, 0xee, 0xf3, 0x36, 0x6f, 0xb2, 0xdf, 0x47, 0x99, 0x22, 0xc0, 0x66, 0x04, 0x0b, 0x15, 0x13, 0x52, 0xd0, 0x01, 0x71, 0x61, 0x49, @@ -1546,7 +1546,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = 0x01, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, - 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0xdf, 0xf8, 0xbf, 0x00, 0x30, 0xa9, 0xa6, 0x6e, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0xdf, 0xf8, 0xbf, 0x00, 0xf7, 0x8c, 0xa3, 0xd4, 0x00, 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1617,7 +1617,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0xed, 0xfc, 0x53, 0x8c, 0x28, 0xcf, 0x1b, 0x38, 0x78, 0x8f, 0x6d, 0xdb, 0xf6, 0xcc, 0x19, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0xc6, 0xb6, 0x6d, 0xdb, 0xf6, 0xfe, 0xfe, 0xef, 0xdd, 0xfb, 0xdd, 0x8b, 0xcd, 0x5e, 0x6e, 0x72, 0x3e, 0x37, 0xd5, 0xd5, 0x49, 0xf7, 0xd3, 0x49, - 0xa7, 0x9e, 0x54, 0x75, 0x57, 0x95, 0x04, 0x00, 0xc2, 0x4c, 0x06, 0x40, 0x1c, 0x00, 0x28, 0x40, + 0xa7, 0x2a, 0x55, 0xdd, 0xf5, 0x94, 0x04, 0x00, 0xc2, 0x4c, 0x06, 0x40, 0x1c, 0x00, 0x28, 0x40, 0xf7, 0x51, 0xfe, 0x7b, 0xcb, 0x0f, 0xa0, 0x04, 0x00, 0xe2, 0xff, 0x39, 0x01, 0x01, 0x0a, 0xf0, 0xff, 0xab, 0x46, 0x00, 0x00, 0x00, 0xfe, 0x24, 0x03, 0xf8, 0xd2, 0x03, 0x00, 0xbc, 0x01, 0xbd, 0x01, 0xbc, 0x03, 0xc5, 0x00, 0x00, 0x01, 0xf4, 0xee, 0xec, 0xfe, 0xfe, 0xfe, 0xc2, 0x47, 0x00, @@ -1630,7 +1630,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x76, 0x3f, 0x7d, 0xbc, 0x83, 0xbd, 0x01, 0xff, 0xef, 0x6e, 0x40, 0x29, 0xf0, 0x10, 0x3b, 0xff, 0x27, 0xf2, 0xf7, 0x3b, 0x68, 0x04, 0x80, 0x1e, 0xc0, 0x77, 0x2e, 0x48, 0x57, 0x3c, 0x50, 0x6b, 0x32, 0xc2, 0xff, 0xea, 0x3f, 0x1f, 0x00, 0xbe, 0xff, 0x7b, 0x9e, 0x37, 0xa0, 0xee, 0xe2, 0x4f, - 0xc0, 0xb8, 0xf2, 0x39, 0x98, 0x08, 0x02, 0x6a, 0x80, 0xfc, 0xbc, 0x37, 0x80, 0xb8, 0xff, 0x95, + 0xc0, 0xb8, 0xdb, 0x6e, 0x88, 0x08, 0x02, 0x6a, 0x80, 0xfc, 0xbc, 0x37, 0x80, 0xb8, 0xff, 0x95, 0xbd, 0xbf, 0x4f, 0x0c, 0x5f, 0x3f, 0x12, 0x80, 0xf9, 0x79, 0xbc, 0x77, 0x00, 0xff, 0x7f, 0x24, 0x7b, 0x99, 0x38, 0x20, 0x57, 0xa9, 0xf6, 0xd8, 0x98, 0x95, 0x68, 0x6d, 0xb9, 0xfc, 0x47, 0x33, 0xe4, 0x25, 0x2b, 0x40, 0x25, 0xe4, 0x06, 0x32, 0x8b, 0xf9, 0xf0, 0xf4, 0x86, 0x5e, 0xec, 0xa5, @@ -1717,9 +1717,9 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x03, 0xde, 0x69, 0xa0, 0x94, 0xca, 0xa4, 0x50, 0xba, 0xae, 0x77, 0xa9, 0xde, 0xf2, 0xa4, 0x59, 0xad, 0x5b, 0x3d, 0x1e, 0x52, 0x0e, 0xc7, 0xec, 0x9b, 0x77, 0x4e, 0x09, 0x36, 0xe1, 0x11, 0x3a, 0x72, 0x8a, 0x75, 0x36, 0xf9, 0x86, 0x10, 0xeb, 0x8d, 0xb8, 0xac, 0xbb, 0x25, 0x06, 0x33, 0x68, - 0x0c, 0x61, 0x6b, 0x9e, 0x85, 0x5f, 0xaa, 0xc8, 0xa5, 0x62, 0xa1, 0x6c, 0xe1, 0x63, 0x8a, 0x7d, - 0xe8, 0x6f, 0xde, 0xc2, 0x5b, 0x11, 0xce, 0x46, 0x21, 0xcc, 0x04, 0xbe, 0xeb, 0x9e, 0x72, 0xec, - 0x1d, 0x27, 0x10, 0xc4, 0x94, 0xc5, 0x97, 0x86, 0x5e, 0x29, 0xa8, 0x04, 0x7b, 0xf2, 0xb5, 0x1e, + 0x0c, 0x61, 0x6b, 0x9e, 0x85, 0x5f, 0xaa, 0xc8, 0xa5, 0x62, 0xa1, 0x6c, 0xe1, 0x63, 0x8a, 0xbd, + 0x13, 0x2b, 0x67, 0x1e, 0x33, 0x4a, 0x90, 0xff, 0x16, 0x52, 0xb5, 0x92, 0x4b, 0x8d, 0x10, 0x04, + 0xef, 0x2f, 0x67, 0x24, 0x1b, 0x24, 0x19, 0x79, 0x12, 0xc0, 0x65, 0x6f, 0x85, 0x2b, 0xc4, 0x0d, 0xa1, 0x6e, 0xb3, 0xb2, 0x11, 0xc5, 0x51, 0xfb, 0x18, 0xa1, 0x8b, 0xf3, 0x57, 0x1c, 0xfa, 0xf7, 0xd9, 0x5a, 0x2c, 0x84, 0x07, 0xf8, 0x8e, 0xa4, 0x14, 0xa3, 0x61, 0x97, 0x28, 0xe6, 0x9c, 0xaf, 0xf2, 0xee, 0xee, 0x41, 0xe1, 0xc9, 0x56, 0x95, 0xcc, 0xd3, 0x3c, 0xeb, 0xbc, 0xd9, 0xfb, 0xa7, @@ -1857,710 +1857,710 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x7a, 0xed, 0x1b, 0xab, 0xf6, 0x4a, 0x2e, 0x3b, 0x99, 0x1d, 0x06, 0x5c, 0xb1, 0xab, 0x32, 0x2c, 0x95, 0x0d, 0x20, 0x9a, 0x52, 0x51, 0x93, 0xd9, 0x0b, 0x8b, 0x7a, 0x8e, 0x73, 0xa6, 0xa9, 0xab, 0x0d, 0x48, 0x06, 0x3b, 0x8a, 0x52, 0x7a, 0x15, 0x0f, 0xa5, 0xf7, 0xc5, 0x74, 0x13, 0x1e, 0x48, - 0x36, 0xfe, 0x9b, 0xdf, 0x31, 0x36, 0xe2, 0xb3, 0x4f, 0x93, 0x46, 0xc4, 0x9a, 0xc8, 0xa9, 0x6d, - 0x86, 0xcc, 0x9d, 0x73, 0x98, 0x75, 0x70, 0xbe, 0x13, 0x6a, 0xb9, 0xad, 0xa1, 0x14, 0xca, 0x19, - 0xfa, 0x15, 0xec, 0x68, 0xbf, 0x97, 0x2b, 0xcd, 0xdb, 0x25, 0x43, 0xfd, 0xcd, 0x67, 0x03, 0x9c, - 0xe7, 0x8c, 0x57, 0xf5, 0x12, 0x27, 0xb2, 0xef, 0xbd, 0x07, 0x1e, 0x05, 0x14, 0xe5, 0x74, 0x18, - 0x92, 0xc3, 0x4c, 0x1e, 0xf2, 0x77, 0xb2, 0xd9, 0xf1, 0xd1, 0x49, 0xbb, 0x3b, 0xf3, 0xcf, 0xd9, - 0x1b, 0x2a, 0x9c, 0xa0, 0x1b, 0x81, 0x9e, 0x34, 0xff, 0xe4, 0x11, 0xd0, 0x9e, 0x72, 0x85, 0x79, - 0xbd, 0x6e, 0xbe, 0x62, 0x2a, 0x35, 0x7c, 0x89, 0xcc, 0xd3, 0xa9, 0x97, 0x09, 0xa3, 0x64, 0x7c, - 0x03, 0x07, 0x6d, 0xd2, 0xda, 0x0a, 0x61, 0xac, 0x1a, 0xee, 0xf0, 0xe4, 0xe1, 0xf4, 0xf2, 0x1c, - 0xe5, 0x3d, 0x69, 0x63, 0xc0, 0xa3, 0xcc, 0x92, 0x32, 0xb0, 0xe1, 0xc9, 0xb9, 0x4b, 0xe7, 0xce, - 0x35, 0x2e, 0xf6, 0x79, 0xb5, 0x73, 0x77, 0xb5, 0xe2, 0x5d, 0x76, 0x62, 0x58, 0x30, 0xe2, 0x51, - 0x3d, 0x16, 0x03, 0xd7, 0x8a, 0x5c, 0x32, 0x9e, 0xb9, 0x97, 0x9d, 0xc2, 0xa5, 0x40, 0x3a, 0xb7, - 0xb7, 0x99, 0x74, 0xc3, 0xe1, 0x39, 0x5b, 0xe6, 0x1e, 0x92, 0x3e, 0x1c, 0xe5, 0x41, 0x6b, 0x8f, - 0xe9, 0x98, 0x36, 0x75, 0x07, 0x54, 0xdb, 0xf1, 0x54, 0x39, 0xe9, 0x13, 0xb9, 0xec, 0xef, 0x47, - 0x97, 0x95, 0xb8, 0x72, 0xdd, 0x78, 0x7e, 0x8e, 0xf3, 0xfc, 0x21, 0xee, 0x86, 0xa1, 0x9e, 0x8c, - 0x48, 0xa2, 0xce, 0x9f, 0x27, 0x23, 0x4a, 0xb8, 0x73, 0x62, 0xd4, 0x42, 0x70, 0xe1, 0x94, 0x16, - 0xb0, 0x78, 0x28, 0xf2, 0x13, 0x15, 0xa3, 0x84, 0x1b, 0x24, 0x54, 0xe3, 0xe7, 0xe2, 0x35, 0x77, - 0x09, 0xbb, 0x2e, 0xfb, 0xda, 0x17, 0xeb, 0x9f, 0x8f, 0xb0, 0x28, 0x2b, 0xde, 0xcd, 0x5b, 0x3d, - 0xde, 0x8b, 0xc1, 0x5f, 0x0d, 0x50, 0x71, 0xba, 0x96, 0xec, 0x0a, 0xfc, 0x43, 0x8a, 0xfd, 0x96, - 0x77, 0xae, 0xcf, 0x4d, 0x16, 0xaf, 0x55, 0x26, 0x4d, 0xc4, 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0x51, + 0x5a, 0x6d, 0x1e, 0x19, 0x9a, 0xe5, 0x6d, 0x8b, 0x72, 0xe5, 0xfb, 0xef, 0xb2, 0xaf, 0x6d, 0xd3, + 0x82, 0xc2, 0x5e, 0x11, 0x92, 0xdc, 0xb6, 0x7b, 0x18, 0x5c, 0xc5, 0x58, 0x25, 0xfb, 0x82, 0x0d, + 0xb1, 0xc6, 0xe7, 0x4a, 0xf4, 0x7c, 0x56, 0xbb, 0x93, 0x9d, 0xab, 0x5d, 0x83, 0x22, 0x34, 0x38, + 0x25, 0x18, 0x8c, 0x9f, 0xbb, 0x7d, 0x11, 0xb1, 0xe8, 0x5e, 0x86, 0x03, 0x2e, 0x0e, 0x08, 0x65, + 0xb5, 0x29, 0xe7, 0x79, 0xfa, 0x9b, 0xef, 0x1a, 0xa9, 0xea, 0xc2, 0xe6, 0xad, 0x38, 0xdc, 0x87, + 0xb5, 0xe8, 0x0b, 0x59, 0x93, 0xa5, 0x2b, 0x72, 0x46, 0x49, 0x15, 0x99, 0x62, 0x23, 0x43, 0x65, + 0x45, 0xad, 0x05, 0x4e, 0xa8, 0x2f, 0xcc, 0x0a, 0x90, 0x9e, 0x30, 0xe8, 0x7e, 0x33, 0xe6, 0x28, + 0x33, 0xb2, 0xbd, 0xde, 0x47, 0x30, 0xab, 0x1a, 0xd9, 0xdb, 0xaf, 0x60, 0x38, 0x9e, 0x9f, 0xee, + 0x02, 0x1d, 0x3b, 0xc9, 0x59, 0xb3, 0xa5, 0x91, 0x9e, 0xf6, 0xc3, 0x1a, 0xc9, 0x37, 0xe5, 0xf4, + 0x29, 0x87, 0x97, 0x78, 0x3e, 0x7b, 0x67, 0x18, 0x14, 0x13, 0x13, 0x42, 0x25, 0xd8, 0xcb, 0xe8, + 0x29, 0x2d, 0xad, 0x3d, 0xc4, 0xdc, 0x30, 0x03, 0xeb, 0xca, 0xbf, 0xb4, 0xa5, 0xbf, 0x9a, 0x57, + 0x19, 0x9b, 0x63, 0x7c, 0xa9, 0x51, 0x14, 0x0d, 0xe6, 0x4a, 0x73, 0x54, 0xe3, 0x10, 0x58, 0x6a, + 0xfe, 0xc6, 0xf9, 0x88, 0x97, 0x80, 0x02, 0x7b, 0x81, 0xaa, 0x1d, 0x3e, 0x0d, 0xd4, 0xd0, 0x66, + 0xc8, 0xe9, 0x0e, 0xc9, 0xf7, 0xba, 0xfc, 0x37, 0x5f, 0x6c, 0xec, 0x99, 0xca, 0x46, 0xca, 0x44, 0x8a, 0x92, 0x65, 0x69, 0x11, 0x0c, 0x01, 0x1c, 0x00, 0x72, 0x16, 0x44, 0xb5, 0x7c, 0xc2, 0x65, 0x75, 0xca, 0xb1, 0x70, 0x11, 0x86, 0x71, 0xb5, 0x56, 0x0d, 0xef, 0x3e, 0x21, 0x0f, 0xd9, 0x08, 0xd1, 0x9c, 0x85, 0xa8, 0x8c, 0x2c, 0x86, 0x68, 0xea, 0xa0, 0x81, 0x1a, 0x8c, 0xf2, 0x22, 0x14, @@ -2573,7 +2573,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x16, 0xd5, 0x21, 0x19, 0x4d, 0x22, 0x12, 0x05, 0x14, 0x22, 0xf6, 0x60, 0xca, 0xbb, 0x61, 0x57, 0x47, 0xa5, 0x43, 0x60, 0x4e, 0x30, 0x9a, 0xfb, 0x4c, 0x10, 0xc3, 0x1d, 0x88, 0x8a, 0xc2, 0x7f, 0x5d, 0x3c, 0x89, 0x00, 0x71, 0x68, 0x65, 0x92, 0xf8, 0x23, 0x1b, 0x33, 0x72, 0x7f, 0x71, 0xf5, - 0xed, 0x7f, 0x7d, 0xad, 0xac, 0x7c, 0x1d, 0xed, 0x76, 0xed, 0x50, 0x73, 0xe5, 0x4d, 0xb3, 0xc2, + 0xed, 0x7f, 0x63, 0xad, 0xac, 0x7c, 0x1d, 0xed, 0x76, 0xed, 0x50, 0x73, 0xe5, 0x4d, 0xb3, 0xc2, 0xa4, 0x47, 0xc3, 0x95, 0x28, 0xdf, 0x72, 0xc2, 0x4e, 0xad, 0x95, 0xea, 0x81, 0xc2, 0xef, 0x8d, 0xdc, 0xaa, 0x3d, 0x64, 0x2e, 0xe0, 0x77, 0x1a, 0xc8, 0xa3, 0x28, 0x52, 0x71, 0xcb, 0xd5, 0x37, 0x0c, 0x3b, 0xe7, 0x55, 0x13, 0xee, 0x78, 0xe3, 0xaf, 0x02, 0xb9, 0x22, 0x71, 0x8b, 0xe2, 0x51, @@ -2617,7 +2617,7 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0xac, 0x8f, 0x3b, 0x3f, 0xb9, 0x4a, 0xaa, 0xce, 0x6b, 0x59, 0x72, 0xbe, 0x7c, 0xda, 0x74, 0x2e, 0x3d, 0xb6, 0x94, 0x29, 0x92, 0x19, 0x98, 0x46, 0x2a, 0x09, 0xa7, 0x89, 0xbb, 0xe3, 0x37, 0x50, 0xfb, 0x8b, 0x49, 0x89, 0xd8, 0x1e, 0x1a, 0x16, 0xd7, 0x98, 0xde, 0x1a, 0xb1, 0xca, 0xf0, 0xed, - 0x16, 0x7f, 0x86, 0x99, 0x1a, 0x9e, 0xce, 0xb7, 0x40, 0x73, 0xfe, 0x3b, 0x3f, 0xa0, 0xa2, 0x21, + 0x16, 0x7f, 0x86, 0x99, 0x1a, 0x9e, 0xce, 0xb7, 0x40, 0x73, 0xfe, 0xbb, 0x3e, 0xa0, 0xa2, 0x21, 0x37, 0x71, 0x06, 0x88, 0xc7, 0x55, 0xf2, 0x69, 0x5b, 0x7d, 0xc4, 0x89, 0x42, 0x45, 0xba, 0x08, 0x7c, 0xf5, 0xf2, 0x63, 0xc1, 0x73, 0xf7, 0xe4, 0xcf, 0x58, 0xad, 0x08, 0xa3, 0xad, 0x24, 0x87, 0x21, 0x9d, 0x36, 0xd7, 0xb0, 0xf0, 0xe5, 0x59, 0x74, 0x74, 0x4d, 0x55, 0xda, 0x12, 0x8d, 0xc1, @@ -2646,16 +2646,16 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x65, 0x12, 0x46, 0x94, 0x86, 0x00, 0xc1, 0x72, 0x21, 0xa8, 0x9d, 0xaf, 0x89, 0x87, 0x34, 0xfb, 0x00, 0x3e, 0x39, 0xa2, 0xff, 0x82, 0x23, 0xaf, 0xd9, 0x77, 0x2a, 0x39, 0xfd, 0xed, 0xc1, 0xb4, 0x5b, 0x9b, 0xc1, 0x28, 0xf6, 0x24, 0xd3, 0x46, 0x84, 0x6b, 0xcb, 0xbb, 0xb9, 0x13, 0xfb, 0x6f, - 0x7e, 0x75, 0x37, 0x40, 0x3b, 0x4d, 0x5f, 0x02, 0xe5, 0xf9, 0x9b, 0x33, 0xd7, 0x1d, 0x61, 0xe8, - 0x91, 0x57, 0x0c, 0x3f, 0x2c, 0x7a, 0xf7, 0xa6, 0x4d, 0x32, 0x12, 0x88, 0x13, 0x38, 0xc7, 0xbb, - 0x8e, 0xad, 0x72, 0x50, 0x1d, 0x39, 0x37, 0xac, 0x3d, 0x9a, 0x4b, 0xe9, 0x11, 0x29, 0x66, 0x28, - 0x01, 0x4d, 0x7e, 0x35, 0xe0, 0x08, 0xf2, 0x3d, 0xbd, 0x42, 0x6b, 0xc6, 0x04, 0xc9, 0x8f, 0xde, - 0x11, 0xa9, 0xa2, 0x9c, 0x55, 0xbd, 0x57, 0x88, 0x62, 0x87, 0x64, 0xd2, 0x61, 0xb7, 0x2f, 0x63, - 0xc6, 0x84, 0x5e, 0x74, 0x8c, 0xfc, 0x78, 0x02, 0xfd, 0x96, 0x63, 0xa3, 0x02, 0x65, 0x9b, 0xdf, - 0x5d, 0xf4, 0xf9, 0x4a, 0x47, 0xc6, 0x58, 0x0f, 0xd2, 0x3a, 0xa0, 0x16, 0xe4, 0xa8, 0xe7, 0x84, - 0x18, 0x7d, 0x15, 0x56, 0x19, 0x85, 0xfa, 0xcb, 0xda, 0x85, 0xe5, 0x20, 0x63, 0x75, 0x44, 0xab, - 0x35, 0x3f, 0x2c, 0x43, 0x32, 0xd2, 0xfd, 0xf4, 0x93, 0xca, 0xd1, 0xa3, 0x6a, 0x40, 0x42, 0xca, - 0x73, 0xf7, 0xdf, 0xf5, 0xbf, 0x2f, 0x86, 0x48, 0x19, 0x66, 0xd2, 0x03, 0xa6, 0x28, 0x8d, 0xe9, + 0xff, 0xea, 0x6e, 0x80, 0x76, 0x9a, 0xbe, 0x04, 0xca, 0xf3, 0x37, 0x67, 0xae, 0x3b, 0xc2, 0xd0, + 0x23, 0xaf, 0x18, 0x7e, 0x58, 0xf4, 0xee, 0x4d, 0x9b, 0x64, 0x24, 0x10, 0x27, 0x70, 0x8e, 0x77, + 0x1d, 0x5b, 0xe5, 0xa0, 0x3a, 0x72, 0x6e, 0x58, 0x7b, 0x34, 0x97, 0xd2, 0x23, 0x52, 0xcc, 0x50, + 0x02, 0x9a, 0xfc, 0x6a, 0xc0, 0x11, 0xe4, 0x7b, 0x7a, 0x85, 0xd6, 0x8c, 0x09, 0x92, 0x1f, 0xbd, + 0x23, 0x52, 0x45, 0x39, 0xab, 0x7a, 0xaf, 0x10, 0xc5, 0x0e, 0xc9, 0xa4, 0xc3, 0x6e, 0x5f, 0xc6, + 0x8c, 0x09, 0xbd, 0xe8, 0x18, 0xf9, 0xf1, 0x04, 0xfa, 0x2d, 0xc7, 0x46, 0x05, 0xca, 0x36, 0xbf, + 0xbb, 0xe8, 0xf3, 0x95, 0x8e, 0x8c, 0xb1, 0x1e, 0xa4, 0x75, 0x40, 0x2d, 0xc8, 0x51, 0xcf, 0x09, + 0x31, 0xfa, 0x2a, 0xac, 0x32, 0x0a, 0xf5, 0x97, 0xb5, 0x0b, 0xcb, 0x41, 0xc6, 0xea, 0x88, 0x56, + 0x6b, 0x7e, 0x58, 0x86, 0x64, 0xa4, 0xfb, 0xe9, 0x27, 0x95, 0xa3, 0x47, 0xd5, 0x80, 0x84, 0x94, + 0xe7, 0xee, 0xbf, 0xf9, 0xbf, 0x2f, 0x86, 0x48, 0x19, 0x66, 0xd2, 0x03, 0xa6, 0x28, 0x8d, 0xe9, 0x6b, 0xe7, 0xe6, 0xc5, 0xa3, 0x5a, 0xa2, 0x40, 0xbf, 0x29, 0x86, 0x23, 0xd9, 0xd2, 0x0d, 0xc7, 0x84, 0x69, 0x2a, 0x28, 0x08, 0xcf, 0x0a, 0x60, 0x42, 0x65, 0xc7, 0xbe, 0x73, 0x74, 0xd1, 0xc7, 0x21, 0x8a, 0xf8, 0x43, 0x9b, 0xd5, 0x4b, 0xfc, 0x69, 0x1f, 0x03, 0x7a, 0x31, 0xb9, 0x5a, 0xc4, @@ -2688,17 +2688,17 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0xe5, 0x45, 0x7c, 0xde, 0xef, 0xb1, 0x3d, 0x0c, 0x88, 0x58, 0x87, 0x43, 0xce, 0x76, 0x12, 0x61, 0xab, 0x02, 0x4e, 0x43, 0x8f, 0x10, 0xb5, 0x21, 0x53, 0x63, 0xd2, 0x07, 0x82, 0x65, 0x86, 0x7c, 0x1a, 0xa6, 0xf4, 0xb1, 0x6c, 0xb5, 0x64, 0x82, 0xa8, 0xdc, 0xcd, 0x1c, 0x4e, 0xe3, 0xc0, 0x3a, - 0x83, 0x66, 0xeb, 0x72, 0xf4, 0x42, 0x2a, 0x5c, 0x37, 0x59, 0x50, 0xbe, 0xd9, 0x0a, 0x16, 0x61, - 0x88, 0x15, 0x16, 0x58, 0xde, 0xe3, 0x7a, 0x39, 0x1c, 0x51, 0xa7, 0x49, 0x5a, 0x3d, 0x09, 0x12, - 0x23, 0x42, 0xf7, 0xda, 0xff, 0x97, 0x03, 0xe9, 0xc8, 0x29, 0x90, 0x56, 0x98, 0x17, 0x9c, 0x54, + 0x83, 0x66, 0xeb, 0x72, 0xf4, 0x60, 0x05, 0x4d, 0x6d, 0xa0, 0x9e, 0xb9, 0x29, 0x36, 0x40, 0x88, + 0x20, 0x38, 0x8d, 0xc9, 0xae, 0xa2, 0x69, 0x4d, 0x7b, 0x61, 0xe9, 0xc4, 0xb0, 0xd2, 0xbb, 0xc9, + 0x03, 0x1f, 0x94, 0xd2, 0x2c, 0x02, 0xc2, 0xe8, 0xc8, 0x29, 0x90, 0x56, 0x98, 0x17, 0x9c, 0x54, 0x00, 0x29, 0xe7, 0x76, 0xa1, 0x6a, 0xc8, 0x61, 0xb7, 0x2a, 0x1a, 0x90, 0xb1, 0xd3, 0x3c, 0xb6, 0x77, 0x96, 0xb2, 0x84, 0x02, 0xb5, 0xdc, 0x08, 0xc5, 0x4b, 0x71, 0x34, 0xee, 0x20, 0x8a, 0x61, 0x09, 0x05, 0x8e, 0x39, 0xb5, 0xe8, 0xae, 0xb4, 0x37, 0x43, 0x88, 0x76, 0xc1, 0x2c, 0x95, 0x93, 0xf2, 0xfe, 0x74, 0xaf, 0xef, 0xd4, 0x23, 0xa2, 0x4a, 0x28, 0x62, 0xeb, 0xea, 0xbf, 0xfc, 0x85, 0x65, 0xf5, 0xfe, 0x42, 0x98, 0xdf, 0x5b, 0x78, 0x62, 0x6b, 0x63, 0x86, 0x3c, 0x68, 0xb7, 0x18, 0x3f, 0xdc, 0x05, 0x94, 0x8d, 0x00, 0xd3, 0x99, 0x79, 0xa8, 0xab, 0xc6, 0x64, 0xc4, 0xd6, 0x34, - 0xd9, 0xbc, 0x4a, 0x73, 0xbe, 0x3e, 0x66, 0x3a, 0x59, 0xa0, 0xaa, 0x2b, 0xbe, 0x68, 0xa2, 0x89, - 0xeb, 0x49, 0xe0, 0x4d, 0xfe, 0x81, 0x4b, 0x85, 0x78, 0xe8, 0x84, 0x64, 0xde, 0xbb, 0x40, 0x1d, + 0xd9, 0xbc, 0x4a, 0x73, 0xbe, 0x66, 0x32, 0x9f, 0xd3, 0xf3, 0xda, 0x2d, 0xa4, 0x21, 0xd0, 0x6b, + 0xd3, 0xe8, 0x4f, 0x44, 0x02, 0x84, 0x4b, 0x85, 0x78, 0xe8, 0x84, 0x64, 0xde, 0xbb, 0x40, 0x1d, 0x5c, 0x3d, 0x5f, 0x4e, 0x46, 0x95, 0xad, 0xc8, 0xdf, 0xe4, 0x13, 0x36, 0x38, 0xe2, 0xed, 0x6e, 0x9e, 0x2d, 0x4c, 0x9e, 0x5f, 0x08, 0x2a, 0x7b, 0x9d, 0x71, 0x4f, 0xf8, 0x6e, 0x93, 0x50, 0x69, 0x06, 0xcd, 0x71, 0x26, 0xc1, 0x00, 0x21, 0x65, 0x4d, 0xfb, 0x68, 0xaf, 0xf6, 0xbe, 0x89, 0x65, @@ -2749,8 +2749,8 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x31, 0x9f, 0xd8, 0x05, 0xa0, 0x2c, 0x09, 0xcc, 0x12, 0xcb, 0xa9, 0xfe, 0x54, 0x76, 0x39, 0x07, 0xe9, 0xe4, 0xd8, 0x0c, 0xe7, 0x3c, 0x85, 0xe3, 0xae, 0x8e, 0xe9, 0x5c, 0x33, 0xf4, 0x61, 0x84, 0xa4, 0x47, 0xb1, 0xbd, 0x03, 0x91, 0x15, 0x69, 0xbb, 0x00, 0xa8, 0xe6, 0x74, 0xc1, 0x20, 0x6e, - 0x0d, 0xa8, 0x58, 0xc0, 0xbd, 0x1c, 0x48, 0x68, 0x4e, 0x40, 0x3a, 0x46, 0xfd, 0x1b, 0xa0, 0x12, - 0xe7, 0x06, 0x28, 0x1b, 0x64, 0x0b, 0xbc, 0x1a, 0x96, 0x5d, 0x9f, 0xd6, 0xe3, 0x9a, 0x9e, 0xf8, + 0x0d, 0xa8, 0x58, 0xc0, 0xbd, 0x5c, 0x09, 0x29, 0xfe, 0x83, 0x15, 0xc6, 0x16, 0x3c, 0x9c, 0xf5, + 0x0b, 0x33, 0x6a, 0x0a, 0x50, 0x11, 0xbc, 0x1a, 0x96, 0x5d, 0x9f, 0xd6, 0xe3, 0x9a, 0x9e, 0xf8, 0xb0, 0xe4, 0xfd, 0x07, 0xc9, 0xd8, 0xde, 0x82, 0xc9, 0x54, 0x4d, 0x21, 0xc6, 0xef, 0x0f, 0xfe, 0xec, 0x8e, 0x2b, 0xad, 0xfd, 0xf8, 0xcb, 0x80, 0x75, 0x42, 0xeb, 0xf6, 0x7a, 0xde, 0x45, 0x2d, 0x56, 0xbc, 0x61, 0xa2, 0x61, 0x95, 0xad, 0xa5, 0x42, 0x60, 0x41, 0x5d, 0x44, 0xaa, 0xbc, 0xed, @@ -2770,359 +2770,359 @@ static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] 0x74, 0xd5, 0xe4, 0x45, 0x00, 0xbc, 0x15, 0xa1, 0xe7, 0x0b, 0xe0, 0x6b, 0x3f, 0x9e, 0xeb, 0x8a, 0xdb, 0xbf, 0x03, 0x5a, 0xc4, 0xd7, 0xd2, 0x86, 0x2e, 0x3b, 0xd5, 0x70, 0xf7, 0xb5, 0x34, 0x29, 0xea, 0x03, 0x5e, 0x11, 0x1d, 0x9a, 0x2a, 0xec, 0x33, 0x97, 0x39, 0x0d, 0x0c, 0x8f, 0x89, 0xec, - 0x53, 0x06, 0x8d, 0x16, 0x54, 0x97, 0xff, 0x5d, 0x9f, 0x07, 0x13, 0xef, 0xb1, 0x81, 0xf5, 0x64, - 0x3f, 0x15, 0xd4, 0x5c, 0xc4, 0x06, 0x77, 0x4e, 0x2b, 0xa9, 0x0d, 0x88, 0xdb, 0x16, 0x93, 0x8f, - 0xcb, 0x3b, 0x58, 0x15, 0xbc, 0xf9, 0x92, 0x50, 0x75, 0x92, 0xfc, 0xdb, 0xba, 0x72, 0x3b, 0xf6, - 0x07, 0xc9, 0x2c, 0xaf, 0x9c, 0x17, 0x74, 0x59, 0x97, 0xae, 0x74, 0xb6, 0xeb, 0xe8, 0xd7, 0x2e, - 0x68, 0x59, 0xe3, 0x13, 0x42, 0xf2, 0x29, 0xfa, 0xbd, 0xd1, 0x35, 0x88, 0x87, 0x74, 0x4e, 0x5c, - 0xee, 0xb3, 0x9b, 0xc9, 0x0b, 0x7b, 0x63, 0x37, 0x29, 0xbc, 0xd6, 0x0a, 0x2c, 0x2a, 0xa6, 0xfd, - 0x21, 0xf5, 0xa3, 0x4c, 0x97, 0xd2, 0x00, 0xef, 0xcf, 0x0f, 0xaf, 0x45, 0x5d, 0xc0, 0xed, 0x45, - 0x79, 0x81, 0x4c, 0xe4, 0x86, 0xb1, 0x7b, 0x89, 0xef, 0xe7, 0xf7, 0x52, 0xec, 0xd7, 0xd8, 0x60, - 0x6c, 0xd7, 0xf5, 0x58, 0x04, 0xf8, 0x7e, 0xd3, 0xac, 0xb8, 0xa7, 0xe5, 0xd9, 0xa2, 0x1b, 0x9f, - 0x12, 0xa8, 0xdf, 0xe7, 0x4c, 0xf2, 0xcf, 0x4c, 0xeb, 0xa0, 0xfb, 0x6a, 0xdd, 0x79, 0xc8, 0xe7, - 0xb8, 0xed, 0xb3, 0xf6, 0x3b, 0x57, 0xe2, 0x99, 0x86, 0xad, 0xc4, 0x67, 0xac, 0x3a, 0x10, 0x06, - 0x3d, 0x54, 0xc7, 0xfa, 0x1d, 0x94, 0x3b, 0xab, 0x8c, 0x36, 0x20, 0x50, 0x19, 0xa5, 0x02, 0x13, - 0xea, 0x41, 0xd1, 0xc1, 0x25, 0xee, 0x8d, 0xaf, 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0xa2, 0xc9, 0x10, 0xdc, 0x83, + 0x1e, 0x93, 0x31, 0xf1, 0x22, 0xaf, 0x51, 0x19, 0x4c, 0x36, 0x57, 0x34, 0x8e, 0x1a, 0x36, 0xcb, + 0xa1, 0x60, 0x5c, 0x84, 0x4b, 0x1d, 0x17, 0x11, 0xae, 0x7e, 0xb8, 0x87, 0x0d, 0xc6, 0x06, 0xe7, + 0x61, 0xd8, 0x64, 0x5b, 0xeb, 0xf4, 0xd6, 0x08, 0xc5, 0x5b, 0xcd, 0xfe, 0x63, 0xd7, 0x31, 0x9b, + 0x38, 0x1c, 0xa2, 0x20, 0x81, 0xe6, 0x2a, 0x1a, 0xd0, 0xed, 0x74, 0xcf, 0x4d, 0x86, 0x4d, 0x68, + 0x4d, 0x27, 0xa8, 0x79, 0xc3, 0x82, 0x48, 0x5d, 0xe4, 0xc2, 0x27, 0x40, 0x0f, 0xf5, 0xdf, 0xfe, + 0x55, 0x16, 0xc4, 0xb3, 0xe5, 0x7d, 0xd2, 0x06, 0xdf, 0x6d, 0xb1, 0x3d, 0x6e, 0x23, 0xe5, 0xcc, + 0x63, 0x25, 0x9d, 0xb9, 0x6b, 0x18, 0xee, 0x56, 0x0d, 0x8a, 0x83, 0xf1, 0x40, 0x81, 0xd3, 0xc8, + 0x57, 0x9b, 0x9b, 0xa5, 0x85, 0xab, 0xdc, 0xea, 0xd1, 0x7a, 0x85, 0xfb, 0xfe, 0x70, 0x91, 0x98, + 0xac, 0x6d, 0x28, 0xcc, 0x06, 0x7c, 0xf0, 0xa6, 0xc9, 0xc7, 0xc9, 0x81, 0x41, 0x3f, 0x83, 0x1a, + 0x13, 0x88, 0xf9, 0xcf, 0xb4, 0x60, 0x03, 0x8a, 0xb5, 0xbc, 0x61, 0xd6, 0x6d, 0x5e, 0xff, 0x30, + 0xc7, 0x6d, 0x61, 0x11, 0x14, 0x8f, 0x4c, 0xd3, 0xe4, 0x7d, 0x66, 0xd8, 0x00, 0xdb, 0x4a, 0x81, + 0xb9, 0x08, 0xef, 0x5a, 0x89, 0x0a, 0x13, 0xb7, 0x11, 0xdd, 0x90, 0x52, 0xb0, 0x24, 0x55, 0x31, + 0x6b, 0x73, 0x66, 0x8a, 0x38, 0x19, 0x57, 0xe8, 0x9b, 0x0f, 0x18, 0x6c, 0xe6, 0xb9, 0x23, 0x9f, + 0x80, 0x23, 0xce, 0xd2, 0xb1, 0x5c, 0x2f, 0xd9, 0x4e, 0x6c, 0x8d, 0x54, 0xd6, 0xfd, 0xd9, 0x97, + 0x07, 0x2b, 0x38, 0x21, 0xb4, 0xcf, 0xb3, 0xfb, 0xea, 0xcd, 0x43, 0xa0, 0xf9, 0xec, 0x5a, 0xb0, + 0xc3, 0x7f, 0xe3, 0x8b, 0xd0, 0xca, 0x40, 0xed, 0xcc, 0xd5, 0xc7, 0xf3, 0x81, 0x0f, 0x09, 0xf8, + 0x4c, 0x95, 0x1e, 0x9d, 0xdd, 0xb7, 0x7c, 0xb3, 0x9d, 0x04, 0xbe, 0x25, 0xcb, 0x40, 0x01, 0xa0, + 0xb4, 0xaa, 0x84, 0x11, 0x32, 0xfc, 0x92, 0x95, 0xc4, 0x25, 0x27, 0x03, 0x90, 0x08, 0x3c, 0x70, + 0x40, 0x66, 0x8b, 0xcf, 0x76, 0xa7, 0xc0, 0x4a, 0x20, 0x77, 0x8e, 0x8d, 0xc3, 0xe7, 0x02, 0xd2, + 0xcc, 0x9c, 0x52, 0x1f, 0xe5, 0xad, 0xdd, 0x14, 0x88, 0x2a, 0xd0, 0x3f, 0x0b, 0xd0, 0x7b, 0x55, + 0x4c, 0xfe, 0xa0, 0xeb, 0x21, 0x5d, 0x1e, 0xf0, 0x72, 0x6b, 0xd3, 0xb7, 0xdd, 0x78, 0x8d, 0x42, + 0x90, 0x3a, 0xc4, 0x24, 0x86, 0xd8, 0xed, 0x4d, 0x46, 0x3a, 0xbb, 0x11, 0x8c, 0xd6, 0xd9, 0x34, + 0x3e, 0x46, 0x14, 0x00, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, - 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, - 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0x7f, 0xc6, 0xff, 0x05, 0xd9, - 0x47, 0x1b, 0xdc, 0x00, 0x8b, 0x00, 0x00, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0x9f, 0xf1, 0x7f, 0x01, 0xe8, + 0x2b, 0x8b, 0xbf, 0x00, 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3189,7 +3189,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0x8b, 0x1c, 0x78, 0x34, 0xe5, 0x94, 0xac, 0x85, 0x59, 0x61, 0x6e, 0x28, 0x20, 0xca, 0xa6, 0x19, + 0xa0, 0x36, 0x85, 0x48, 0xdb, 0x21, 0x06, 0x83, 0x93, 0x8c, 0xb1, 0xa2, 0xe3, 0xef, 0x78, 0x7e, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3222,7 +3222,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0x95, 0x28, 0x91, 0x0c, 0x23, 0xf7, 0xa5, 0xcc, 0x80, 0x32, 0xd5, 0x1d, 0x15, 0x69, 0x91, 0x78, + 0xec, 0x58, 0xd9, 0x1f, 0x66, 0x9d, 0xcc, 0xa0, 0x7d, 0xa7, 0xec, 0xee, 0x64, 0xab, 0xcd, 0xd9, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c new file mode 100644 index 000000000..05fe73c52 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -0,0 +1,1369 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("image_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_dbg.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_data_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 8960 +// COMPRESSED SIZE (bytes): 7012 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = +{ + 0xed, 0x99, 0x65, 0x50, 0x5d, 0xdd, 0x96, 0xae, 0x91, 0x04, 0x77, 0x77, 0x87, 0x8d, 0xbb, 0xbb, + 0xbb, 0x07, 0x77, 0xdf, 0xc1, 0x09, 0x6e, 0xc1, 0xdd, 0xdd, 0x82, 0xbb, 0xbb, 0x06, 0x0b, 0x12, + 0x3c, 0xb8, 0x67, 0xe3, 0xbe, 0x71, 0x87, 0x60, 0xcd, 0xe9, 0xfe, 0x6e, 0xdd, 0xae, 0xaf, 0xee, + 0xfd, 0xd3, 0xdd, 0x55, 0xe7, 0x47, 0x9f, 0xb7, 0xea, 0x59, 0x63, 0x8c, 0xb9, 0x46, 0xd5, 0xbb, + 0xe6, 0x9c, 0x7f, 0xd6, 0x5c, 0x0b, 0x02, 0xe2, 0x7f, 0xb7, 0x04, 0xc8, 0x73, 0x46, 0x6b, 0xbf, + 0xba, 0xc4, 0x84, 0x3a, 0x44, 0x68, 0xc4, 0xc9, 0x5f, 0x74, 0x04, 0x14, 0xdd, 0x38, 0x91, 0x74, + 0xfa, 0x31, 0x9c, 0x98, 0xf5, 0xcb, 0x3c, 0x7c, 0x7b, 0xec, 0xdc, 0xef, 0x4c, 0x1d, 0x8e, 0x65, + 0x08, 0xed, 0x80, 0xaf, 0xf6, 0x4d, 0xb3, 0x3b, 0xa5, 0x5d, 0x6d, 0x5b, 0x95, 0xb0, 0x26, 0x4c, + 0xe6, 0x0c, 0x84, 0xaf, 0x0f, 0x13, 0x6e, 0xa8, 0x21, 0xf4, 0x5e, 0x29, 0x2b, 0x54, 0x03, 0x0f, + 0x56, 0xef, 0xef, 0x9c, 0x18, 0x48, 0x08, 0x24, 0xe1, 0x1a, 0xdb, 0xfe, 0xec, 0xdc, 0x87, 0xd7, + 0xbd, 0x10, 0x83, 0xe1, 0x53, 0xec, 0x8f, 0x9a, 0x9a, 0xf3, 0x53, 0xde, 0xa6, 0x42, 0x95, 0x72, + 0x47, 0xa0, 0x45, 0x32, 0x9d, 0xe4, 0xd5, 0xc5, 0xab, 0xf7, 0x6f, 0x32, 0x58, 0xd1, 0x72, 0x26, + 0x77, 0x25, 0x80, 0x52, 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0x1d, + 0x2c, 0xdf, 0x0b, 0x55, 0x05, 0xb1, 0xbf, 0x0a, 0x32, 0x7d, 0xf5, 0x4f, 0x62, 0x64, 0xf6, 0x8e, + 0x16, 0x96, 0x86, 0x7f, 0x1b, 0x97, 0x92, 0x90, 0xf8, 0x6b, 0xfc, 0x5d, 0xbc, 0x1f, 0xdf, 0x2f, + 0xef, 0xb0, 0xbd, 0x07, 0xb2, 0xff, 0xe1, 0x39, 0x21, 0xbd, 0x83, 0xfb, 0x0e, 0xf9, 0x3b, 0x52, + 0xef, 0x1e, 0x68, 0xef, 0xb0, 0xbe, 0xe7, 0x50, 0x90, 0xff, 0xef, 0x7e, 0xfa, 0xff, 0x86, 0x17, + 0x0e, 0xc4, 0x7f, 0x3c, 0xbf, 0xe1, 0x7f, 0xf2, 0xf9, 0x00, 0xf7, 0xff, 0xef, 0x4f, 0xff, 0x4f, + 0x79, 0xc6, 0x3b, 0x99, 0xef, 0xc8, 0xbc, 0x23, 0xfb, 0x8e, 0xdc, 0x3b, 0xf2, 0x7f, 0xdd, 0x53, + 0xfc, 0x2b, 0x2a, 0xfd, 0xcd, 0x87, 0xec, 0x2f, 0x9f, 0x7f, 0xac, 0xdd, 0xbf, 0xef, 0x01, 0xc4, + 0xfb, 0x12, 0x43, 0x7c, 0x92, 0x62, 0xfd, 0x2f, 0xce, 0xe1, 0xdf, 0x00, 0x73, 0x77, 0xcf, 0xf4, + 0x00, 0x23, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 8960, // uncompressed data size (bytes) + 7012, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("header_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_dbg.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_header_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("image_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_prod.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_data_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 8960 +// COMPRESSED SIZE (bytes): 7010 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data[] = +{ + 0xed, 0x99, 0x55, 0x70, 0x1d, 0xcb, 0x92, 0xae, 0xc5, 0x6c, 0x31, 0x33, 0x33, 0x93, 0x85, 0x16, + 0xb3, 0x96, 0xd8, 0x62, 0x66, 0x66, 0x8b, 0x99, 0x99, 0x99, 0x59, 0x5a, 0x96, 0x2c, 0x26, 0x8b, + 0xb5, 0x2c, 0x66, 0x96, 0xc5, 0xcc, 0x16, 0x33, 0x8f, 0xce, 0xcc, 0xbe, 0x71, 0x27, 0x76, 0xdc, + 0xfb, 0x32, 0x33, 0x11, 0xe7, 0x61, 0xce, 0x1f, 0xf1, 0x75, 0x66, 0x56, 0x67, 0xc4, 0xdf, 0x55, + 0xfd, 0x52, 0xd5, 0x0d, 0x06, 0xf6, 0xbf, 0x5b, 0x7a, 0x16, 0x14, 0xad, 0x4a, 0x82, 0xcc, 0xb0, + 0x6f, 0x6f, 0xe2, 0xbc, 0xfa, 0x14, 0xf2, 0x32, 0xa7, 0x8d, 0x76, 0x95, 0x13, 0xf7, 0x7d, 0x7d, + 0x49, 0x4a, 0x71, 0x07, 0xba, 0x6b, 0xaa, 0x01, 0xca, 0x14, 0x4c, 0xd0, 0xa3, 0x0a, 0x2a, 0x2a, + 0x46, 0xf3, 0x66, 0x39, 0xcf, 0xfa, 0xc3, 0xb3, 0x5b, 0xa1, 0x85, 0x4d, 0x32, 0xf0, 0x4b, 0x7a, + 0xf1, 0x1e, 0xa3, 0xf7, 0xdd, 0xbf, 0x4c, 0xea, 0x62, 0x3c, 0xa2, 0xd6, 0xd3, 0x2f, 0x9c, 0xcd, + 0xc8, 0x6e, 0xd4, 0xdf, 0xd3, 0x56, 0x61, 0x3e, 0xbd, 0xc2, 0xee, 0xa2, 0x87, 0x94, 0xe2, 0x5c, + 0xa5, 0x7d, 0x26, 0x5e, 0x36, 0x29, 0x70, 0xa4, 0xcc, 0xa7, 0x2a, 0xfb, 0x26, 0xf0, 0x53, 0x20, + 0x8f, 0xab, 0x90, 0xcf, 0x5a, 0x7d, 0xeb, 0xd2, 0xd5, 0xbc, 0x15, 0x56, 0xa8, 0x9e, 0x15, 0x31, + 0x89, 0xae, 0x85, 0x53, 0x41, 0x3c, 0xfe, 0xcb, 0xf7, 0xd1, 0x5f, 0x81, 0x27, 0x55, 0x3a, 0xea, + 0x9b, 0x09, 0xa0, 0x28, 0x43, 0xcf, 0x2d, 0xba, 0xaf, 0x89, 0x1b, 0x24, 0xef, 0x09, 0xd0, 0xe5, + 0xd3, 0x82, 0xc0, 0x53, 0x47, 0x7b, 0xaa, 0xe1, 0xa4, 0x8a, 0x58, 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0x1c, 0x71, 0x0e, 0x98, 0x51, 0x2f, 0x4a, 0xd7, 0x09, 0x1f, 0xed, 0x2a, 0xd4, 0x69, 0xd6, 0x21, + 0x07, 0x60, 0xe8, 0x8d, 0xdb, 0x5a, 0x2f, 0xda, 0xc1, 0x58, 0x0d, 0x3a, 0xdf, 0xba, 0x8b, 0x0a, + 0xb2, 0x2f, 0x4b, 0x6e, 0xb0, 0x58, 0xe5, 0x2a, 0x63, 0x21, 0x51, 0x8c, 0xe8, 0x99, 0x6c, 0xbf, + 0xb9, 0x6e, 0x8d, 0x62, 0x9f, 0x2b, 0xf9, 0xfb, 0x38, 0x6f, 0x63, 0xa0, 0xcf, 0x8e, 0xf9, 0xb1, + 0x7e, 0x6f, 0xc3, 0x9b, 0x31, 0x94, 0x1c, 0x14, 0xf1, 0xf9, 0x21, 0xeb, 0xa2, 0xc1, 0x8e, 0x7b, + 0xf9, 0x39, 0xec, 0x2e, 0x6e, 0x7b, 0x7c, 0x0d, 0x1a, 0x8a, 0x08, 0x21, 0xe8, 0xfa, 0xd6, 0xe8, + 0xab, 0x02, 0x07, 0xc9, 0x31, 0x8a, 0x67, 0xdc, 0xdb, 0xcf, 0x70, 0xdc, 0xad, 0x5b, 0x84, 0x87, + 0x64, 0xf3, 0xcd, 0xb9, 0x20, 0xa8, 0x02, 0x65, 0x5e, 0x69, 0x2f, 0xa7, 0x6f, 0xfe, 0xc9, 0xf5, + 0x6a, 0x3b, 0x5c, 0xf5, 0x51, 0x93, 0x6f, 0x66, 0xe3, 0xaf, 0xec, 0x08, 0x0e, 0x7d, 0xa6, 0x63, + 0x5c, 0xa6, 0xd2, 0xd6, 0x63, 0x9b, 0x77, 0xc6, 0xcd, 0xf0, 0x3e, 0x46, 0x5c, 0xc5, 0x6e, 0x57, + 0xd5, 0x35, 0x43, 0x37, 0x1e, 0xab, 0xf9, 0xee, 0x45, 0xda, 0x9e, 0xfa, 0x8c, 0x58, 0xf1, 0x67, + 0x5d, 0xd5, 0xa5, 0x62, 0x12, 0x1c, 0x0d, 0xaf, 0xf2, 0x1e, 0x68, 0xf6, 0x0f, 0xdf, 0xea, 0x12, + 0x2c, 0x8a, 0xc8, 0x83, 0x04, 0xba, 0x29, 0x1e, 0x21, 0xb0, 0x68, 0xa6, 0x6a, 0x7b, 0x5b, 0xfe, + 0x34, 0x45, 0x86, 0x4a, 0x38, 0xa8, 0xa5, 0xfe, 0x9e, 0xcf, 0xed, 0x60, 0x7e, 0x6a, 0x5c, 0x1f, + 0x59, 0x66, 0x89, 0x26, 0x36, 0x70, 0xa3, 0xf4, 0x58, 0xfc, 0x67, 0xd7, 0xff, 0xec, 0xff, 0x6f, + 0xff, 0xd2, 0xbf, 0xf4, 0x2f, 0xfd, 0x4b, 0xff, 0x2c, 0x75, 0xc0, 0x80, 0x81, 0x41, 0x7c, 0x44, + 0xf0, 0xbf, 0x00, 0xc1, 0xfc, 0xdf, 0xfc, 0x1f, 0x0c, 0xc0, 0xfc, 0x47, 0xdf, 0xff, 0xa9, 0xc1, + 0xd0, 0xbd, 0xfe, 0x3d, 0x2a, 0xa8, 0xab, 0x28, 0x48, 0x91, 0x9a, 0xd9, 0x5b, 0x58, 0xd9, 0x9b, + 0x7d, 0x14, 0x4a, 0x72, 0x22, 0x7f, 0x15, 0xa4, 0x3a, 0x2a, 0xaa, 0x22, 0xa4, 0x76, 0x0e, 0xa6, + 0x66, 0x7a, 0x7f, 0x1b, 0x97, 0x10, 0x13, 0xfb, 0x6b, 0xfc, 0x43, 0x3c, 0xd0, 0x1f, 0x97, 0x0f, + 0xd8, 0x3e, 0x02, 0xe9, 0xff, 0xf0, 0x9c, 0x90, 0x3e, 0xc0, 0xf9, 0x80, 0xec, 0x03, 0x89, 0x0f, + 0x0f, 0xd4, 0x0f, 0x58, 0x3f, 0x72, 0x08, 0xf0, 0xff, 0x77, 0x3f, 0xfd, 0x7f, 0xc3, 0x0b, 0x1b, + 0xec, 0x3f, 0x9e, 0x5f, 0xef, 0x3f, 0xf9, 0x40, 0xc1, 0xfd, 0xff, 0xfb, 0xd3, 0xff, 0x53, 0x9e, + 0xf1, 0x41, 0xe6, 0x07, 0x52, 0x1f, 0x48, 0x7f, 0x20, 0xf3, 0x81, 0xec, 0x5f, 0xf7, 0xe4, 0xff, + 0x8a, 0x80, 0xbf, 0xf9, 0x90, 0xfe, 0xe5, 0xf3, 0x8f, 0xb5, 0xfb, 0xf7, 0x77, 0x00, 0xf6, 0xb1, + 0xc4, 0x60, 0xaa, 0x12, 0xac, 0xff, 0xc5, 0x39, 0xfc, 0x1b, 0x5e, 0xbe, 0x55, 0xca, 0x00, 0x23, + 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 8960, // uncompressed data size (bytes) + 7010, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("header_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_prod.h +// FILE TYPE: TEXT +// VAR NAME: booter_ucode_header_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("sig_dbg") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_unload_sig_dbg_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x05, 0xc8, 0x8d, 0x0a, 0x2d, 0x7a, 0xb2, 0x85, 0x54, 0x06, 0xb2, + 0x6c, 0x83, 0x69, 0x50, 0x0e, 0xd3, 0xf1, 0x2a, 0xc6, 0x07, 0xfc, 0xae, 0x72, 0x6e, 0x18, 0x6c, + 0x3c, 0x00, 0x84, 0x54, 0xfb, 0xa8, 0x65, 0x12, 0xb8, 0x5e, 0xfd, 0xe9, 0x49, 0xea, 0x94, 0x46, + 0x40, 0xed, 0x54, 0x94, 0x74, 0x28, 0x78, 0x68, 0x96, 0x2c, 0xa9, 0xce, 0x90, 0x9c, 0x5b, 0x26, + 0x3a, 0x2e, 0xd7, 0xbe, 0xf5, 0x54, 0xe1, 0x8a, 0xe5, 0x7d, 0xd7, 0x50, 0xec, 0x77, 0x91, 0xfe, + 0x3e, 0x2d, 0xa0, 0x46, 0xea, 0x76, 0x41, 0x6f, 0x61, 0x57, 0x2b, 0x80, 0x20, 0x48, 0xd2, 0x9c, + 0x3c, 0xc5, 0x35, 0x82, 0x85, 0xd0, 0xd5, 0x4f, 0x64, 0xa4, 0x23, 0xc0, 0x0f, 0x50, 0xae, 0xce, + 0x8d, 0x9f, 0xc9, 0xed, 0x52, 0x74, 0xa0, 0xfd, 0x51, 0xd6, 0x7c, 0x8b, 0xd7, 0x6a, 0x18, 0xc5, + 0xa6, 0xea, 0x33, 0x8e, 0x9c, 0x9b, 0x88, 0x23, 0x35, 0x8e, 0x13, 0x0e, 0x59, 0x46, 0x67, 0xd7, + 0xa5, 0x74, 0x47, 0xbf, 0xa7, 0x8e, 0xdc, 0xea, 0x4e, 0xd7, 0x8b, 0x05, 0xca, 0x2c, 0x4d, 0x16, + 0x92, 0xdf, 0xad, 0xd4, 0x32, 0x0f, 0x31, 0xe0, 0x6b, 0x28, 0x36, 0x74, 0xee, 0x0d, 0xae, 0x91, + 0x8a, 0x5d, 0x18, 0xa9, 0x52, 0x85, 0x21, 0x57, 0x27, 0xd7, 0xed, 0x7e, 0x5f, 0x95, 0x5a, 0x40, + 0xd3, 0xf2, 0x17, 0xda, 0xc7, 0x25, 0xdf, 0x92, 0xe5, 0x46, 0x4e, 0x7b, 0x11, 0xe9, 0x95, 0xa4, + 0x88, 0x44, 0x56, 0x68, 0xe6, 0xdf, 0xf3, 0x89, 0xf1, 0x5b, 0x34, 0x2e, 0xea, 0xed, 0xb4, 0x96, + 0xd9, 0xfd, 0x1e, 0xfe, 0x34, 0x13, 0xf7, 0xbd, 0xc2, 0xfe, 0x41, 0x2c, 0xb8, 0x46, 0x24, 0x0f, + 0x62, 0x7d, 0x6f, 0x4a, 0x81, 0x96, 0xba, 0xd5, 0xfd, 0xf7, 0x6b, 0x51, 0xab, 0x33, 0x16, 0x44, + 0xd3, 0x5d, 0xe6, 0x1d, 0x7a, 0x97, 0x06, 0x1d, 0xd0, 0x62, 0xc7, 0x66, 0x5f, 0x9e, 0x76, 0xa8, + 0x6c, 0xf9, 0x92, 0xb0, 0xe9, 0xee, 0x10, 0x98, 0xef, 0xdf, 0xb4, 0x5b, 0x28, 0x96, 0x3b, 0xfd, + 0x22, 0xf4, 0x9a, 0x68, 0x04, 0x2c, 0xd3, 0x42, 0xce, 0xab, 0x65, 0x43, 0xfc, 0x1e, 0x12, 0xc1, + 0xaa, 0x82, 0xad, 0x7a, 0x6c, 0xa5, 0x86, 0x38, 0xc5, 0x53, 0xa0, 0x4f, 0xd7, 0xe1, 0x8d, 0xb9, + 0x4f, 0xe2, 0x20, 0x4e, 0x24, 0x2e, 0x54, 0xb1, 0x67, 0x5e, 0x0d, 0x90, 0xe4, 0xef, 0xd4, 0x56, + 0x6c, 0x22, 0x14, 0xb9, 0x83, 0xd6, 0xae, 0xf8, 0x91, 0x38, 0xda, 0x71, 0x11, 0x40, 0xd0, 0x05, + 0x56, 0x25, 0x2c, 0x8b, 0xa0, 0xd8, 0x59, 0xe7, 0x38, 0x2b, 0x53, 0xf0, 0x23, 0x9f, 0x18, 0x44, + 0x2b, 0xca, 0x29, 0x07, 0xfa, 0x9d, 0x33, 0x8f, 0x32, 0x71, 0xb2, 0x39, 0x7e, 0x4a, 0x45, 0xd7, + 0xd2, 0xdb, 0xd5, 0xd3, 0x0a, 0x02, 0x67, 0xc4, 0x2c, 0x91, 0x2d, 0x70, 0xde, 0x01, 0xc7, 0x23, + 0x7a, 0xbb, 0xd6, 0xe8, 0x76, 0xb6, 0x97, 0xce, 0x91, 0x8e, 0x16, 0xa4, 0x71, 0x35, 0x20, 0x39, + 0xe0, 0x85, 0xb3, 0x96, 0x01, 0xa2, 0x15, 0x84, 0x34, 0x6c, 0xea, 0x29, 0x22, 0x5b, 0x24, 0x8d, + 0x2e, 0x7d, 0x98, 0x84, 0xe7, 0xc9, 0xdf, 0xfe, 0x9a, 0xba, 0x05, 0x04, 0x95, 0x56, 0xf0, 0xc7, + 0x09, 0xc0, 0xa3, 0x2e, 0xfb, 0x90, 0xe5, 0x74, 0xd2, 0xb9, 0xad, 0xe3, 0x1d, 0x45, 0x8c, 0x2e, + 0x45, 0xfa, 0x47, 0x78, 0xa8, 0x98, 0x63, 0x4a, 0xbb, 0xa2, 0x16, 0xb5, 0xca, 0x26, 0xb3, 0x74, + 0x45, 0xb9, 0xc2, 0x76, 0x84, 0xcc, 0xec, 0x01, 0x50, 0x25, 0x33, 0x84, 0x0d, 0x1a, 0xcb, 0x19, + 0x26, 0xdb, 0xd3, 0x71, 0xcb, 0x09, 0x59, 0x75, 0xbb, 0x9d, 0xd2, 0xd5, 0x63, 0x98, 0x2e, 0xe0, + 0x09, 0xea, 0xc3, 0x5c, 0xf6, 0xd8, 0x1c, 0x38, 0xbc, 0xc1, 0xe5, 0xfa, 0x98, 0xf5, 0xf8, 0x07, + 0xe2, 0x66, 0x75, 0x2b, 0x49, 0xcc, 0x34, 0x0d, 0x06, 0x8f, 0xbe, 0x42, 0xec, 0xeb, 0xf9, 0xa6, + 0x97, 0xa9, 0xe7, 0x8e, 0x20, 0xb6, 0x91, 0x0a, 0xd3, 0x9c, 0x67, 0xec, 0xea, 0x0e, 0x0f, 0xee, + 0xa9, 0xc4, 0x68, 0xd5, 0xaa, 0x0d, 0xd1, 0xbe, 0x8f, 0x7a, 0xff, 0xef, 0x2e, 0xcb, 0x6a, 0x28, + 0xf3, 0x46, 0x29, 0xc0, 0xf7, 0x34, 0x01, 0xf6, 0x0e, 0xaa, 0x9b, 0xad, 0x52, 0x2d, 0x50, 0x31, + 0x57, 0x3e, 0x88, 0x8c, 0x17, 0x49, 0x5d, 0x9a, 0xaa, 0xc5, 0xa1, 0x82, 0x96, 0x2f, 0xea, 0x4f, + 0xac, 0x4b, 0xd8, 0x9b, 0x0f, 0xf3, 0x07, 0x12, 0xe6, 0xa2, 0x85, 0xd1, 0x7c, 0xb6, 0x63, 0x73, + 0x76, 0x90, 0xfc, 0x5b, 0x6e, 0xaf, 0xba, 0x93, 0x12, 0xeb, 0x35, 0xcb, 0x26, 0x0e, 0xe0, 0xf7, + 0x45, 0x27, 0x69, 0xb5, 0x60, 0xa6, 0xb3, 0xe4, 0x32, 0x59, 0xae, 0xc8, 0x15, 0x5f, 0xe0, 0x59, + 0x1b, 0xd5, 0x4e, 0xfb, 0xcf, 0xaf, 0x94, 0xec, 0xad, 0xe9, 0x9a, 0xe2, 0x7f, 0x8f, 0x7f, 0xfb, + 0xdd, 0xd7, 0xfd, 0x65, 0x9f, 0x58, 0x88, 0x86, 0xf4, 0x80, 0xa3, 0xd4, 0x7d, 0x98, 0x15, 0x6b, + 0x6f, 0x84, 0x7b, 0x29, 0xdd, 0x34, 0xcb, 0x9c, 0xd2, 0x4e, 0x33, 0x62, 0x0c, 0x1c, 0x97, 0x14, + 0x46, 0x7b, 0x0c, 0x15, 0xfb, 0x73, 0x2a, 0x10, 0xfc, 0x8d, 0xc7, 0x68, 0x4b, 0x2b, 0xbc, 0x48, + 0xb7, 0x76, 0xd0, 0x7b, 0x9e, 0xb7, 0xec, 0x9c, 0x10, 0x55, 0xc1, 0x14, 0x96, 0xb9, 0x52, 0x4d, + 0x3e, 0x5d, 0x37, 0x31, 0x16, 0x88, 0x0c, 0x2d, 0x35, 0xde, 0xb9, 0x7e, 0x2e, 0x87, 0x8d, 0x1d, + 0x7b, 0xbb, 0x84, 0x07, 0x62, 0xc3, 0x99, 0x6f, 0x33, 0x61, 0x68, 0xf7, 0x86, 0x2d, 0xdc, 0x2a, + 0x06, 0x0b, 0xb1, 0x04, 0x09, 0x09, 0x06, 0x4c, 0xe5, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("sig_prod") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_unload_sig_prod_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x2c, 0x46, 0x0f, 0x69, 0x91, 0xb0, 0xb3, 0x3e, 0x62, 0xfc, 0xd8, + 0x7f, 0x3b, 0x5e, 0x6c, 0xb8, 0xe2, 0x16, 0x00, 0x63, 0x7e, 0xb1, 0x99, 0xc7, 0xb7, 0x61, 0x47, + 0x04, 0x4b, 0xd6, 0x2d, 0x9d, 0x7f, 0x4f, 0x86, 0xe8, 0x83, 0x65, 0x9e, 0x62, 0x46, 0xb7, 0x0a, + 0x47, 0x1d, 0x36, 0xed, 0x40, 0x32, 0xfa, 0x35, 0xcc, 0x54, 0x96, 0x5e, 0x61, 0x5a, 0xcb, 0xb4, + 0x13, 0xc7, 0x10, 0xb5, 0xf6, 0xba, 0xf8, 0xde, 0xf5, 0xbc, 0x41, 0x52, 0x41, 0x11, 0xce, 0xb8, + 0x17, 0xcf, 0x31, 0x69, 0x12, 0x6f, 0x66, 0x33, 0x18, 0x38, 0xbb, 0xfc, 0xfd, 0xa8, 0x68, 0x12, + 0xbe, 0xae, 0x10, 0x18, 0xe1, 0x86, 0xd3, 0x92, 0x4b, 0x81, 0x68, 0x44, 0xf1, 0x0a, 0xc6, 0x90, + 0xe1, 0x12, 0x0b, 0xe8, 0x52, 0x73, 0x0d, 0x9a, 0x7d, 0x66, 0x4a, 0xf9, 0x16, 0x4f, 0x2b, 0xc3, + 0x24, 0x51, 0xd4, 0x48, 0xf8, 0x1d, 0x81, 0x30, 0xd4, 0x9b, 0xd4, 0x02, 0xad, 0x9b, 0x12, 0x9f, + 0x23, 0x8b, 0x83, 0x8f, 0x10, 0x56, 0x79, 0x74, 0x3a, 0xaa, 0xbc, 0x05, 0x6e, 0x85, 0x0e, 0xc0, + 0xe4, 0x87, 0xa3, 0xab, 0x03, 0xa3, 0x13, 0x67, 0x60, 0x68, 0xda, 0xca, 0xb9, 0xb8, 0x4c, 0xba, + 0x96, 0x86, 0xbd, 0x1b, 0x93, 0xf6, 0xe3, 0xfa, 0xc7, 0xbb, 0xde, 0x26, 0x67, 0x56, 0x95, 0x36, + 0xc1, 0x34, 0x2a, 0x9a, 0xc8, 0x42, 0x23, 0xa8, 0xbc, 0xbd, 0x8d, 0x16, 0x09, 0x95, 0xdd, 0x55, + 0x79, 0xff, 0xec, 0xae, 0x73, 0x27, 0x36, 0x77, 0x53, 0x00, 0xa7, 0xa4, 0x3f, 0x7c, 0x1c, 0xd5, + 0x9e, 0x00, 0x0d, 0x52, 0x26, 0x9e, 0x4f, 0x63, 0x49, 0xbc, 0x26, 0x8a, 0x36, 0x93, 0x31, 0xe7, + 0xcf, 0x77, 0xd0, 0xb5, 0xe8, 0x2a, 0xac, 0xd8, 0x4c, 0x76, 0xa5, 0x43, 0x2e, 0x05, 0xbc, 0x16, + 0x7b, 0x3c, 0x59, 0x0f, 0x98, 0xcb, 0xa2, 0xc3, 0x4c, 0x69, 0xab, 0xed, 0x86, 0xb5, 0x51, 0x5e, + 0x61, 0x65, 0x92, 0x15, 0x41, 0x2c, 0x08, 0xec, 0xc1, 0x01, 0x0a, 0x30, 0xb3, 0x7f, 0xe7, 0x0d, + 0x55, 0x03, 0xf8, 0x17, 0xc7, 0xdf, 0xc5, 0x02, 0x14, 0xaa, 0xf2, 0x46, 0x55, 0x95, 0xe9, 0x6b, + 0x13, 0xc6, 0xc1, 0x35, 0xc6, 0x66, 0x0d, 0x6e, 0xcf, 0x63, 0x4a, 0x3a, 0x34, 0x1c, 0xb3, 0x82, + 0x58, 0x76, 0x47, 0x7d, 0xfb, 0x26, 0x7e, 0x3c, 0x05, 0x3f, 0x73, 0x5e, 0x3c, 0x0e, 0x45, 0xad, + 0xc0, 0xff, 0xa0, 0x09, 0xe1, 0x12, 0x68, 0x2a, 0x1e, 0xb9, 0x30, 0xde, 0x85, 0x67, 0xc7, 0x56, + 0x37, 0x19, 0x97, 0x2a, 0xc3, 0xae, 0x8a, 0xcf, 0xff, 0x8d, 0x45, 0x66, 0x1b, 0x01, 0x27, 0x39, + 0x04, 0x95, 0x14, 0x42, 0xb7, 0x9d, 0x1b, 0xe9, 0xb4, 0x1a, 0x78, 0xdf, 0x3c, 0x83, 0xfc, 0x10, + 0xe2, 0xdd, 0x5a, 0x98, 0x06, 0x40, 0x19, 0x87, 0xde, 0x00, 0x79, 0x03, 0x9b, 0x03, 0xca, 0x54, + 0x9a, 0x9b, 0x9c, 0x29, 0x6f, 0x5f, 0xb0, 0xec, 0x17, 0x72, 0xbe, 0x02, 0xd5, 0xdd, 0xed, 0x3a, + 0xc0, 0xf8, 0x39, 0x07, 0x8b, 0xbe, 0x89, 0x3f, 0x50, 0xb3, 0xd5, 0xa7, 0xae, 0x25, 0x7d, 0xab, + 0x2f, 0xc2, 0x4f, 0xbd, 0x19, 0xb0, 0x37, 0x31, 0x86, 0xd9, 0x32, 0x5b, 0xcd, 0x67, 0x86, 0xc0, + 0x27, 0x04, 0x26, 0x74, 0xe1, 0xdc, 0xb1, 0x04, 0xf2, 0xc0, 0xb0, 0xd2, 0x7b, 0x96, 0xeb, 0x25, + 0xdc, 0x4e, 0xa1, 0x6e, 0x3b, 0x7e, 0x27, 0xbf, 0x7b, 0x94, 0xf4, 0x69, 0x9c, 0xc9, 0x50, 0xb9, + 0x95, 0x52, 0x58, 0xc7, 0xce, 0x3d, 0xce, 0xa9, 0xc3, 0x88, 0x94, 0x0f, 0xce, 0xaa, 0xf1, 0x4b, + 0x07, 0x9d, 0x65, 0x4c, 0x8e, 0x37, 0xe1, 0xaf, 0x59, 0x01, 0x30, 0x21, 0xa1, 0x23, 0xb8, 0x57, + 0xf4, 0xa3, 0xc4, 0xfe, 0x9e, 0xf6, 0x84, 0x85, 0x4a, 0x89, 0xf9, 0x6b, 0x50, 0xd0, 0x5c, 0xb3, + 0xb2, 0x0c, 0x26, 0x83, 0x19, 0xd5, 0xe4, 0xc8, 0x89, 0xce, 0xc0, 0x0f, 0xf1, 0x70, 0x9e, 0x53, + 0xf5, 0x4f, 0x8e, 0xb6, 0x40, 0x88, 0x9f, 0x8d, 0xa1, 0x37, 0x89, 0xa2, 0x6a, 0x63, 0x84, 0x84, + 0xfe, 0x1a, 0xb9, 0x37, 0x4a, 0xa8, 0x76, 0x50, 0x5e, 0xb1, 0xc3, 0x42, 0x00, 0x99, 0x94, 0x02, + 0xdd, 0x47, 0x62, 0x3c, 0xad, 0x3e, 0x4a, 0x66, 0x93, 0x3b, 0x32, 0x54, 0x58, 0x8e, 0x92, 0xfc, + 0x67, 0x2f, 0x37, 0xcc, 0x62, 0x1d, 0xdb, 0xba, 0xaa, 0xaa, 0x8a, 0x92, 0x28, 0xdd, 0xf2, 0x60, + 0xf0, 0xff, 0xba, 0x13, 0xfa, 0x62, 0x3f, 0x13, 0x27, 0x53, 0x60, 0xad, 0xf6, 0xd9, 0x68, 0xea, + 0x8f, 0xd2, 0x88, 0x0f, 0x15, 0xd4, 0x4f, 0x2d, 0x12, 0x4d, 0x7a, 0xa8, 0x1c, 0xb3, 0xfc, 0x87, + 0xc7, 0x65, 0xa6, 0xd9, 0x3d, 0x1c, 0x58, 0x23, 0x96, 0x71, 0x9f, 0x77, 0x1e, 0xfe, 0xe7, 0x7a, + 0x6b, 0xfc, 0xa5, 0x55, 0x42, 0x20, 0x45, 0x01, 0x67, 0x5f, 0xfc, 0x21, 0xe8, 0xfd, 0xe6, 0x04, + 0xf6, 0x90, 0xc7, 0x82, 0x09, 0x9f, 0x5b, 0x3a, 0xd1, 0xbd, 0xc0, 0xb5, 0xb3, 0xbd, 0x0e, 0xdc, + 0x3f, 0x77, 0x43, 0x78, 0x41, 0x10, 0x11, 0x0a, 0x54, 0xa9, 0x93, 0x41, 0xe8, 0x3d, 0x76, 0x5d, + 0x00, 0xf7, 0x00, 0x42, 0x6b, 0xf0, 0x88, 0x9e, 0x12, 0x05, 0xec, 0x02, 0x0b, 0xb5, 0xaa, 0xba, + 0xeb, 0x34, 0x34, 0x32, 0x70, 0xb6, 0x44, 0x74, 0xaa, 0x7f, 0x93, 0x1b, 0x7b, 0xea, 0x7a, 0xa0, + 0x86, 0xdf, 0x77, 0xa7, 0x30, 0xb0, 0x52, 0xf8, 0xb3, 0x1d, 0x14, 0x52, 0x37, 0x98, 0x4e, 0x1e, + 0x66, 0x7b, 0x2a, 0x00, 0x51, 0xd8, 0x47, 0x19, 0xa9, 0x14, 0xbe, 0x59, 0x2f, 0xe1, 0x6c, 0x3e, + 0x3e, 0x8f, 0xe3, 0x35, 0x6f, 0x09, 0x5e, 0x1d, 0x37, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("patch_loc") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_unload_sig_ad10x_patch_location +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data[] = +{ + 0x10, 0x1c, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("patch_sig") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_unload_sig_ad10x_patch_signature +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_sig_data[] = +{ + 0x00, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_patch_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_patch_sig_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("patch_meta") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: booter_unload_sig_ad10x_patch_meta_data +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 12 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_meta_data[] = +{ + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_patch_meta_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 12, // uncompressed data size (bytes) + 12, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_patch_meta_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveBooterUnloadUcode_AD102("num_sigs") +// FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: num_sigs_per_ucode +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_num_sigs_data[] = +{ + 0x02, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_num_sigs_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + kgspBinArchiveBooterUnloadUcode_AD102_num_sigs_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterUnloadUcode_AD102 = +{ + 10, // entryNum + { + // entries[] : { "name", pBinStorage } + { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt }, + { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt }, + { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt }, + { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pvt }, + { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_storage_pvt }, + { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt }, + { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_storage_pvt }, + { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_patch_sig_storage_pvt }, + { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_patch_meta_storage_pvt }, + { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterUnloadUcode_AD102_num_sigs_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_AD102(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveBooterUnloadUcode_AD102; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c new file mode 100644 index 000000000..f70694604 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -0,0 +1,1111 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_image_dbg") +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ad102_riscv_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 12288 +// COMPRESSED SIZE (bytes): 7342 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = +{ + 0xed, 0x97, 0x65, 0x54, 0x94, 0x6d, 0xd7, 0xf7, 0x67, 0x88, 0x19, 0x40, 0x3a, 0x87, 0x90, 0xee, + 0xee, 0x96, 0x90, 0x4e, 0xe9, 0x46, 0x62, 0x84, 0x01, 0x24, 0x86, 0x46, 0xba, 0x07, 0x04, 0xa9, + 0xa1, 0x1b, 0x44, 0x5a, 0xa5, 0x43, 0xe9, 0x46, 0x10, 0x91, 0xe6, 0xa2, 0x1b, 0x04, 0xa5, 0x91, + 0x10, 0x78, 0xf4, 0x82, 0xfb, 0x7e, 0x9e, 0x8f, 0xef, 0xf7, 0xd7, 0xff, 0x5a, 0xb3, 0x7e, 0x73, + 0xee, 0xbd, 0xcf, 0x63, 0x1f, 0x7b, 0xaf, 0x7d, 0x1c, 0x6b, 0xc6, 0x75, 0x57, 0x53, 0x68, 0x00, + 0x59, 0xbd, 0xb2, 0xf1, 0x4c, 0xc6, 0xe4, 0xe3, 0xf7, 0xf6, 0xe0, 0x71, 0x3d, 0xeb, 0x61, 0x2a, + 0x6a, 0x69, 0xbf, 0xca, 0xe4, 0xf8, 0xa6, 0x5a, 0xf7, 0x82, 0xa4, 0xd7, 0xd8, 0xfb, 0xc4, 0xc2, + 0x35, 0x44, 0x62, 0x2d, 0xef, 0x3f, 0xe1, 0xbe, 0xd7, 0x8a, 0xbf, 0xe5, 0x2e, 0x0e, 0x3f, 0x8f, + 0x10, 0xe0, 0x64, 0x3b, 0x16, 0xb3, 0x9f, 0xa1, 0x07, 0x35, 0xce, 0x7d, 0x14, 0x91, 0x58, 0xe2, + 0xd0, 0xaa, 0xba, 0x7a, 0x23, 0x54, 0x75, 0xd0, 0x30, 0x23, 0xe6, 0xd6, 0x4b, 0x7b, 0xb9, 0xdc, + 0xf8, 0xd4, 0x3e, 0x79, 0xd2, 0xa3, 0x9b, 0xfe, 0x8c, 0xba, 0x91, 0x43, 0x22, 0x0c, 0x82, 0x75, + 0xd4, 0x69, 0x9a, 0xd5, 0x3f, 0xf0, 0x4d, 0xe5, 0xb1, 0x76, 0x9c, 0xc9, 0x3f, 0x93, 0x9a, 0x5f, + 0xfa, 0x45, 0x55, 0xb8, 0xb9, 0xdb, 0xdd, 0xb0, 0x71, 0x74, 0x66, 0x70, 0x85, 0x43, 0x30, 0x40, + 0x49, 0x4a, 0xa7, 0x4e, 0x65, 0x9f, 0xcf, 0x4d, 0x93, 0xec, 0x1a, 0x4e, 0xb1, 0x85, 0xcc, 0x9e, + 0x0f, 0x93, 0x4a, 0xa1, 0xf9, 0xe7, 0x2e, 0x49, 0xa3, 0x18, 0xa1, 0x8d, 0x4f, 0x0c, 0xbb, 0x8b, + 0xc9, 0xb6, 0x68, 0x46, 0x2c, 0x2b, 0x8a, 0xef, 0x85, 0x00, 0xe7, 0xfb, 0x78, 0x34, 0xdd, 0x15, + 0x93, 0xa8, 0x52, 0xdb, 0x5a, 0x20, 0x41, 0xa3, 0xa7, 0x9b, 0xae, 0x93, 0xef, 0x46, 0x31, 0xfd, + 0xc4, 0xba, 0xdb, 0x05, 0x19, 0x43, 0xd1, 0xa3, 0x58, 0x2c, 0xf7, 0x66, 0x46, 0x35, 0x25, 0xcc, + 0xb2, 0x47, 0x3d, 0xdd, 0x94, 0x76, 0x56, 0xc2, 0x0d, 0x7a, 0xb3, 0x8e, 0x30, 0xcb, 0x9f, 0x4d, + 0x7d, 0x9d, 0xe6, 0x95, 0x5d, 0x99, 0x2d, 0x76, 0xb7, 0xa3, 0xc9, 0x1d, 0x75, 0x92, 0x94, 0x0b, + 0x16, 0xdd, 0x6a, 0x4f, 0x1d, 0xb2, 0x40, 0x8c, 0x11, 0x9a, 0xb0, 0x3f, 0xab, 0xc9, 0x4d, 0xf6, + 0x74, 0x15, 0x29, 0xf2, 0x9b, 0xfc, 0x59, 0x38, 0xcc, 0x6b, 0x7e, 0x6c, 0xcb, 0xf8, 0xdd, 0xdf, + 0x31, 0x34, 0xe1, 0x15, 0x76, 0xda, 0x27, 0x66, 0x57, 0x47, 0x3d, 0x47, 0xbc, 0x27, 0x32, 0xbe, + 0x8f, 0x77, 0xbc, 0x04, 0xec, 0xdb, 0x33, 0xca, 0x71, 0x1f, 0x99, 0x2a, 0xd0, 0x08, 0x09, 0xa9, + 0xac, 0xde, 0x94, 0x48, 0x38, 0xe4, 0x69, 0x47, 0xff, 0x6a, 0x2e, 0x05, 0x39, 0x1a, 0xa5, 0x59, + 0x75, 0xc5, 0x23, 0x0b, 0xa8, 0x3b, 0x04, 0x29, 0x39, 0x29, 0x04, 0xf8, 0xd2, 0xbf, 0x2c, 0xf1, + 0x63, 0x9f, 0xd1, 0x66, 0x7b, 0xc4, 0x79, 0x5d, 0xd5, 0x0b, 0x36, 0xc8, 0xf1, 0x79, 0xfe, 0x48, + 0xe0, 0x30, 0x5c, 0x0f, 0x02, 0xcc, 0xcd, 0x66, 0x66, 0x52, 0x78, 0x97, 0x9e, 0xf6, 0xb3, 0x84, + 0x3c, 0x54, 0x67, 0xa0, 0x58, 0x1a, 0x6f, 0xdb, 0x41, 0x29, 0xaa, 0x56, 0x40, 0x1d, 0x5b, 0x69, + 0xfa, 0xa6, 0x86, 0xf9, 0xde, 0x29, 0x0e, 0x1e, 0x24, 0x33, 0x6d, 0xf7, 0x7c, 0xae, 0x21, 0x22, + 0xc0, 0x06, 0xf7, 0x11, 0xef, 0xae, 0xb4, 0xd1, 0x15, 0x87, 0xbc, 0x5c, 0x1d, 0xca, 0xfb, 0x57, + 0xde, 0x5b, 0x95, 0x2b, 0xb1, 0x40, 0x7d, 0xee, 0x38, 0x93, 0xfd, 0x68, 0x3f, 0x5d, 0x93, 0xd5, + 0xae, 0x9b, 0xb0, 0x83, 0x4d, 0x24, 0x5d, 0x96, 0xca, 0x83, 0x80, 0x5a, 0xdb, 0x4c, 0xf8, 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0x3d, 0x86, 0x81, 0xf6, 0xef, 0x5f, + 0x19, 0x5a, 0x41, 0xb4, 0xd0, 0x7f, 0x79, 0x1e, 0x7c, 0xf7, 0xcc, 0x58, 0x4a, 0xf3, 0x2f, 0x59, + 0xef, 0x99, 0x7f, 0xaf, 0x5a, 0x4b, 0x0a, 0x11, 0xba, 0x77, 0xe2, 0xf3, 0xd8, 0xc0, 0xfb, 0x38, + 0xd0, 0x1d, 0xd1, 0xee, 0x89, 0x71, 0x4f, 0xfc, 0x7b, 0x3f, 0xeb, 0x3d, 0x21, 0xf7, 0x24, 0xbe, + 0x27, 0xd5, 0x3d, 0x97, 0x51, 0xee, 0x08, 0x40, 0xbf, 0x5f, 0xe7, 0x9e, 0x9c, 0xff, 0x79, 0xbe, + 0xdf, 0x1f, 0x9c, 0xe4, 0x8e, 0x1e, 0xf7, 0xf4, 0xb9, 0xe7, 0x7f, 0x2f, 0x64, 0x62, 0xc8, 0xbf, + 0x60, 0x06, 0xe0, 0xff, 0xcb, 0xdb, 0x7b, 0xfd, 0xd7, 0xcf, 0x7b, 0xff, 0xf9, 0x2d, 0x19, 0xac, + 0xff, 0xf7, 0x7b, 0xfe, 0xaf, 0xfe, 0xea, 0xaf, 0xfe, 0xea, 0xaf, 0xfe, 0xea, 0xaf, 0xfe, 0xea, + 0xaf, 0xfe, 0xea, 0x8f, 0xfe, 0x07, 0xfa, 0xf0, 0x75, 0x19, 0x00, 0x30, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 12288, // uncompressed data size (bytes) + 7342, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_desc_dbg") +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ad102_riscv_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 43 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = +{ + 0x63, 0x65, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, + 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x36, 0x75, 0x06, + 0x10, 0x41, 0x00, 0x42, 0x1a, 0xfd, 0xdc, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 43, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_image_prod") +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ad102_riscv_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 12288 +// COMPRESSED SIZE (bytes): 7340 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = +{ + 0xed, 0x94, 0x75, 0x54, 0xd4, 0x5d, 0xb7, 0xc7, 0x87, 0x9a, 0x01, 0x09, 0xe9, 0x19, 0x87, 0x90, + 0x1e, 0xba, 0x4b, 0x4a, 0xba, 0x91, 0x92, 0x6e, 0x86, 0x50, 0x1a, 0x14, 0x24, 0x14, 0xe9, 0xee, + 0x94, 0x92, 0xee, 0x16, 0xa4, 0x11, 0x18, 0xba, 0xa5, 0x43, 0xba, 0x91, 0x41, 0x09, 0x29, 0x25, + 0xae, 0x3e, 0xf0, 0xbc, 0xf7, 0xfd, 0xf3, 0xfe, 0x7f, 0xfd, 0xae, 0x35, 0xeb, 0x33, 0x67, 0xef, + 0xfd, 0x3b, 0xfb, 0xec, 0xbd, 0xf6, 0x39, 0x5d, 0xbb, 0x52, 0x5d, 0xed, 0x7d, 0x8f, 0xca, 0x4d, + 0xcc, 0xcb, 0x60, 0x06, 0x08, 0x4e, 0x84, 0xfe, 0x55, 0x22, 0xbb, 0xe4, 0x4c, 0xc1, 0xf3, 0x10, + 0x78, 0xca, 0xf8, 0xe4, 0x2a, 0xea, 0x90, 0xed, 0xbc, 0x7f, 0xc0, 0x5e, 0xc3, 0x4d, 0x00, 0x75, + 0x9e, 0xac, 0xba, 0xb6, 0x6d, 0x3b, 0x1b, 0x3d, 0xca, 0x93, 0xb8, 0x6f, 0xc1, 0x2b, 0x0d, 0x44, + 0xb5, 0x1f, 0x3c, 0x9c, 0xe6, 0x9b, 0x19, 0xea, 0x1c, 0xbb, 0x54, 0x30, 0x98, 0xaa, 0x15, 0x12, + 0x9e, 0xa9, 0xd5, 0x8c, 0x5c, 0x2a, 0x5f, 0x32, 0xb9, 0xc2, 0x98, 0xa0, 0xd1, 0x38, 0xa7, 0x18, + 0x8e, 0x40, 0x8e, 0xef, 0x19, 0x6f, 0xde, 0xda, 0xd2, 0xe7, 0x71, 0xd0, 0x3f, 0x66, 0x6a, 0x71, + 0xe8, 0x9a, 0x98, 0x2a, 0xec, 0x89, 0xe3, 0x63, 0xfe, 0x45, 0xdd, 0x79, 0x34, 0x86, 0x64, 0x52, + 0x8b, 0x7c, 0xab, 0x65, 0xc0, 0x9b, 0xd2, 0x85, 0x37, 0xe2, 0xad, 0xbf, 0x7a, 0xf1, 0x8b, 0x92, + 0x71, 0x14, 0xdd, 0x43, 0x9f, 0x4b, 0x1e, 0x81, 0x86, 0xf5, 0x83, 0xa1, 0x9c, 0xdb, 0xb3, 0x6c, + 0xc5, 0xe4, 0x27, 0xf3, 0xe7, 0x70, 0x8f, 0x03, 0x63, 0x6e, 0xd4, 0xa3, 0xaf, 0x64, 0x0f, 0xa5, + 0xcf, 0x26, 0x19, 0xbb, 0xb2, 0xd0, 0xb7, 0xf6, 0x69, 0x06, 0xe4, 0x75, 0x5d, 0xa0, 0xd7, 0x03, + 0xdf, 0xd8, 0x25, 0xa1, 0x36, 0x17, 0x98, 0xf4, 0x8b, 0x20, 0x34, 0xfa, 0xd9, 0x08, 0x14, 0x96, + 0xc6, 0xe7, 0x93, 0x8f, 0x9c, 0x68, 0x8b, 0x4e, 0x5f, 0x1a, 0xba, 0xd3, 0xe7, 0xbc, 0xa2, 0xf6, + 0xe0, 0x23, 0x71, 0xfd, 0x16, 0xdb, 0xf5, 0xe3, 0x47, 0x0a, 0x0e, 0x4d, 0xbd, 0x75, 0x94, 0x60, + 0x49, 0xd2, 0x07, 0xaa, 0xfe, 0x3e, 0x28, 0x2c, 0xaa, 0xa6, 0x72, 0x9e, 0x9a, 0x85, 0x0e, 0x8f, + 0xef, 0x0a, 0xcd, 0x09, 0x53, 0xe4, 0xa1, 0x32, 0x3a, 0x8a, 0x66, 0xf8, 0xb8, 0xca, 0x4f, 0x98, + 0xb1, 0xd4, 0x37, 0x53, 0xb4, 0xa9, 0x78, 0xb8, 0x88, 0x55, 0x91, 0x33, 0x63, 0xd9, 0xaf, 0x09, + 0x0d, 0x13, 0xf1, 0xf4, 0xcf, 0x70, 0x1c, 0x31, 0xb0, 0xc3, 0xaf, 0x44, 0xdf, 0xa5, 0xa4, 0xa7, + 0x29, 0x6d, 0x7b, 0x7a, 0x2a, 0x0f, 0xdc, 0xc1, 0x4f, 0x8f, 0xbe, 0x3e, 0x2a, 0x23, 0x46, 0xaf, + 0x7d, 0x13, 0xff, 0xf6, 0xf3, 0xc2, 0xb3, 0xf0, 0x07, 0x64, 0xc4, 0xce, 0xa1, 0xcb, 0x23, 0x65, + 0x5f, 0x31, 0x22, 0x5e, 0x37, 0x69, 0xd6, 0x78, 0x29, 0xda, 0xe9, 0x6d, 0x61, 0x2c, 0x6e, 0xd8, + 0x64, 0xef, 0x4c, 0x4f, 0x4e, 0xc5, 0xb5, 0x38, 0xea, 0x48, 0x90, 0x69, 0x56, 0x41, 0x79, 0x93, + 0x41, 0x06, 0x54, 0x59, 0x87, 0xa7, 0xc3, 0x88, 0x82, 0xc8, 0xe3, 0x1a, 0xbe, 0xac, 0x12, 0x05, + 0x3f, 0x95, 0x6d, 0xd5, 0xb0, 0xde, 0x2f, 0xeb, 0x27, 0x14, 0xa1, 0x10, 0x52, 0x72, 0xb5, 0x34, + 0x8a, 0xfb, 0x35, 0xd2, 0xf5, 0x8a, 0xe9, 0x2d, 0xb9, 0xef, 0x6c, 0xdb, 0x6d, 0xa1, 0x72, 0xb5, + 0xea, 0x0b, 0xbf, 0xf0, 0x82, 0x7b, 0xb5, 0x3b, 0x7a, 0xed, 0xb6, 0x0e, 0xde, 0x64, 0xc9, 0x9e, + 0x83, 0xb5, 0xa4, 0x02, 0x28, 0x04, 0x8a, 0x2c, 0xbc, 0x87, 0xdf, 0xc4, 0x77, 0x93, 0xce, 0x70, + 0x2f, 0x45, 0x75, 0x53, 0x19, 0x59, 0xda, 0xa1, 0x56, 0x02, 0xbe, 0x09, 0x85, 0x62, 0xa1, 0xfb, + 0x15, 0xb6, 0x7b, 0x04, 0x6c, 0x2f, 0x25, 0x3b, 0x80, 0x56, 0x75, 0x1b, 0xe5, 0xbc, 0x64, 0x3e, + 0x31, 0xac, 0x7b, 0x9a, 0x87, 0xce, 0x0c, 0x65, 0x9a, 0x81, 0x3a, 0x55, 0xae, 0x09, 0x96, 0xb5, + 0x0a, 0xf7, 0x03, 0x8a, 0xb9, 0x6b, 0xe9, 0x76, 0x76, 0xea, 0xd3, 0xaa, 0x3f, 0xfb, 0x0d, 0xf5, + 0x4d, 0x29, 0x1a, 0x45, 0x2c, 0x22, 0x7a, 0x8c, 0x0b, 0x54, 0x4a, 0xe7, 0x72, 0x9e, 0xe9, 0x1c, + 0x3d, 0x93, 0x9d, 0x71, 0x7d, 0x87, 0xf6, 0x29, 0x0c, 0xbb, 0xf5, 0x7b, 0xc9, 0xb2, 0x0c, 0x7a, + 0xdd, 0x33, 0xfb, 0xce, 0x43, 0xd7, 0x44, 0xee, 0xb0, 0xf4, 0x28, 0x78, 0x62, 0xa8, 0x57, 0x32, + 0xeb, 0xd3, 0x65, 0xa0, 0x88, 0xa4, 0x66, 0xe0, 0x9b, 0xcb, 0xb4, 0x7d, 0xd2, 0x14, 0xaf, 0x89, + 0x8f, 0x2a, 0x54, 0x5f, 0x09, 0xa0, 0xa9, 0xfc, 0x38, 0xad, 0xbc, 0xbd, 0xf9, 0x9a, 0x76, 0xe9, + 0xe1, 0xac, 0x89, 0x5a, 0x1d, 0x2e, 0x4c, 0x6b, 0x49, 0x4a, 0x93, 0x2a, 0x85, 0xd6, 0xa1, 0x4f, + 0x0b, 0x20, 0x53, 0xad, 0x54, 0x5d, 0x53, 0xa5, 0x76, 0xfe, 0xc9, 0x67, 0xa3, 0x89, 0xe3, 0x74, + 0xc0, 0x42, 0x94, 0x1f, 0xfc, 0xd1, 0x6d, 0x1a, 0xfd, 0xaf, 0xec, 0xcb, 0x58, 0x77, 0x88, 0x93, + 0x39, 0x9f, 0xc4, 0xd0, 0x5e, 0x9f, 0xdd, 0x27, 0x41, 0xbe, 0xea, 0xee, 0x40, 0x15, 0x0a, 0xe2, + 0x3d, 0x06, 0x08, 0x20, 0x30, 0xbf, 0x5f, 0x7d, 0x0c, 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0x1d, 0x31, 0xef, 0x88, 0x7f, 0xe7, 0x67, 0xbc, 0x23, 0xe4, 0x8e, 0xc4, 0x77, 0x24, 0xbf, + 0xe3, 0x0a, 0xea, 0x2d, 0x01, 0x18, 0x77, 0xfb, 0xdc, 0x91, 0xf5, 0xdf, 0xf5, 0xdd, 0xf9, 0x9c, + 0x48, 0x6e, 0xf9, 0xf2, 0x8e, 0xee, 0x77, 0xfc, 0xcf, 0x83, 0x4c, 0x0c, 0xf9, 0x07, 0x0c, 0x00, + 0xfc, 0x7f, 0x78, 0x73, 0xa7, 0xff, 0xf8, 0x39, 0xef, 0x7e, 0xbf, 0x25, 0x7e, 0xef, 0xff, 0xfe, + 0xce, 0xff, 0xd5, 0x5f, 0xfd, 0xd5, 0x5f, 0xfd, 0xd5, 0x5f, 0xfd, 0xd5, 0x5f, 0xfd, 0xd5, 0x5f, + 0xfd, 0xd1, 0xff, 0x00, 0x4d, 0x03, 0xf4, 0xee, 0x00, 0x30, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 12288, // uncompressed data size (bytes) + 7340, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_desc_prod") +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ad102_riscv_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 43 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = +{ + 0x63, 0x65, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, + 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x36, 0x75, 0x06, + 0x10, 0x41, 0x00, 0x42, 0x1a, 0xfd, 0xdc, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 43, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmBoot_AD102 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt }, + { "ucode_desc_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt }, + { "ucode_image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt }, + { "ucode_desc_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmBoot_AD102; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index 6e38a9929..748d948b9 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -35,470 +35,470 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7345 +// COMPRESSED SIZE (bytes): 7350 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0x97, 0x65, 0x54, 0x94, 0x5d, 0xd7, 0xc7, 0x27, 0x80, 0x19, 0x42, 0xba, 0x04, 0x14, 0x18, - 0x3a, 0x14, 0x44, 0xba, 0x43, 0x4a, 0xa4, 0x04, 0x01, 0xa5, 0x19, 0x4a, 0x40, 0xba, 0x41, 0x7a, - 0x18, 0xba, 0x06, 0x18, 0x90, 0x92, 0x14, 0x50, 0xba, 0xbb, 0x43, 0xa4, 0x14, 0x90, 0x90, 0x6e, - 0x04, 0xa4, 0x1b, 0xf4, 0xd5, 0x1b, 0xee, 0xe7, 0x7d, 0x3e, 0xbe, 0xdf, 0x5f, 0xff, 0x6b, 0xcd, - 0xfa, 0xcd, 0xb5, 0xf7, 0xbe, 0xce, 0x3e, 0x7b, 0xaf, 0x7d, 0xce, 0x5a, 0xd7, 0x44, 0x8f, 0xf4, - 0xfb, 0x72, 0x86, 0xdb, 0x91, 0x6c, 0x82, 0x0e, 0xf4, 0x52, 0x5f, 0xd5, 0x7e, 0x95, 0xb9, 0x79, - 0x7f, 0x9e, 0x64, 0x13, 0xed, 0x90, 0x6a, 0x4d, 0xc9, 0xfe, 0xea, 0x7b, 0x9a, 0x25, 0xb1, 0x12, - 0xa6, 0x89, 0x75, 0x72, 0x26, 0xcf, 0xda, 0xc4, 0xa3, 0x52, 0x98, 0xbe, 0x4a, 0x96, 0x61, 0x55, - 0x98, 0xcf, 0xca, 0x38, 0x43, 0xcb, 0xfd, 0x24, 0x41, 0xc4, 0x1e, 0x3d, 0x8f, 0x68, 0xed, 0x64, - 0xfb, 0x25, 0x99, 0x43, 0xae, 0xe4, 0xa6, 0x3b, 0x7e, 0xdf, 0xf4, 0xf2, 0x6b, 0x81, 0x62, 0xa3, - 0x4e, 0x0a, 0x05, 0x71, 0x85, 0x80, 0x91, 0x40, 0x38, 0x7d, 0x10, 0x30, 0x5b, 0x24, 0xb7, 0x2b, - 0x82, 0x9c, 0x29, 0x70, 0xd7, 0x42, 0x57, 0xf9, 0x47, 0xa8, 0x92, 0x5a, 0xfc, 0xec, 0xda, 0xaa, - 0x0a, 0x54, 0x6c, 0xb9, 0xa9, 0x27, 0x81, 0x50, 0xca, 0xf4, 0xdd, 0x9b, 0x23, 0xd2, 0x82, 0xe9, - 0xa7, 0xee, 0xf6, 0x30, 0xf1, 0xaa, 0xfa, 0x48, 0x2f, 0xb3, 0x15, 0x07, 0xe2, 0xb1, 0xa9, 0xe8, - 0xbe, 0x20, 0x94, 0x16, 0x65, 0xfe, 0x9c, 0x1d, 0xe9, 0x89, 0x03, 0x4c, 0x8c, 0x67, 0x13, 0xa1, - 0xba, 0xba, 0x7e, 0xac, 0xa7, 0xcd, 0x5d, 0x72, 0xa6, 0xf9, 0x3e, 0xeb, 0xd6, 0x34, 0xa5, 0x9b, - 0x05, 0x0f, 0xd4, 0x8e, 0x25, 0x16, 0x39, 0xfc, 0x62, 0xb0, 0x89, 0x03, 0x55, 0x2f, 0xf2, 0x6a, - 0x2a, 0x5f, 0xda, 0xb0, 0x47, 0xb6, 0xe5, 0x1e, 0xf5, 0x8f, 0xe8, 0xf2, 0x85, 0x00, 0x64, 0x7e, - 0x5f, 0x81, 0x1b, 0xf3, 0x78, 0x4a, 0x3c, 0x04, 0xac, 0x82, 0x8f, 0x2d, 0x50, 0xe3, 0xcb, 0x6e, - 0x66, 0x39, 0x44, 0xca, 0xbb, 0x19, 0x24, 0xe3, 0xba, 0xfd, 0x36, 0x5f, 0x0b, 0x0d, 0x02, 0x82, - 0x8c, 0x46, 0xc5, 0x07, 0x79, 0xe8, 0x32, 0x68, 0x65, 0xcb, 0x47, 0x45, 0x66, 0xbb, 0x86, 0x7a, - 0x95, 0xcf, 0xe4, 0x33, 0xcb, 0x1b, 0xf0, 0x23, 0x67, 0xc3, 0x8b, 0x4d, 0xfb, 0x2a, 0x9e, 0x6c, - 0x84, 0x34, 0x31, 0xea, 0x3b, 0x50, 0xdf, 0x9b, 0x0f, 0x0d, 0xb8, 0x1c, 0x8c, 0x3d, 0x94, 0x9d, - 0xac, 0x22, 0x36, 0x6f, 0x75, 0x0c, 0xaf, 0x65, 0x2f, 0xca, 0x0b, 0x76, 0x50, 0x16, 0x93, 0x6d, - 0x35, 0x7e, 0x59, 0x55, 0x92, 0xa3, 0x59, 0x79, 0xb5, 0x55, 0x2c, 0x50, 0xf6, 0x5c, 0xa0, 0x6c, - 0x8a, 0x36, 0x66, 0x7b, 0x0f, 0x33, 0x76, 0xfd, 0xf9, 0x07, 0x37, 0xc1, 0x3a, 0xdd, 0x07, 0x95, - 0x49, 0x0b, 0x1f, 0x1a, 0x30, 0xbf, 0x13, 0x06, 0x7b, 0x64, 0x64, 0x24, 0x87, 0xcc, 0x3c, 0x1b, - 0xc2, 0x6f, 0xce, 0x88, 0xde, 0x20, 0x82, 0x46, 0xeb, 0x18, 0x30, 0x57, 0x7d, 0x12, 0x09, 0x1e, - 0x7e, 0x47, 0xee, 0xc2, 0xf9, 0xc3, 0x1c, 0x99, 0xd8, 0x5a, 0x43, 0x42, 0x77, 0xa9, 0x79, 0x99, - 0xf6, 0x78, 0x45, 0xbe, 0x8f, 0x8a, 0xc9, 0xfd, 0xc8, 0xc8, 0x66, 0x90, 0x90, 0x6c, 0x87, 0x56, - 0x69, 0x31, 0x6d, 0x3f, 0x73, 0x7e, 0x7c, 0x29, 0xf7, 0x49, 0x34, 0xf6, 0x52, 0xf2, 0xea, 0x1c, - 0x65, 0x9e, 0xaa, 0xfd, 0xda, 0xf0, 0x52, 0xb6, 0x2c, 0xb0, 0xf0, 0x45, 0x65, 0x76, 0x16, 0xc2, - 0xa1, 0x35, 0xaa, 0xfc, 0x6e, 0x6b, 0x22, 0x72, 0x98, 0x8a, 0xa7, 0xec, 0x3b, 0x9a, 0x69, 0x29, - 0x25, 0x9a, 0x74, 0xb5, 0xdd, 0xd4, 0x8e, 0x71, 0x46, 0xf0, 0xdd, 0x53, 0x95, 0x06, 0xca, 0xb7, - 0x13, 0xbf, 0xb6, 0xb9, 0xf9, 0x69, 0xb0, 0xd5, 0x06, 0x34, 0x29, 0xe3, 0xea, 0x78, 0x83, 0x31, - 0xf7, 0xcd, 0x5c, 0x52, 0x9c, 0x06, 0xb4, 0xbf, 0x15, 0xb0, 0x98, 0x11, 0x08, 0x3a, 0x57, 0xe0, - 0x84, 0xdd, 0x99, 0x2d, 0xe2, 0x30, 0x4d, 0x90, 0x62, 0x36, 0x5e, 0xcb, 0x92, 0xf5, 0xc3, 0x89, - 0x9d, 0x0d, 0x4d, 0x28, 0x79, 0x33, 0x9e, 0x3d, 0x02, 0xf0, 0x0c, 0x61, 0x9f, 0xb3, 0x4f, 0x5b, - 0x7a, 0x56, 0x9c, 0xa2, 0xd8, 0x1c, 0xf0, 0x3a, 0xb8, 0xe3, 0x2e, 0x15, 0x94, 0xc2, 0x1d, 0x5b, - 0x7b, 0x97, 0x9f, 0xd8, 0x6a, 0xe1, 0xe7, 0x5e, 0x22, 0x7b, 0xb8, 0x78, 0xe7, 0xc1, 0xa5, 0x6d, - 0x54, 0x40, 0xde, 0x6b, 0xe9, 0xe7, 0x89, 0x82, 0xd9, 0xe2, 0xe4, 0x19, 0xf1, 0x0c, 0x9a, 0x15, - 0x0d, 0x46, 0x15, 0x3c, 0xce, 0x6a, 0x98, 0x92, 0x87, 0x28, 0x3e, 0x7b, 0xb4, 0x6f, 0x1a, 0xdc, - 0x54, 0x2d, 0xf9, 0xad, 0x55, 0xb6, 0x22, 0xc6, 0x30, 0x94, 0xb2, 0xc6, 0x16, 0x5b, 0xed, 0xc7, - 0xcf, 0x3a, 0x8e, 0x28, 0x7a, 0xe0, 0x0a, 0x48, 0x71, 0xdb, 0x69, 0x94, 0xb9, 0xa8, 0xce, 0x92, - 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0x91, 0x35, 0x0d, 0xce, 0x1c, 0x97, 0x9a, 0xd4, + 0x0d, 0x08, 0xc5, 0xe0, 0x45, 0xa4, 0x5b, 0x9e, 0x47, 0xb7, 0x5b, 0xde, 0xed, 0x41, 0x21, 0xc1, + 0xa6, 0xd3, 0xd1, 0x97, 0xef, 0x15, 0xc0, 0x02, 0x14, 0x69, 0x48, 0x7e, 0xef, 0x87, 0x24, 0x1a, + 0x86, 0xfe, 0x4d, 0x54, 0x74, 0x34, 0xec, 0x6e, 0x01, 0xad, 0x0c, 0x5e, 0x84, 0xeb, 0x2f, 0x90, + 0x10, 0x09, 0x80, 0x85, 0xc9, 0x12, 0x00, 0xaa, 0x23, 0x01, 0x30, 0x60, 0x28, 0xdb, 0x53, 0x91, + 0x60, 0xa8, 0x58, 0x50, 0x1d, 0x00, 0x1e, 0xda, 0x03, 0x00, 0xd5, 0x40, 0x00, 0xeb, 0xad, 0xbf, + 0x57, 0x32, 0x7e, 0xde, 0x0a, 0xb3, 0xfc, 0xb3, 0xcb, 0xff, 0xad, 0x01, 0x40, 0xf5, 0xdf, 0x5d, + 0x42, 0xc2, 0xfe, 0xed, 0x92, 0x24, 0xf2, 0x72, 0x57, 0x96, 0xf4, 0x09, 0xf0, 0x34, 0xd9, 0xb0, + 0x88, 0xc3, 0xd9, 0xab, 0xf9, 0xa6, 0xff, 0x73, 0x1a, 0x52, 0xc7, 0x39, 0x00, 0xbf, 0x4f, 0xca, + 0x55, 0x5d, 0x73, 0xdd, 0xff, 0x74, 0x3f, 0xe4, 0xdf, 0xee, 0xb7, 0x91, 0xfe, 0xf7, 0x9a, 0x8a, + 0x8c, 0xc9, 0x70, 0x11, 0x47, 0xfc, 0x33, 0xd1, 0x83, 0xab, 0x3e, 0xd3, 0xd2, 0xc2, 0xdf, 0x2b, + 0xe0, 0x59, 0xfc, 0xdb, 0xdb, 0x1e, 0x1a, 0x5a, 0x78, 0x1d, 0x3e, 0x29, 0x00, 0x05, 0x01, 0x02, + 0xff, 0xd3, 0x7f, 0x1a, 0x4a, 0x38, 0xa3, 0x25, 0x3d, 0x18, 0xec, 0x90, 0xdc, 0x71, 0x69, 0xb1, + 0xa4, 0xa6, 0x84, 0xd7, 0xe1, 0xad, 0xfd, 0x6a, 0x42, 0xd4, 0x03, 0x62, 0x3b, 0xfe, 0xcc, 0x24, + 0x2a, 0x24, 0x9f, 0x2a, 0xd6, 0x94, 0x02, 0x02, 0xa0, 0x26, 0xee, 0xb8, 0x3c, 0x4b, 0xec, 0x54, + 0x10, 0x53, 0x16, 0x26, 0x3c, 0xa0, 0x50, 0x28, 0x2e, 0xf4, 0x92, 0xa0, 0x7f, 0x28, 0x88, 0xb8, + 0x8a, 0xa7, 0x00, 0x55, 0xe1, 0x03, 0x40, 0x9c, 0x20, 0x00, 0x85, 0x07, 0x2d, 0x60, 0x91, 0x01, + 0x72, 0x01, 0x35, 0x15, 0x0a, 0xd5, 0xbe, 0x05, 0x31, 0x61, 0x61, 0xc2, 0xff, 0xf3, 0xd6, 0x83, + 0x4b, 0xde, 0xd7, 0xf8, 0x43, 0xe2, 0x76, 0x14, 0x1e, 0x80, 0x98, 0xb8, 0x23, 0xd6, 0x94, 0x52, + 0x16, 0x11, 0x7e, 0x78, 0x41, 0x0b, 0xff, 0xd3, 0xc7, 0x3f, 0xf3, 0x02, 0x73, 0xff, 0xef, 0x29, + 0x98, 0x03, 0x2c, 0x38, 0x30, 0xff, 0xa7, 0x5a, 0x4b, 0x92, 0x34, 0xf8, 0xe5, 0x0c, 0x5c, 0x4d, + 0x7c, 0xcd, 0xe5, 0x3d, 0x06, 0xc1, 0x25, 0xfb, 0x03, 0x26, 0x7e, 0xdc, 0xc0, 0x7f, 0x78, 0xec, + 0x7f, 0xf9, 0xcc, 0x5a, 0x70, 0xf3, 0x1f, 0x72, 0x5e, 0xf1, 0xcd, 0x95, 0xaa, 0x8c, 0xe9, 0x84, + 0x98, 0x4b, 0x45, 0xa7, 0x88, 0x81, 0x57, 0x71, 0xf8, 0x97, 0xc4, 0xbd, 0x22, 0xe4, 0x8a, 0xd0, + 0x2b, 0x3f, 0xe7, 0x15, 0x69, 0xaf, 0x48, 0x79, 0x45, 0x86, 0x2b, 0xce, 0xe1, 0x5c, 0x12, 0x80, + 0x77, 0xb5, 0xce, 0x15, 0x6f, 0xfd, 0xfb, 0x7c, 0xb5, 0x3f, 0x07, 0xaa, 0x4b, 0xba, 0x5c, 0xd1, + 0xe3, 0x8a, 0xff, 0xb9, 0x90, 0x29, 0x69, 0xff, 0x01, 0x3b, 0x00, 0xfa, 0x0f, 0x7f, 0x5d, 0xe9, + 0x3f, 0x7e, 0xbe, 0xab, 0xdf, 0x6f, 0x49, 0x13, 0xfe, 0xdf, 0xef, 0xf9, 0xbf, 0xfa, 0xab, 0xbf, + 0xfa, 0xab, 0xbf, 0xfa, 0xab, 0xbf, 0xfa, 0xab, 0xbf, 0xfa, 0xab, 0x3f, 0xfa, 0x1f, 0x71, 0x44, + 0x87, 0xe7, 0x00, 0x30, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -509,7 +509,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 12288, // uncompressed data size (bytes) - 7345, // compressed data size (bytes) + 7350, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c new file mode 100644 index 000000000..5d4ba5fa1 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -0,0 +1,15498 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_dbg") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 122880 +// COMPRESSED SIZE (bytes): 122261 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = +{ + 0xec, 0x97, 0xd3, 0x92, 0x28, 0x0a, 0x94, 0x64, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x79, 0xca, 0xb6, 0x5d, 0xd5, 0xf7, 0x0b, 0xe6, 0x69, 0x22, + 0xfa, 0xa5, 0xf3, 0x17, 0x56, 0xc6, 0xde, 0x2b, 0x01, 0x00, 0xfe, 0x2f, 0xff, 0x9b, 0xe9, 0xf8, + 0x48, 0xfc, 0xb7, 0x25, 0x55, 0xb9, 0x1c, 0xff, 0x68, 0x32, 0x75, 0xfb, 0xcb, 0x46, 0xe2, 0x4e, + 0x31, 0x74, 0xaa, 0x1a, 0x2b, 0x9a, 0x0c, 0xd4, 0xde, 0xb7, 0x0a, 0xad, 0x71, 0x36, 0x61, 0xfe, + 0x1c, 0xb9, 0x39, 0x47, 0xcd, 0x44, 0xdd, 0xaf, 0xbd, 0x55, 0x31, 0x04, 0xe5, 0x1c, 0xe2, 0xc9, + 0x1a, 0xfe, 0xcb, 0xd4, 0x45, 0x8a, 0x02, 0xf4, 0xcf, 0xd8, 0x9f, 0x34, 0x0f, 0xe7, 0x7c, 0x1b, + 0x5d, 0x4e, 0x48, 0x7f, 0xd7, 0x6e, 0x87, 0x50, 0xf0, 0x06, 0xc7, 0xad, 0xe7, 0x1a, 0x06, 0x40, + 0x10, 0x99, 0x8f, 0xa6, 0x79, 0xfa, 0x3b, 0xc0, 0x01, 0x7f, 0x3e, 0x97, 0xaa, 0x80, 0xdf, 0x27, + 0x29, 0x22, 0x51, 0xce, 0xef, 0x3b, 0x3c, 0x5b, 0x82, 0xa8, 0x4d, 0x21, 0x6f, 0x35, 0xc7, 0x07, + 0x27, 0xa5, 0x1f, 0xf4, 0x35, 0x24, 0x35, 0x2b, 0xd5, 0x4e, 0x4b, 0x82, 0x99, 0x71, 0x06, 0x5e, + 0x3e, 0xe8, 0x50, 0xd9, 0x06, 0x75, 0xdd, 0x18, 0xc7, 0x9b, 0x2d, 0x3c, 0x2c, 0xd8, 0x54, 0x25, + 0x3b, 0xa2, 0xd0, 0x97, 0x13, 0x67, 0xe9, 0xd3, 0x36, 0x78, 0x1b, 0x60, 0x19, 0x4a, 0x91, 0x2b, + 0x47, 0xae, 0x95, 0x20, 0x7d, 0x55, 0x73, 0xcc, 0xf0, 0x7a, 0x80, 0x98, 0xfe, 0x74, 0x3a, 0x17, + 0x5a, 0x4e, 0xc6, 0xf9, 0x1f, 0x35, 0x38, 0x7d, 0x40, 0x71, 0x6e, 0xf1, 0x1b, 0x7c, 0xd2, 0x95, + 0x23, 0x12, 0x88, 0xaf, 0xd0, 0x2f, 0x79, 0xbb, 0x04, 0x73, 0x89, 0x76, 0xca, 0x7c, 0x49, 0xa7, + 0x7f, 0xc7, 0xa4, 0xbd, 0x32, 0x9a, 0x7c, 0xc0, 0x8a, 0x0a, 0x15, 0xc6, 0x85, 0x4f, 0x5f, 0xe2, + 0x54, 0x64, 0x1f, 0xc5, 0x7d, 0xfd, 0x11, 0x8c, 0x16, 0x1e, 0xcb, 0xbb, 0x94, 0x94, 0xde, 0x3f, + 0x3d, 0x2f, 0x1e, 0xc9, 0xe5, 0x33, 0x57, 0xc6, 0x1f, 0x8d, 0xc5, 0x44, 0x3b, 0xc1, 0x6b, 0xe8, + 0xee, 0x7f, 0x90, 0xc4, 0x64, 0xa3, 0xc4, 0xa0, 0xb6, 0xa5, 0x77, 0x47, 0xc7, 0x8a, 0xd6, 0x02, + 0xd1, 0x08, 0xa5, 0x5d, 0x5e, 0x04, 0x44, 0xfc, 0xc5, 0xde, 0x7d, 0xbe, 0xa9, 0xc8, 0x74, 0x44, + 0xfc, 0x7b, 0xa3, 0x94, 0xbd, 0x4b, 0xef, 0xa4, 0xdf, 0xd8, 0xb6, 0x4c, 0xed, 0xee, 0xb0, 0x82, + 0xef, 0x8e, 0xd1, 0xa6, 0x88, 0xe2, 0x68, 0x13, 0xf6, 0x7e, 0xc0, 0x73, 0xc9, 0x84, 0x42, 0x9c, + 0xbd, 0x76, 0x59, 0xd7, 0xfe, 0x17, 0x3a, 0x2b, 0x3f, 0x82, 0x78, 0xed, 0x72, 0x42, 0xaa, 0xe0, + 0xea, 0xac, 0x08, 0x9c, 0xa0, 0xc0, 0x6c, 0xd2, 0x3d, 0x6f, 0x6d, 0xb1, 0x71, 0x53, 0x35, 0x3f, + 0xc3, 0x70, 0x28, 0x2a, 0xf9, 0xba, 0x7a, 0x78, 0xce, 0x81, 0x10, 0x51, 0x7e, 0xe8, 0x74, 0x30, + 0xe1, 0xb9, 0x4b, 0x76, 0x39, 0x2a, 0xe7, 0x85, 0x96, 0x8e, 0x3c, 0xac, 0x7f, 0x4c, 0x72, 0x42, + 0xff, 0x31, 0xa8, 0xfa, 0x7f, 0xf0, 0x41, 0x2c, 0x1a, 0x5a, 0x35, 0xf7, 0x46, 0x42, 0xc2, 0xae, + 0x8a, 0x61, 0x14, 0x55, 0x1f, 0x3e, 0xfc, 0xff, 0xcd, 0x7f, 0xa5, 0xa8, 0xe5, 0x8e, 0x9b, 0xfd, + 0x8e, 0x69, 0xbd, 0xe4, 0x29, 0xbe, 0x1b, 0xae, 0x2e, 0xee, 0x39, 0xae, 0x0e, 0xe0, 0x4c, 0xf8, + 0x35, 0x88, 0x61, 0x66, 0x48, 0x99, 0x38, 0xaa, 0xba, 0x69, 0xf8, 0xe8, 0x62, 0x69, 0xba, 0x9f, + 0x13, 0xbb, 0x58, 0xaf, 0xc7, 0x2b, 0x07, 0x80, 0x1e, 0x4b, 0x78, 0x95, 0x6f, 0x6c, 0x7d, 0x80, + 0xfc, 0xb1, 0x00, 0xe8, 0xd8, 0x68, 0x1a, 0xed, 0x92, 0x5d, 0xf3, 0x56, 0x17, 0x34, 0x4f, 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0x71, 0x6d, 0x28, 0x5b, 0x47, 0x8c, + 0x9a, 0x41, 0x67, 0x8f, 0xa1, 0x67, 0x51, 0x60, 0xbe, 0xcb, 0xb1, 0xa9, 0xe8, 0x28, 0xc3, 0x92, + 0x34, 0xe7, 0x2a, 0x75, 0x01, 0x60, 0xf8, 0x1a, 0xe0, 0x89, 0xe1, 0xbd, 0x62, 0x7e, 0x3b, 0x1c, + 0x3b, 0x3d, 0x14, 0x2c, 0xd0, 0x17, 0xd6, 0xee, 0x38, 0xdb, 0xed, 0xe1, 0xd4, 0x47, 0x35, 0xb3, + 0xa4, 0xf1, 0x26, 0x28, 0x7a, 0x06, 0x2d, 0x8c, 0xb5, 0x13, 0x94, 0x1a, 0xbe, 0x9a, 0x62, 0x75, + 0x5b, 0xa9, 0x06, 0xa6, 0x02, 0x88, 0xce, 0x0a, 0x47, 0x98, 0x5e, 0x4a, 0x46, 0xfe, 0x06, 0x2e, + 0x40, 0xec, 0xf9, 0x70, 0xd9, 0x2f, 0xbb, 0x67, 0x9c, 0xde, 0x4c, 0x01, 0x04, 0x33, 0xf7, 0x23, + 0x68, 0x8b, 0x11, 0x9d, 0x57, 0xbd, 0xa9, 0x14, 0xa2, 0xdf, 0x00, 0xef, 0xb9, 0xe0, 0x84, 0x0b, + 0x3c, 0x6e, 0x12, 0x49, 0xa4, 0x0f, 0xe3, 0x74, 0x8c, 0x5a, 0xa9, 0x41, 0x58, 0x2d, 0xed, 0x9e, + 0x51, 0xa4, 0x5f, 0xc6, 0x6e, 0x47, 0x58, 0x2f, 0xd0, 0x01, 0xb1, 0x47, 0xe6, 0xc3, 0x31, 0x20, + 0xda, 0x6d, 0x47, 0x10, 0xc5, 0x31, 0x9d, 0x6c, 0xe0, 0xc3, 0x8a, 0x8f, 0x67, 0x04, 0x04, 0xfb, + 0x3d, 0x90, 0xd0, 0xc0, 0x7f, 0x63, 0x7b, 0xd4, 0x6f, 0xa8, 0x9c, 0x27, 0xbb, 0x8b, 0x5c, 0x79, + 0xba, 0xcc, 0x62, 0x7d, 0x50, 0x1d, 0xae, 0x60, 0x83, 0x04, 0x21, 0x7a, 0x91, 0x4b, 0x29, 0xb3, + 0xf1, 0xae, 0xb7, 0x9d, 0x8b, 0xd0, 0x51, 0x64, 0xd9, 0x89, 0x87, 0x00, 0x62, 0x43, 0x5e, 0x77, + 0xc0, 0x1f, 0x71, 0xf0, 0xf7, 0x99, 0xf5, 0x0c, 0xf6, 0x2b, 0xb7, 0x24, 0x5d, 0xd6, 0xda, 0x26, + 0xd4, 0x00, 0xf9, 0xe7, 0xc0, 0xcb, 0x69, 0xbd, 0x0c, 0xe4, 0x62, 0x1d, 0x8b, 0xa7, 0x02, 0x22, + 0xce, 0xc0, 0xf3, 0x75, 0x88, 0xb1, 0x4e, 0xf7, 0x0d, 0x21, 0x7f, 0xc6, 0xe1, 0x3e, 0x68, 0xc4, + 0xa1, 0x0c, 0x40, 0xa2, 0x41, 0x84, 0x00, 0xc2, 0x99, 0xac, 0xcb, 0x69, 0x9b, 0x1a, 0x85, 0xcf, + 0x6c, 0x33, 0xa9, 0x5d, 0x9f, 0x55, 0xed, 0x09, 0xf0, 0x7f, 0xae, 0xff, 0x01, 0xf4, 0x1b, 0x90, + 0x8a, 0x00, 0xe0, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 122880, // uncompressed data size (bytes) + 122261, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_dbg") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data[] = +{ + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x0c, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0x80, 0x97, 0x91, 0xad, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 122880 +// COMPRESSED SIZE (bytes): 122636 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = +{ + 0x9c, 0x96, 0xc3, 0x8e, 0x28, 0x0a, 0x80, 0x44, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xbe, 0x6d, 0xdb, 0xf3, 0x7e, 0x60, 0x66, 0x31, 0x67, + 0x5d, 0x8b, 0x4a, 0x2a, 0x39, 0xa9, 0xa6, 0x9f, 0x6f, 0x9e, 0xcd, 0x13, 0xb6, 0x50, 0x1e, 0x13, + 0xe2, 0x49, 0xec, 0x24, 0x69, 0x30, 0x4f, 0xac, 0x14, 0x37, 0x47, 0x33, 0x63, 0x26, 0x83, 0xcc, + 0x46, 0xcd, 0xcd, 0x3d, 0xe3, 0x77, 0xe6, 0x76, 0xb3, 0xd2, 0x6f, 0xff, 0x72, 0x21, 0xfa, 0x3d, + 0x97, 0x8d, 0x83, 0xcd, 0x44, 0x98, 0xcd, 0x44, 0xca, 0x5b, 0xb7, 0x4e, 0xbc, 0x09, 0x09, 0x9c, + 0x53, 0x06, 0x37, 0xdb, 0x27, 0x6c, 0xd2, 0x09, 0xc1, 0x18, 0x62, 0xa2, 0x5b, 0x49, 0x7e, 0x28, + 0x26, 0x9f, 0x33, 0x63, 0x70, 0xa4, 0x79, 0x37, 0x49, 0x4c, 0xbe, 0xb0, 0xa6, 0x5e, 0xa8, 0x1c, + 0x6c, 0x80, 0xd6, 0x36, 0x95, 0x06, 0xbf, 0xbe, 0x54, 0xd1, 0x39, 0x77, 0x88, 0x2b, 0x51, 0x83, + 0x31, 0x76, 0xf6, 0xaf, 0x8a, 0x4f, 0x96, 0x84, 0x3c, 0x7e, 0x03, 0xf0, 0xe5, 0xd9, 0xfe, 0x00, + 0x97, 0xaa, 0x31, 0xc3, 0x5d, 0xab, 0x65, 0xb8, 0x18, 0xe5, 0x6a, 0x2f, 0x39, 0x68, 0xf2, 0xd2, + 0x19, 0x3d, 0xad, 0x06, 0x01, 0x24, 0x6a, 0x2f, 0x0d, 0x00, 0x22, 0x48, 0x88, 0xb2, 0xab, 0x22, + 0x37, 0xc3, 0xb2, 0xf5, 0x56, 0x00, 0x5a, 0x82, 0xab, 0xef, 0x91, 0x38, 0xc4, 0xfe, 0xce, 0x59, + 0xd7, 0xd8, 0xd5, 0xc2, 0x88, 0x85, 0x3c, 0xa2, 0xf8, 0x23, 0x04, 0x82, 0x8d, 0x58, 0x39, 0xc1, + 0x5b, 0x78, 0xe2, 0x56, 0xd2, 0x2f, 0xcc, 0x7a, 0xed, 0x5e, 0xc9, 0xc1, 0x21, 0x8a, 0x9d, 0x38, + 0x7a, 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0xd4, 0x6c, 0x59, 0x66, 0xd3, 0xbb, 0x9c, 0x2d, 0x14, 0xa7, 0x0d, 0xdc, 0xa8, 0x39, + 0xa7, 0x74, 0x33, 0x3b, 0x4c, 0x7c, 0xc6, 0xea, 0xb4, 0xf8, 0x1a, 0x5b, 0x45, 0xea, 0x0c, 0x08, + 0x26, 0xed, 0x5c, 0x46, 0xa7, 0xdf, 0x65, 0xe2, 0x09, 0xe2, 0x94, 0xd2, 0x56, 0xed, 0xcc, 0xd7, + 0x54, 0x75, 0x81, 0x61, 0x1f, 0xf9, 0x61, 0x65, 0x6a, 0x09, 0x5e, 0xe6, 0x35, 0xc4, 0xd9, 0xbc, + 0xb1, 0x3d, 0x72, 0xca, 0x99, 0xa4, 0x48, 0x5e, 0x47, 0xf1, 0x51, 0x67, 0x35, 0x60, 0xa5, 0x31, + 0xdb, 0x5f, 0x07, 0xb9, 0x8a, 0x48, 0x04, 0x29, 0x25, 0xf4, 0x82, 0xaf, 0x7d, 0x5d, 0xba, 0xa2, + 0x21, 0x81, 0x8b, 0x46, 0x26, 0xe4, 0x59, 0x95, 0x52, 0x41, 0xf0, 0x6e, 0x6d, 0x69, 0xcf, 0xf7, + 0x30, 0x19, 0xdd, 0xb6, 0xee, 0x37, 0xff, 0xda, 0xbb, 0x9f, 0x29, 0x53, 0x96, 0x95, 0x97, 0xa6, + 0xb5, 0xbe, 0x48, 0xd9, 0x46, 0x2e, 0xcb, 0xb6, 0x02, 0xeb, 0xb9, 0x63, 0xbc, 0x59, 0xa5, 0x35, + 0xbe, 0x40, 0x4e, 0xfb, 0xea, 0x1f, 0x86, 0xcd, 0x6c, 0xbe, 0xfd, 0x68, 0x65, 0x9c, 0xe8, 0xb6, + 0x28, 0x4d, 0x94, 0xa0, 0xbf, 0xbd, 0xc2, 0x7f, 0x3a, 0x70, 0x88, 0x3f, 0xf8, 0x69, 0x92, 0x2d, + 0xaa, 0x78, 0x77, 0xb1, 0x10, 0xce, 0x99, 0xc5, 0x32, 0xdd, 0xc7, 0x3f, 0x64, 0xda, 0x5e, 0xdd, + 0x92, 0xfd, 0x4b, 0xfc, 0xa1, 0x20, 0x28, 0x25, 0xfc, 0xc1, 0x45, 0xb7, 0x40, 0x78, 0xec, 0xb7, + 0x0f, 0xf0, 0x84, 0xa9, 0x8a, 0x4a, 0x80, 0xe9, 0xe3, 0x45, 0x46, 0x78, 0xb0, 0x5b, 0x0e, 0xf9, + 0xe7, 0xb3, 0x1b, 0x07, 0xea, 0x41, 0x6b, 0x71, 0x43, 0x01, 0xab, 0x3d, 0x18, 0x18, 0x78, 0x33, + 0x30, 0x97, 0xe5, 0x7b, 0x6f, 0x87, 0x72, 0x25, 0x3f, 0xde, 0x96, 0x5d, 0x18, 0x31, 0xa3, 0xcd, + 0x9d, 0x2b, 0x6b, 0x7c, 0xcb, 0x42, 0x6b, 0x53, 0xc6, 0x12, 0x21, 0x8d, 0x1a, 0x5f, 0x27, 0x23, + 0x54, 0x37, 0xb4, 0x16, 0x36, 0x27, 0x06, 0xb9, 0x36, 0xb3, 0x5d, 0xe3, 0x50, 0x8e, 0xb3, 0xce, + 0x97, 0x4a, 0x94, 0xfa, 0x13, 0x98, 0x30, 0xc6, 0x11, 0x50, 0x07, 0x55, 0x71, 0x60, 0xd6, 0x09, + 0x78, 0x81, 0x57, 0x47, 0x6e, 0xd4, 0x69, 0x32, 0x5c, 0x00, 0x75, 0x65, 0x0c, 0xe8, 0x42, 0xec, + 0xbd, 0xa1, 0x9a, 0x84, 0x17, 0x47, 0x70, 0xbc, 0xec, 0xc0, 0xc6, 0x80, 0xcd, 0x51, 0x11, 0x0e, + 0x52, 0x27, 0x59, 0x62, 0x59, 0xc2, 0x3a, 0xd1, 0x10, 0xda, 0x95, 0xb8, 0x74, 0xa1, 0xaa, 0x2e, + 0x48, 0xe6, 0x53, 0xc6, 0xa1, 0xff, 0xc9, 0x28, 0x4f, 0x25, 0x4a, 0x64, 0xb2, 0x48, 0xfc, 0x2a, + 0xad, 0xf4, 0x4b, 0x18, 0x89, 0x9c, 0x3a, 0x81, 0x45, 0xb8, 0xef, 0x0f, 0xd5, 0x0f, 0x30, 0x0c, + 0xec, 0x22, 0x5f, 0x08, 0x6b, 0xcd, 0x62, 0xf9, 0x0e, 0x75, 0x1d, 0x62, 0x11, 0x9e, 0x15, 0x7a, + 0x77, 0xbb, 0xa3, 0x95, 0x9f, 0x5b, 0xa1, 0xbf, 0xa4, 0x44, 0x3b, 0x98, 0xe4, 0x42, 0x5c, 0xe9, + 0xb3, 0x12, 0x01, 0x65, 0x34, 0x13, 0x7d, 0xef, 0x63, 0x31, 0x4d, 0xe7, 0x03, 0x23, 0xb7, 0x42, + 0x01, 0x2a, 0x88, 0x9c, 0x11, 0x82, 0x28, 0x7f, 0xce, 0xe4, 0x37, 0x88, 0xb5, 0xaf, 0x6b, 0xe7, + 0x8c, 0xd4, 0x60, 0x6e, 0xa8, 0x2a, 0x05, 0xe3, 0xe2, 0x90, 0x0c, 0x74, 0x8c, 0x19, 0xb0, 0xe4, + 0x45, 0xa6, 0x05, 0x92, 0xc4, 0xdc, 0xf0, 0xeb, 0x4d, 0x65, 0x3c, 0xf7, 0xff, 0x83, 0x08, 0x7d, + 0x84, 0x51, 0xc6, 0x6c, 0x86, 0x3b, 0x22, 0xca, 0x34, 0xbb, 0xa0, 0x7c, 0x2b, 0x31, 0xb9, 0xe5, + 0x46, 0xa1, 0xd5, 0x82, 0xe4, 0x9c, 0x77, 0x87, 0x1a, 0xd5, 0x98, 0x45, 0xfa, 0xdc, 0xc5, 0xd3, + 0x1d, 0x72, 0x52, 0x90, 0xa8, 0x66, 0xbf, 0xbc, 0x1c, 0x2b, 0xcb, 0x6e, 0xb1, 0xa9, 0x31, 0xaf, + 0xdb, 0x00, 0x31, 0xe9, 0x2f, 0x70, 0xcd, 0x48, 0x6d, 0x3d, 0x02, 0xd1, 0x54, 0x2c, 0x21, 0xc0, + 0x12, 0xb9, 0x98, 0x61, 0x7f, 0xcc, 0x5c, 0x6b, 0x38, 0xee, 0x35, 0x27, 0x14, 0x42, 0xea, 0x29, + 0xeb, 0xb8, 0x20, 0xc1, 0x2c, 0x88, 0x7f, 0x92, 0x21, 0xda, 0x7c, 0x4c, 0x4d, 0x0a, 0x5d, 0x7e, + 0x9e, 0xec, 0x1d, 0xb7, 0xee, 0x23, 0x78, 0xad, 0x46, 0xff, 0xc6, 0x93, 0xd3, 0x6b, 0xe9, 0xc0, + 0xa7, 0x85, 0x62, 0x81, 0x99, 0xcc, 0xf6, 0xb0, 0xe5, 0x12, 0x24, 0xe8, 0x47, 0x88, 0x03, 0x8f, + 0x83, 0xe6, 0x17, 0x63, 0x99, 0x5b, 0x20, 0xfe, 0xb4, 0xc8, 0xec, 0x52, 0x07, 0x68, 0xb7, 0x05, + 0xf8, 0x3f, 0xe7, 0x7f, 0xa5, 0x6e, 0x00, 0xbc, 0x00, 0xe0, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 122880, // uncompressed data size (bytes) + 122636, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data[] = +{ + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x0c, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0x80, 0x97, 0x91, 0xad, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmBoot_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt }, + { "ucode_desc_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt }, + { "ucode_image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt }, + { "ucode_desc_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmBoot_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c new file mode 100644 index 000000000..a2683b4f2 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c @@ -0,0 +1,7884 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 122696 +// COMPRESSED SIZE (bytes): 122284 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_data[] = +{ + 0x8c, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x90, 0x44, 0x9b, 0xb7, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xdd, 0x3d, 0x2f, 0x26, 0xe6, 0x03, 0x26, + 0x37, 0x55, 0xeb, 0xcc, 0x88, 0x3a, 0x95, 0xc0, 0x20, 0xe2, 0x00, 0x00, 0x7b, 0x80, 0x00, 0xff, + 0x2b, 0xed, 0xff, 0x9b, 0x1e, 0x00, 0x00, 0x20, 0xff, 0xb7, 0x02, 0x92, 0x03, 0xfc, 0xbf, 0x24, + 0x54, 0x6d, 0xb5, 0xb9, 0x11, 0xb0, 0x95, 0x3c, 0xcf, 0xdd, 0x01, 0x90, 0x65, 0x0b, 0xf3, 0x30, + 0xf7, 0x27, 0x7d, 0xaa, 0x7c, 0x4d, 0x0a, 0xbd, 0xeb, 0x1e, 0xad, 0x10, 0xb3, 0x58, 0xca, 0x4d, + 0xd3, 0x45, 0x15, 0x97, 0xd1, 0xff, 0xb2, 0xe5, 0xc8, 0xea, 0xc6, 0x69, 0xa8, 0x3b, 0xc9, 0x7b, + 0x7f, 0x9e, 0x11, 0xb6, 0x17, 0x2b, 0x0d, 0x18, 0xf8, 0x22, 0x86, 0x89, 0xdc, 0x0d, 0xbe, 0x72, + 0x1b, 0x91, 0xb5, 0xab, 0xe2, 0x16, 0x44, 0x15, 0xbd, 0x74, 0x28, 0x41, 0x6a, 0x87, 0x16, 0x41, + 0xbd, 0x2a, 0xec, 0x3d, 0xc2, 0x4d, 0x56, 0x12, 0x46, 0x69, 0x36, 0xf7, 0xcd, 0xb2, 0x50, 0xc4, + 0x8b, 0x44, 0x11, 0x56, 0x98, 0xc9, 0x7e, 0xba, 0xd5, 0xa7, 0xea, 0xb6, 0x2a, 0xb1, 0x59, 0x5e, + 0x5d, 0x8c, 0x8f, 0x33, 0x4a, 0xa5, 0x73, 0xdb, 0x0c, 0xc7, 0x55, 0x78, 0x9f, 0x7d, 0x29, 0xeb, + 0xa7, 0x33, 0x49, 0xb8, 0xb5, 0x46, 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0x07, 0x92, 0xaa, 0x9c, 0xf7, 0x37, + 0xa7, 0xf1, 0x49, 0x83, 0x26, 0x2b, 0x1f, 0x51, 0xe3, 0x6e, 0x21, 0x10, 0xad, 0xc7, 0x0f, 0x56, + 0x1f, 0x07, 0x04, 0x23, 0x37, 0x51, 0xbc, 0x31, 0x48, 0xad, 0x5a, 0x48, 0x99, 0x24, 0x40, 0x8f, + 0xf6, 0xa0, 0x3e, 0x78, 0x44, 0x55, 0xfb, 0x38, 0x30, 0x8b, 0xe0, 0xaa, 0x1c, 0xd2, 0x56, 0x11, + 0xd5, 0x95, 0xea, 0x7b, 0x88, 0xcf, 0xbb, 0x5e, 0x09, 0x10, 0x84, 0x9b, 0x9b, 0xa4, 0x52, 0x5a, + 0x6c, 0xab, 0x20, 0x27, 0x2f, 0x04, 0xd5, 0xaf, 0xc3, 0xac, 0xb9, 0x0d, 0x61, 0xed, 0x3e, 0x76, + 0x1f, 0x7d, 0x5f, 0x08, 0x7d, 0xa3, 0x7a, 0x50, 0xf1, 0x17, 0x37, 0x27, 0x6b, 0xfd, 0xd5, 0x45, + 0x30, 0x18, 0x5f, 0x18, 0xaf, 0xb2, 0xa8, 0x7f, 0x84, 0x8f, 0x6a, 0xe9, 0xfa, 0x47, 0x45, 0x77, + 0xd1, 0x4b, 0xf1, 0x80, 0x97, 0xf3, 0x83, 0x6e, 0xa4, 0xc5, 0xf2, 0x6f, 0x7a, 0x59, 0xc5, 0xb4, + 0x6d, 0x40, 0x54, 0xca, 0xbd, 0x94, 0xed, 0xaf, 0x06, 0xd4, 0x73, 0x39, 0xa3, 0x3d, 0x54, 0x20, + 0x67, 0xf4, 0x7f, 0x00, 0x2b, 0x55, 0x36, 0x8f, 0x48, 0xdf, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 122696, // uncompressed data size (bytes) + 122284, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x31, 0xf2, 0x97, 0xfe, 0xfc, 0x97, 0x35, 0xc5, 0x70, 0x3e, 0x99, + 0x52, 0xcf, 0x77, 0x03, 0xf9, 0xc2, 0x58, 0x50, 0xe1, 0x94, 0x84, 0x2c, 0xbf, 0xf3, 0x76, 0xd3, + 0x8c, 0xfc, 0x09, 0xec, 0x19, 0x7e, 0x19, 0x1d, 0x68, 0x56, 0xe6, 0x59, 0xf1, 0x80, 0x39, 0x6d, + 0xc0, 0x7a, 0x97, 0x26, 0x0f, 0x9a, 0x32, 0xb1, 0x5c, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x82, 0x47, 0xd5, 0x77, 0x95, 0x34, 0x94, 0xf2, 0x7a, 0x82, 0xe8, + 0x78, 0xb7, 0x08, 0x96, 0xdd, 0xf5, 0x58, 0xd8, 0x5a, 0x7f, 0x9f, 0xff, 0x29, 0x70, 0x91, 0x41, + 0x75, 0xd5, 0x9d, 0xb8, 0xd8, 0x62, 0xe3, 0xb3, 0x81, 0xf6, 0x0c, 0x3d, 0x91, 0x73, 0xa5, 0x64, + 0x95, 0xf5, 0xf0, 0x10, 0x2a, 0x80, 0x5e, 0x93, 0x4d, 0xda, 0x7e, 0x44, 0xdd, 0x60, 0xc8, 0x87, + 0x69, 0xf3, 0x1e, 0x46, 0x3b, 0x4a, 0xd8, 0x8a, 0x3a, 0xe5, 0x3b, 0x17, 0xbb, 0xc0, 0x06, 0x7d, + 0x25, 0xe5, 0x9a, 0x1d, 0x31, 0xc6, 0x1a, 0x48, 0xe2, 0xdd, 0x4b, 0x99, 0xfb, 0x1e, 0x92, 0x5c, + 0xcf, 0x6c, 0x7f, 0x37, 0x95, 0x5b, 0xc4, 0xca, 0x8b, 0x9f, 0xe1, 0x3a, 0xef, 0x35, 0xbd, 0x66, + 0x75, 0x8b, 0x9e, 0x1e, 0xc0, 0x57, 0x7d, 0x7b, 0x87, 0x88, 0x13, 0x4b, 0xe1, 0xb1, 0xe3, 0xad, + 0x6f, 0xed, 0xeb, 0x5f, 0x9f, 0x98, 0xbe, 0xf5, 0x3f, 0xfe, 0x09, 0xf9, 0xe6, 0xc8, 0x4c, 0x4c, + 0x73, 0x6d, 0x01, 0xa3, 0x61, 0x20, 0x9e, 0xb3, 0x33, 0x8b, 0x07, 0xc1, 0xb2, 0xe7, 0x84, 0x18, + 0x94, 0x95, 0x97, 0xa3, 0xf8, 0x93, 0xf7, 0x3a, 0x71, 0xbf, 0x92, 0xb0, 0x18, 0xf7, 0xe8, 0xa5, + 0x85, 0xdb, 0x74, 0xa7, 0x90, 0x9d, 0x9b, 0x2f, 0xf8, 0x67, 0xe5, 0x05, 0x3d, 0xb4, 0xec, 0xf2, + 0xa1, 0x75, 0x22, 0xb6, 0x58, 0x09, 0x28, 0xa1, 0x72, 0x3f, 0xe3, 0xe7, 0x11, 0x1b, 0xfe, 0x18, + 0xdf, 0x53, 0xab, 0x5d, 0xb5, 0xbc, 0xcb, 0xa9, 0x12, 0x9a, 0xac, 0x89, 0xc2, 0xfa, 0xca, 0xe3, + 0xa9, 0xc6, 0x9e, 0xe1, 0xbe, 0x51, 0x15, 0xfc, 0x74, 0x58, 0x0c, 0x33, 0x4e, 0x2a, 0x54, 0x90, + 0x0e, 0x1f, 0xcf, 0x0c, 0x07, 0x9d, 0x7c, 0xf1, 0xd9, 0x38, 0xb4, 0x58, 0x30, 0xb6, 0xb5, 0x15, + 0x62, 0x4f, 0x36, 0x92, 0x24, 0x34, 0x29, 0x88, 0xb5, 0x8a, 0x84, 0x43, 0xb9, 0xf6, 0x22, 0x2e, + 0xaa, 0x84, 0x39, 0x15, 0xf7, 0x22, 0x93, 0x3c, 0x03, 0x05, 0x82, 0xd7, 0x02, 0x2c, 0xf2, 0x72, + 0xfc, 0x9b, 0xb6, 0x83, 0xf0, 0x77, 0x53, 0x76, 0xb3, 0xa2, 0xa6, 0xb2, 0x23, 0xda, 0xda, 0x77, + 0x4d, 0x94, 0xbf, 0xfd, 0x33, 0xc5, 0xc0, 0xd2, 0x00, 0xdf, 0xc5, 0x59, 0x82, 0x65, 0x5d, 0xdd, + 0xf0, 0x9e, 0x99, 0xd0, 0xf8, 0x00, 0x63, 0x3e, 0x3b, 0xef, 0x53, 0xbe, 0xf5, 0x4d, 0x78, 0xa7, + 0x59, 0x6a, 0x1c, 0x44, 0xd6, 0x99, 0xa1, 0xb9, 0xd5, 0x7f, 0xd9, 0x83, 0xbd, 0xae, 0x17, 0x3b, + 0xbe, 0x97, 0x91, 0x80, 0x7c, 0xad, 0x92, 0xdb, 0x5c, 0x25, 0x6b, 0x09, 0x5c, 0xc4, 0x13, 0xaa, + 0xc7, 0x1c, 0x6c, 0xa5, 0x48, 0xd1, 0x0a, 0x7f, 0xb5, 0x42, 0x27, 0x87, 0x56, 0x79, 0x40, 0x43, + 0x5e, 0x63, 0x93, 0x03, 0x08, 0x71, 0x34, 0xab, 0x24, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb1, 0xb2, 0x7a, 0x80, 0x2b, 0x7d, 0x7c, 0xc5, 0x65, 0x9b, 0x93, + 0x52, 0x4d, 0x36, 0x1d, 0xf9, 0x78, 0x50, 0xd6, 0x3f, 0x24, 0xad, 0x30, 0x50, 0x48, 0x5e, 0xe7, + 0x17, 0xea, 0xa5, 0x90, 0xd0, 0x16, 0xf8, 0xb2, 0xf2, 0x8e, 0x5c, 0x85, 0x38, 0x65, 0xab, 0xa7, + 0x28, 0x02, 0xef, 0x55, 0x9f, 0x32, 0x16, 0x19, 0x49, 0xc8, 0x71, 0x8e, 0x5f, 0x2d, 0xf7, 0x48, + 0x75, 0x47, 0xc1, 0x7f, 0xd7, 0x17, 0xb7, 0x8c, 0xbb, 0xad, 0xa7, 0xf2, 0x8b, 0xcb, 0x0f, 0xad, + 0xef, 0x3d, 0x09, 0x88, 0x47, 0x0f, 0x43, 0xdc, 0x6b, 0x0f, 0xc6, 0xac, 0x9e, 0x9e, 0x76, 0x09, + 0xa8, 0xbd, 0xc6, 0xe5, 0x9c, 0x20, 0xc2, 0x60, 0x3f, 0x10, 0xa8, 0xe1, 0x62, 0x91, 0x97, 0x4f, + 0x95, 0x52, 0x3a, 0xd3, 0xa8, 0xfe, 0x66, 0xe4, 0xe4, 0xef, 0xbb, 0xab, 0x20, 0xd8, 0x1b, 0xf2, + 0xc9, 0x04, 0x01, 0x1d, 0x39, 0xe6, 0x3c, 0x1a, 0xe4, 0xfd, 0xb6, 0xd1, 0x18, 0x81, 0x5e, 0x78, + 0xec, 0xee, 0x63, 0xd4, 0x91, 0x3a, 0x05, 0x2c, 0x36, 0x84, 0xbd, 0xb1, 0xfa, 0xb7, 0xf4, 0x5a, + 0xf6, 0xd0, 0x7f, 0x78, 0xe4, 0x16, 0x00, 0x2b, 0xc0, 0xac, 0x9e, 0x89, 0x50, 0x78, 0xbb, 0xe7, + 0x4d, 0x9d, 0xf4, 0xc9, 0xfe, 0xb7, 0x29, 0x65, 0x6f, 0x33, 0x91, 0x2c, 0x3a, 0x7d, 0x8e, 0xc5, + 0x84, 0xd6, 0x55, 0x3b, 0x79, 0x0c, 0xea, 0x93, 0x9f, 0x64, 0x49, 0x1a, 0xf5, 0x2c, 0xc8, 0x10, + 0x92, 0x90, 0xb1, 0xe3, 0x0e, 0xd0, 0xf4, 0xad, 0x11, 0x3b, 0x20, 0xb1, 0x2d, 0xc7, 0xa6, 0x6e, + 0xd3, 0x9c, 0x67, 0x49, 0x3e, 0xad, 0xea, 0x44, 0x09, 0x96, 0x96, 0xce, 0x1e, 0x7a, 0xcd, 0x40, + 0x30, 0xa2, 0xdb, 0xce, 0x60, 0x19, 0xd8, 0x8d, 0x96, 0x5e, 0x0c, 0x30, 0xcd, 0xe3, 0xcb, 0x02, + 0x3e, 0x2b, 0x26, 0x38, 0x2b, 0x2c, 0x09, 0xa6, 0xc8, 0xad, 0xbb, 0xde, 0x67, 0x33, 0xaf, 0x53, + 0x72, 0x7c, 0x77, 0xe2, 0xb8, 0xe2, 0xe0, 0x11, 0xb8, 0x26, 0xe7, 0x92, 0x29, 0x8b, 0xe1, 0xef, + 0x6a, 0x7e, 0x49, 0x09, 0x37, 0xde, 0x61, 0xc5, 0xeb, 0x11, 0x72, 0x47, 0x85, 0x2a, 0x66, 0x6c, + 0x5f, 0x02, 0xb5, 0x86, 0x82, 0x81, 0x56, 0x8e, 0x1c, 0xa4, 0xf8, 0xab, 0x7e, 0x1f, 0x9b, 0x84, + 0x5b, 0xdd, 0xc1, 0x7d, 0x62, 0xa1, 0xd2, 0x96, 0xc8, 0x1e, 0x2f, 0x32, 0xcd, 0x18, 0x0d, 0x6c, + 0x4a, 0x1c, 0xa0, 0x82, 0x74, 0x28, 0x15, 0xf9, 0xa1, 0x65, 0x52, 0x03, 0x8a, 0x7f, 0x0d, 0xff, + 0xd1, 0x15, 0x04, 0x99, 0x7d, 0xd8, 0xa3, 0x04, 0xe3, 0x22, 0x60, 0x40, 0x74, 0xf6, 0x08, 0x48, + 0x24, 0xe8, 0xbc, 0x54, 0x19, 0x3c, 0xc4, 0x38, 0xfc, 0xa9, 0x5e, 0x92, 0xa4, 0xae, 0x0a, 0x8a, + 0xef, 0xca, 0x63, 0x96, 0x9d, 0xf3, 0x87, 0x94, 0x2b, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c new file mode 100644 index 000000000..9a0e49ea0 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c @@ -0,0 +1,7908 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 122696 +// COMPRESSED SIZE (bytes): 122661 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_data[] = +{ + 0x8c, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x80, 0x43, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0x6e, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xad, 0x79, 0x35, 0x35, 0x1f, 0x30, 0xd9, + 0x24, 0xab, 0x64, 0x7b, 0x02, 0x0c, 0x22, 0x0e, 0x00, 0xb0, 0x07, 0x08, 0xf0, 0xbf, 0xd2, 0xfe, + 0x3f, 0xf7, 0x00, 0x00, 0x00, 0xf9, 0xbf, 0x08, 0x48, 0x01, 0xf0, 0xff, 0x12, 0x33, 0xf9, 0x53, + 0x57, 0xad, 0x8f, 0xcf, 0xc0, 0xbf, 0xf7, 0xa0, 0xb8, 0x6c, 0x38, 0xa1, 0x8e, 0x02, 0x68, 0x59, + 0x1e, 0xac, 0x5c, 0x19, 0xbc, 0xc3, 0x3f, 0x7b, 0xec, 0x4b, 0x63, 0xdf, 0x1e, 0x07, 0x73, 0xb1, + 0x13, 0x10, 0x8a, 0xb1, 0xdd, 0x34, 0x24, 0xbc, 0xcc, 0x9e, 0xec, 0x77, 0x91, 0x62, 0xa7, 0x5f, + 0x07, 0x5a, 0x89, 0x8d, 0xeb, 0x7e, 0x7b, 0x19, 0xc3, 0xda, 0xb5, 0x8a, 0xb4, 0x68, 0x3a, 0x43, + 0x30, 0x07, 0x98, 0x73, 0x98, 0x1b, 0x46, 0x46, 0xe8, 0x76, 0x03, 0x33, 0x34, 0x12, 0x43, 0x70, + 0x3d, 0x39, 0x22, 0xe1, 0x27, 0x78, 0x72, 0xf4, 0x2f, 0xd6, 0xca, 0x18, 0xe4, 0xae, 0x84, 0x22, + 0x46, 0xc0, 0x1a, 0xe7, 0x3a, 0xb0, 0x4b, 0x75, 0x25, 0xc4, 0xd2, 0xa2, 0x3a, 0x43, 0x07, 0x4f, + 0x89, 0x2b, 0xed, 0x9d, 0x17, 0x5c, 0x71, 0xa9, 0xbd, 0x3b, 0x0b, 0xde, 0xda, 0xf3, 0x99, 0x92, + 0x89, 0xb0, 0xb5, 0x0f, 0xb0, 0xf2, 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0x06, 0x99, 0x49, 0x1a, 0x49, 0xdd, + 0xef, 0x1b, 0x68, 0x3e, 0xc1, 0xfe, 0x09, 0xef, 0x2a, 0xf9, 0x7a, 0xaa, 0x75, 0xe0, 0x38, 0x65, + 0xe3, 0x1c, 0xd3, 0x9b, 0x2d, 0x8a, 0x47, 0xcd, 0x9e, 0x72, 0xfe, 0xd4, 0xe6, 0xd9, 0x2a, 0x1e, + 0xc8, 0x58, 0x16, 0x67, 0x1b, 0x77, 0x00, 0xe1, 0x30, 0xfe, 0xd6, 0xd3, 0x64, 0x72, 0xce, 0xe6, + 0x10, 0x65, 0x06, 0x47, 0xb9, 0x89, 0x6c, 0xa6, 0xff, 0x29, 0xbe, 0x9f, 0x0f, 0x36, 0xed, 0x67, + 0x7c, 0x25, 0x51, 0x2e, 0xfd, 0xdb, 0xa7, 0x65, 0x40, 0xf1, 0x83, 0x71, 0xb7, 0x9c, 0xa8, 0xae, + 0x0b, 0xa9, 0x93, 0x5f, 0x2f, 0xb6, 0x3e, 0xc2, 0x40, 0x93, 0x79, 0x12, 0x3a, 0x46, 0xcc, 0x38, + 0x83, 0x85, 0x27, 0x90, 0xa7, 0x6e, 0x3b, 0x8f, 0x31, 0x67, 0x59, 0xe5, 0xca, 0x2b, 0xc0, 0x96, + 0x2f, 0x1f, 0x47, 0xfe, 0x2d, 0x44, 0x1d, 0x61, 0x2f, 0x20, 0x0c, 0x20, 0xd7, 0xb4, 0xf9, 0x08, + 0x73, 0xdd, 0xaa, 0x23, 0x18, 0x6e, 0x82, 0x4c, 0x8a, 0x4f, 0x8c, 0xe7, 0x32, 0xe1, 0x3d, 0x19, + 0xdd, 0x80, 0x91, 0x81, 0x94, 0xe6, 0xc3, 0x2e, 0x19, 0xc6, 0x65, 0x94, 0x63, 0x94, 0x5f, 0xfe, + 0x8b, 0xe0, 0xd3, 0x0e, 0x3f, 0x17, 0xa4, 0x90, 0xf3, 0x81, 0xb7, 0xb5, 0x89, 0x01, 0x5d, 0xf3, + 0x75, 0x1c, 0x3d, 0x52, 0x10, 0xd0, 0x07, 0x24, 0x94, 0x12, 0x9b, 0x3c, 0x59, 0x31, 0x1c, 0x33, + 0xd0, 0x75, 0x58, 0x07, 0xeb, 0xb9, 0xf6, 0x3e, 0x12, 0xa2, 0x1b, 0x26, 0xbf, 0xd6, 0xaa, 0x0a, + 0x9b, 0x84, 0xa2, 0xdc, 0x4e, 0x98, 0x20, 0x06, 0x58, 0xe7, 0x8b, 0xa3, 0x0e, 0x29, 0x2d, 0x17, + 0x78, 0x82, 0x31, 0x66, 0x99, 0x6a, 0xf1, 0xa2, 0x9e, 0x89, 0x29, 0x61, 0xb4, 0xc4, 0x09, 0x7b, + 0x81, 0x2a, 0x24, 0x66, 0x05, 0xe2, 0x1f, 0xa0, 0xe4, 0x2f, 0xd7, 0x17, 0xe0, 0xd8, 0xb2, 0xdb, + 0xbf, 0x0f, 0xaf, 0x2c, 0x32, 0xbc, 0x70, 0x6d, 0x52, 0x6e, 0x9e, 0xcd, 0xd0, 0x2f, 0xdd, 0xe2, + 0x77, 0x7f, 0x88, 0x34, 0xbd, 0x95, 0xc8, 0x0b, 0xbf, 0x7b, 0xfa, 0x53, 0x94, 0x60, 0xca, 0xb2, + 0x8d, 0xb2, 0x91, 0x93, 0x5f, 0xbb, 0x4a, 0xa9, 0xac, 0x3d, 0xa6, 0xe3, 0x81, 0xa0, 0xee, 0xf1, + 0xf6, 0x8e, 0xda, 0x92, 0x24, 0xb0, 0xf5, 0x13, 0x38, 0x49, 0xb6, 0x1f, 0x8e, 0xce, 0x64, 0x58, + 0x71, 0xd9, 0x9d, 0x75, 0x8e, 0x38, 0xdf, 0x08, 0xfb, 0xcf, 0x40, 0x45, 0x74, 0xc7, 0xaf, 0xd0, + 0x1d, 0x47, 0x2e, 0x93, 0x78, 0xa5, 0x8c, 0x4c, 0xfe, 0xf9, 0x65, 0x79, 0xc2, 0x3e, 0x42, 0xa4, + 0x44, 0xa2, 0x62, 0xc5, 0xb9, 0xfb, 0xb4, 0xfc, 0x20, 0x03, 0xa1, 0xcd, 0x29, 0x4e, 0x17, 0x4a, + 0x10, 0x56, 0xec, 0x71, 0x46, 0x9b, 0x45, 0xd4, 0xbc, 0xae, 0x42, 0x0b, 0xa2, 0x54, 0x6d, 0x0a, + 0x74, 0xfe, 0x57, 0x33, 0x38, 0x9d, 0xd8, 0x79, 0x5f, 0xf2, 0x98, 0x91, 0xf9, 0x80, 0x65, 0xf6, + 0xc6, 0x2a, 0x39, 0xbe, 0x2b, 0x49, 0xaa, 0xcb, 0xf0, 0x51, 0x2a, 0x94, 0x8d, 0x4d, 0x71, 0x19, + 0x2d, 0x26, 0xc6, 0xea, 0xb3, 0x8e, 0x22, 0xb5, 0x16, 0x37, 0x7e, 0x53, 0x2d, 0x5b, 0x60, 0x91, + 0x19, 0xb6, 0x2f, 0xb7, 0x6d, 0x11, 0x87, 0x7f, 0xcb, 0x54, 0x0d, 0x32, 0xdb, 0xc8, 0xa0, 0xeb, + 0xd5, 0x1e, 0x87, 0x1a, 0xe6, 0xe4, 0x90, 0x32, 0xb3, 0x62, 0xb9, 0x84, 0xb7, 0xf2, 0x96, 0x9d, + 0x52, 0xba, 0x8b, 0xa7, 0x7e, 0x91, 0xfa, 0x96, 0xf7, 0x3d, 0xf3, 0x30, 0x88, 0x65, 0x51, 0xb7, + 0x20, 0xfe, 0x30, 0x53, 0x0f, 0x82, 0x86, 0xb1, 0x3d, 0x9f, 0x05, 0x0c, 0xe4, 0x22, 0x54, 0xc0, + 0x60, 0xbc, 0x55, 0x20, 0x4e, 0x70, 0x38, 0xcb, 0x1b, 0xe5, 0x89, 0x2a, 0xc3, 0x32, 0x85, 0x18, + 0xad, 0x3a, 0x5a, 0x7a, 0xa4, 0xda, 0x42, 0x39, 0x02, 0xfc, 0x36, 0xff, 0x03, 0x35, 0x74, 0x57, + 0x90, 0x48, 0xdf, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 122696, // uncompressed data size (bytes) + 122661, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x7d, 0x76, 0xf8, 0x43, 0xa9, 0xee, 0xe8, 0x60, 0xa1, 0xad, 0x46, + 0x44, 0x30, 0xd9, 0xf4, 0xc4, 0x7f, 0xbd, 0xed, 0xdd, 0xd2, 0x4b, 0x5e, 0x16, 0x37, 0xe2, 0x5b, + 0x50, 0x76, 0xa8, 0x48, 0x87, 0xe5, 0xe0, 0x64, 0x59, 0x1c, 0x8a, 0xb7, 0x59, 0xe8, 0x71, 0x30, + 0x76, 0x8b, 0x26, 0x84, 0x9e, 0xb5, 0x51, 0xd5, 0x33, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x04, 0x4a, 0x26, 0x73, 0x30, 0x94, 0xde, 0xaa, 0x24, 0xa2, 0xc3, + 0xb5, 0x00, 0x22, 0xa4, 0x0a, 0xef, 0x1a, 0xaa, 0x39, 0x70, 0xc7, 0x17, 0xcc, 0x6e, 0x54, 0x2d, + 0xe2, 0x2a, 0xad, 0xfd, 0x00, 0xee, 0xdd, 0xa3, 0xb3, 0x16, 0xf0, 0x26, 0x78, 0x04, 0xe6, 0xfc, + 0x7d, 0xf1, 0x11, 0x5a, 0xc9, 0x1b, 0xcc, 0x98, 0xc1, 0x51, 0x84, 0xeb, 0x92, 0x34, 0xd9, 0x28, + 0x76, 0x17, 0x76, 0x55, 0x14, 0x97, 0x68, 0x0a, 0xb8, 0xe8, 0xa3, 0xe0, 0x07, 0x6c, 0xdc, 0x2b, + 0x31, 0x0a, 0x82, 0x1d, 0xb9, 0x52, 0x74, 0x3c, 0x09, 0xec, 0x68, 0x7d, 0x1b, 0x18, 0x31, 0x16, + 0x3b, 0x7a, 0x94, 0x36, 0x0e, 0x75, 0x57, 0x74, 0x4b, 0x1b, 0x7f, 0xae, 0x03, 0x6e, 0x50, 0x6b, + 0x6d, 0x09, 0x92, 0x9a, 0x3b, 0xec, 0x71, 0x5c, 0x54, 0x15, 0x75, 0x79, 0x43, 0x4d, 0x38, 0xcd, + 0xdf, 0xfd, 0xe4, 0x00, 0x7e, 0xdf, 0x19, 0x1e, 0x89, 0xb9, 0x23, 0x66, 0x93, 0x11, 0x7d, 0x22, + 0xab, 0x82, 0xe6, 0x3d, 0x34, 0xd8, 0x63, 0xfa, 0xae, 0x6e, 0x44, 0xaf, 0x4b, 0x58, 0xdf, 0xd3, + 0x16, 0x5b, 0xe2, 0xbf, 0x75, 0x3f, 0xa1, 0x96, 0x38, 0x09, 0x0f, 0x3e, 0x50, 0xef, 0x0b, 0x16, + 0xe3, 0x89, 0xad, 0xc2, 0x81, 0x83, 0xe6, 0x38, 0xf9, 0xaa, 0x33, 0x09, 0x0e, 0x93, 0x5e, 0x76, + 0x5f, 0xfd, 0x99, 0x82, 0xbd, 0xd0, 0xe4, 0xd8, 0x15, 0x26, 0x58, 0x0f, 0xfb, 0x49, 0xbd, 0xf7, + 0xbd, 0x6b, 0x07, 0xef, 0x3d, 0x26, 0xd0, 0x8b, 0x5b, 0x5b, 0x60, 0x94, 0xcb, 0xd6, 0x67, 0x96, + 0x83, 0xaa, 0xe9, 0x66, 0xd7, 0x21, 0x40, 0x2c, 0xd4, 0xbd, 0x84, 0xf1, 0xcb, 0x8e, 0x1c, 0xf1, + 0xdd, 0xad, 0x46, 0x4d, 0x08, 0xdc, 0x33, 0xcf, 0x62, 0x3b, 0xc0, 0x78, 0x4d, 0x80, 0x96, 0x44, + 0x9e, 0x2f, 0xae, 0x80, 0xb1, 0x29, 0xef, 0x1f, 0x1d, 0xb3, 0x76, 0x57, 0x2c, 0x01, 0xca, 0x03, + 0x0e, 0x06, 0xc3, 0xe9, 0xc1, 0xe7, 0xeb, 0xd9, 0x6a, 0x7c, 0x27, 0x17, 0xeb, 0x8e, 0x7a, 0xe2, + 0xe0, 0x28, 0xbd, 0x6f, 0x6e, 0x4e, 0xe6, 0x07, 0xe5, 0x22, 0x27, 0x34, 0x78, 0x56, 0xdf, 0xd5, + 0x90, 0x27, 0xdb, 0x63, 0xb5, 0xc5, 0x1b, 0x8a, 0x17, 0x66, 0x04, 0x75, 0x9d, 0xc6, 0x2b, 0xcf, + 0xde, 0xb6, 0xe1, 0xe9, 0xfe, 0x54, 0xcf, 0x5d, 0xa2, 0xc8, 0xc7, 0xb3, 0x86, 0xf9, 0xd4, 0x25, + 0xf5, 0xc8, 0x36, 0x13, 0x8e, 0xf5, 0xe5, 0xc9, 0xf6, 0x2d, 0xa3, 0x48, 0xa0, 0x13, 0xb6, 0x07, + 0xb5, 0x25, 0x2f, 0xae, 0x63, 0x06, 0x71, 0xf7, 0x11, 0x74, 0xa4, 0xac, 0xc7, 0x3c, 0xc9, 0x09, + 0x82, 0xf2, 0xa5, 0x60, 0xcc, 0x11, 0x0a, 0xb4, 0xe7, 0xa8, 0xf0, 0x0a, 0x5a, 0x2c, 0x63, 0x30, + 0xe7, 0x21, 0x48, 0xb2, 0xbe, 0xfd, 0xc2, 0x18, 0x58, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, + 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, + 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, + 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, + 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, + 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, + 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, + 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, + 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, + 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, + 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, + 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, + 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, + 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, + 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, + 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, + 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, + 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, + 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, + 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, + 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, + 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, + 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, + 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, + 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcGfwProdSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmCcGfwProdSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + + + + diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.c b/src/nvidia/generated/g_chips2halspec_nvoc.c index 6bb8d21ed..210fc7ffe 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.c +++ b/src/nvidia/generated/g_chips2halspec_nvoc.c @@ -64,6 +64,26 @@ void __nvoc_init_halspec_ChipHal(ChipHal *pChipHal, NvU32 arch, NvU32 impl, NvU3 { pChipHal->__nvoc_HalVarIdx = 47; } + // AD102 + else if(arch == 0x19 && impl == 0x2) + { + pChipHal->__nvoc_HalVarIdx = 52; + } + // AD103 + else if(arch == 0x19 && impl == 0x3) + { + pChipHal->__nvoc_HalVarIdx = 53; + } + // AD104 + else if(arch == 0x19 && impl == 0x4) + { + pChipHal->__nvoc_HalVarIdx = 54; + } + // GH100 + else if(arch == 0x18 && impl == 0x0) + { + pChipHal->__nvoc_HalVarIdx = 59; + } } void __nvoc_init_halspec_RmVariantHal(RmVariantHal *pRmVariantHal, RM_RUNTIME_VARIANT rmVariant) @@ -87,6 +107,11 @@ void __nvoc_init_halspec_DispIpHal(DispIpHal *pDispIpHal, NvU32 ipver) { pDispIpHal->__nvoc_HalVarIdx = 11; } + // DISPv0404 + else if(ipver == 0x4040000) + { + pDispIpHal->__nvoc_HalVarIdx = 14; + } // DISPv0000 else if(ipver == 0x0) { diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.h b/src/nvidia/generated/g_chips2halspec_nvoc.h index a03cd49de..01e8af72a 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.h +++ b/src/nvidia/generated/g_chips2halspec_nvoc.h @@ -99,6 +99,8 @@ void __nvoc_init_halspec_DispIpHal(DispIpHal*, NvU32); // delete ~DISPv0400 & (TU102 | TU104 | TU106 | TU116 | TU117); // delete DISPv0401 & ~(GA102 | GA103 | GA104 | GA106 | GA107); // delete ~DISPv0401 & (GA102 | GA103 | GA104 | GA106 | GA107); +// delete DISPv0404 & ~(AD102 | AD103 | AD104); +// delete ~DISPv0404 & (AD102 | AD103 | AD104); /* DPU IP versions */ diff --git a/src/nvidia/generated/g_chipset_nvoc.c b/src/nvidia/generated/g_chipset_nvoc.c index e3ddddf7b..2d1ec5e32 100644 --- a/src/nvidia/generated/g_chipset_nvoc.c +++ b/src/nvidia/generated/g_chipset_nvoc.c @@ -73,6 +73,7 @@ void __nvoc_dtor_OBJCL(OBJCL *pThis) { void __nvoc_init_dataField_OBJCL(OBJCL *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); pThis->setProperty(pThis, PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR, ((NvBool)(0 != 0))); } NV_STATUS __nvoc_ctor_Object(Object* ); diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index 0233c99d7..f06fd1a38 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -76,7 +76,9 @@ struct PCIECONFIGSPACEBASE // CL_IS_ROOT_PORT() returns NV_TRUE if root port of PCI-E Root Complex // Device/Port type is 23:20 // Root port is 0100b -#define CL_IS_ROOT_PORT(p) (((p & 0xf00000) >> 20) == 0x4) +#define CL_IS_ROOT_PORT(p) (((p & 0xf00000) >> 20) == 0x4) +#define CL_IS_UPSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x5) +#define CL_IS_DOWNSTREAM_PORT(p) (((p & 0xf00000) >> 20) == 0x6) #define CL_AVG_LINK_WIDTH 8 #define CL_DAGWOOD_LINK_WIDTH 8 #define CL_SINGLE_DW_LINK_WIDTH 8 @@ -145,12 +147,33 @@ struct PCIECONFIGSPACEBASE #define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34) #define CL_AER_END (CL_AER_BEGIN + 0x34) +// PCI Express Device Capabilities 2 +#define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6) +#define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7) +#define CL_PCIE_DEV_CAP_2_ATOMIC_64BIT NVBIT(8) +#define CL_PCIE_DEV_CAP_2_ATOMIC_128BIT NVBIT(9) + +// PCI Express Device Control & Status 2 +#define CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT NVBIT(7) + +// Defines for Atomic Mask +#define CL_ATOMIC_32BIT NVBIT(0) +#define CL_ATOMIC_64BIT NVBIT(1) +#define CL_ATOMIC_128BIT NVBIT(2) + #define CL_IS_L0_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L0S_BIT)) #define CL_IS_L1_SUPPORTED(p) (((p) & CL_PCIE_LINK_CAP_ASPM_L1_BIT)) #define CL_IS_LTR_PORT_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_LTR_SUPPORTED_BIT)) #define CL_IS_LTR_PORT_ENABLED(p) (((p) & CL_PCIE_DEV_CTRL_2_LTR_ENABLED_BIT)) +#define CL_IS_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT)) +#define CL_IS_ATOMICS_EGRESS_BLOCKED(p) (((p) & CL_PCIE_DEV_CTRL_2_ATOMICS_EGRESS_BLOCK_BIT)) + +#define CL_IS_32BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_32BIT)) +#define CL_IS_64BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_64BIT)) +#define CL_IS_128BIT_ATOMICS_SUPPORTED(p) (((p) & CL_PCIE_DEV_CAP_2_ATOMIC_128BIT)) + // // This defines PCI-E Advanced Error Reporting Capability structure per PCI-E manual // (refer to section 7.10 of PCI Express Base Specification, v1.1) @@ -266,6 +289,8 @@ struct OBJCL { NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT; NvBool PDB_PROP_CL_DISABLE_IOMAP_WC; NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE; + NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR; + NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS; NBADDR NBAddr; NvBool EnteredRecoverySinceErrorsLastChecked; struct OBJHWBC *pHWBC; @@ -310,6 +335,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL; #define PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE_BASE_NAME PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_CAST #define PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED_BASE_NAME PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED +#define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_CAST +#define PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS_BASE_NAME PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_CAST #define PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG_BASE_NAME PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG #define PDB_PROP_CL_ON_PCIE_GEN3_PATSBURG_BASE_CAST @@ -362,6 +389,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL; #define PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390_BASE_NAME PDB_PROP_CL_FORCE_SNOOP_READS_AND_WRITES_WAR_BUG_410390 #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY +#define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_CAST +#define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_NAME PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR #define PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE_BASE_CAST #define PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE_BASE_NAME PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_CAST @@ -993,6 +1022,19 @@ static inline NV_STATUS clControlL0sL1LinkControlUpstreamPort(struct OBJGPU *arg #define clControlL0sL1LinkControlUpstreamPort_HAL(arg0, arg1, arg2) clControlL0sL1LinkControlUpstreamPort(arg0, arg1, arg2) +NV_STATUS clChipsetAspmPublicControl_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2); + +#ifdef __nvoc_chipset_h_disabled +static inline NV_STATUS clChipsetAspmPublicControl(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_chipset_h_disabled +#define clChipsetAspmPublicControl(arg0, arg1, arg2) clChipsetAspmPublicControl_IMPL(arg0, arg1, arg2) +#endif //__nvoc_chipset_h_disabled + +#define clChipsetAspmPublicControl_HAL(arg0, arg1, arg2) clChipsetAspmPublicControl(arg0, arg1, arg2) + NvBool clRootportNeedsNosnoopWAR_FWCLIENT(struct OBJGPU *arg0, struct OBJCL *arg1); #ifdef __nvoc_chipset_h_disabled @@ -1050,6 +1092,16 @@ static inline NV_STATUS clCheckUpstreamLtrSupport(struct OBJGPU *arg0, struct OB #define clCheckUpstreamLtrSupport(arg0, arg1, arg2) clCheckUpstreamLtrSupport_IMPL(arg0, arg1, arg2) #endif //__nvoc_chipset_h_disabled +NV_STATUS clGetAtomicTypesSupported_IMPL(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3); +#ifdef __nvoc_chipset_h_disabled +static inline NV_STATUS clGetAtomicTypesSupported(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_chipset_h_disabled +#define clGetAtomicTypesSupported(arg0, arg1, arg2, arg3) clGetAtomicTypesSupported_IMPL(arg0, arg1, arg2, arg3) +#endif //__nvoc_chipset_h_disabled + void clSyncWithGsp_IMPL(struct OBJCL *arg0, GspSystemInfo *arg1); #ifdef __nvoc_chipset_h_disabled static inline void clSyncWithGsp(struct OBJCL *arg0, GspSystemInfo *arg1) { diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 217aa4107..33a763b88 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -459,12 +459,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [18] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + /*flags=*/ 0x7u, /*accessRight=*/0x0u, /*methodId=*/ 0x13du, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS), @@ -1434,7 +1434,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetRmInstanceId__ = &cliresCtrlCmdSystemGetRmInstanceId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) pThis->__cliresCtrlCmdSystemGetClientDatabaseInfo__ = &cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index e713760f8..e4f37695b 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -233,6 +233,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBifAspmCyaUpdate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800105u, + /*paramSize=*/ sizeof(NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdBifAspmCyaUpdate" +#endif + }, + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -247,7 +262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslist" #endif }, - { /* [4] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -262,7 +277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetNumSubdevices" #endif }, - { /* [5] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -277,7 +292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuModifyGpuSwStatePersistence" #endif }, - { /* [6] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -292,7 +307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuQueryGpuSwStatePersistence" #endif }, - { /* [7] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -307,7 +322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVirtualizationMode" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -322,7 +337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSparseTextureComputeMode" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -337,7 +352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetSparseTextureComputeMode" #endif }, - { /* [10] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -352,7 +367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVgxCaps" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -367,7 +382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [12] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -382,7 +397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -397,7 +412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -412,7 +427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -427,7 +442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -442,7 +457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -457,7 +472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -472,7 +487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -487,7 +502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [20] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -502,7 +517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [21] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -517,7 +532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [22] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -532,7 +547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [23] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -547,7 +562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [24] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -562,7 +577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [25] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -577,7 +592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [26] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -592,7 +607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [27] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -607,7 +622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [28] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -622,7 +637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [29] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -637,7 +652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [30] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -652,7 +667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [31] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -667,7 +682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [32] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -682,7 +697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [33] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -697,7 +712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [34] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -712,7 +727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [35] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -727,7 +742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [36] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -742,7 +757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [37] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -757,7 +772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -772,7 +787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [39] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -787,7 +802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -802,7 +817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [41] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -817,7 +832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [42] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -832,7 +847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -847,7 +862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -862,7 +877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -877,7 +892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -892,7 +907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [47] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -907,7 +922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [48] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -922,7 +937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [49] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -937,7 +952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [50] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -952,7 +967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [51] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -967,7 +982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [52] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -982,7 +997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [53] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -997,7 +1012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [54] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1012,7 +1027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [55] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1027,7 +1042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [56] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1047,7 +1062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 57, + /*numEntries=*/ 58, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1100,6 +1115,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdBifAspmFeatureSupported__ = &deviceCtrlCmdBifAspmFeatureSupported_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__deviceCtrlCmdBifAspmCyaUpdate__ = &deviceCtrlCmdBifAspmCyaUpdate_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__deviceCtrlCmdDmaGetPteInfo__ = &deviceCtrlCmdDmaGetPteInfo_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index d21e89d58..a1e0f4921 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -89,6 +89,7 @@ struct Device { NV_STATUS (*__deviceCtrlCmdBifReset__)(struct Device *, NV0080_CTRL_BIF_RESET_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifGetDmaBaseSysmemAddr__)(struct Device *, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmFeatureSupported__)(struct Device *, NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS *); + NV_STATUS (*__deviceCtrlCmdBifAspmCyaUpdate__)(struct Device *, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaGetPteInfo__)(struct Device *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaUpdatePde2__)(struct Device *, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaSetPageDirectory__)(struct Device *, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *); @@ -217,6 +218,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdBifReset(pDevice, pBifResetParams) deviceCtrlCmdBifReset_DISPATCH(pDevice, pBifResetParams) #define deviceCtrlCmdBifGetDmaBaseSysmemAddr(pDevice, pBifDmaBaseSysmemParams) deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(pDevice, pBifDmaBaseSysmemParams) #define deviceCtrlCmdBifAspmFeatureSupported(pDevice, pBifAspmParams) deviceCtrlCmdBifAspmFeatureSupported_DISPATCH(pDevice, pBifAspmParams) +#define deviceCtrlCmdBifAspmCyaUpdate(pDevice, pBifAspmCyaParams) deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(pDevice, pBifAspmCyaParams) #define deviceCtrlCmdDmaGetPteInfo(pDevice, pParams) deviceCtrlCmdDmaGetPteInfo_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaUpdatePde2(pDevice, pParams) deviceCtrlCmdDmaUpdatePde2_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaSetPageDirectory(pDevice, pParams) deviceCtrlCmdDmaSetPageDirectory_DISPATCH(pDevice, pParams) @@ -321,6 +323,12 @@ static inline NV_STATUS deviceCtrlCmdBifAspmFeatureSupported_DISPATCH(struct Dev return pDevice->__deviceCtrlCmdBifAspmFeatureSupported__(pDevice, pBifAspmParams); } +NV_STATUS deviceCtrlCmdBifAspmCyaUpdate_IMPL(struct Device *pDevice, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *pBifAspmCyaParams); + +static inline NV_STATUS deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(struct Device *pDevice, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *pBifAspmCyaParams) { + return pDevice->__deviceCtrlCmdBifAspmCyaUpdate__(pDevice, pBifAspmCyaParams); +} + NV_STATUS deviceCtrlCmdDmaGetPteInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams); static inline NV_STATUS deviceCtrlCmdDmaGetPteInfo_DISPATCH(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams) { diff --git a/src/nvidia/generated/g_disp_channel_nvoc.h b/src/nvidia/generated/g_disp_channel_nvoc.h index 53ef73b2e..6b9091cf0 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.h +++ b/src/nvidia/generated/g_disp_channel_nvoc.h @@ -314,24 +314,19 @@ static inline NV_STATUS dispchnGrabChannel(struct DispChannel *pDispChannel, NvH #define dispchnGrabChannel(pDispChannel, hClient, hParent, hChannel, hClass, pAllocParms) dispchnGrabChannel_IMPL(pDispChannel, hClient, hParent, hChannel, hClass, pAllocParms) #endif //__nvoc_disp_channel_h_disabled -NV_STATUS dispchnBindCtx_IMPL(struct DispChannel *pDispChannel, struct OBJGPU *pGpu, struct ContextDma *pContextDma); +NV_STATUS dispchnBindCtx_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma, NvHandle hDispChannel); +#define dispchnBindCtx(pGpu, pContextDma, hDispChannel) dispchnBindCtx_IMPL(pGpu, pContextDma, hDispChannel) +NV_STATUS dispchnUnbindCtx_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma, NvHandle hDispChannel); +#define dispchnUnbindCtx(pGpu, pContextDma, hDispChannel) dispchnUnbindCtx_IMPL(pGpu, pContextDma, hDispChannel) +void dispchnUnbindCtxFromAllChannels_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma); +#define dispchnUnbindCtxFromAllChannels(pGpu, pContextDma) dispchnUnbindCtxFromAllChannels_IMPL(pGpu, pContextDma) +void dispchnUnbindAllCtx_IMPL(struct OBJGPU *pGpu, struct DispChannel *pDispChannel); #ifdef __nvoc_disp_channel_h_disabled -static inline NV_STATUS dispchnBindCtx(struct DispChannel *pDispChannel, struct OBJGPU *pGpu, struct ContextDma *pContextDma) { +static inline void dispchnUnbindAllCtx(struct OBJGPU *pGpu, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("DispChannel was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_disp_channel_h_disabled -#define dispchnBindCtx(pDispChannel, pGpu, pContextDma) dispchnBindCtx_IMPL(pDispChannel, pGpu, pContextDma) -#endif //__nvoc_disp_channel_h_disabled - -NV_STATUS dispchnUnbindCtx_IMPL(struct DispChannel *pDispChannel, struct OBJGPU *pGpu, struct ContextDma *pContextDma); -#ifdef __nvoc_disp_channel_h_disabled -static inline NV_STATUS dispchnUnbindCtx(struct DispChannel *pDispChannel, struct OBJGPU *pGpu, struct ContextDma *pContextDma) { - NV_ASSERT_FAILED_PRECOMP("DispChannel was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_disp_channel_h_disabled -#define dispchnUnbindCtx(pDispChannel, pGpu, pContextDma) dispchnUnbindCtx_IMPL(pDispChannel, pGpu, pContextDma) +#define dispchnUnbindAllCtx(pGpu, pDispChannel) dispchnUnbindAllCtx_IMPL(pGpu, pDispChannel) #endif //__nvoc_disp_channel_h_disabled NV_STATUS dispchnGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDisplayChannel, struct DispChannel **ppDispChannel); diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.c b/src/nvidia/generated/g_disp_inst_mem_nvoc.c index a813df6ce..d884a48e2 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.c +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.c @@ -110,7 +110,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGetSize__ = &instmemGetSize_v03_00; } @@ -123,7 +123,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; } @@ -136,7 +136,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemIsValid__ = &instmemIsValid_v03_00; } @@ -149,7 +149,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; } @@ -162,7 +162,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; } @@ -175,7 +175,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; } @@ -188,7 +188,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; } diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.h b/src/nvidia/generated/g_disp_inst_mem_nvoc.h index 88bab8eb4..6ca7157e1 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.h +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.h @@ -310,6 +310,24 @@ static inline NV_STATUS instmemUnbindContextDma(OBJGPU *pGpu, struct DisplayInst #define instmemUnbindContextDma(pGpu, pInstMem, pContextDma, pDispChannel) instmemUnbindContextDma_IMPL(pGpu, pInstMem, pContextDma, pDispChannel) #endif //__nvoc_disp_inst_mem_h_disabled +void instmemUnbindContextDmaFromAllChannels_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma); +#ifdef __nvoc_disp_inst_mem_h_disabled +static inline void instmemUnbindContextDmaFromAllChannels(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) { + NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); +} +#else //__nvoc_disp_inst_mem_h_disabled +#define instmemUnbindContextDmaFromAllChannels(pGpu, pInstMem, pContextDma) instmemUnbindContextDmaFromAllChannels_IMPL(pGpu, pInstMem, pContextDma) +#endif //__nvoc_disp_inst_mem_h_disabled + +void instmemUnbindDispChannelContextDmas_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel); +#ifdef __nvoc_disp_inst_mem_h_disabled +static inline void instmemUnbindDispChannelContextDmas(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel) { + NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); +} +#else //__nvoc_disp_inst_mem_h_disabled +#define instmemUnbindDispChannelContextDmas(pGpu, pInstMem, pDispChannel) instmemUnbindDispChannelContextDmas_IMPL(pGpu, pInstMem, pDispChannel) +#endif //__nvoc_disp_inst_mem_h_disabled + NV_STATUS instmemReserveContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset); #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemReserveContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset) { diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index aedf5c9b2..015935023 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -875,12 +875,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [20] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetSorPwm_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x50700420u, /*paramSize=*/ sizeof(NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS), @@ -890,12 +890,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [21] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdSetSorPwm_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x50700421u, /*paramSize=*/ sizeof(NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS), @@ -905,12 +905,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetSorOpMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x50700422u, /*paramSize=*/ sizeof(NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS), @@ -920,12 +920,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdSetSorOpMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x50700423u, /*paramSize=*/ sizeof(NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS), @@ -965,12 +965,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdSetSorFlushMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x50700457u, /*paramSize=*/ sizeof(NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS), @@ -1167,23 +1167,23 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjCtrlCmdSeqProgSpeed__ = &dispobjCtrlCmdSeqProgSpeed_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispobjCtrlCmdGetSorPwm__ = &dispobjCtrlCmdGetSorPwm_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispobjCtrlCmdSetSorPwm__ = &dispobjCtrlCmdSetSorPwm_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispobjCtrlCmdGetSorOpMode__ = &dispobjCtrlCmdGetSorOpMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispobjCtrlCmdSetSorOpMode__ = &dispobjCtrlCmdSetSorOpMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispobjCtrlCmdSetSorFlushMode__ = &dispobjCtrlCmdSetSorFlushMode_IMPL; #endif @@ -3153,6 +3153,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [47] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificDispI2cReadWrite_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x7302acu, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" +#endif + }, + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3167,7 +3182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [48] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3182,7 +3197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [49] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3197,7 +3212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [50] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3212,7 +3227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [51] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3227,7 +3242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [52] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3242,7 +3257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [53] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3257,7 +3272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [54] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3272,7 +3287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [55] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3287,7 +3302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [56] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3302,7 +3317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [57] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3317,7 +3332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [58] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3332,7 +3347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [59] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3347,7 +3362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [60] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3362,7 +3377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [61] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3377,7 +3392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [62] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3392,7 +3407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [63] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3407,7 +3422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [64] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3422,7 +3437,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [65] */ + { /* [66] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetFixedModeTiming_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) + /*flags=*/ 0x202u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731172u, + /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" +#endif + }, + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3437,7 +3467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [66] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3452,7 +3482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [67] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3467,7 +3497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [68] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3482,7 +3512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [69] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3497,7 +3527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [70] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3512,7 +3542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [71] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3527,7 +3557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [72] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3542,7 +3572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [73] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3557,7 +3587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [74] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3572,7 +3602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [75] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3587,7 +3617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [76] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3602,7 +3632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [77] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3617,7 +3647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [78] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3632,7 +3662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [79] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3647,7 +3677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [80] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3662,7 +3692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [81] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3677,7 +3707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [82] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3692,7 +3722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [83] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3707,7 +3737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [84] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3722,7 +3752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [85] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3737,7 +3767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [86] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3752,22 +3782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [87] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetMSAProperties_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x73136au, - /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "dispcmnCtrlCmdDpSetMSAProperties" -#endif - }, - { /* [88] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3782,7 +3797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [89] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3797,7 +3812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [90] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3812,7 +3827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [91] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3827,7 +3842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [92] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3842,7 +3857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [93] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3857,7 +3872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [94] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3872,7 +3887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [95] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3887,7 +3902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [96] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3902,7 +3917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [97] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3917,7 +3932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [98] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3932,7 +3947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [99] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3947,7 +3962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [100] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3962,7 +3977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [101] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3977,7 +3992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [102] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,6 +4005,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" +#endif + }, + { /* [104] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetMSAPropertiesv2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731381u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2" #endif }, @@ -3997,7 +4027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 103, + /*numEntries=*/ 105, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4273,6 +4303,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__ = &dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSpecificDispI2cReadWrite__ = &dispcmnCtrlCmdSpecificDispI2cReadWrite_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdDfpGetInfo__ = &dispcmnCtrlCmdDfpGetInfo_IMPL; #endif @@ -4317,6 +4351,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpGetPadlinkMask__ = &dispcmnCtrlCmdDfpGetPadlinkMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) + pThis->__dispcmnCtrlCmdDfpGetFixedModeTiming__ = &dispcmnCtrlCmdDfpGetFixedModeTiming_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__dispcmnCtrlCmdDpAuxchCtrl__ = &dispcmnCtrlCmdDpAuxchCtrl_IMPL; #endif @@ -4390,7 +4428,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__dispcmnCtrlCmdDpSetMSAProperties__ = &dispcmnCtrlCmdDpSetMSAProperties_IMPL; + pThis->__dispcmnCtrlCmdDpSetMSAPropertiesv2__ = &dispcmnCtrlCmdDpSetMSAPropertiesv2_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index 1af355547..976126449 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -1365,6 +1365,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdmiScdcData__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificDispI2cReadWrite__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDisplayportDongleInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSetEldAudioCaps__)(struct DispCommon *, NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS *); @@ -1376,6 +1377,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDfpGetDsiModeTiming__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpConfigTwoHeadOneOr__)(struct DispCommon *, NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetPadlinkMask__)(struct DispCommon *, NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpGetFixedModeTiming__)(struct DispCommon *, NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpAuxchCtrl__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpAuxchSetSema__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpCtrl__)(struct DispCommon *, NV0073_CTRL_DP_CTRL_PARAMS *); @@ -1394,7 +1396,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDpSendACT__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetManualDisplayPort__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetCaps__)(struct DispCommon *, NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS *); - NV_STATUS (*__dispcmnCtrlCmdDpSetMSAProperties__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDpSetMSAPropertiesv2__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetStereoMSAProperties__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGenerateFakeInterrupt__)(struct DispCommon *, NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpConfigRadScratchReg__)(struct DispCommon *, NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS *); @@ -1523,6 +1525,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSpecificGetHdmiScdcData(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetHdmiScdcData_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificIsDirectmodeDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificIsDirectmodeDisplay_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificDispI2cReadWrite(pDispCommon, pParams) dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDisplayportDongleInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDisplayportDongleInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSetEldAudioCaps(pDispCommon, pEldAudioCapsParams) dispcmnCtrlCmdDfpSetEldAudioCaps_DISPATCH(pDispCommon, pEldAudioCapsParams) @@ -1534,6 +1537,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDfpGetDsiModeTiming(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDsiModeTiming_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpConfigTwoHeadOneOr(pDispCommon, pParams) dispcmnCtrlCmdDfpConfigTwoHeadOneOr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetPadlinkMask(pDispCommon, pParams) dispcmnCtrlCmdDfpGetPadlinkMask_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDfpGetFixedModeTiming(pDispCommon, pParams) dispcmnCtrlCmdDfpGetFixedModeTiming_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpAuxchCtrl(pDispCommon, pAuxchCtrlParams) dispcmnCtrlCmdDpAuxchCtrl_DISPATCH(pDispCommon, pAuxchCtrlParams) #define dispcmnCtrlCmdDpAuxchSetSema(pDispCommon, pSemaParams) dispcmnCtrlCmdDpAuxchSetSema_DISPATCH(pDispCommon, pSemaParams) #define dispcmnCtrlCmdDpCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpCtrl_DISPATCH(pDispCommon, pParams) @@ -1552,7 +1556,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDpSendACT(pDispCommon, pParams) dispcmnCtrlCmdDpSendACT_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetManualDisplayPort(pDispCommon, pParams) dispcmnCtrlCmdDpSetManualDisplayPort_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetCaps(pDispCommon, pParams) dispcmnCtrlCmdDpGetCaps_DISPATCH(pDispCommon, pParams) -#define dispcmnCtrlCmdDpSetMSAProperties(pDispCommon, pParams) dispcmnCtrlCmdDpSetMSAProperties_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDpSetMSAPropertiesv2(pDispCommon, pParams) dispcmnCtrlCmdDpSetMSAPropertiesv2_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetStereoMSAProperties(pDispCommon, pParams) dispcmnCtrlCmdDpSetStereoMSAProperties_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGenerateFakeInterrupt(pDispCommon, pParams) dispcmnCtrlCmdDpGenerateFakeInterrupt_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpConfigRadScratchReg(pDispCommon, pParams) dispcmnCtrlCmdDpConfigRadScratchReg_DISPATCH(pDispCommon, pParams) @@ -1949,6 +1953,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISP return pDispCommon->__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificDispI2cReadWrite_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificDispI2cReadWrite__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpGetInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpGetInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams) { @@ -2015,6 +2025,12 @@ static inline NV_STATUS dispcmnCtrlCmdDfpGetPadlinkMask_DISPATCH(struct DispComm return pDispCommon->__dispcmnCtrlCmdDfpGetPadlinkMask__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdDfpGetFixedModeTiming_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpGetFixedModeTiming_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpGetFixedModeTiming__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDpAuxchCtrl_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DP_AUXCH_CTRL_PARAMS *pAuxchCtrlParams); static inline NV_STATUS dispcmnCtrlCmdDpAuxchCtrl_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DP_AUXCH_CTRL_PARAMS *pAuxchCtrlParams) { @@ -2123,10 +2139,10 @@ static inline NV_STATUS dispcmnCtrlCmdDpGetCaps_DISPATCH(struct DispCommon *pDis return pDispCommon->__dispcmnCtrlCmdDpGetCaps__(pDispCommon, pParams); } -NV_STATUS dispcmnCtrlCmdDpSetMSAProperties_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *pParams); +NV_STATUS dispcmnCtrlCmdDpSetMSAPropertiesv2_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS *pParams); -static inline NV_STATUS dispcmnCtrlCmdDpSetMSAProperties_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *pParams) { - return pDispCommon->__dispcmnCtrlCmdDpSetMSAProperties__(pDispCommon, pParams); +static inline NV_STATUS dispcmnCtrlCmdDpSetMSAPropertiesv2_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDpSetMSAPropertiesv2__(pDispCommon, pParams); } NV_STATUS dispcmnCtrlCmdDpSetStereoMSAProperties_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS *pParams); diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index 79cbf1fcd..affe9030b 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -200,6 +200,18 @@ typedef struct OBJFBFLCN OBJFBFLCN; #endif /* __nvoc_class_id_OBJFBFLCN */ +struct OBJHSHUBMANAGER; + +#ifndef __NVOC_CLASS_OBJHSHUBMANAGER_TYPEDEF__ +#define __NVOC_CLASS_OBJHSHUBMANAGER_TYPEDEF__ +typedef struct OBJHSHUBMANAGER OBJHSHUBMANAGER; +#endif /* __NVOC_CLASS_OBJHSHUBMANAGER_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJHSHUBMANAGER +#define __nvoc_class_id_OBJHSHUBMANAGER 0xbb32b9 +#endif /* __nvoc_class_id_OBJHSHUBMANAGER */ + + struct OBJHSHUB; #ifndef __NVOC_CLASS_OBJHSHUB_TYPEDEF__ @@ -1208,18 +1220,6 @@ typedef struct Ioctrl Ioctrl; #endif /* __nvoc_class_id_Ioctrl */ -struct KernelNvdec; - -#ifndef __NVOC_CLASS_KernelNvdec_TYPEDEF__ -#define __NVOC_CLASS_KernelNvdec_TYPEDEF__ -typedef struct KernelNvdec KernelNvdec; -#endif /* __NVOC_CLASS_KernelNvdec_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelNvdec -#define __nvoc_class_id_KernelNvdec 0xaba9df -#endif /* __nvoc_class_id_KernelNvdec */ - - struct KernelSec2; #ifndef __NVOC_CLASS_KernelSec2_TYPEDEF__ @@ -1340,6 +1340,18 @@ typedef struct OBJGMMU OBJGMMU; #endif /* __nvoc_class_id_OBJGMMU */ +struct KernelCcu; + +#ifndef __NVOC_CLASS_KernelCcu_TYPEDEF__ +#define __NVOC_CLASS_KernelCcu_TYPEDEF__ +typedef struct KernelCcu KernelCcu; +#endif /* __NVOC_CLASS_KernelCcu_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCcu +#define __nvoc_class_id_KernelCcu 0x5d5b68 +#endif /* __nvoc_class_id_KernelCcu */ + + // // Engine tags to be used by both RM/HAL to reference specific engines. // @@ -1370,6 +1382,7 @@ typedef struct OBJGMMU OBJGMMU; #define ENG_KERNEL_PERF MKENGDESC(classId(KernelPerf), 0) #define ENG_BIF MKENGDESC(classId(OBJBIF), 0) #define ENG_KERNEL_BIF MKENGDESC(classId(KernelBif), 0) +#define ENG_HSHUBMANAGER MKENGDESC(classId(OBJHSHUBMANAGER)), 0) #define ENG_SF MKENGDESC(classId(OBJSF), 0) #define ENG_GPIO MKENGDESC(classId(OBJGPIO), 0) #define ENG_CLK MKENGDESC(classId(ClockManager), 0) @@ -1425,7 +1438,6 @@ typedef struct OBJGMMU OBJGMMU; #define ENG_KERNEL_FSP MKENGDESC(classId(KernelFsp), 0) #define ENG_OFA MKENGDESC(classId(OBJOFA), 0) #define ENG_KERNEL_GSP MKENGDESC(classId(KernelGsp), 0) -#define ENG_KERNEL_NVDEC MKENGDESC(classId(KernelNvdec), 0) #define ENG_KERNEL_SEC2 MKENGDESC(classId(KernelSec2), 0) #define ENG_DISPMACRO MKENGDESC(classId(OBJDISPMACRO), 0) #define ENG_NNE MKENGDESC(classId(OBJNNE), 0) @@ -1436,6 +1448,7 @@ typedef struct OBJGMMU OBJGMMU; #define ENG_KERNEL_NVLINK MKENGDESC(classId(KernelNvlink), 0) #define ENG_GMMU MKENGDESC(classId(OBJGMMU), 0) #define ENG_KERNEL_GMMU MKENGDESC(classId(KernelGmmu), 0) +#define ENG_KERNEL_CCU MKENGDESC(classId(KernelCcu), 0) // Indexed CE engine tag reference #define ENG_CE(x) MKENGDESC(classId(OBJCE), x) @@ -1451,7 +1464,7 @@ typedef struct OBJGMMU OBJGMMU; // Indexed BSP/NVDEC Engine Tag Reference #define ENG_NVDEC(x) MKENGDESC(classId(OBJBSP), x) -#define ENG_NVDEC__SIZE_1 5 +#define ENG_NVDEC__SIZE_1 8 #define IS_NVDEC(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(OBJBSP)) #define GET_NVDEC_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) @@ -1463,7 +1476,7 @@ typedef struct OBJGMMU OBJGMMU; // Indexed NVJPEG Engine Tag Reference #define ENG_NVJPEG(x) MKENGDESC(classId(OBJNVJPG), x) -#define ENG_NVJPEG__SIZE_1 1 +#define ENG_NVJPEG__SIZE_1 8 #define IS_NVJPEG(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(OBJNVJPG)) #define GET_NVJPEG_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) diff --git a/src/nvidia/generated/g_event_nvoc.c b/src/nvidia/generated/g_event_nvoc.c index 8d94c5b24..570e4f2b8 100644 --- a/src/nvidia/generated/g_event_nvoc.c +++ b/src/nvidia/generated/g_event_nvoc.c @@ -473,6 +473,13 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_INotifier = { }, }; +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// inotifyGetNotificationListPtr +// inotifySetNotificationShare +// inotifyGetNotificationShare +// inotifyUnregisterEvent +// inotifyGetOrAllocNotifShare const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier = { /*classInfo=*/ { @@ -575,6 +582,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_Notifier = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index d87d5d4b9..719979936 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -101,11 +101,11 @@ static void __nvoc_init_funcTable_OBJFBSR_1(OBJFBSR *pThis, RmHalspecOwner *pRmh PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- fbsrBegin - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__fbsrBegin__ = &fbsrBegin_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__fbsrBegin__ = &fbsrBegin_GM107; } @@ -114,11 +114,11 @@ static void __nvoc_init_funcTable_OBJFBSR_1(OBJFBSR *pThis, RmHalspecOwner *pRmh } // Hal function -- fbsrEnd - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__fbsrEnd__ = &fbsrEnd_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__fbsrEnd__ = &fbsrEnd_GM107; } diff --git a/src/nvidia/generated/g_gpu_class_list.c b/src/nvidia/generated/g_gpu_class_list.c index 945a03ff2..c8736a795 100644 --- a/src/nvidia/generated/g_gpu_class_list.c +++ b/src/nvidia/generated/g_gpu_class_list.c @@ -707,3 +707,295 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses) } + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) +{ + static const CLASSDESCRIPTOR halAD102ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { ADA_A, ENG_GR(0) }, + { ADA_COMPUTE_A, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_DMA_COPY_B, ENG_CE(0) }, + { AMPERE_DMA_COPY_B, ENG_CE(1) }, + { AMPERE_DMA_COPY_B, ENG_CE(2) }, + { AMPERE_DMA_COPY_B, ENG_CE(3) }, + { AMPERE_DMA_COPY_B, ENG_CE(4) }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_DISP_SW, ENG_SW }, + { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, + { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, + { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, + { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, + { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, + { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVC9FA_VIDEO_OFA, ENG_OFA }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASS_DESCS); + + *pNumClasses = HALAD102_NUM_CLASS_DESCS; + return halAD102ClassDescriptorList; +} + + + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) +{ + static const CLASSDESCRIPTOR halAD103ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { ADA_A, ENG_GR(0) }, + { ADA_COMPUTE_A, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_DMA_COPY_B, ENG_CE(0) }, + { AMPERE_DMA_COPY_B, ENG_CE(1) }, + { AMPERE_DMA_COPY_B, ENG_CE(2) }, + { AMPERE_DMA_COPY_B, ENG_CE(3) }, + { AMPERE_DMA_COPY_B, ENG_CE(4) }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_DISP_SW, ENG_SW }, + { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, + { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, + { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, + { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, + { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, + { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVC9FA_VIDEO_OFA, ENG_OFA }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASS_DESCS); + + *pNumClasses = HALAD103_NUM_CLASS_DESCS; + return halAD103ClassDescriptorList; +} + + + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) +{ + static const CLASSDESCRIPTOR halAD104ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { ADA_A, ENG_GR(0) }, + { ADA_COMPUTE_A, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_DMA_COPY_B, ENG_CE(0) }, + { AMPERE_DMA_COPY_B, ENG_CE(1) }, + { AMPERE_DMA_COPY_B, ENG_CE(2) }, + { AMPERE_DMA_COPY_B, ENG_CE(3) }, + { AMPERE_DMA_COPY_B, ENG_CE(4) }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_DISP_SW, ENG_SW }, + { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, + { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, + { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, + { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, + { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, + { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVC9FA_VIDEO_OFA, ENG_OFA }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASS_DESCS); + + *pNumClasses = HALAD104_NUM_CLASS_DESCS; + return halAD104ClassDescriptorList; +} + + + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses) +{ + static const CLASSDESCRIPTOR halGH100ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { HOPPER_A, ENG_GR(0) }, + { HOPPER_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { HOPPER_COMPUTE_A, ENG_GR(0) }, + { HOPPER_COMPUTE_A, ENG_GR(1) }, + { HOPPER_COMPUTE_A, ENG_GR(2) }, + { HOPPER_COMPUTE_A, ENG_GR(3) }, + { HOPPER_COMPUTE_A, ENG_GR(4) }, + { HOPPER_COMPUTE_A, ENG_GR(5) }, + { HOPPER_COMPUTE_A, ENG_GR(6) }, + { HOPPER_COMPUTE_A, ENG_GR(7) }, + { HOPPER_DMA_COPY_A, ENG_CE(0) }, + { HOPPER_DMA_COPY_A, ENG_CE(1) }, + { HOPPER_DMA_COPY_A, ENG_CE(2) }, + { HOPPER_DMA_COPY_A, ENG_CE(3) }, + { HOPPER_DMA_COPY_A, ENG_CE(4) }, + { HOPPER_DMA_COPY_A, ENG_CE(5) }, + { HOPPER_DMA_COPY_A, ENG_CE(6) }, + { HOPPER_DMA_COPY_A, ENG_CE(7) }, + { HOPPER_DMA_COPY_A, ENG_CE(8) }, + { HOPPER_DMA_COPY_A, ENG_CE(9) }, + { HOPPER_USERMODE_A, ENG_GPU }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(4) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(5) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(6) }, + { NVB8B0_VIDEO_DECODER, ENG_NVDEC(7) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(4) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(5) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) }, + { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) }, + { NVB8FA_VIDEO_OFA, ENG_OFA }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALGH100_NUM_CLASS_DESCS (sizeof(halGH100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASS_DESCS); + + *pNumClasses = HALGH100_NUM_CLASS_DESCS; + return halGH100ClassDescriptorList; +} + + diff --git a/src/nvidia/generated/g_gpu_halspec_nvoc.c b/src/nvidia/generated/g_gpu_halspec_nvoc.c index fd4826455..90b0c909b 100644 --- a/src/nvidia/generated/g_gpu_halspec_nvoc.c +++ b/src/nvidia/generated/g_gpu_halspec_nvoc.c @@ -36,6 +36,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_RmHalspecOwner = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index ed97fc351..f2cae81b3 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -143,7 +143,7 @@ typedef struct _def_gpumgr_save_vbios_state // because there were compilation dependencies that prevented us // from adding gpu/ce/ce.h // -#define NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX 18 +#define NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX 32 #define NV_CE_GRCE_CONFIG__SIZE_1 2 #define NV_CE_MAX_HSHUBS 5 // Same as GPU_MAX_HSHUBS @@ -229,6 +229,8 @@ typedef struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY NvU64 domainBusDevice; // Flag checking whether we have restored from static info since boot NvBool bVgpuRestoredFromStaticInfo; + // MIG state last registered for the GPU this struct was saved for. + NvBool bMIGEnabled; // Saved instance information. May or may not have any valid entries. GPUMGR_SAVE_GPU_INSTANCE saveGI[GPUMGR_MAX_GPU_INSTANCES]; } GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY; @@ -349,6 +351,10 @@ void gpumgrAddSystemMIGInstanceTopo_IMPL(NvU64 domainBusDevice); #define gpumgrAddSystemMIGInstanceTopo(domainBusDevice) gpumgrAddSystemMIGInstanceTopo_IMPL(domainBusDevice) NvBool gpumgrGetSystemMIGInstanceTopo_IMPL(NvU64 domainBusDevice, struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY **ppTopoParams); #define gpumgrGetSystemMIGInstanceTopo(domainBusDevice, ppTopoParams) gpumgrGetSystemMIGInstanceTopo_IMPL(domainBusDevice, ppTopoParams) +NvBool gpumgrIsSystemMIGEnabled_IMPL(NvU64 domainBusDevice); +#define gpumgrIsSystemMIGEnabled(domainBusDevice) gpumgrIsSystemMIGEnabled_IMPL(domainBusDevice) +void gpumgrSetSystemMIGEnabled_IMPL(NvU64 domainBusDevice, NvBool bMIGEnabled); +#define gpumgrSetSystemMIGEnabled(domainBusDevice, bMIGEnabled) gpumgrSetSystemMIGEnabled_IMPL(domainBusDevice, bMIGEnabled) void gpumgrUnregisterRmCapsForMIGGI_IMPL(NvU64 gpuDomainBusDevice); #define gpumgrUnregisterRmCapsForMIGGI(gpuDomainBusDevice) gpumgrUnregisterRmCapsForMIGGI_IMPL(gpuDomainBusDevice) void gpumgrUpdateBoardId_IMPL(struct OBJGPU *arg0); diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index c54acebbb..23f67babe 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -114,6 +114,26 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_IGPU + if (0) + { + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_IGPU, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_ATS_SUPPORTED + if (0) + { + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_ATS_SUPPORTED, ((NvBool)(0 != 0))); + } + // NVOC Property Hal field -- PDB_PROP_GPU_IS_UEFI if (0) { @@ -145,7 +165,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_MIG_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 == 0))); } @@ -156,7 +176,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 == 0))); } @@ -166,6 +186,39 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_IS_COT_ENABLED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 != 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); + } + pThis->boardId = ~0; pThis->deviceInstance = 32; @@ -220,7 +273,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // Hal field -- bInstLoc47bitPaWar - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bInstLoc47bitPaWar = ((NvBool)(0 == 0)); } @@ -241,7 +294,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // Hal field -- bClientRmAllocatedCtxBuffer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 == 0)); } @@ -252,8 +305,9 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // Hal field -- bVidmemPreservationBrokenBug3172217 - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 == 0)); } // default else @@ -274,7 +328,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bIsGeforce = ((NvBool)(0 == 0)); // Hal field -- bComputePolicyTimesliceSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 == 0)); } @@ -325,6 +379,134 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- gpuWriteBusConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; + } + else if (0) + { + } + else if (0) + { + } + + // Hal function -- gpuReadBusConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; + } + else if (0) + { + } + else if (0) + { + } + + // Hal function -- gpuReadBusConfigRegEx + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; + } + else if (0) + { + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_46f6a7; + } + + // Hal function -- gpuReadFunctionConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; + } + + // Hal function -- gpuWriteFunctionConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; + } + + // Hal function -- gpuWriteFunctionConfigRegEx + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; + } + + // Hal function -- gpuGetIdInfo + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; + } + else if (0) + { + } + else if (0) + { + } + else if (0) + { + } + else if (0) + { + } + else if (0) + { + } + + // Hal function -- gpuHandleSanityCheckRegReadError + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; + } + else if (0) + { + } + // Hal function -- gpuGetChildrenPresent if (0) { @@ -376,8 +558,9 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; } else if (0) { @@ -388,6 +571,10 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { else if (0) { } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; + } else if (0) { } @@ -474,12 +661,20 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { else if (0) { } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; + } else if (0) { } else if (0) { } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; + } else if (0) { } @@ -501,6 +696,28 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { else if (0) { } + + // Hal function -- gpuGetPhysAddrWidth + if (0) + { + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; + } + else if (0) + { + } else if (0) { } @@ -513,7 +730,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } @@ -531,7 +748,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } @@ -543,7 +760,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_PHYSICAL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } @@ -553,7 +770,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { // Hal function -- gpuConstructDeviceInfoTable if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; } @@ -566,7 +783,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { else if (0) { #if 0 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_GA100; } @@ -579,17 +796,29 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuGetFlaVasSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46; } + + // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; + } + // default + else + { + pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 41e5e01d6..009543ab8 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -80,6 +80,7 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "core/system.h" #include "core/info_block.h" #include "core/hal.h" +#include "nvoc/utility.h" #include "gpu/mem_mgr/mem_desc.h" #include "gpu/gpu_resource_desc.h" #include "diagnostics/traceable.h" @@ -828,12 +829,22 @@ struct OBJGPU { struct RmHalspecOwner *__nvoc_pbase_RmHalspecOwner; struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; struct OBJGPU *__nvoc_pbase_OBJGPU; + NV_STATUS (*__gpuWriteBusConfigReg__)(struct OBJGPU *, NvU32, NvU32); + NV_STATUS (*__gpuReadBusConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); + NV_STATUS (*__gpuReadBusConfigRegEx__)(struct OBJGPU *, NvU32, NvU32 *, THREAD_STATE_NODE *); + NV_STATUS (*__gpuReadFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32 *); + NV_STATUS (*__gpuWriteFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32); + NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU *, NvU32, NvU32, NvU32, THREAD_STATE_NODE *); + void (*__gpuGetIdInfo__)(struct OBJGPU *); + void (*__gpuHandleSanityCheckRegReadError__)(struct OBJGPU *, NvU32, NvU32); const GPUCHILDPRESENT *(*__gpuGetChildrenPresent__)(struct OBJGPU *, NvU32 *); const CLASSDESCRIPTOR *(*__gpuGetClassDescriptorList__)(struct OBJGPU *, NvU32 *); + NvU32 (*__gpuGetPhysAddrWidth__)(struct OBJGPU *, NV_ADDRESS_SPACE); NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); + NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); NvBool PDB_PROP_GPU_IN_STANDBY; NvBool PDB_PROP_GPU_IN_HIBERNATE; NvBool PDB_PROP_GPU_IN_PM_CODEPATH; @@ -858,6 +869,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IN_TIMEOUT_RECOVERY; NvBool PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT; NvBool PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY; + NvBool PDB_PROP_GPU_TEGRA_SOC_IGPU; NvBool PDB_PROP_GPU_ATS_SUPPORTED; NvBool PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING; NvBool PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE; @@ -866,6 +878,8 @@ struct OBJGPU { NvBool PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE; NvBool PDB_PROP_GPU_MIG_SUPPORTED; NvBool PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED; + NvBool PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED; + NvBool PDB_PROP_GPU_IS_COT_ENABLED; NvBool PDB_PROP_GPU_SWRL_GRANULAR_LOCKING; NvBool PDB_PROP_GPU_IN_SLI_LINK_CODEPATH; NvBool PDB_PROP_GPU_IS_PLX_PRESENT; @@ -889,6 +903,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_ACCOUNTING_ON; NvBool PDB_PROP_GPU_INACCESSIBLE; NvBool PDB_PROP_GPU_NVLINK_SYSMEM; + NvBool PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK; NvBool PDB_PROP_GPU_C2C_SYSMEM; NvBool PDB_PROP_GPU_IN_TCC_MODE; NvBool PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE; @@ -966,7 +981,6 @@ struct OBJGPU { struct OBJTMR *pTmr; struct KernelBus *pKernelBus; struct KernelGmmu *pKernelGmmu; - struct KernelNvdec *pKernelNvdec; struct KernelSec2 *pKernelSec2; struct KernelGsp *pKernelGsp; struct VirtMemAllocator *pDma; @@ -984,6 +998,8 @@ struct OBJGPU { struct KernelNvlink *pKernelNvlink; struct OBJGPUMON *pGpuMon; struct OBJSWENG *pSwEng; + struct KernelFsp *pKernelFsp; + struct KernelCcu *pKernelCcu; HWBC_LIST *pHWBCList; GPUCLDATA gpuClData; _GPU_ENGINE_DB engineDB; @@ -994,9 +1010,9 @@ struct OBJGPU { RmCtrlDeferredCmd pRmCtrlDeferredCmd[2]; ACPI_DATA acpi; NvU32 activeFifoEventMthdNotifiers; - struct Falcon *constructedFalcons[60]; + struct Falcon *constructedFalcons[70]; NvU32 numConstructedFalcons; - struct GenericKernelFalcon *genericKernelFalcons[60]; + struct GenericKernelFalcon *genericKernelFalcons[70]; NvU32 numGenericKernelFalcons; NvU8 *pUserRegisterAccessMap; NvU8 *pUnrestrictedRegisterAccessMap; @@ -1038,6 +1054,7 @@ struct OBJGPU { NvBool bIsRtlsim; NvBool bIsPassthru; NvBool bIsVirtualWithSriov; + NvBool bCpuFirmwareHandlesFbEccInterruptEnabled; NvBool bStateLoading; NvBool bStateUnloading; NvBool bStateLoaded; @@ -1118,10 +1135,12 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_PM_RESUME_CODEPATH #define PDB_PROP_GPU_IN_STANDBY_BASE_CAST #define PDB_PROP_GPU_IN_STANDBY_BASE_NAME PDB_PROP_GPU_IN_STANDBY -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED +#define PDB_PROP_GPU_IS_COT_ENABLED_BASE_CAST +#define PDB_PROP_GPU_IS_COT_ENABLED_BASE_NAME PDB_PROP_GPU_IS_COT_ENABLED #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_CAST #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_NAME PDB_PROP_GPU_COHERENT_CPU_MAPPING +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_CAST @@ -1138,6 +1157,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_HYBRID_MGPU_BASE_NAME PDB_PROP_GPU_HYBRID_MGPU #define PDB_PROP_GPU_3D_CONTROLLER_BASE_CAST #define PDB_PROP_GPU_3D_CONTROLLER_BASE_NAME PDB_PROP_GPU_3D_CONTROLLER +#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST @@ -1222,6 +1243,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_ZERO_FB_BASE_NAME PDB_PROP_GPU_ZERO_FB #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_NAME PDB_PROP_GPU_SWRL_GRANULAR_LOCKING +#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST +#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK +#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST +#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED #define PDB_PROP_GPU_EMULATION_BASE_CAST @@ -1247,10 +1272,28 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32 #define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) \ __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) +#define gpuWriteBusConfigReg(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) +#define gpuWriteBusConfigReg_HAL(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) +#define gpuReadBusConfigReg(pGpu, index, data) gpuReadBusConfigReg_DISPATCH(pGpu, index, data) +#define gpuReadBusConfigReg_HAL(pGpu, index, data) gpuReadBusConfigReg_DISPATCH(pGpu, index, data) +#define gpuReadBusConfigRegEx(pGpu, index, data, pThreadState) gpuReadBusConfigRegEx_DISPATCH(pGpu, index, data, pThreadState) +#define gpuReadBusConfigRegEx_HAL(pGpu, index, data, pThreadState) gpuReadBusConfigRegEx_DISPATCH(pGpu, index, data, pThreadState) +#define gpuReadFunctionConfigReg(pGpu, function, reg, data) gpuReadFunctionConfigReg_DISPATCH(pGpu, function, reg, data) +#define gpuReadFunctionConfigReg_HAL(pGpu, function, reg, data) gpuReadFunctionConfigReg_DISPATCH(pGpu, function, reg, data) +#define gpuWriteFunctionConfigReg(pGpu, function, reg, data) gpuWriteFunctionConfigReg_DISPATCH(pGpu, function, reg, data) +#define gpuWriteFunctionConfigReg_HAL(pGpu, function, reg, data) gpuWriteFunctionConfigReg_DISPATCH(pGpu, function, reg, data) +#define gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState) +#define gpuWriteFunctionConfigRegEx_HAL(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState) +#define gpuGetIdInfo(pGpu) gpuGetIdInfo_DISPATCH(pGpu) +#define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu) +#define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) +#define gpuHandleSanityCheckRegReadError_HAL(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) #define gpuGetChildrenPresent(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetChildrenPresent_HAL(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetClassDescriptorList(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) #define gpuGetClassDescriptorList_HAL(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) +#define gpuGetPhysAddrWidth(pGpu, arg0) gpuGetPhysAddrWidth_DISPATCH(pGpu, arg0) +#define gpuGetPhysAddrWidth_HAL(pGpu, arg0) gpuGetPhysAddrWidth_DISPATCH(pGpu, arg0) #define gpuFuseSupportsDisplay(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) @@ -1259,6 +1302,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32 #define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) +#define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) +#define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -1667,84 +1712,6 @@ static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) { #define gpuDestroyOverrides_HAL(pGpu) gpuDestroyOverrides(pGpu) -NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuWriteBusConfigReg(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuWriteBusConfigReg(pGpu, index, value) gpuWriteBusConfigReg_GM107(pGpu, index, value) -#endif //__nvoc_gpu_h_disabled - -#define gpuWriteBusConfigReg_HAL(pGpu, index, value) gpuWriteBusConfigReg(pGpu, index, value) - -NV_STATUS gpuReadBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuReadBusConfigReg(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuReadBusConfigReg(pGpu, index, data) gpuReadBusConfigReg_GM107(pGpu, index, data) -#endif //__nvoc_gpu_h_disabled - -#define gpuReadBusConfigReg_HAL(pGpu, index, data) gpuReadBusConfigReg(pGpu, index, data) - -NV_STATUS gpuReadBusConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuReadBusConfigRegEx(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuReadBusConfigRegEx(pGpu, index, data, pThreadState) gpuReadBusConfigRegEx_GM107(pGpu, index, data, pThreadState) -#endif //__nvoc_gpu_h_disabled - -#define gpuReadBusConfigRegEx_HAL(pGpu, index, data, pThreadState) gpuReadBusConfigRegEx(pGpu, index, data, pThreadState) - -NV_STATUS gpuReadFunctionConfigReg_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 *data); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuReadFunctionConfigReg(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 *data) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuReadFunctionConfigReg(pGpu, function, reg, data) gpuReadFunctionConfigReg_GM107(pGpu, function, reg, data) -#endif //__nvoc_gpu_h_disabled - -#define gpuReadFunctionConfigReg_HAL(pGpu, function, reg, data) gpuReadFunctionConfigReg(pGpu, function, reg, data) - -NV_STATUS gpuWriteFunctionConfigReg_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuWriteFunctionConfigReg(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuWriteFunctionConfigReg(pGpu, function, reg, data) gpuWriteFunctionConfigReg_GM107(pGpu, function, reg, data) -#endif //__nvoc_gpu_h_disabled - -#define gpuWriteFunctionConfigReg_HAL(pGpu, function, reg, data) gpuWriteFunctionConfigReg(pGpu, function, reg, data) - -NV_STATUS gpuWriteFunctionConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data, THREAD_STATE_NODE *pThreadState); - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuWriteFunctionConfigRegEx(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data, THREAD_STATE_NODE *pThreadState) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_GM107(pGpu, function, reg, data, pThreadState) -#endif //__nvoc_gpu_h_disabled - -#define gpuWriteFunctionConfigRegEx_HAL(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) - NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3); #ifdef __nvoc_gpu_h_disabled @@ -1758,18 +1725,6 @@ static inline NV_STATUS gpuSetPower(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, #define gpuSetPower_HAL(pGpu, arg1, arg2, arg3) gpuSetPower(pGpu, arg1, arg2, arg3) -void gpuGetIdInfo_GM107(struct OBJGPU *pGpu); - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuGetIdInfo(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuGetIdInfo(pGpu) gpuGetIdInfo_GM107(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo(pGpu) - static inline void gpuUpdateIdInfo_b3696a(struct OBJGPU *pGpu) { return; } @@ -1879,18 +1834,6 @@ static inline NV_STATUS gpuGetRegBaseOffset(struct OBJGPU *pGpu, NvU32 arg0, NvU #define gpuGetRegBaseOffset_HAL(pGpu, arg0, arg1) gpuGetRegBaseOffset(pGpu, arg0, arg1) -void gpuHandleSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuHandleSanityCheckRegReadError(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_GM107(pGpu, addr, value) -#endif //__nvoc_gpu_h_disabled - -#define gpuHandleSanityCheckRegReadError_HAL(pGpu, addr, value) gpuHandleSanityCheckRegReadError(pGpu, addr, value) - static inline void gpuGetSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString) { return; } @@ -1959,19 +1902,6 @@ static inline const GPUCHILDORDER *gpuGetChildrenOrder(struct OBJGPU *pGpu, NvU3 #define gpuGetChildrenOrder_HAL(pGpu, pNumEntries) gpuGetChildrenOrder(pGpu, pNumEntries) -NvU32 gpuGetPhysAddrWidth_TU102(struct OBJGPU *pGpu, NV_ADDRESS_SPACE arg0); - -#ifdef __nvoc_gpu_h_disabled -static inline NvU32 gpuGetPhysAddrWidth(struct OBJGPU *pGpu, NV_ADDRESS_SPACE arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetPhysAddrWidth(pGpu, arg0) gpuGetPhysAddrWidth_TU102(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetPhysAddrWidth_HAL(pGpu, arg0) gpuGetPhysAddrWidth(pGpu, arg0) - NV_STATUS gpuInitSriov_FWCLIENT(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -2162,21 +2092,6 @@ static inline NvU32 gpuGetLitterValues(struct OBJGPU *pGpu, NvU32 index) { #define gpuGetLitterValues_HAL(pGpu, index) gpuGetLitterValues(pGpu, index) -static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -#ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; -} -#else //__nvoc_gpu_h_disabled -#define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_491d52(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) - NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -2233,6 +2148,94 @@ static inline NV_STATUS gpuSetVFBarSizes(struct OBJGPU *pGpu, NV0080_CTRL_GPU_SE #define gpuSetVFBarSizes_HAL(pGpu, arg0) gpuSetVFBarSizes(pGpu, arg0) +NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); + +NV_STATUS gpuWriteBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 value); + +static inline NV_STATUS gpuWriteBusConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS gpuWriteBusConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { + return pGpu->__gpuWriteBusConfigReg__(pGpu, index, value); +} + +NV_STATUS gpuReadBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data); + +NV_STATUS gpuReadBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data); + +static inline NV_STATUS gpuReadBusConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS gpuReadBusConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { + return pGpu->__gpuReadBusConfigReg__(pGpu, index, data); +} + +NV_STATUS gpuReadBusConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState); + +static inline NV_STATUS gpuReadBusConfigRegEx_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS gpuReadBusConfigRegEx_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { + return pGpu->__gpuReadBusConfigRegEx__(pGpu, index, data, pThreadState); +} + +NV_STATUS gpuReadFunctionConfigReg_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 *data); + +static inline NV_STATUS gpuReadFunctionConfigReg_5baef9(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 *data) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuReadFunctionConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 *data) { + return pGpu->__gpuReadFunctionConfigReg__(pGpu, function, reg, data); +} + +NV_STATUS gpuWriteFunctionConfigReg_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data); + +static inline NV_STATUS gpuWriteFunctionConfigReg_5baef9(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuWriteFunctionConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data) { + return pGpu->__gpuWriteFunctionConfigReg__(pGpu, function, reg, data); +} + +NV_STATUS gpuWriteFunctionConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data, THREAD_STATE_NODE *pThreadState); + +static inline NV_STATUS gpuWriteFunctionConfigRegEx_5baef9(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data, THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuWriteFunctionConfigRegEx_DISPATCH(struct OBJGPU *pGpu, NvU32 function, NvU32 reg, NvU32 data, THREAD_STATE_NODE *pThreadState) { + return pGpu->__gpuWriteFunctionConfigRegEx__(pGpu, function, reg, data, pThreadState); +} + +void gpuGetIdInfo_GM107(struct OBJGPU *pGpu); + +void gpuGetIdInfo_GH100(struct OBJGPU *pGpu); + +static inline void gpuGetIdInfo_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuGetIdInfo_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuGetIdInfo__(pGpu); +} + +void gpuHandleSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); + +void gpuHandleSanityCheckRegReadError_GH100(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); + +static inline void gpuHandleSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { + return; +} + +static inline void gpuHandleSanityCheckRegReadError_DISPATCH(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { + pGpu->__gpuHandleSanityCheckRegReadError__(pGpu, addr, value); +} + const GPUCHILDPRESENT *gpuGetChildrenPresent_TU102(struct OBJGPU *pGpu, NvU32 *pNumEntries); const GPUCHILDPRESENT *gpuGetChildrenPresent_TU104(struct OBJGPU *pGpu, NvU32 *pNumEntries); @@ -2243,6 +2246,10 @@ const GPUCHILDPRESENT *gpuGetChildrenPresent_GA100(struct OBJGPU *pGpu, NvU32 *p const GPUCHILDPRESENT *gpuGetChildrenPresent_GA102(struct OBJGPU *pGpu, NvU32 *pNumEntries); +const GPUCHILDPRESENT *gpuGetChildrenPresent_AD102(struct OBJGPU *pGpu, NvU32 *pNumEntries); + +const GPUCHILDPRESENT *gpuGetChildrenPresent_GH100(struct OBJGPU *pGpu, NvU32 *pNumEntries); + static inline const GPUCHILDPRESENT *gpuGetChildrenPresent_DISPATCH(struct OBJGPU *pGpu, NvU32 *pNumEntries) { return pGpu->__gpuGetChildrenPresent__(pGpu, pNumEntries); } @@ -2259,10 +2266,22 @@ const CLASSDESCRIPTOR *gpuGetClassDescriptorList_GA100(struct OBJGPU *pGpu, NvU3 const CLASSDESCRIPTOR *gpuGetClassDescriptorList_GA102(struct OBJGPU *pGpu, NvU32 *arg0); +const CLASSDESCRIPTOR *gpuGetClassDescriptorList_AD102(struct OBJGPU *pGpu, NvU32 *arg0); + +const CLASSDESCRIPTOR *gpuGetClassDescriptorList_GH100(struct OBJGPU *pGpu, NvU32 *arg0); + static inline const CLASSDESCRIPTOR *gpuGetClassDescriptorList_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0) { return pGpu->__gpuGetClassDescriptorList__(pGpu, arg0); } +NvU32 gpuGetPhysAddrWidth_TU102(struct OBJGPU *pGpu, NV_ADDRESS_SPACE arg0); + +NvU32 gpuGetPhysAddrWidth_GH100(struct OBJGPU *pGpu, NV_ADDRESS_SPACE arg0); + +static inline NvU32 gpuGetPhysAddrWidth_DISPATCH(struct OBJGPU *pGpu, NV_ADDRESS_SPACE arg0) { + return pGpu->__gpuGetPhysAddrWidth__(pGpu, arg0); +} + NvBool gpuFuseSupportsDisplay_GM107(struct OBJGPU *pGpu); NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); @@ -2301,6 +2320,8 @@ static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu NvU64 gpuGetFlaVasSize_GA100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); +NvU64 gpuGetFlaVasSize_GH100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); + static inline NvU64 gpuGetFlaVasSize_474d46(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization) { NV_ASSERT_OR_RETURN_PRECOMP(0, 0); } @@ -2309,6 +2330,16 @@ static inline NvU64 gpuGetFlaVasSize_DISPATCH(struct OBJGPU *pGpu, NvBool bNvswi return pGpu->__gpuGetFlaVasSize__(pGpu, bNvswitchVirtualization); } +NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsAtsSupportedWithSmcMemPartitioning__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -2542,6 +2573,10 @@ static inline NvBool gpuIsComputePolicyTimesliceSupported(struct OBJGPU *pGpu) { return pGpu->bComputePolicyTimesliceSupported; } +static inline NvBool gpuIsCpuFirmwareHandlesFbEccInterruptEnabled(struct OBJGPU *pGpu) { + return pGpu->bCpuFirmwareHandlesFbEccInterruptEnabled; +} + NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); #define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance) NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1); @@ -3514,27 +3549,6 @@ NV_STATUS gpuValidateRegOps(struct OBJGPU *, NV2080_CTRL_GPU_REG_OP *, NvU32, Nv #define NV_REG_BASE_LAST NV_REG_BASE_USERMODE ct_assert(NV_REG_BASE_LAST < NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX); -// Macros for CPU family information -#define NV_CPU_FAMILY 3:0 -#define NV_CPU_EXTENDED_FAMILY 11:4 - -// Macros for CPU model information -#define NV_CPU_MODEL 3:0 -#define NV_CPU_EXTENDED_MODEL 7:4 - -// Macros for AMD CPU information -#define NV_CPU_ID_AMD_FAMILY 0xF -#define NV_CPU_ID_AMD_EXTENDED_FAMILY 0xA -#define NV_CPU_ID_AMD_MODEL 0x0 -#define NV_CPU_ID_AMD_EXTENDED_MODEL 0x4 - -// Macros for Intel CPU information -#define NV_CPU_ID_INTEL_FAMILY 0x6 -#define NV_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 -#define NV_CPU_ID_INTEL_CORE_S_MODEL 0x7 -#define NV_CPU_ID_INTEL_CORE_P_MODEL 0xA -#define NV_CPU_ID_INTEL_EXTENDED_MODEL 0x9 - #define GPU_READ_PRI_ERROR_MASK 0xFFF00000 #define GPU_READ_PRI_ERROR_CODE 0xBAD00000 diff --git a/src/nvidia/generated/g_hal.h b/src/nvidia/generated/g_hal.h index 2671c56f5..0d8243635 100644 --- a/src/nvidia/generated/g_hal.h +++ b/src/nvidia/generated/g_hal.h @@ -118,6 +118,10 @@ typedef enum HAL_IMPL_GA107, HAL_IMPL_GA10B, HAL_IMPL_GA102F, + HAL_IMPL_AD102, + HAL_IMPL_AD103, + HAL_IMPL_AD104, + HAL_IMPL_GH100, HAL_IMPL_T001_FERMI_NOT_EXIST, HAL_IMPL_T124, HAL_IMPL_T132, @@ -147,7 +151,11 @@ typedef enum { HAL_IMPL_GA103, "GA103" }, \ { HAL_IMPL_GA104, "GA104" }, \ { HAL_IMPL_GA106, "GA106" }, \ - { HAL_IMPL_GA107, "GA107" } + { HAL_IMPL_GA107, "GA107" }, \ + { HAL_IMPL_AD102, "AD102" }, \ + { HAL_IMPL_AD103, "AD103" }, \ + { HAL_IMPL_AD104, "AD104" }, \ + { HAL_IMPL_GH100, "GH100" } #endif // _G_RMCFG_HAL_H_ diff --git a/src/nvidia/generated/g_hal_archimpl.h b/src/nvidia/generated/g_hal_archimpl.h index 5c6d8f38b..be9fd50a8 100644 --- a/src/nvidia/generated/g_hal_archimpl.h +++ b/src/nvidia/generated/g_hal_archimpl.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_archimpl.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _G_RMCFG_HAL_ARCHIMPL_H_ @@ -77,6 +77,10 @@ const struct ChipID { NV_PMC_BOOT_0_ARCHITECTURE_GA100, NV_PMC_BOOT_0_IMPLEMENTATION_7, 0x0 } , // GA107 { 0x0, 0x0, 0x0 } , // GA10B (disabled) { 0x0, 0x0, 0x0 } , // GA102F (disabled) + { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_2, 0x0 } , // AD102 + { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_3, 0x0 } , // AD103 + { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_4, 0x0 } , // AD104 + { NV_PMC_BOOT_0_ARCHITECTURE_GH100, NV_PMC_BOOT_0_IMPLEMENTATION_0, 0x0 } , // GH100 { 0x0, 0x0, 0x0 } , // T001_FERMI_NOT_EXIST (disabled) { 0x0, 0x0, 0x0 } , // T124 (disabled) { 0x0, 0x0, 0x0 } , // T132 (disabled) diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.h b/src/nvidia/generated/g_hal_mgr_nvoc.h index 30f2cf43b..8485dce72 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.h +++ b/src/nvidia/generated/g_hal_mgr_nvoc.h @@ -63,7 +63,7 @@ struct OBJHALMGR { struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct OBJHALMGR *__nvoc_pbase_OBJHALMGR; - struct OBJHAL *pHalList[60]; + struct OBJHAL *pHalList[64]; }; #ifndef __NVOC_CLASS_OBJHALMGR_TYPEDEF__ diff --git a/src/nvidia/generated/g_hal_private.h b/src/nvidia/generated/g_hal_private.h index 2ba33973b..9d7df66e0 100644 --- a/src/nvidia/generated/g_hal_private.h +++ b/src/nvidia/generated/g_hal_private.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_private.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // // @@ -26,6 +26,8 @@ #if defined(RMCFG_HAL_SETUP_ALL) # define RMCFG_HAL_SETUP_TU10X 1 # define RMCFG_HAL_SETUP_GA10X 1 +# define RMCFG_HAL_SETUP_AD10X 1 +# define RMCFG_HAL_SETUP_GH10X 1 #endif // RMCFG_HAL_SETUP_ALL // @@ -49,6 +51,16 @@ # define RMCFG_HAL_SETUP_GA107 1 #endif // GA10X +#if defined(RMCFG_HAL_SETUP_AD10X) +# define RMCFG_HAL_SETUP_AD102 1 +# define RMCFG_HAL_SETUP_AD103 1 +# define RMCFG_HAL_SETUP_AD104 1 +#endif // AD10X + +#if defined(RMCFG_HAL_SETUP_GH10X) +# define RMCFG_HAL_SETUP_GH100 1 +#endif // GH10X + #endif // RMCFG_ENGINE_SETUP // pull in private headers for each engine @@ -228,6 +240,66 @@ NV_STATUS registerHalModule_GA107(void) #endif // GA10X or GA107 +#if defined(RMCFG_HAL_SETUP_AD102) + +static const HAL_IFACE_SETUP halIface_AD102 = { + + rpcHalIfacesSetup_AD102, + +}; + +NV_STATUS registerHalModule_AD102(void) +{ + return registerHalModule(HAL_IMPL_AD102, &halIface_AD102); +} + +#endif // AD10X or AD102 + +#if defined(RMCFG_HAL_SETUP_AD103) + +static const HAL_IFACE_SETUP halIface_AD103 = { + + rpcHalIfacesSetup_AD103, + +}; + +NV_STATUS registerHalModule_AD103(void) +{ + return registerHalModule(HAL_IMPL_AD103, &halIface_AD103); +} + +#endif // AD10X or AD103 + +#if defined(RMCFG_HAL_SETUP_AD104) + +static const HAL_IFACE_SETUP halIface_AD104 = { + + rpcHalIfacesSetup_AD104, + +}; + +NV_STATUS registerHalModule_AD104(void) +{ + return registerHalModule(HAL_IMPL_AD104, &halIface_AD104); +} + +#endif // AD10X or AD104 + +#if defined(RMCFG_HAL_SETUP_GH100) + +static const HAL_IFACE_SETUP halIface_GH100 = { + + rpcHalIfacesSetup_GH100, + +}; + +NV_STATUS registerHalModule_GH100(void) +{ + return registerHalModule(HAL_IMPL_GH100, &halIface_GH100); +} + +#endif // GH10X or GH100 + #endif // _G_RMCFG_HAL_PRIVATE_H_ diff --git a/src/nvidia/generated/g_hal_register.h b/src/nvidia/generated/g_hal_register.h index b3b4d49c0..d48b6eec6 100644 --- a/src/nvidia/generated/g_hal_register.h +++ b/src/nvidia/generated/g_hal_register.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_register.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _G_RMCFG_HAL_REGISTER_H_ @@ -87,6 +87,42 @@ static NV_STATUS NV_INLINE REGISTER_GA10X_HALS(void) return NV_OK; } +NV_STATUS registerHalModule_AD102(void); +NV_STATUS registerHalModule_AD103(void); +NV_STATUS registerHalModule_AD104(void); + +static NV_STATUS NV_INLINE REGISTER_AD10X_HALS(void) +{ + NV_STATUS rmStatus; + + rmStatus = registerHalModule_AD102(); + if (rmStatus != NV_OK) + return rmStatus; + + rmStatus = registerHalModule_AD103(); + if (rmStatus != NV_OK) + return rmStatus; + + rmStatus = registerHalModule_AD104(); + if (rmStatus != NV_OK) + return rmStatus; + + return NV_OK; +} + +NV_STATUS registerHalModule_GH100(void); + +static NV_STATUS NV_INLINE REGISTER_GH10X_HALS(void) +{ + NV_STATUS rmStatus; + + rmStatus = registerHalModule_GH100(); + if (rmStatus != NV_OK) + return rmStatus; + + return NV_OK; +} + // // This routine can be used by platform dependent code to // enable all HAL modules. @@ -107,6 +143,18 @@ static NV_STATUS NV_INLINE REGISTER_ALL_HALS(void) return rmStatus; } + rmStatus = REGISTER_AD10X_HALS(); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + rmStatus = REGISTER_GH10X_HALS(); + if (rmStatus != NV_OK) + { + return rmStatus; + } + return NV_OK; } diff --git a/src/nvidia/generated/g_hal_stubs.h b/src/nvidia/generated/g_hal_stubs.h index 6ab5f5cd9..01607b635 100644 --- a/src/nvidia/generated/g_hal_stubs.h +++ b/src/nvidia/generated/g_hal_stubs.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_stubs.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _G_RMCFG_HAL_STUBS_H_ @@ -655,7 +655,7 @@ NvU32 gpioInitAndGetPinNum_FWCLIENT( return (NvU32) 0; } -// RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcVgpuPfRegRead32_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -667,7 +667,7 @@ NV_STATUS rpcVgpuPfRegRead32_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcDumpProtobufComponent_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -679,7 +679,7 @@ NV_STATUS rpcDumpProtobufComponent_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcAllocMemory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -694,7 +694,7 @@ NV_STATUS rpcAllocMemory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcGpuExecRegOps_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -707,7 +707,7 @@ NV_STATUS rpcGpuExecRegOps_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_INIT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:RMFS_INIT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcRmfsInit_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -717,7 +717,7 @@ NV_STATUS rpcRmfsInit_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcUnsetPageDirectory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -729,7 +729,7 @@ NV_STATUS rpcUnsetPageDirectory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcGetGspStaticInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -738,7 +738,7 @@ NV_STATUS rpcGetGspStaticInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcGspSetSystemInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -747,7 +747,7 @@ NV_STATUS rpcGspSetSystemInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLEANUP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:RMFS_CLEANUP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcRmfsCleanup_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -756,7 +756,7 @@ NV_STATUS rpcRmfsCleanup_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcSetPageDirectory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -768,7 +768,7 @@ NV_STATUS rpcSetPageDirectory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcUnloadingGuestDriver_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -780,7 +780,7 @@ NV_STATUS rpcUnloadingGuestDriver_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcSetRegistry_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -789,7 +789,7 @@ NV_STATUS rpcSetRegistry_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLOSE_QUEUE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:RMFS_CLOSE_QUEUE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcRmfsCloseQueue_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -798,7 +798,7 @@ NV_STATUS rpcRmfsCloseQueue_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:GET_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcGetStaticInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -807,7 +807,7 @@ NV_STATUS rpcGetStaticInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcIdleChannels_STUB( OBJGPU *pArg1, POBJRPC pRpc, @@ -822,7 +822,7 @@ NV_STATUS rpcIdleChannels_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcUpdateBarPde_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -834,7 +834,7 @@ NV_STATUS rpcUpdateBarPde_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcMapMemoryDma_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -851,7 +851,7 @@ NV_STATUS rpcMapMemoryDma_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcUnmapMemoryDma_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -866,7 +866,7 @@ NV_STATUS rpcUnmapMemoryDma_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_TEST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// RPC:hal:RMFS_TEST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X NV_STATUS rpcRmfsTest_STUB( POBJGPU pGpu, POBJRPC pRpc, diff --git a/src/nvidia/generated/g_host_eng_nvoc.c b/src/nvidia/generated/g_host_eng_nvoc.c index 871fefe6f..5e2b392c8 100644 --- a/src/nvidia/generated/g_host_eng_nvoc.c +++ b/src/nvidia/generated/g_host_eng_nvoc.c @@ -33,6 +33,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_OBJHOSTENG = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_OBJHOSTENG = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_intr_nvoc.c b/src/nvidia/generated/g_intr_nvoc.c index 1e71b0622..65fd44b05 100644 --- a/src/nvidia/generated/g_intr_nvoc.c +++ b/src/nvidia/generated/g_intr_nvoc.c @@ -172,7 +172,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC, ((NvBool)(0 == 0))); } @@ -194,7 +194,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // NVOC Property Hal field -- PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 == 0))); } @@ -205,7 +205,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // NVOC Property Hal field -- PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE, ((NvBool)(0 == 0))); } @@ -216,7 +216,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // NVOC Property Hal field -- PDB_PROP_INTR_MASK_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_MASK_SUPPORTED, ((NvBool)(0 == 0))); } @@ -227,7 +227,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // Hal field -- bDefaultNonstallNotify - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0)); } @@ -289,7 +289,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; } @@ -299,7 +299,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; } @@ -312,7 +312,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100; } @@ -321,7 +321,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrSetDisplayInterruptEnable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_TU102; } @@ -336,7 +336,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; } @@ -349,7 +349,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; } @@ -362,7 +362,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; } @@ -370,13 +370,66 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { } + // Hal function -- intrGetStallSubtreeLast + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_GH100; + } + else if (0) + { + } + + // Hal function -- intrGetNumLeaves + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; + } + else if (0) + { + } + + // Hal function -- intrGetLeafSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; + } + else if (0) + { + } + + // Hal function -- intrGetIntrTopNonStallMask + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; + } + else if (0) + { + } + // Hal function -- intrSanityCheckEngineIntrStallVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; } // default else @@ -385,12 +438,13 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrSanityCheckEngineIntrNotificationVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; } // default else @@ -405,7 +459,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrStateLoad__ = &intrStateLoad_TU102; } @@ -420,7 +474,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrStateUnload__ = &intrStateUnload_TU102; } @@ -436,7 +490,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7; } @@ -449,7 +503,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104; } @@ -462,7 +516,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553; } diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index 312cdfb59..4e539e581 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -211,6 +211,10 @@ struct Intr { NvU32 (*__intrReadRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnClear__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); + NvU32 (*__intrGetStallSubtreeLast__)(OBJGPU *, struct Intr *); + NvU32 (*__intrGetNumLeaves__)(OBJGPU *, struct Intr *); + NvU32 (*__intrGetLeafSize__)(OBJGPU *, struct Intr *); + NvU32 (*__intrGetIntrTopNonStallMask__)(OBJGPU *, struct Intr *); void (*__intrSanityCheckEngineIntrStallVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); void (*__intrSanityCheckEngineIntrNotificationVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); NV_STATUS (*__intrStateLoad__)(OBJGPU *, struct Intr *, NvU32); @@ -335,6 +339,14 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrWriteRegTopEnSet_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnSet_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) +#define intrGetStallSubtreeLast(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) +#define intrGetStallSubtreeLast_HAL(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) +#define intrGetNumLeaves(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) +#define intrGetNumLeaves_HAL(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) +#define intrGetLeafSize(pGpu, pIntr) intrGetLeafSize_DISPATCH(pGpu, pIntr) +#define intrGetLeafSize_HAL(pGpu, pIntr) intrGetLeafSize_DISPATCH(pGpu, pIntr) +#define intrGetIntrTopNonStallMask(pGpu, pIntr) intrGetIntrTopNonStallMask_DISPATCH(pGpu, pIntr) +#define intrGetIntrTopNonStallMask_HAL(pGpu, pIntr) intrGetIntrTopNonStallMask_DISPATCH(pGpu, pIntr) #define intrSanityCheckEngineIntrStallVector(pGpu, pIntr, vector, mcEngine) intrSanityCheckEngineIntrStallVector_DISPATCH(pGpu, pIntr, vector, mcEngine) #define intrSanityCheckEngineIntrStallVector_HAL(pGpu, pIntr, vector, mcEngine) intrSanityCheckEngineIntrStallVector_DISPATCH(pGpu, pIntr, vector, mcEngine) #define intrSanityCheckEngineIntrNotificationVector(pGpu, pIntr, vector, mcEngine) intrSanityCheckEngineIntrNotificationVector_DISPATCH(pGpu, pIntr, vector, mcEngine) @@ -937,58 +949,6 @@ static inline void intrWriteRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0 #define intrWriteRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) -NvU32 intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetStallSubtreeLast(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetStallSubtreeLast(pGpu, pIntr) intrGetStallSubtreeLast_TU102(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrGetStallSubtreeLast_HAL(pGpu, pIntr) intrGetStallSubtreeLast(pGpu, pIntr) - -NvU32 intrGetNumLeaves_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetNumLeaves(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetNumLeaves(pGpu, pIntr) intrGetNumLeaves_TU102(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrGetNumLeaves_HAL(pGpu, pIntr) intrGetNumLeaves(pGpu, pIntr) - -NvU32 intrGetLeafSize_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetLeafSize(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetLeafSize(pGpu, pIntr) intrGetLeafSize_TU102(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrGetLeafSize_HAL(pGpu, pIntr) intrGetLeafSize(pGpu, pIntr) - -NvU32 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetIntrTopNonStallMask(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetIntrTopNonStallMask(pGpu, pIntr) intrGetIntrTopNonStallMask_TU102(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrGetIntrTopNonStallMask_HAL(pGpu, pIntr) intrGetIntrTopNonStallMask(pGpu, pIntr) - static inline NvU32 intrUpdateIntrCtrlValue_4a4dee(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { return 0; } @@ -1513,8 +1473,58 @@ static inline void intrWriteRegTopEnClear_DISPATCH(OBJGPU *pGpu, struct Intr *pI pIntr->__intrWriteRegTopEnClear__(pGpu, pIntr, arg0, arg1, arg2); } +NvU32 intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NvU32 intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetStallSubtreeLast_474d46(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 intrGetStallSubtreeLast_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrGetStallSubtreeLast__(pGpu, pIntr); +} + +NvU32 intrGetNumLeaves_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NvU32 intrGetNumLeaves_GH100(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetNumLeaves_474d46(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 intrGetNumLeaves_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrGetNumLeaves__(pGpu, pIntr); +} + +NvU32 intrGetLeafSize_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NvU32 intrGetLeafSize_GH100(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetLeafSize_474d46(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 intrGetLeafSize_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrGetLeafSize__(pGpu, pIntr); +} + +NvU32 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NvU32 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetIntrTopNonStallMask_474d46(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrGetIntrTopNonStallMask__(pGpu, pIntr); +} + void intrSanityCheckEngineIntrStallVector_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine); +void intrSanityCheckEngineIntrStallVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine); + static inline void intrSanityCheckEngineIntrStallVector_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine) { return; } @@ -1525,6 +1535,8 @@ static inline void intrSanityCheckEngineIntrStallVector_DISPATCH(OBJGPU *pGpu, s void intrSanityCheckEngineIntrNotificationVector_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine); +void intrSanityCheckEngineIntrNotificationVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine); + static inline void intrSanityCheckEngineIntrNotificationVector_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, NvU16 mcEngine) { return; } diff --git a/src/nvidia/generated/g_intr_service_nvoc.c b/src/nvidia/generated/g_intr_service_nvoc.c index 7636f6f7d..6409131c9 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.c +++ b/src/nvidia/generated/g_intr_service_nvoc.c @@ -33,6 +33,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_IntrService = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_intrable_nvoc.c b/src/nvidia/generated/g_intrable_nvoc.c index 5e6406d64..916ac4e2f 100644 --- a/src/nvidia/generated/g_intrable_nvoc.c +++ b/src/nvidia/generated/g_intrable_nvoc.c @@ -33,6 +33,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_OBJINTRABLE = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_journal_nvoc.h b/src/nvidia/generated/g_journal_nvoc.h index 593e6554c..46edce4e6 100644 --- a/src/nvidia/generated/g_journal_nvoc.h +++ b/src/nvidia/generated/g_journal_nvoc.h @@ -155,8 +155,7 @@ typedef struct _nocatQueueDescriptor RM_NOCAT_ASSERT_DIAG_BUFFER lastAssertData; NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; NvU64 cacheFreshnessPeriodticks; - NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; // cache contains the state of the - // associated GPU if there is one. + NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; // cache contains the state of the NvU32 nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; } nocatQueueDescriptor; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index 527deb935..aa5d41b3f 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -172,7 +172,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bFlaDummyPageEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->bFlaDummyPageEnabled = ((NvBool)(0 == 0)); } @@ -183,7 +183,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe } // Hal field -- bP2pMailboxClientAllocatedBug3466714VoltaAndUp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bP2pMailboxClientAllocatedBug3466714VoltaAndUp = ((NvBool)(0 == 0)); } @@ -194,7 +194,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe } // Hal field -- bBug2751296LimitBar2PtSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bBug2751296LimitBar2PtSize = ((NvBool)(0 == 0)); } @@ -238,7 +238,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe } // Hal field -- bReadCpuPointerToFlush - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bReadCpuPointerToFlush = ((NvBool)(0 == 0)); } @@ -252,7 +252,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBUS_IS_MISSING, ((NvBool)(0 != 0))); } @@ -287,7 +287,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusConstructEngine__ = &kbusConstructEngine_IMPL; // Hal function -- kbusStatePreInitLocked - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; } @@ -301,7 +301,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; // Hal function -- kbusStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; } @@ -310,7 +310,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; } @@ -324,7 +324,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; } @@ -334,7 +334,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusStateDestroy - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; } @@ -342,8 +342,88 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { } + // Hal function -- kbusTeardownBar2CpuAperture + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; + } + else if (0) + { + } + } + + // Hal function -- kbusGetP2PMailboxAttributes + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; + } + else if (0) + { + } + + // Hal function -- kbusCreateP2PMapping + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; + } + else if (0) + { + } + + // Hal function -- kbusRemoveP2PMapping + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; + } + else if (0) + { + } + + // Hal function -- kbusGetPeerId + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; + } + // Hal function -- kbusGetUnusedPciePeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; } @@ -352,12 +432,25 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_TU102; } + // Hal function -- kbusIsPeerIdValid + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; + } + // Hal function -- kbusGetNvlinkP2PPeerId if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; } @@ -366,8 +459,44 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; } + // Hal function -- kbusWriteP2PWmbTag + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; + } + else if (0) + { + } + + // Hal function -- kbusSetupP2PDomainAccess + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; + } + else if (0) + { + } + + // Hal function -- kbusNeedWarForBug999673 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; + } + // Hal function -- kbusRemoveNvlinkPeerMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusRemoveNvlinkPeerMapping__ = &kbusRemoveNvlinkPeerMapping_GP100; } @@ -376,8 +505,30 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusRemoveNvlinkPeerMapping__ = &kbusRemoveNvlinkPeerMapping_56cd7a; } + // Hal function -- kbusCreateP2PMappingForC2C + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCreateP2PMappingForC2C__ = &kbusCreateP2PMappingForC2C_GH100; + } + // default + else + { + pThis->__kbusCreateP2PMappingForC2C__ = &kbusCreateP2PMappingForC2C_46f6a7; + } + + // Hal function -- kbusRemoveP2PMappingForC2C + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRemoveP2PMappingForC2C__ = &kbusRemoveP2PMappingForC2C_GH100; + } + // default + else + { + pThis->__kbusRemoveP2PMappingForC2C__ = &kbusRemoveP2PMappingForC2C_46f6a7; + } + // Hal function -- kbusUnreserveP2PPeerIds - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_GP100; } @@ -386,102 +537,135 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_46f6a7; } + // Hal function -- kbusCreateP2PMappingForBar1P2P + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_GH100; + } + // default + else + { + pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_46f6a7; + } + + // Hal function -- kbusRemoveP2PMappingForBar1P2P + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_GH100; + } + // default + else + { + pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_46f6a7; + } + + // Hal function -- kbusHasPcieBar1P2PMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_GH100; + } + // default + else + { + pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_491d52; + } + // Hal function -- kbusAllocateFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusAllocateFlaVaspace__ = &kbusAllocateFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusAllocateFlaVaspace__ = &kbusAllocateFlaVaspace_395e98; } // Hal function -- kbusAllocateHostManagedFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_395e98; } // Hal function -- kbusInitFla - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusInitFla__ = &kbusInitFla_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusInitFla__ = &kbusInitFla_ac1694; } // Hal function -- kbusGetFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_395e98; } // Hal function -- kbusDestroyFla - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusDestroyFla__ = &kbusDestroyFla_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusDestroyFla__ = &kbusDestroyFla_d44104; } // Hal function -- kbusDestroyHostManagedFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_d44104; } // Hal function -- kbusVerifyFlaRange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_bf6dfa; } // Hal function -- kbusConstructFlaInstBlk - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_395e98; } // Hal function -- kbusDestructFlaInstBlk - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_d44104; } // Hal function -- kbusValidateFlaBaseAddress - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_395e98; } @@ -491,7 +675,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GA100; } @@ -501,7 +685,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GA100; } @@ -509,6 +693,115 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { } + // Hal function -- kbusSetBAR0WindowVidOffset + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; + } + else if (0) + { + } + else if (0) + { + } + else if (0) + { + } + } + + // Hal function -- kbusGetBAR0WindowVidOffset + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; + } + else if (0) + { + } + else if (0) + { + } + else if (0) + { + } + + // Hal function -- kbusVerifyBar2 + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; + } + else if (0) + { + } + else if (0) + { + } + } + + // Hal function -- kbusFlushPcieForBar0Doorbell + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_56cd7a; + } + + // Hal function -- kbusMapCoherentCpuMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusMapCoherentCpuMapping__ = &kbusMapCoherentCpuMapping_GV100; + } + // default + else + { + pThis->__kbusMapCoherentCpuMapping__ = &kbusMapCoherentCpuMapping_9e2234; + } + + // Hal function -- kbusUnmapCoherentCpuMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusUnmapCoherentCpuMapping__ = &kbusUnmapCoherentCpuMapping_GV100; + } + // default + else + { + pThis->__kbusUnmapCoherentCpuMapping__ = &kbusUnmapCoherentCpuMapping_d44104; + } + + // Hal function -- kbusTeardownCoherentCpuMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_GV100; + } + // default + else + { + pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_d44104; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBus_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelBus_engstateStatePreInitLocked; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index a9126e231..bdfb1180a 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -189,11 +189,6 @@ struct __nvoc_inner_struc_KernelBus_1__ { }; struct __nvoc_inner_struc_KernelBus_2__ { - NvU32 busBar1PeerRefcount[32]; - NvU32 busBar1HostRefcount[32]; -}; - -struct __nvoc_inner_struc_KernelBus_3__ { RmPhysAddr physAddr; NvU64 bar2OffsetInBar0Window; NvU64 cpuVisibleBase; @@ -224,7 +219,7 @@ struct __nvoc_inner_struc_KernelBus_3__ { NvU32 pageTblInit; }; -struct __nvoc_inner_struc_KernelBus_4__ { +struct __nvoc_inner_struc_KernelBus_3__ { struct OBJEHEAP *pVASpaceHeap; struct OBJEHEAP *pVASpaceHiddenHeap; VirtualBar2MapEntry *pMapListMemory; @@ -245,7 +240,7 @@ struct __nvoc_inner_struc_KernelBus_4__ { NvU32 evictions; }; -struct __nvoc_inner_struc_KernelBus_5__ { +struct __nvoc_inner_struc_KernelBus_4__ { NvHandle hClient; NvHandle hDevice; NvHandle hSubDevice; @@ -259,7 +254,7 @@ struct __nvoc_inner_struc_KernelBus_5__ { NvU64 size; }; -struct __nvoc_inner_struc_KernelBus_6__ { +struct __nvoc_inner_struc_KernelBus_5__ { NvBool bCoherentCpuMapping; NvU32 nrMapping; NvP64 pCpuMapping[3]; @@ -268,7 +263,7 @@ struct __nvoc_inner_struc_KernelBus_6__ { RmPhysAddr physAddr[3]; }; -struct __nvoc_inner_struc_KernelBus_7__ { +struct __nvoc_inner_struc_KernelBus_6__ { NvBool bNvlinkPeerIdsReserved; NvU32 busNvlinkPeerNumberMask[32]; NvU32 busNvlinkMappingRefcountPerGpu[32]; @@ -276,13 +271,17 @@ struct __nvoc_inner_struc_KernelBus_7__ { NvU32 busNvlinkMappingRefcountPerPeerIdSpa[8]; }; -struct __nvoc_inner_struc_KernelBus_8__ { +struct __nvoc_inner_struc_KernelBus_7__ { NvU32 peerNumberMask[32]; KBUS_PCIE_PEER busPeer[8]; NvU64 writeMailboxBar1Addr; NvU64 writeMailboxTotalSize; }; +struct __nvoc_inner_struc_KernelBus_8__ { + NvU32 busBar1PeerRefcount[32]; +}; + struct __nvoc_inner_struc_KernelBus_9__ { NvU32 busC2CPeerNumberMask[32]; NvU32 busC2CMappingRefcountPerPeerId[8]; @@ -302,10 +301,24 @@ struct KernelBus { NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateUnload__)(OBJGPU *, struct KernelBus *, NvU32); void (*__kbusStateDestroy__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusTeardownBar2CpuAperture__)(OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusGetP2PMailboxAttributes__)(OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); + NV_STATUS (*__kbusCreateP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); + NV_STATUS (*__kbusRemoveP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); + NvU32 (*__kbusGetPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); NvU32 (*__kbusGetUnusedPciePeerId__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusIsPeerIdValid__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *); + void (*__kbusWriteP2PWmbTag__)(OBJGPU *, struct KernelBus *, NvU32, NvU64); + RmPhysAddr (*__kbusSetupP2PDomainAccess__)(OBJGPU *, struct KernelBus *, OBJGPU *, PMEMORY_DESCRIPTOR *); + NvBool (*__kbusNeedWarForBug999673__)(OBJGPU *, struct KernelBus *, OBJGPU *); NV_STATUS (*__kbusRemoveNvlinkPeerMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, NvU32, NvU32); + NV_STATUS (*__kbusCreateP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); + NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NV_STATUS (*__kbusUnreserveP2PPeerIds__)(OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusHasPcieBar1P2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusAllocateFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusAllocateHostManagedFlaVaspace__)(OBJGPU *, struct KernelBus *, NvHandle, NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU32); NV_STATUS (*__kbusInitFla__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); @@ -318,6 +331,13 @@ struct KernelBus { NV_STATUS (*__kbusValidateFlaBaseAddress__)(OBJGPU *, struct KernelBus *, NvU64); NV_STATUS (*__kbusIsDirectMappingAllowed__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU32, NvBool *); NV_STATUS (*__kbusUseDirectSysmemMap__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvBool *); + NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *, NvU64); + NvU64 (*__kbusGetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusVerifyBar2__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); + NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(OBJGPU *, struct KernelBus *); + NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); + void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); + void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); NV_STATUS (*__kbusReconcileTunableState__)(POBJGPU, struct KernelBus *, void *); NV_STATUS (*__kbusStateLoad__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreLoad__)(POBJGPU, struct KernelBus *, NvU32); @@ -341,21 +361,22 @@ struct KernelBus { NvU8 *pDefaultBar0Pointer; NvU64 physicalBar0WindowSize; struct __nvoc_inner_struc_KernelBus_1__ bar1[64]; - struct __nvoc_inner_struc_KernelBus_2__ bar1PeerInfo; - struct __nvoc_inner_struc_KernelBus_3__ bar2[64]; - struct __nvoc_inner_struc_KernelBus_4__ virtualBar2[64]; - struct __nvoc_inner_struc_KernelBus_5__ flaInfo; + struct __nvoc_inner_struc_KernelBus_2__ bar2[64]; + struct __nvoc_inner_struc_KernelBus_3__ virtualBar2[64]; + struct __nvoc_inner_struc_KernelBus_4__ flaInfo; NvBool bFlaSupported; NvBool bFlaEnabled; NvBool bFlaDummyPageEnabled; - struct __nvoc_inner_struc_KernelBus_6__ coherentCpuMapping; + struct __nvoc_inner_struc_KernelBus_5__ coherentCpuMapping; NvU64 coherentLinkTestBufferBase; - struct __nvoc_inner_struc_KernelBus_7__ p2p; - struct __nvoc_inner_struc_KernelBus_8__ p2pPcie; + struct __nvoc_inner_struc_KernelBus_6__ p2p; + struct __nvoc_inner_struc_KernelBus_7__ p2pPcie; + struct __nvoc_inner_struc_KernelBus_8__ p2pPcieBar1; struct __nvoc_inner_struc_KernelBus_9__ c2cPeerInfo; NvU32 numPeers; NvBool p2pMapSpecifyId; NvU32 p2pMapPeerId; + NvU32 totalP2pObjectsAliveRefCount; NvBool bP2pInitialized; NvBool bP2pMailboxClientAllocated; NvBool bP2pMailboxClientAllocatedBug3466714VoltaAndUp; @@ -426,14 +447,42 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStateUnload_HAL(pGpu, pKernelBus, flags) kbusStateUnload_DISPATCH(pGpu, pKernelBus, flags) #define kbusStateDestroy(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusStateDestroy_HAL(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) +#define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusGetP2PMailboxAttributes(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes_DISPATCH(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) +#define kbusGetP2PMailboxAttributes_HAL(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes_DISPATCH(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) +#define kbusCreateP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusCreateP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusRemoveP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusRemoveP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) +#define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetUnusedPciePeerId(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) #define kbusGetUnusedPciePeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) +#define kbusIsPeerIdValid(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) +#define kbusIsPeerIdValid_HAL(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) #define kbusGetNvlinkP2PPeerId(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) #define kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) +#define kbusWriteP2PWmbTag(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) +#define kbusWriteP2PWmbTag_HAL(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) +#define kbusSetupP2PDomainAccess(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_DISPATCH(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) +#define kbusSetupP2PDomainAccess_HAL(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_DISPATCH(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) +#define kbusNeedWarForBug999673(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673_DISPATCH(pGpu, pKernelBus, pRemoteGpu) +#define kbusNeedWarForBug999673_HAL(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673_DISPATCH(pGpu, pKernelBus, pRemoteGpu) #define kbusRemoveNvlinkPeerMapping(pGpu, pKernelBus, pGpu1, arg0, attributes) kbusRemoveNvlinkPeerMapping_DISPATCH(pGpu, pKernelBus, pGpu1, arg0, attributes) #define kbusRemoveNvlinkPeerMapping_HAL(pGpu, pKernelBus, pGpu1, arg0, attributes) kbusRemoveNvlinkPeerMapping_DISPATCH(pGpu, pKernelBus, pGpu1, arg0, attributes) +#define kbusCreateP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusCreateP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusRemoveP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusUnreserveP2PPeerIds(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) #define kbusUnreserveP2PPeerIds_HAL(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) +#define kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) +#define kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) +#define kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) +#define kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) +#define kbusHasPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusHasPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusAllocateFlaVaspace(pGpu, pKernelBus, arg0, arg1) kbusAllocateFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusAllocateFlaVaspace_HAL(pGpu, pKernelBus, arg0, arg1) kbusAllocateFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusAllocateHostManagedFlaVaspace(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) kbusAllocateHostManagedFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) @@ -458,6 +507,20 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusIsDirectMappingAllowed_HAL(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusUseDirectSysmemMap(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusUseDirectSysmemMap_HAL(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) +#define kbusSetBAR0WindowVidOffset(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus, vidOffset) +#define kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus, vidOffset) +#define kbusGetBAR0WindowVidOffset(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) +#define kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) +#define kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) +#define kbusVerifyBar2_HAL(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) +#define kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) +#define kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) +#define kbusMapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusUnmapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusReconcileTunableState(pGpu, pEngstate, pTunableState) kbusReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbusStateLoad(pGpu, pEngstate, arg0) kbusStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbusStatePreLoad(pGpu, pEngstate, arg0) kbusStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -877,19 +940,6 @@ static inline NV_STATUS kbusSetupBar2CpuAperture(OBJGPU *pGpu, struct KernelBus #define kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusSetupBar2CpuAperture(pGpu, pKernelBus, gfid) -NV_STATUS kbusTeardownBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusTeardownBar2CpuAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_GM107(pGpu, pKernelBus, gfid) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) - NV_STATUS kbusSetP2PMailboxBar1Area_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize); #ifdef __nvoc_kern_bus_h_disabled @@ -928,18 +978,6 @@ static inline NV_STATUS kbusAllocP2PMailboxBar1(OBJGPU *pGpu, struct KernelBus * #define kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax) kbusAllocP2PMailboxBar1(pGpu, pKernelBus, gfid, vaRangeMax) -void kbusGetP2PMailboxAttributes_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusGetP2PMailboxAttributes(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusGetP2PMailboxAttributes(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes_GM200(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusGetP2PMailboxAttributes_HAL(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) - RmPhysAddr kbusSetupMailboxAccess_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc); #ifdef __nvoc_kern_bus_h_disabled @@ -967,45 +1005,6 @@ static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusDestroyPeerAccess_HAL(pGpu, pKernelBus, peerNum) kbusDestroyPeerAccess(pGpu, pKernelBus, peerNum) -NV_STATUS kbusCreateP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateP2PMapping(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusCreateP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_GP100(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusCreateP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) - -NV_STATUS kbusRemoveP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusRemoveP2PMapping(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusRemoveP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_GP100(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusRemoveP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) - -NvU32 kbusGetPeerId_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetPeerId(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return 0; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_GP100(pGpu, pKernelBus, pPeerGpu) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) - NvU32 kbusGetPeerIdFromTable_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); #ifdef __nvoc_kern_bus_h_disabled @@ -1032,19 +1031,6 @@ static inline NvU32 kbusGetUnusedPeerId(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusGetUnusedPeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPeerId(pGpu, pKernelBus) -NV_STATUS kbusIsPeerIdValid_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusIsPeerIdValid(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusIsPeerIdValid(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_GP100(pGpu, pKernelBus, peerId) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusIsPeerIdValid_HAL(pGpu, pKernelBus, peerId) kbusIsPeerIdValid(pGpu, pKernelBus, peerId) - NV_STATUS kbusReserveP2PPeerIds_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); #ifdef __nvoc_kern_bus_h_disabled @@ -1096,46 +1082,6 @@ static inline void kbusSetupMailboxes(OBJGPU *pGpu0, struct KernelBus *pKernelBu #define kbusSetupMailboxes_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, arg0, arg1) kbusSetupMailboxes(pGpu0, pKernelBus0, pGpu1, pKernelBus1, arg0, arg1) -void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusWriteP2PWmbTag(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusWriteP2PWmbTag(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_GM200(pGpu, pKernelBus, remote2Local, p2pWmbTag) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusWriteP2PWmbTag_HAL(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag(pGpu, pKernelBus, remote2Local, p2pWmbTag) - -RmPhysAddr kbusSetupP2PDomainAccess_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); - -#ifdef __nvoc_kern_bus_h_disabled -static inline RmPhysAddr kbusSetupP2PDomainAccess(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - RmPhysAddr ret; - portMemSet(&ret, 0, sizeof(RmPhysAddr)); - return ret; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupP2PDomainAccess(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_GM200(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupP2PDomainAccess_HAL(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) - -NvBool kbusNeedWarForBug999673_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusNeedWarForBug999673(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusNeedWarForBug999673(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673_GM200(pGpu, pKernelBus, pRemoteGpu) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusNeedWarForBug999673_HAL(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673(pGpu, pKernelBus, pRemoteGpu) - NV_STATUS kbusCreateP2PMappingForNvlink_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); #ifdef __nvoc_kern_bus_h_disabled @@ -1162,36 +1108,6 @@ static inline NV_STATUS kbusRemoveP2PMappingForNvlink(OBJGPU *pGpu0, struct Kern #define kbusRemoveP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForNvlink(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -static inline NV_STATUS kbusCreateP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateP2PMappingForC2C(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusCreateP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C_46f6a7(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusCreateP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) - -static inline NV_STATUS kbusRemoveP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusRemoveP2PMappingForC2C(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusRemoveP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_46f6a7(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) - NvU32 kbusGetNvlinkPeerNumberMask_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); #ifdef __nvoc_kern_bus_h_disabled @@ -1217,65 +1133,34 @@ static inline void kbusUnlinkP2P(OBJGPU *pGpu, struct KernelBus *pKernelBu) { #define kbusUnlinkP2P_HAL(pGpu, pKernelBu) kbusUnlinkP2P(pGpu, pKernelBu) -static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateP2PMappingForBar1P2P(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_46f6a7(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) - -static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_46f6a7(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) - -static inline NvBool kbusIsPcieBar1P2PMapping_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { return ((NvBool)(0 != 0)); } #ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusIsPcieBar1P2PMapping(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusIsPcieBar1P2PMappingSupported(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_FALSE; } #else //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMapping_491d52(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_491d52(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #endif //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) -static inline NvBool kbusIsPcieBar1P2PCapable_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { - return ((NvBool)(0 != 0)); +static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; } #ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusIsPcieBar1P2PCapable(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline void kbusSetupBar1P2PCapability(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_FALSE; } #else //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PCapable(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PCapable_491d52(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_b3696a(pGpu, pKernelBus) #endif //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PCapable_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PCapable(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability(pGpu, pKernelBus) NV_STATUS kbusSetupUnbindFla_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1380,32 +1265,6 @@ static inline NV_STATUS kbusMemCopyBar0Window(OBJGPU *pGpu, struct KernelBus *pK #define kbusMemCopyBar0Window_HAL(pGpu, pKernelBus, physAddr, pData, copySize, bRead) kbusMemCopyBar0Window(pGpu, pKernelBus, physAddr, pData, copySize, bRead) -NV_STATUS kbusSetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetBAR0WindowVidOffset(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetBAR0WindowVidOffset(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_GM107(pGpu, pKernelBus, vidOffset) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset(pGpu, pKernelBus, vidOffset) - -NvU64 kbusGetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU64 kbusGetBAR0WindowVidOffset(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return 0; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusGetBAR0WindowVidOffset(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_GM107(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset(pGpu, pKernelBus) - NvU64 kbusGetBAR0WindowAddress_GM107(struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled @@ -1470,34 +1329,6 @@ static inline NV_STATUS kbusDestroyBar2(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusDestroyBar2_HAL(pGpu, pKernelBus, gfid) kbusDestroyBar2(pGpu, pKernelBus, gfid) -NV_STATUS kbusVerifyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusVerifyBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_GM107(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusVerifyBar2_HAL(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) - -static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return NV_OK; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusVerifyCoherentLink(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusVerifyCoherentLink(pGpu, pKernelBus) kbusVerifyCoherentLink_56cd7a(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusVerifyCoherentLink_HAL(pGpu, pKernelBus) kbusVerifyCoherentLink(pGpu, pKernelBus) - NV_STATUS kbusInitBar1_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled @@ -1618,21 +1449,6 @@ static inline NvBool kbusCheckEngine(OBJGPU *pGpu, struct KernelBus *pKernelBus, #define kbusCheckEngine_HAL(pGpu, pKernelBus, desc) kbusCheckEngine(pGpu, pKernelBus, desc) -static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return NV_OK; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusFlushPcieForBar0Doorbell(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_56cd7a(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) - NV_STATUS kbusFlush_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled @@ -1661,35 +1477,6 @@ static inline NV_STATUS kbusCreateCoherentCpuMapping(OBJGPU *pGpu, struct Kernel #define kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush) kbusCreateCoherentCpuMapping(pGpu, pKernelBus, bFlush) -static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { - return ((void *)0); -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusMapCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NULL; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusMapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_9e2234(pGpu, pKernelBus, arg0) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping(pGpu, pKernelBus, arg0) - -static inline void kbusUnmapCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { - return; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnmapCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusUnmapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_d44104(pGpu, pKernelBus, arg0) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping(pGpu, pKernelBus, arg0) - static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } @@ -1704,20 +1491,6 @@ static inline void kbusTeardownCoherentCpuMappingAcr(OBJGPU *pGpu, struct Kernel #define kbusTeardownCoherentCpuMappingAcr_HAL(pGpu, pKernelBus) kbusTeardownCoherentCpuMappingAcr(pGpu, pKernelBus) -static inline void kbusTeardownCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { - return; -} - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusTeardownCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_d44104(pGpu, pKernelBus, arg0) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) - NV_STATUS kbusConstructEngine_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0); static inline NV_STATUS kbusConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0) { @@ -1776,6 +1549,62 @@ static inline void kbusStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKe pKernelBus->__kbusStateDestroy__(pGpu, pKernelBus); } +static inline NV_STATUS kbusTeardownBar2CpuAperture_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return NV_OK; +} + +NV_STATUS kbusTeardownBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +NV_STATUS kbusTeardownBar2CpuAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusTeardownBar2CpuAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusTeardownBar2CpuAperture__(pGpu, pKernelBus, gfid); +} + +void kbusGetP2PMailboxAttributes_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); + +void kbusGetP2PMailboxAttributes_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); + +static inline void kbusGetP2PMailboxAttributes_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { + return; +} + +static inline void kbusGetP2PMailboxAttributes_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { + pKernelBus->__kbusGetP2PMailboxAttributes__(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB); +} + +NV_STATUS kbusCreateP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); + +NV_STATUS kbusCreateP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); + +static inline NV_STATUS kbusCreateP2PMapping_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusCreateP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { + return pKernelBus0->__kbusCreateP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); +} + +NV_STATUS kbusRemoveP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); + +NV_STATUS kbusRemoveP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); + +static inline NV_STATUS kbusRemoveP2PMapping_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusRemoveP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { + return pKernelBus0->__kbusRemoveP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); +} + +NvU32 kbusGetPeerId_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); + +NvU32 kbusGetPeerId_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); + +static inline NvU32 kbusGetPeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { + return pKernelBus->__kbusGetPeerId__(pGpu, pKernelBus, pPeerGpu); +} + NvU32 kbusGetUnusedPciePeerId_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); NvU32 kbusGetUnusedPciePeerId_TU102(OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1784,6 +1613,14 @@ static inline NvU32 kbusGetUnusedPciePeerId_DISPATCH(OBJGPU *pGpu, struct Kernel return pKernelBus->__kbusGetUnusedPciePeerId__(pGpu, pKernelBus); } +NV_STATUS kbusIsPeerIdValid_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); + +NV_STATUS kbusIsPeerIdValid_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); + +static inline NV_STATUS kbusIsPeerIdValid_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { + return pKernelBus->__kbusIsPeerIdValid__(pGpu, pKernelBus, peerId); +} + NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); @@ -1796,6 +1633,40 @@ static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct Ke return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer); } +void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); + +void kbusWriteP2PWmbTag_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); + +static inline void kbusWriteP2PWmbTag_f2d351(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kbusWriteP2PWmbTag_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { + pKernelBus->__kbusWriteP2PWmbTag__(pGpu, pKernelBus, remote2Local, p2pWmbTag); +} + +RmPhysAddr kbusSetupP2PDomainAccess_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); + +RmPhysAddr kbusSetupP2PDomainAccess_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); + +static inline RmPhysAddr kbusSetupP2PDomainAccess_100832(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ~0ULL); +} + +static inline RmPhysAddr kbusSetupP2PDomainAccess_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { + return pKernelBus0->__kbusSetupP2PDomainAccess__(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc); +} + +NvBool kbusNeedWarForBug999673_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu); + +static inline NvBool kbusNeedWarForBug999673_491d52(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusNeedWarForBug999673_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu) { + return pKernelBus->__kbusNeedWarForBug999673__(pGpu, pKernelBus, pRemoteGpu); +} + NV_STATUS kbusRemoveNvlinkPeerMapping_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 arg0, NvU32 attributes); static inline NV_STATUS kbusRemoveNvlinkPeerMapping_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 arg0, NvU32 attributes) { @@ -1806,6 +1677,26 @@ static inline NV_STATUS kbusRemoveNvlinkPeerMapping_DISPATCH(OBJGPU *pGpu, struc return pKernelBus->__kbusRemoveNvlinkPeerMapping__(pGpu, pKernelBus, pGpu1, arg0, attributes); } +NV_STATUS kbusCreateP2PMappingForC2C_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); + +static inline NV_STATUS kbusCreateP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusCreateP2PMappingForC2C_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { + return pKernelBus0->__kbusCreateP2PMappingForC2C__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); +} + +NV_STATUS kbusRemoveP2PMappingForC2C_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); + +static inline NV_STATUS kbusRemoveP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusRemoveP2PMappingForC2C_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { + return pKernelBus0->__kbusRemoveP2PMappingForC2C__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); +} + NV_STATUS kbusUnreserveP2PPeerIds_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); static inline NV_STATUS kbusUnreserveP2PPeerIds_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { @@ -1816,6 +1707,36 @@ static inline NV_STATUS kbusUnreserveP2PPeerIds_DISPATCH(OBJGPU *pGpu, struct Ke return pKernelBus->__kbusUnreserveP2PPeerIds__(pGpu, pKernelBus, peerMask); } +NV_STATUS kbusCreateP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); + +static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { + return pKernelBus0->__kbusCreateP2PMappingForBar1P2P__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); +} + +NV_STATUS kbusRemoveP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); + +static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { + return pKernelBus0->__kbusRemoveP2PMappingForBar1P2P__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); +} + +NvBool kbusHasPcieBar1P2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1); + +static inline NvBool kbusHasPcieBar1P2PMapping_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusHasPcieBar1P2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return pKernelBus0->__kbusHasPcieBar1P2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); +} + NV_STATUS kbusAllocateFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); static inline NV_STATUS kbusAllocateFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { @@ -1936,6 +1857,87 @@ static inline NV_STATUS kbusUseDirectSysmemMap_DISPATCH(OBJGPU *pGpu, struct Ker return pKernelBus->__kbusUseDirectSysmemMap__(pGpu, pKernelBus, arg0, arg1); } +static inline NV_STATUS kbusSetBAR0WindowVidOffset_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { + return NV_OK; +} + +NV_STATUS kbusSetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); + +NV_STATUS kbusSetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); + +static inline NV_STATUS kbusSetBAR0WindowVidOffset_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusSetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { + return pKernelBus->__kbusSetBAR0WindowVidOffset__(pGpu, pKernelBus, vidOffset); +} + +NvU64 kbusGetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NvU64 kbusGetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU64 kbusGetBAR0WindowVidOffset_13cd8d(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +static inline NvU64 kbusGetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetBAR0WindowVidOffset__(pGpu, pKernelBus); +} + +static inline NV_STATUS kbusVerifyBar2_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { + return NV_OK; +} + +NV_STATUS kbusVerifyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); + +NV_STATUS kbusVerifyBar2_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); + +static inline NV_STATUS kbusVerifyBar2_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { + return pKernelBus->__kbusVerifyBar2__(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size); +} + +NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +static inline NV_STATUS kbusFlushPcieForBar0Doorbell_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusFlushPcieForBar0Doorbell__(pGpu, pKernelBus); +} + +NvU8 *kbusMapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); + +static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { + return ((void *)0); +} + +static inline NvU8 *kbusMapCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { + return pKernelBus->__kbusMapCoherentCpuMapping__(pGpu, pKernelBus, arg0); +} + +void kbusUnmapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); + +static inline void kbusUnmapCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { + return; +} + +static inline void kbusUnmapCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { + pKernelBus->__kbusUnmapCoherentCpuMapping__(pGpu, pKernelBus, arg0); +} + +void kbusTeardownCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0); + +static inline void kbusTeardownCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { + return; +} + +static inline void kbusTeardownCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { + pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); +} + static inline NV_STATUS kbusReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { return pEngstate->__kbusReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -2056,6 +2058,10 @@ static inline void kbusSetBar1P2pCapable(struct KernelBus *pKernelBus, NvBool va pKernelBus->bBar1P2pCapable = val; } +static inline NvBool kbusIsBar1P2PCapable(struct KernelBus *pKernelBus) { + return pKernelBus->bBar1P2pCapable; +} + void kbusDestruct_IMPL(struct KernelBus *pKernelBus); #define __nvoc_kbusDestruct(pKernelBus) kbusDestruct_IMPL(pKernelBus) void kbusGetDeviceCaps_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized); @@ -2120,6 +2126,16 @@ static inline RmPhysAddr kbusGetPciBarOffset(struct KernelBus *pKernelBus, NvU32 #define kbusGetPciBarOffset(pKernelBus, index) kbusGetPciBarOffset_IMPL(pKernelBus, index) #endif //__nvoc_kern_bus_h_disabled +NV_STATUS kbusIsGpuP2pAlive_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +#ifdef __nvoc_kern_bus_h_disabled +static inline NV_STATUS kbusIsGpuP2pAlive(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_bus_h_disabled +#define kbusIsGpuP2pAlive(pGpu, pKernelBus) kbusIsGpuP2pAlive_IMPL(pGpu, pKernelBus) +#endif //__nvoc_kern_bus_h_disabled + void kbusDetermineBar1Force64KBMapping_IMPL(struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDetermineBar1Force64KBMapping(struct KernelBus *pKernelBus) { diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index f4deaa1dc..0fb018501 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -212,7 +212,7 @@ void __nvoc_init_dataField_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *p } // NVOC Property Hal field -- PDB_PROP_KDISP_IMP_ENABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } @@ -298,7 +298,7 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe else if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; } @@ -313,7 +313,7 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe else if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; } @@ -331,18 +331,19 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe else if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_v03_00; } // Hal function -- kdispGetDisplayCapsBaseAndSize - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_b3696a; } else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ )) + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_v03_00; } @@ -355,7 +356,7 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe else if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_v03_00; } @@ -371,24 +372,23 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe else if (0) { } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 */ + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_v03_00; } // Hal function -- kdispGetVgaWorkspaceBase - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; } // default else { - pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_ceaee8; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c new file mode 100644 index 000000000..84c61e6b5 --- /dev/null +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -0,0 +1,534 @@ +#define NVOC_KERN_FSP_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kern_fsp_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x87fb96 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFsp; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; + +void __nvoc_init_KernelFsp(KernelFsp*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelFsp(KernelFsp*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelFsp(KernelFsp*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelFsp(KernelFsp*, RmHalspecOwner* ); +void __nvoc_dtor_KernelFsp(KernelFsp*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelFsp; + +static const struct NVOC_RTTI __nvoc_rtti_KernelFsp_KernelFsp = { + /*pClassDef=*/ &__nvoc_class_def_KernelFsp, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelFsp, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelFsp_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelFsp, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelFsp_OBJENGSTATE = { + /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelFsp, __nvoc_base_OBJENGSTATE), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelFsp = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_KernelFsp_KernelFsp, + &__nvoc_rtti_KernelFsp_OBJENGSTATE, + &__nvoc_rtti_KernelFsp_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFsp = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelFsp), + /*classId=*/ classId(KernelFsp), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelFsp", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelFsp, + /*pCastInfo=*/ &__nvoc_castinfo_KernelFsp, + /*pExportInfo=*/ &__nvoc_export_info_KernelFsp +}; + +static NV_STATUS __nvoc_thunk_KernelFsp_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelFsp, ENGDESCRIPTOR arg0) { + return kfspConstructEngine(pGpu, (struct KernelFsp *)(((unsigned char *)pKernelFsp) - __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static void __nvoc_thunk_KernelFsp_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelFsp) { + kfspStateDestroy(pGpu, (struct KernelFsp *)(((unsigned char *)pKernelFsp) - __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateUnload(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateInitLocked(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePreLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePostUnload(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePreUnload(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateInitUnlocked(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_OBJENGSTATE_kfspInitMissing(POBJGPU pGpu, struct KernelFsp *pEngstate) { + engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePreInitLocked(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePreInitUnlocked(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspGetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspCompareTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { + return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunables1, pTunables2); +} + +static void __nvoc_thunk_OBJENGSTATE_kfspFreeTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePostLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspAllocTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { + return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), ppTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspSetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_kfspIsPresent(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelFsp = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_KernelFsp(KernelFsp *pThis) { + __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + // NVOC Property Hal field -- PDB_PROP_KFSP_IS_MISSING + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KFSP_IS_MISSING, ((NvBool)(0 != 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KFSP_IS_MISSING, ((NvBool)(0 == 0))); + } +} + +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + if (status != NV_OK) goto __nvoc_ctor_KernelFsp_fail_OBJENGSTATE; + __nvoc_init_dataField_KernelFsp(pThis, pRmhalspecowner); + goto __nvoc_ctor_KernelFsp_exit; // Success + +__nvoc_ctor_KernelFsp_fail_OBJENGSTATE: +__nvoc_ctor_KernelFsp_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + pThis->__kfspConstructEngine__ = &kfspConstructEngine_IMPL; + + pThis->__kfspStateDestroy__ = &kfspStateDestroy_IMPL; + + pThis->__kfspSecureReset__ = &kfspSecureReset_IMPL; + + pThis->__kfspSendPacket__ = &kfspSendPacket_IMPL; + + pThis->__kfspSendAndReadMessage__ = &kfspSendAndReadMessage_IMPL; + + pThis->__kfspIsQueueEmpty__ = &kfspIsQueueEmpty_IMPL; + + pThis->__kfspPollForQueueEmpty__ = &kfspPollForQueueEmpty_IMPL; + + pThis->__kfspIsMsgQueueEmpty__ = &kfspIsMsgQueueEmpty_IMPL; + + pThis->__kfspPollForResponse__ = &kfspPollForResponse_IMPL; + + // Hal function -- kfspGspFmcIsEnforced + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGspFmcIsEnforced__ = &kfspGspFmcIsEnforced_GH100; + } + // default + else + { + pThis->__kfspGspFmcIsEnforced__ = &kfspGspFmcIsEnforced_491d52; + } + + // Hal function -- kfspSendBootCommands + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_ac1694; + } + + // Hal function -- kfspWaitForSecureBoot + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_395e98; + } + + // Hal function -- kfspGetRmChannelSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_b2b553; + } + + // Hal function -- kfspConfigEmemc + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_395e98; + } + + // Hal function -- kfspUpdateQueueHeadTail + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_d44104; + } + + // Hal function -- kfspGetQueueHeadTail + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_d44104; + } + + // Hal function -- kfspUpdateMsgQueueHeadTail + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_d44104; + } + + // Hal function -- kfspGetMsgQueueHeadTail + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_d44104; + } + + // Hal function -- kfspNvdmToSeid + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_b2b553; + } + + // Hal function -- kfspCreateMctpHeader + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_b2b553; + } + + // Hal function -- kfspCreateNvdmHeader + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_b2b553; + } + + // Hal function -- kfspWriteToEmem + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_395e98; + } + + // Hal function -- kfspReadFromEmem + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_395e98; + } + + // Hal function -- kfspGetPacketInfo + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_395e98; + } + + // Hal function -- kfspValidateMctpPayloadHeader + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_395e98; + } + + // Hal function -- kfspProcessNvdmMessage + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_395e98; + } + + // Hal function -- kfspProcessCommandResponse + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_395e98; + } + + // Hal function -- kfspDumpDebugState + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_d44104; + } + + // Hal function -- kfspErrorCode2NvStatusMap + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_395e98; + } + + // Hal function -- kfspCheckGspSecureScratch + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspCheckGspSecureScratch__ = &kfspCheckGspSecureScratch_GH100; + } + // default + else + { + pThis->__kfspCheckGspSecureScratch__ = &kfspCheckGspSecureScratch_491d52; + } + + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFsp_engstateConstructEngine; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFsp_engstateStateDestroy; + + pThis->__kfspReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState; + + pThis->__kfspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStateLoad; + + pThis->__kfspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfspStateUnload; + + pThis->__kfspStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStateInitLocked; + + pThis->__kfspStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreLoad; + + pThis->__kfspStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePostUnload; + + pThis->__kfspStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreUnload; + + pThis->__kfspStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStateInitUnlocked; + + pThis->__kfspInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kfspInitMissing; + + pThis->__kfspStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreInitLocked; + + pThis->__kfspStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreInitUnlocked; + + pThis->__kfspGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspGetTunableState; + + pThis->__kfspCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspCompareTunableState; + + pThis->__kfspFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspFreeTunableState; + + pThis->__kfspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePostLoad; + + pThis->__kfspAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspAllocTunableState; + + pThis->__kfspSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspSetTunableState; + + pThis->__kfspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kfspIsPresent; +} + +void __nvoc_init_funcTable_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelFsp_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_KernelFsp = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; + pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_funcTable_KernelFsp(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + KernelFsp *pThis; + RmHalspecOwner *pRmhalspecowner; + + pThis = portMemAllocNonPaged(sizeof(KernelFsp)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelFsp)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFsp); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_KernelFsp(pThis, pRmhalspecowner); + status = __nvoc_ctor_KernelFsp(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_KernelFsp_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelFsp_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_KernelFsp(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h new file mode 100644 index 000000000..f80d1d387 --- /dev/null +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -0,0 +1,656 @@ +#ifndef _G_KERN_FSP_NVOC_H_ +#define _G_KERN_FSP_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kern_fsp_nvoc.h" + +#ifndef KERN_FSP_H +#define KERN_FSP_H + +#include "core/core.h" +#include "gpu/eng_state.h" +#include "kernel/gpu/fifo/channel_descendant.h" +#include "kernel/gpu/intrable/intrable.h" +#include "kernel/gpu/intr/intr_service.h" +#include "fsp/nvdm_payload_cmd_response.h" + +#if RMCFG_MODULE_ENABLED (FSP) +#include "gpu/falcon/falcon.h" +#include "gpu/falcon/falcon_queue.h" +#include "objflcnable.h" +#endif + +// +// VBIOS ucode descriptor v4 format. Used for the CPU command to FSP to boot +// GSP FMC. +// +typedef struct +{ + NvU8 flags; + NvU8 version; + NvU16 structSize; + NvU32 storeSize; + NvU32 IMEMOffset; + NvU32 IMEMSize; + NvU32 DMEMOffset; + NvU32 DMEMSize; + NvU8 ucodeId; + NvU8 ucodeVersion; + NvU16 payloadCount; + NvU16 payloadSize; + NvU8 ucodeVerMajor; + NvU8 ucodeVerMinor; + NvU32 cryptoData[10]; // unused +} FSP_UCODE_DESC_V4; + +#pragma pack(1) +typedef struct +{ + NvU32 constBlob; + NvU8 msgType; + NvU16 vendorId; +} MCTP_HEADER; + +// Needed to remove unnecessary padding +#pragma pack(1) +typedef struct +{ + NvU16 version; + NvU16 size; + NvU64 gspFmcSysmemOffset; + NvU64 frtsSysmemOffset; + NvU32 frtsSysmemSize; + + // Note this is an offset from the end of FB + NvU64 frtsVidmemOffset; + NvU32 frtsVidmemSize; + + // Authentication related fields + NvU32 hash384[12]; + NvU32 publicKey[96]; + NvU32 signature[96]; + + NvU64 gspBootArgsSysmemOffset; +} NVDM_PAYLOAD_COT; +#pragma pack() + +typedef struct +{ + NvU8 nvdmType; + + // We can make this a union when adding more NVDM payloads + NVDM_PAYLOAD_COT cotPayload; +} NVDM_PACKET; + +// The structure cannot have embedded pointers to send as byte stream +typedef struct +{ + MCTP_HEADER header; + NVDM_PACKET nvdmPacket; +} MCTP_PACKET, *PMCTP_PACKET; + +// Type of packet, can either be SOM, EOM, neither, or both (1-packet messages) +typedef enum +{ + MCTP_PACKET_STATE_START, + MCTP_PACKET_STATE_INTERMEDIATE, + MCTP_PACKET_STATE_END, + MCTP_PACKET_STATE_SINGLE_PACKET +} MCTP_PACKET_STATE; + +#ifdef NVOC_KERN_FSP_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelFsp { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelFsp *__nvoc_pbase_KernelFsp; + NV_STATUS (*__kfspConstructEngine__)(struct OBJGPU *, struct KernelFsp *, ENGDESCRIPTOR); + void (*__kfspStateDestroy__)(struct OBJGPU *, struct KernelFsp *); + void (*__kfspSecureReset__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspSendPacket__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + NV_STATUS (*__kfspSendAndReadMessage__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32, NvU32, NvU8 *, NvU32); + NvBool (*__kfspIsQueueEmpty__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspPollForQueueEmpty__)(struct OBJGPU *, struct KernelFsp *); + NvBool (*__kfspIsMsgQueueEmpty__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspPollForResponse__)(struct OBJGPU *, struct KernelFsp *); + NvBool (*__kfspGspFmcIsEnforced__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspSendBootCommands__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspWaitForSecureBoot__)(struct OBJGPU *, struct KernelFsp *); + NvU32 (*__kfspGetRmChannelSize__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspConfigEmemc__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvBool, NvBool); + void (*__kfspUpdateQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvU32); + void (*__kfspGetQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); + void (*__kfspUpdateMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvU32); + void (*__kfspGetMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); + NvU8 (*__kfspNvdmToSeid__)(POBJGPU, struct KernelFsp *, NvU8); + NvU32 (*__kfspCreateMctpHeader__)(struct OBJGPU *, struct KernelFsp *, NvU8, NvU8, NvU8, NvU8); + NvU32 (*__kfspCreateNvdmHeader__)(struct OBJGPU *, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspWriteToEmem__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + NV_STATUS (*__kfspReadFromEmem__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + NV_STATUS (*__kfspGetPacketInfo__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32, MCTP_PACKET_STATE *, NvU8 *); + NV_STATUS (*__kfspValidateMctpPayloadHeader__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + NV_STATUS (*__kfspProcessNvdmMessage__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + NV_STATUS (*__kfspProcessCommandResponse__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); + void (*__kfspDumpDebugState__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspErrorCode2NvStatusMap__)(struct OBJGPU *, struct KernelFsp *, NvU32); + NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspReconcileTunableState__)(POBJGPU, struct KernelFsp *, void *); + NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspStateUnload__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspStateInitLocked__)(POBJGPU, struct KernelFsp *); + NV_STATUS (*__kfspStatePreLoad__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspStatePostUnload__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspStatePreUnload__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspStateInitUnlocked__)(POBJGPU, struct KernelFsp *); + void (*__kfspInitMissing__)(POBJGPU, struct KernelFsp *); + NV_STATUS (*__kfspStatePreInitLocked__)(POBJGPU, struct KernelFsp *); + NV_STATUS (*__kfspStatePreInitUnlocked__)(POBJGPU, struct KernelFsp *); + NV_STATUS (*__kfspGetTunableState__)(POBJGPU, struct KernelFsp *, void *); + NV_STATUS (*__kfspCompareTunableState__)(POBJGPU, struct KernelFsp *, void *, void *); + void (*__kfspFreeTunableState__)(POBJGPU, struct KernelFsp *, void *); + NV_STATUS (*__kfspStatePostLoad__)(POBJGPU, struct KernelFsp *, NvU32); + NV_STATUS (*__kfspAllocTunableState__)(POBJGPU, struct KernelFsp *, void **); + NV_STATUS (*__kfspSetTunableState__)(POBJGPU, struct KernelFsp *, void *); + NvBool (*__kfspIsPresent__)(POBJGPU, struct KernelFsp *); + NvBool PDB_PROP_KFSP_BOOT_COMMAND_OK; + NvBool PDB_PROP_KFSP_GSP_MODE_GSPRM; + NvBool PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM; + NvBool PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM; + NvBool PDB_PROP_KFSP_DISABLE_GSPFMC; + NvBool PDB_PROP_KFSP_HULK_EXECUTED; + MEMORY_DESCRIPTOR *pSysmemFrtsMemdesc; + MEMORY_DESCRIPTOR *pVidmemFrtsMemdesc; + MEMORY_DESCRIPTOR *pGspFmcMemdesc; + MEMORY_DESCRIPTOR *pGspBootArgsMemdesc; + NVDM_PAYLOAD_COT *pCotPayload; + NvBool bGspDebugBufferInitialized; +}; + +#ifndef __NVOC_CLASS_KernelFsp_TYPEDEF__ +#define __NVOC_CLASS_KernelFsp_TYPEDEF__ +typedef struct KernelFsp KernelFsp; +#endif /* __NVOC_CLASS_KernelFsp_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelFsp +#define __nvoc_class_id_KernelFsp 0x87fb96 +#endif /* __nvoc_class_id_KernelFsp */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFsp; + +#define __staticCast_KernelFsp(pThis) \ + ((pThis)->__nvoc_pbase_KernelFsp) + +#ifdef __nvoc_kern_fsp_h_disabled +#define __dynamicCast_KernelFsp(pThis) ((KernelFsp*)NULL) +#else //__nvoc_kern_fsp_h_disabled +#define __dynamicCast_KernelFsp(pThis) \ + ((KernelFsp*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelFsp))) +#endif //__nvoc_kern_fsp_h_disabled + +#define PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM_BASE_CAST +#define PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM_BASE_NAME PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM +#define PDB_PROP_KFSP_DISABLE_GSPFMC_BASE_CAST +#define PDB_PROP_KFSP_DISABLE_GSPFMC_BASE_NAME PDB_PROP_KFSP_DISABLE_GSPFMC +#define PDB_PROP_KFSP_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_KFSP_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_CAST +#define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_NAME PDB_PROP_KFSP_GSP_MODE_GSPRM +#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_CAST +#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_NAME PDB_PROP_KFSP_HULK_EXECUTED +#define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_CAST +#define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_NAME PDB_PROP_KFSP_BOOT_COMMAND_OK +#define PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM_BASE_CAST +#define PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM_BASE_NAME PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM + +NV_STATUS __nvoc_objCreateDynamic_KernelFsp(KernelFsp**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); +#define __objCreate_KernelFsp(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelFsp((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define kfspConstructEngine(pGpu, pKernelFsp, arg0) kfspConstructEngine_DISPATCH(pGpu, pKernelFsp, arg0) +#define kfspStateDestroy(pGpu, pKernelFsp) kfspStateDestroy_DISPATCH(pGpu, pKernelFsp) +#define kfspSecureReset(pGpu, pKernelFsp) kfspSecureReset_DISPATCH(pGpu, pKernelFsp) +#define kfspSendPacket(pGpu, pKernelFsp, pPacket, packetSize) kfspSendPacket_DISPATCH(pGpu, pKernelFsp, pPacket, packetSize) +#define kfspSendAndReadMessage(pGpu, pKernelFsp, pPayload, size, nvdmType, pResponsePayload, responseBufferSize) kfspSendAndReadMessage_DISPATCH(pGpu, pKernelFsp, pPayload, size, nvdmType, pResponsePayload, responseBufferSize) +#define kfspIsQueueEmpty(pGpu, pKernelFsp) kfspIsQueueEmpty_DISPATCH(pGpu, pKernelFsp) +#define kfspPollForQueueEmpty(pGpu, pKernelFsp) kfspPollForQueueEmpty_DISPATCH(pGpu, pKernelFsp) +#define kfspIsMsgQueueEmpty(pGpu, pKernelFsp) kfspIsMsgQueueEmpty_DISPATCH(pGpu, pKernelFsp) +#define kfspPollForResponse(pGpu, pKernelFsp) kfspPollForResponse_DISPATCH(pGpu, pKernelFsp) +#define kfspGspFmcIsEnforced(pGpu, pKernelFsp) kfspGspFmcIsEnforced_DISPATCH(pGpu, pKernelFsp) +#define kfspGspFmcIsEnforced_HAL(pGpu, pKernelFsp) kfspGspFmcIsEnforced_DISPATCH(pGpu, pKernelFsp) +#define kfspSendBootCommands(pGpu, pKernelFsp) kfspSendBootCommands_DISPATCH(pGpu, pKernelFsp) +#define kfspSendBootCommands_HAL(pGpu, pKernelFsp) kfspSendBootCommands_DISPATCH(pGpu, pKernelFsp) +#define kfspWaitForSecureBoot(pGpu, pKernelFsp) kfspWaitForSecureBoot_DISPATCH(pGpu, pKernelFsp) +#define kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp) kfspWaitForSecureBoot_DISPATCH(pGpu, pKernelFsp) +#define kfspGetRmChannelSize(pGpu, pKernelFsp) kfspGetRmChannelSize_DISPATCH(pGpu, pKernelFsp) +#define kfspGetRmChannelSize_HAL(pGpu, pKernelFsp) kfspGetRmChannelSize_DISPATCH(pGpu, pKernelFsp) +#define kfspConfigEmemc(pGpu, pKernelFsp, offset, bAincw, bAincr) kfspConfigEmemc_DISPATCH(pGpu, pKernelFsp, offset, bAincw, bAincr) +#define kfspConfigEmemc_HAL(pGpu, pKernelFsp, offset, bAincw, bAincr) kfspConfigEmemc_DISPATCH(pGpu, pKernelFsp, offset, bAincw, bAincr) +#define kfspUpdateQueueHeadTail(pGpu, pKernelFsp, queueHead, queueTail) kfspUpdateQueueHeadTail_DISPATCH(pGpu, pKernelFsp, queueHead, queueTail) +#define kfspUpdateQueueHeadTail_HAL(pGpu, pKernelFsp, queueHead, queueTail) kfspUpdateQueueHeadTail_DISPATCH(pGpu, pKernelFsp, queueHead, queueTail) +#define kfspGetQueueHeadTail(pGpu, pKernelFsp, pQueueHead, pQueueTail) kfspGetQueueHeadTail_DISPATCH(pGpu, pKernelFsp, pQueueHead, pQueueTail) +#define kfspGetQueueHeadTail_HAL(pGpu, pKernelFsp, pQueueHead, pQueueTail) kfspGetQueueHeadTail_DISPATCH(pGpu, pKernelFsp, pQueueHead, pQueueTail) +#define kfspUpdateMsgQueueHeadTail(pGpu, pKernelFsp, msgqHead, msgqTail) kfspUpdateMsgQueueHeadTail_DISPATCH(pGpu, pKernelFsp, msgqHead, msgqTail) +#define kfspUpdateMsgQueueHeadTail_HAL(pGpu, pKernelFsp, msgqHead, msgqTail) kfspUpdateMsgQueueHeadTail_DISPATCH(pGpu, pKernelFsp, msgqHead, msgqTail) +#define kfspGetMsgQueueHeadTail(pGpu, pKernelFsp, pMsgqHead, pMsgqTail) kfspGetMsgQueueHeadTail_DISPATCH(pGpu, pKernelFsp, pMsgqHead, pMsgqTail) +#define kfspGetMsgQueueHeadTail_HAL(pGpu, pKernelFsp, pMsgqHead, pMsgqTail) kfspGetMsgQueueHeadTail_DISPATCH(pGpu, pKernelFsp, pMsgqHead, pMsgqTail) +#define kfspNvdmToSeid(pGpu, pKernelFsp, nvdmType) kfspNvdmToSeid_DISPATCH(pGpu, pKernelFsp, nvdmType) +#define kfspNvdmToSeid_HAL(pGpu, pKernelFsp, nvdmType) kfspNvdmToSeid_DISPATCH(pGpu, pKernelFsp, nvdmType) +#define kfspCreateMctpHeader(pGpu, pKernelFsp, som, eom, seid, seq) kfspCreateMctpHeader_DISPATCH(pGpu, pKernelFsp, som, eom, seid, seq) +#define kfspCreateMctpHeader_HAL(pGpu, pKernelFsp, som, eom, seid, seq) kfspCreateMctpHeader_DISPATCH(pGpu, pKernelFsp, som, eom, seid, seq) +#define kfspCreateNvdmHeader(pGpu, pKernelFsp, nvdmType) kfspCreateNvdmHeader_DISPATCH(pGpu, pKernelFsp, nvdmType) +#define kfspCreateNvdmHeader_HAL(pGpu, pKernelFsp, nvdmType) kfspCreateNvdmHeader_DISPATCH(pGpu, pKernelFsp, nvdmType) +#define kfspWriteToEmem(pGpu, pKernelFsp, pBuffer, size) kfspWriteToEmem_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspWriteToEmem_HAL(pGpu, pKernelFsp, pBuffer, size) kfspWriteToEmem_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspReadFromEmem(pGpu, pKernelFsp, pBuffer, size) kfspReadFromEmem_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspReadFromEmem_HAL(pGpu, pKernelFsp, pBuffer, size) kfspReadFromEmem_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspGetPacketInfo(pGpu, pKernelFsp, pBuffer, size, pPacketState, pTag) kfspGetPacketInfo_DISPATCH(pGpu, pKernelFsp, pBuffer, size, pPacketState, pTag) +#define kfspGetPacketInfo_HAL(pGpu, pKernelFsp, pBuffer, size, pPacketState, pTag) kfspGetPacketInfo_DISPATCH(pGpu, pKernelFsp, pBuffer, size, pPacketState, pTag) +#define kfspValidateMctpPayloadHeader(pGpu, pKernelFsp, pBuffer, size) kfspValidateMctpPayloadHeader_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspValidateMctpPayloadHeader_HAL(pGpu, pKernelFsp, pBuffer, size) kfspValidateMctpPayloadHeader_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspProcessNvdmMessage(pGpu, pKernelFsp, pBuffer, size) kfspProcessNvdmMessage_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspProcessNvdmMessage_HAL(pGpu, pKernelFsp, pBuffer, size) kfspProcessNvdmMessage_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspProcessCommandResponse(pGpu, pKernelFsp, pBuffer, size) kfspProcessCommandResponse_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspProcessCommandResponse_HAL(pGpu, pKernelFsp, pBuffer, size) kfspProcessCommandResponse_DISPATCH(pGpu, pKernelFsp, pBuffer, size) +#define kfspDumpDebugState(pGpu, pKernelFsp) kfspDumpDebugState_DISPATCH(pGpu, pKernelFsp) +#define kfspDumpDebugState_HAL(pGpu, pKernelFsp) kfspDumpDebugState_DISPATCH(pGpu, pKernelFsp) +#define kfspErrorCode2NvStatusMap(pGpu, pKernelFsp, errorCode) kfspErrorCode2NvStatusMap_DISPATCH(pGpu, pKernelFsp, errorCode) +#define kfspErrorCode2NvStatusMap_HAL(pGpu, pKernelFsp, errorCode) kfspErrorCode2NvStatusMap_DISPATCH(pGpu, pKernelFsp, errorCode) +#define kfspCheckGspSecureScratch(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) +#define kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) +#define kfspReconcileTunableState(pGpu, pEngstate, pTunableState) kfspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kfspStateLoad(pGpu, pEngstate, arg0) kfspStateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kfspStateUnload(pGpu, pEngstate, arg0) kfspStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kfspStateInitLocked(pGpu, pEngstate) kfspStateInitLocked_DISPATCH(pGpu, pEngstate) +#define kfspStatePreLoad(pGpu, pEngstate, arg0) kfspStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kfspStatePostUnload(pGpu, pEngstate, arg0) kfspStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kfspStatePreUnload(pGpu, pEngstate, arg0) kfspStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kfspStateInitUnlocked(pGpu, pEngstate) kfspStateInitUnlocked_DISPATCH(pGpu, pEngstate) +#define kfspInitMissing(pGpu, pEngstate) kfspInitMissing_DISPATCH(pGpu, pEngstate) +#define kfspStatePreInitLocked(pGpu, pEngstate) kfspStatePreInitLocked_DISPATCH(pGpu, pEngstate) +#define kfspStatePreInitUnlocked(pGpu, pEngstate) kfspStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define kfspGetTunableState(pGpu, pEngstate, pTunableState) kfspGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kfspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kfspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) +#define kfspFreeTunableState(pGpu, pEngstate, pTunableState) kfspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kfspStatePostLoad(pGpu, pEngstate, arg0) kfspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kfspAllocTunableState(pGpu, pEngstate, ppTunableState) kfspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) +#define kfspSetTunableState(pGpu, pEngstate, pTunableState) kfspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kfspIsPresent(pGpu, pEngstate) kfspIsPresent_DISPATCH(pGpu, pEngstate) +NV_STATUS kfspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, ENGDESCRIPTOR arg0); + +static inline NV_STATUS kfspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, ENGDESCRIPTOR arg0) { + return pKernelFsp->__kfspConstructEngine__(pGpu, pKernelFsp, arg0); +} + +void kfspStateDestroy_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline void kfspStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + pKernelFsp->__kfspStateDestroy__(pGpu, pKernelFsp); +} + +void kfspSecureReset_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline void kfspSecureReset_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + pKernelFsp->__kfspSecureReset__(pGpu, pKernelFsp); +} + +NV_STATUS kfspSendPacket_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pPacket, NvU32 packetSize); + +static inline NV_STATUS kfspSendPacket_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pPacket, NvU32 packetSize) { + return pKernelFsp->__kfspSendPacket__(pGpu, pKernelFsp, pPacket, packetSize); +} + +NV_STATUS kfspSendAndReadMessage_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pPayload, NvU32 size, NvU32 nvdmType, NvU8 *pResponsePayload, NvU32 responseBufferSize); + +static inline NV_STATUS kfspSendAndReadMessage_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pPayload, NvU32 size, NvU32 nvdmType, NvU8 *pResponsePayload, NvU32 responseBufferSize) { + return pKernelFsp->__kfspSendAndReadMessage__(pGpu, pKernelFsp, pPayload, size, nvdmType, pResponsePayload, responseBufferSize); +} + +NvBool kfspIsQueueEmpty_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvBool kfspIsQueueEmpty_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspIsQueueEmpty__(pGpu, pKernelFsp); +} + +NV_STATUS kfspPollForQueueEmpty_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspPollForQueueEmpty_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspPollForQueueEmpty__(pGpu, pKernelFsp); +} + +NvBool kfspIsMsgQueueEmpty_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvBool kfspIsMsgQueueEmpty_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspIsMsgQueueEmpty__(pGpu, pKernelFsp); +} + +NV_STATUS kfspPollForResponse_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspPollForResponse_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspPollForResponse__(pGpu, pKernelFsp); +} + +NvBool kfspGspFmcIsEnforced_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvBool kfspGspFmcIsEnforced_491d52(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kfspGspFmcIsEnforced_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspGspFmcIsEnforced__(pGpu, pKernelFsp); +} + +NV_STATUS kfspSendBootCommands_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspSendBootCommands_ac1694(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_OK; +} + +static inline NV_STATUS kfspSendBootCommands_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspSendBootCommands__(pGpu, pKernelFsp); +} + +NV_STATUS kfspWaitForSecureBoot_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspWaitForSecureBoot_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspWaitForSecureBoot_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspWaitForSecureBoot__(pGpu, pKernelFsp); +} + +NvU32 kfspGetRmChannelSize_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvU32 kfspGetRmChannelSize_b2b553(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return 0; +} + +static inline NvU32 kfspGetRmChannelSize_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspGetRmChannelSize__(pGpu, pKernelFsp); +} + +NV_STATUS kfspConfigEmemc_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 offset, NvBool bAincw, NvBool bAincr); + +static inline NV_STATUS kfspConfigEmemc_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 offset, NvBool bAincw, NvBool bAincr) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspConfigEmemc_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 offset, NvBool bAincw, NvBool bAincr) { + return pKernelFsp->__kfspConfigEmemc__(pGpu, pKernelFsp, offset, bAincw, bAincr); +} + +void kfspUpdateQueueHeadTail_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 queueHead, NvU32 queueTail); + +static inline void kfspUpdateQueueHeadTail_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 queueHead, NvU32 queueTail) { + return; +} + +static inline void kfspUpdateQueueHeadTail_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 queueHead, NvU32 queueTail) { + pKernelFsp->__kfspUpdateQueueHeadTail__(pGpu, pKernelFsp, queueHead, queueTail); +} + +void kfspGetQueueHeadTail_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pQueueHead, NvU32 *pQueueTail); + +static inline void kfspGetQueueHeadTail_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pQueueHead, NvU32 *pQueueTail) { + return; +} + +static inline void kfspGetQueueHeadTail_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pQueueHead, NvU32 *pQueueTail) { + pKernelFsp->__kfspGetQueueHeadTail__(pGpu, pKernelFsp, pQueueHead, pQueueTail); +} + +void kfspUpdateMsgQueueHeadTail_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 msgqHead, NvU32 msgqTail); + +static inline void kfspUpdateMsgQueueHeadTail_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 msgqHead, NvU32 msgqTail) { + return; +} + +static inline void kfspUpdateMsgQueueHeadTail_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 msgqHead, NvU32 msgqTail) { + pKernelFsp->__kfspUpdateMsgQueueHeadTail__(pGpu, pKernelFsp, msgqHead, msgqTail); +} + +void kfspGetMsgQueueHeadTail_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pMsgqHead, NvU32 *pMsgqTail); + +static inline void kfspGetMsgQueueHeadTail_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pMsgqHead, NvU32 *pMsgqTail) { + return; +} + +static inline void kfspGetMsgQueueHeadTail_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 *pMsgqHead, NvU32 *pMsgqTail) { + pKernelFsp->__kfspGetMsgQueueHeadTail__(pGpu, pKernelFsp, pMsgqHead, pMsgqTail); +} + +NvU8 kfspNvdmToSeid_GH100(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType); + +static inline NvU8 kfspNvdmToSeid_b2b553(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { + return 0; +} + +static inline NvU8 kfspNvdmToSeid_DISPATCH(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { + return pKernelFsp->__kfspNvdmToSeid__(pGpu, pKernelFsp, nvdmType); +} + +NvU32 kfspCreateMctpHeader_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); + +static inline NvU32 kfspCreateMctpHeader_b2b553(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq) { + return 0; +} + +static inline NvU32 kfspCreateMctpHeader_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq) { + return pKernelFsp->__kfspCreateMctpHeader__(pGpu, pKernelFsp, som, eom, seid, seq); +} + +NvU32 kfspCreateNvdmHeader_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 nvdmType); + +static inline NvU32 kfspCreateNvdmHeader_b2b553(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 nvdmType) { + return 0; +} + +static inline NvU32 kfspCreateNvdmHeader_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 nvdmType) { + return pKernelFsp->__kfspCreateNvdmHeader__(pGpu, pKernelFsp, nvdmType); +} + +NV_STATUS kfspWriteToEmem_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size); + +static inline NV_STATUS kfspWriteToEmem_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspWriteToEmem_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return pKernelFsp->__kfspWriteToEmem__(pGpu, pKernelFsp, pBuffer, size); +} + +NV_STATUS kfspReadFromEmem_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size); + +static inline NV_STATUS kfspReadFromEmem_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspReadFromEmem_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return pKernelFsp->__kfspReadFromEmem__(pGpu, pKernelFsp, pBuffer, size); +} + +NV_STATUS kfspGetPacketInfo_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size, MCTP_PACKET_STATE *pPacketState, NvU8 *pTag); + +static inline NV_STATUS kfspGetPacketInfo_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size, MCTP_PACKET_STATE *pPacketState, NvU8 *pTag) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspGetPacketInfo_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size, MCTP_PACKET_STATE *pPacketState, NvU8 *pTag) { + return pKernelFsp->__kfspGetPacketInfo__(pGpu, pKernelFsp, pBuffer, size, pPacketState, pTag); +} + +NV_STATUS kfspValidateMctpPayloadHeader_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size); + +static inline NV_STATUS kfspValidateMctpPayloadHeader_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspValidateMctpPayloadHeader_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return pKernelFsp->__kfspValidateMctpPayloadHeader__(pGpu, pKernelFsp, pBuffer, size); +} + +NV_STATUS kfspProcessNvdmMessage_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size); + +static inline NV_STATUS kfspProcessNvdmMessage_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspProcessNvdmMessage_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return pKernelFsp->__kfspProcessNvdmMessage__(pGpu, pKernelFsp, pBuffer, size); +} + +NV_STATUS kfspProcessCommandResponse_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size); + +static inline NV_STATUS kfspProcessCommandResponse_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspProcessCommandResponse_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 *pBuffer, NvU32 size) { + return pKernelFsp->__kfspProcessCommandResponse__(pGpu, pKernelFsp, pBuffer, size); +} + +void kfspDumpDebugState_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline void kfspDumpDebugState_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return; +} + +static inline void kfspDumpDebugState_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + pKernelFsp->__kfspDumpDebugState__(pGpu, pKernelFsp); +} + +NV_STATUS kfspErrorCode2NvStatusMap_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 errorCode); + +static inline NV_STATUS kfspErrorCode2NvStatusMap_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 errorCode) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspErrorCode2NvStatusMap_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU32 errorCode) { + return pKernelFsp->__kfspErrorCode2NvStatusMap__(pGpu, pKernelFsp, errorCode); +} + +NvBool kfspCheckGspSecureScratch_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvBool kfspCheckGspSecureScratch_491d52(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kfspCheckGspSecureScratch_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspCheckGspSecureScratch__(pGpu, pKernelFsp); +} + +static inline NV_STATUS kfspReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return pEngstate->__kfspReconcileTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kfspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStateLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspStateUnload_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStateUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return pEngstate->__kfspStateInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kfspStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStatePreLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStatePostUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStatePreUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return pEngstate->__kfspStateInitUnlocked__(pGpu, pEngstate); +} + +static inline void kfspInitMissing_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + pEngstate->__kfspInitMissing__(pGpu, pEngstate); +} + +static inline NV_STATUS kfspStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return pEngstate->__kfspStatePreInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kfspStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return pEngstate->__kfspStatePreInitUnlocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kfspGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return pEngstate->__kfspGetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kfspCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { + return pEngstate->__kfspCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +} + +static inline void kfspFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + pEngstate->__kfspFreeTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kfspStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { + return pEngstate->__kfspStatePostLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kfspAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { + return pEngstate->__kfspAllocTunableState__(pGpu, pEngstate, ppTunableState); +} + +static inline NV_STATUS kfspSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { + return pEngstate->__kfspSetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NvBool kfspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { + return pEngstate->__kfspIsPresent__(pGpu, pEngstate); +} + +#undef PRIVATE_FIELD + + +#endif // KERN_FSP_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERN_FSP_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 5a6751ade..5ec7c1151 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -199,7 +199,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED, ((NvBool)(0 == 0))); } @@ -213,7 +213,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->defaultBigPageSize = (64 * 1024); } @@ -222,7 +222,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals } // Hal field -- bHugePageSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bHugePageSupported = ((NvBool)(0 == 0)); } @@ -233,7 +233,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals } // Hal field -- bPageSize512mbSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bPageSize512mbSupported = ((NvBool)(0 == 0)); } @@ -255,7 +255,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals } // Hal field -- bVaspaceInteropSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bVaspaceInteropSupported = ((NvBool)(0 == 0)); } @@ -327,7 +327,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_f03539; } @@ -346,13 +346,13 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_4a4dee; } // Hal function -- kgmmuSetTlbInvalidationScope - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; } @@ -361,6 +361,86 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_46f6a7; } + // Hal function -- kgmmuFmtInitPteComptagLine + if (0) + { + } + else if (0) + { + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; + } + + // Hal function -- kgmmuFmtInitPeerPteFld + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; + } + + // Hal function -- kgmmuFmtInitPte + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; + } + else if (0) + { + } + + // Hal function -- kgmmuFmtInitPde + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; + } + else if (0) + { + } + + // Hal function -- kgmmuFmtIsVersionSupported + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; + } + else if (0) + { + } + // Hal function -- kgmmuFmtInitLevels if (0) { @@ -369,27 +449,117 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; + } else if (0) { } + + // Hal function -- kgmmuFmtInitPdeMulti + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; + } else if (0) { } + // Hal function -- kgmmuFmtFamiliesInit + if (0) + { + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; + } + else if (0) + { + } + + // Hal function -- kgmmuTranslatePtePcfFromSw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_56cd7a; + } + + // Hal function -- kgmmuTranslatePtePcfFromHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_56cd7a; + } + + // Hal function -- kgmmuTranslatePdePcfFromSw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_56cd7a; + } + + // Hal function -- kgmmuTranslatePdePcfFromHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_56cd7a; + } + // Hal function -- kgmmuSetupWarForBug2720120 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_56cd7a; } + // Hal function -- kgmmuGetGraphicsEngineId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; + } + // default + else + { + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelGmmu_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index 54b2137e8..13b8cdf26 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -281,8 +281,20 @@ struct KernelGmmu { NV_STATUS (*__kgmmuInstBlkVaLimitGet__)(struct KernelGmmu *, struct OBJVASPACE *, NvU32, INST_BLK_INIT_PARAMS *, NvU32 *, NvU64 *); NvU32 (*__kgmmuSetTlbInvalidateMembarWarParameters__)(OBJGPU *, struct KernelGmmu *, TLB_INVALIDATE_PARAMS *); NV_STATUS (*__kgmmuSetTlbInvalidationScope__)(OBJGPU *, struct KernelGmmu *, NvU32, TLB_INVALIDATE_PARAMS *); + void (*__kgmmuFmtInitPteComptagLine__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32); + void (*__kgmmuFmtInitPeerPteFld__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32); + void (*__kgmmuFmtInitPte__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *, const NvBool); + void (*__kgmmuFmtInitPde__)(struct KernelGmmu *, struct GMMU_FMT_PDE *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *); + NvBool (*__kgmmuFmtIsVersionSupported__)(struct KernelGmmu *, NvU32); void (*__kgmmuFmtInitLevels__)(struct KernelGmmu *, MMU_FMT_LEVEL *, const NvU32, const NvU32, const NvU32); + void (*__kgmmuFmtInitPdeMulti__)(struct KernelGmmu *, struct GMMU_FMT_PDE_MULTI *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *); + NV_STATUS (*__kgmmuFmtFamiliesInit__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuTranslatePtePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); + NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); + NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); + NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); + NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); @@ -304,7 +316,7 @@ struct KernelGmmu { NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - GMMU_FMT_FAMILY *pFmtFamilies[2]; + GMMU_FMT_FAMILY *pFmtFamilies[3]; NvU32 defaultBigPageSize; NvU32 PDEAperture; NvU32 PDEAttr; @@ -378,10 +390,34 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuSetTlbInvalidateMembarWarParameters_HAL(pGpu, pKernelGmmu, pParams) kgmmuSetTlbInvalidateMembarWarParameters_DISPATCH(pGpu, pKernelGmmu, pParams) #define kgmmuSetTlbInvalidationScope(pGpu, pKernelGmmu, flags, pParams) kgmmuSetTlbInvalidationScope_DISPATCH(pGpu, pKernelGmmu, flags, pParams) #define kgmmuSetTlbInvalidationScope_HAL(pGpu, pKernelGmmu, flags, pParams) kgmmuSetTlbInvalidationScope_DISPATCH(pGpu, pKernelGmmu, flags, pParams) +#define kgmmuFmtInitPteComptagLine(pKernelGmmu, pPte, version) kgmmuFmtInitPteComptagLine_DISPATCH(pKernelGmmu, pPte, version) +#define kgmmuFmtInitPteComptagLine_HAL(pKernelGmmu, pPte, version) kgmmuFmtInitPteComptagLine_DISPATCH(pKernelGmmu, pPte, version) +#define kgmmuFmtInitPeerPteFld(pKernelGmmu, pPte, version) kgmmuFmtInitPeerPteFld_DISPATCH(pKernelGmmu, pPte, version) +#define kgmmuFmtInitPeerPteFld_HAL(pKernelGmmu, pPte, version) kgmmuFmtInitPeerPteFld_DISPATCH(pKernelGmmu, pPte, version) +#define kgmmuFmtInitPte(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) kgmmuFmtInitPte_DISPATCH(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) +#define kgmmuFmtInitPte_HAL(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) kgmmuFmtInitPte_DISPATCH(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) +#define kgmmuFmtInitPde(pKernelGmmu, pPde, version, pPdeApertures) kgmmuFmtInitPde_DISPATCH(pKernelGmmu, pPde, version, pPdeApertures) +#define kgmmuFmtInitPde_HAL(pKernelGmmu, pPde, version, pPdeApertures) kgmmuFmtInitPde_DISPATCH(pKernelGmmu, pPde, version, pPdeApertures) +#define kgmmuFmtIsVersionSupported(pKernelGmmu, version) kgmmuFmtIsVersionSupported_DISPATCH(pKernelGmmu, version) +#define kgmmuFmtIsVersionSupported_HAL(pKernelGmmu, version) kgmmuFmtIsVersionSupported_DISPATCH(pKernelGmmu, version) #define kgmmuFmtInitLevels(pKernelGmmu, pLevels, numLevels, version, bigPageShift) kgmmuFmtInitLevels_DISPATCH(pKernelGmmu, pLevels, numLevels, version, bigPageShift) #define kgmmuFmtInitLevels_HAL(pKernelGmmu, pLevels, numLevels, version, bigPageShift) kgmmuFmtInitLevels_DISPATCH(pKernelGmmu, pLevels, numLevels, version, bigPageShift) +#define kgmmuFmtInitPdeMulti(pKernelGmmu, pPdeMulti, version, pPdeApertures) kgmmuFmtInitPdeMulti_DISPATCH(pKernelGmmu, pPdeMulti, version, pPdeApertures) +#define kgmmuFmtInitPdeMulti_HAL(pKernelGmmu, pPdeMulti, version, pPdeApertures) kgmmuFmtInitPdeMulti_DISPATCH(pKernelGmmu, pPdeMulti, version, pPdeApertures) +#define kgmmuFmtFamiliesInit(pGpu, pKernelGmmu) kgmmuFmtFamiliesInit_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFmtFamiliesInit_HAL(pGpu, pKernelGmmu) kgmmuFmtFamiliesInit_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuTranslatePtePcfFromSw(pKernelGmmu, arg0, arg1) kgmmuTranslatePtePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePtePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuTranslatePtePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePtePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) +#define kgmmuTranslatePtePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePtePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) +#define kgmmuTranslatePdePcfFromSw(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuTranslatePdePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) +#define kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) #define kgmmuSetupWarForBug2720120(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuSetupWarForBug2720120_HAL(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) +#define kgmmuGetGraphicsEngineId(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) +#define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuReconcileTunableState(pGpu, pEngstate, pTunableState) kgmmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -579,79 +615,6 @@ static inline void kgmmuSetPdbToInvalidate(OBJGPU *pGpu, struct KernelGmmu *pKer #define kgmmuSetPdbToInvalidate_HAL(pGpu, pKernelGmmu, pParams) kgmmuSetPdbToInvalidate(pGpu, pKernelGmmu, pParams) -void kgmmuFmtInitPteComptagLine_TU10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuFmtInitPteComptagLine(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtInitPteComptagLine(pKernelGmmu, pPte, version) kgmmuFmtInitPteComptagLine_TU10X(pKernelGmmu, pPte, version) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtInitPteComptagLine_HAL(pKernelGmmu, pPte, version) kgmmuFmtInitPteComptagLine(pKernelGmmu, pPte, version) - -void kgmmuFmtInitPeerPteFld_TU10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuFmtInitPeerPteFld(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtInitPeerPteFld(pKernelGmmu, pPte, version) kgmmuFmtInitPeerPteFld_TU10X(pKernelGmmu, pPte, version) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtInitPeerPteFld_HAL(pKernelGmmu, pPte, version) kgmmuFmtInitPeerPteFld(pKernelGmmu, pPte, version) - -void kgmmuFmtInitPte_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuFmtInitPte(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtInitPte(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) kgmmuFmtInitPte_GP10X(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtInitPte_HAL(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) kgmmuFmtInitPte(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture) - -void kgmmuFmtInitPde_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuFmtInitPde(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtInitPde(pKernelGmmu, pPde, version, pPdeApertures) kgmmuFmtInitPde_GP10X(pKernelGmmu, pPde, version, pPdeApertures) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtInitPde_HAL(pKernelGmmu, pPde, version, pPdeApertures) kgmmuFmtInitPde(pKernelGmmu, pPde, version, pPdeApertures) - -NvBool kgmmuFmtIsVersionSupported_GP10X(struct KernelGmmu *pKernelGmmu, NvU32 version); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NvBool kgmmuFmtIsVersionSupported(struct KernelGmmu *pKernelGmmu, NvU32 version) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtIsVersionSupported(pKernelGmmu, version) kgmmuFmtIsVersionSupported_GP10X(pKernelGmmu, version) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtIsVersionSupported_HAL(pKernelGmmu, version) kgmmuFmtIsVersionSupported(pKernelGmmu, version) - -void kgmmuFmtInitPdeMulti_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuFmtInitPdeMulti(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtInitPdeMulti(pKernelGmmu, pPdeMulti, version, pPdeApertures) kgmmuFmtInitPdeMulti_GP10X(pKernelGmmu, pPdeMulti, version, pPdeApertures) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtInitPdeMulti_HAL(pKernelGmmu, pPdeMulti, version, pPdeApertures) kgmmuFmtInitPdeMulti(pKernelGmmu, pPdeMulti, version, pPdeApertures) - void kgmmuDetermineMaxVASize_GM107(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled @@ -664,79 +627,6 @@ static inline void kgmmuDetermineMaxVASize(OBJGPU *pGpu, struct KernelGmmu *pKer #define kgmmuDetermineMaxVASize_HAL(pGpu, pKernelGmmu) kgmmuDetermineMaxVASize(pGpu, pKernelGmmu) -NV_STATUS kgmmuFmtFamiliesInit_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuFmtFamiliesInit(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuFmtFamiliesInit(pGpu, pKernelGmmu) kgmmuFmtFamiliesInit_TU102(pGpu, pKernelGmmu) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuFmtFamiliesInit_HAL(pGpu, pKernelGmmu) kgmmuFmtFamiliesInit(pGpu, pKernelGmmu) - -static inline NV_STATUS kgmmuTranslatePtePcfFromSw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { - return NV_OK; -} - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuTranslatePtePcfFromSw(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuTranslatePtePcfFromSw(pKernelGmmu, arg0, arg1) kgmmuTranslatePtePcfFromSw_56cd7a(pKernelGmmu, arg0, arg1) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePtePcfFromSw(pKernelGmmu, arg0, arg1) - -static inline NV_STATUS kgmmuTranslatePtePcfFromHw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvBool arg1, NvU32 *arg2) { - return NV_OK; -} - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuTranslatePtePcfFromHw(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvBool arg1, NvU32 *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuTranslatePtePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePtePcfFromHw_56cd7a(pKernelGmmu, arg0, arg1, arg2) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuTranslatePtePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePtePcfFromHw(pKernelGmmu, arg0, arg1, arg2) - -static inline NV_STATUS kgmmuTranslatePdePcfFromSw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { - return NV_OK; -} - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuTranslatePdePcfFromSw(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuTranslatePdePcfFromSw(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw_56cd7a(pKernelGmmu, arg0, arg1) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw(pKernelGmmu, arg0, arg1) - -static inline NV_STATUS kgmmuTranslatePdePcfFromHw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, GMMU_APERTURE arg1, NvU32 *arg2) { - return NV_OK; -} - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuTranslatePdePcfFromHw(struct KernelGmmu *pKernelGmmu, NvU32 arg0, GMMU_APERTURE arg1, NvU32 *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuTranslatePdePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_56cd7a(pKernelGmmu, arg0, arg1, arg2) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw(pKernelGmmu, arg0, arg1, arg2) - NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); #ifdef __nvoc_kern_gmmu_h_disabled @@ -943,19 +833,6 @@ static inline NvBool kgmmuTestAccessCounterWriteNak(OBJGPU *pGpu, struct KernelG #define kgmmuTestAccessCounterWriteNak_HAL(pGpu, pKernelGmmu) kgmmuTestAccessCounterWriteNak(pGpu, pKernelGmmu) -NvU32 kgmmuGetGraphicsEngineId_GV100(struct KernelGmmu *pKernelGmmu); - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetGraphicsEngineId(struct KernelGmmu *pKernelGmmu) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return 0; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuGetGraphicsEngineId(pKernelGmmu) kgmmuGetGraphicsEngineId_GV100(pKernelGmmu) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId(pKernelGmmu) - NV_STATUS kgmmuEnableNvlinkComputePeerAddressing_GV100(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled @@ -1040,10 +917,68 @@ static inline NV_STATUS kgmmuSetTlbInvalidationScope_DISPATCH(OBJGPU *pGpu, stru return pKernelGmmu->__kgmmuSetTlbInvalidationScope__(pGpu, pKernelGmmu, flags, pParams); } +void kgmmuFmtInitPteComptagLine_TU10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version); + +static inline void kgmmuFmtInitPteComptagLine_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { + return; +} + +static inline void kgmmuFmtInitPteComptagLine_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { + pKernelGmmu->__kgmmuFmtInitPteComptagLine__(pKernelGmmu, pPte, version); +} + +void kgmmuFmtInitPeerPteFld_TU10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version); + +static inline void kgmmuFmtInitPeerPteFld_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { + return; +} + +static inline void kgmmuFmtInitPeerPteFld_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version) { + pKernelGmmu->__kgmmuFmtInitPeerPteFld__(pKernelGmmu, pPte, version); +} + +void kgmmuFmtInitPte_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture); + +void kgmmuFmtInitPte_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture); + +static inline void kgmmuFmtInitPte_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture) { + return; +} + +static inline void kgmmuFmtInitPte_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture) { + pKernelGmmu->__kgmmuFmtInitPte__(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture); +} + +void kgmmuFmtInitPde_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); + +void kgmmuFmtInitPde_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); + +static inline void kgmmuFmtInitPde_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { + return; +} + +static inline void kgmmuFmtInitPde_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { + pKernelGmmu->__kgmmuFmtInitPde__(pKernelGmmu, pPde, version, pPdeApertures); +} + +NvBool kgmmuFmtIsVersionSupported_GP10X(struct KernelGmmu *pKernelGmmu, NvU32 version); + +NvBool kgmmuFmtIsVersionSupported_GH10X(struct KernelGmmu *pKernelGmmu, NvU32 version); + +static inline NvBool kgmmuFmtIsVersionSupported_491d52(struct KernelGmmu *pKernelGmmu, NvU32 version) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kgmmuFmtIsVersionSupported_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 version) { + return pKernelGmmu->__kgmmuFmtIsVersionSupported__(pKernelGmmu, version); +} + void kgmmuFmtInitLevels_GP10X(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift); void kgmmuFmtInitLevels_GA10X(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift); +void kgmmuFmtInitLevels_GH10X(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift); + static inline void kgmmuFmtInitLevels_b3696a(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift) { return; } @@ -1052,6 +987,70 @@ static inline void kgmmuFmtInitLevels_DISPATCH(struct KernelGmmu *pKernelGmmu, M pKernelGmmu->__kgmmuFmtInitLevels__(pKernelGmmu, pLevels, numLevels, version, bigPageShift); } +void kgmmuFmtInitPdeMulti_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); + +void kgmmuFmtInitPdeMulti_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); + +static inline void kgmmuFmtInitPdeMulti_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { + return; +} + +static inline void kgmmuFmtInitPdeMulti_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { + pKernelGmmu->__kgmmuFmtInitPdeMulti__(pKernelGmmu, pPdeMulti, version, pPdeApertures); +} + +NV_STATUS kgmmuFmtFamiliesInit_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +NV_STATUS kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NV_STATUS kgmmuFmtFamiliesInit_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_OK; +} + +static inline NV_STATUS kgmmuFmtFamiliesInit_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuFmtFamiliesInit__(pGpu, pKernelGmmu); +} + +NV_STATUS kgmmuTranslatePtePcfFromSw_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1); + +static inline NV_STATUS kgmmuTranslatePtePcfFromSw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { + return NV_OK; +} + +static inline NV_STATUS kgmmuTranslatePtePcfFromSw_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { + return pKernelGmmu->__kgmmuTranslatePtePcfFromSw__(pKernelGmmu, arg0, arg1); +} + +NV_STATUS kgmmuTranslatePtePcfFromHw_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvBool arg1, NvU32 *arg2); + +static inline NV_STATUS kgmmuTranslatePtePcfFromHw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvBool arg1, NvU32 *arg2) { + return NV_OK; +} + +static inline NV_STATUS kgmmuTranslatePtePcfFromHw_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvBool arg1, NvU32 *arg2) { + return pKernelGmmu->__kgmmuTranslatePtePcfFromHw__(pKernelGmmu, arg0, arg1, arg2); +} + +NV_STATUS kgmmuTranslatePdePcfFromSw_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1); + +static inline NV_STATUS kgmmuTranslatePdePcfFromSw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { + return NV_OK; +} + +static inline NV_STATUS kgmmuTranslatePdePcfFromSw_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1) { + return pKernelGmmu->__kgmmuTranslatePdePcfFromSw__(pKernelGmmu, arg0, arg1); +} + +NV_STATUS kgmmuTranslatePdePcfFromHw_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0, GMMU_APERTURE arg1, NvU32 *arg2); + +static inline NV_STATUS kgmmuTranslatePdePcfFromHw_56cd7a(struct KernelGmmu *pKernelGmmu, NvU32 arg0, GMMU_APERTURE arg1, NvU32 *arg2) { + return NV_OK; +} + +static inline NV_STATUS kgmmuTranslatePdePcfFromHw_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0, GMMU_APERTURE arg1, NvU32 *arg2) { + return pKernelGmmu->__kgmmuTranslatePdePcfFromHw__(pKernelGmmu, arg0, arg1, arg2); +} + NV_STATUS kgmmuSetupWarForBug2720120_GA100(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam); static inline NV_STATUS kgmmuSetupWarForBug2720120_56cd7a(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam) { @@ -1062,6 +1061,18 @@ static inline NV_STATUS kgmmuSetupWarForBug2720120_DISPATCH(struct KernelGmmu *p return pKernelGmmu->__kgmmuSetupWarForBug2720120__(pKernelGmmu, pFam); } +NvU32 kgmmuGetGraphicsEngineId_GV100(struct KernelGmmu *pKernelGmmu); + +NvU32 kgmmuGetGraphicsEngineId_GH100(struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetGraphicsEngineId_4a4dee(struct KernelGmmu *pKernelGmmu) { + return 0; +} + +static inline NvU32 kgmmuGetGraphicsEngineId_DISPATCH(struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetGraphicsEngineId__(pKernelGmmu); +} + static inline NV_STATUS kgmmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { return pEngstate->__kgmmuReconcileTunableState__(pGpu, pEngstate, pTunableState); } diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index 32e009fb4..d8c9de3be 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -182,7 +182,7 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp } // Hal field -- bGpuCacheEnable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bGpuCacheEnable = ((NvBool)(0 == 0)); } @@ -196,7 +196,7 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp pThis->bNumaNodesAdded = ((NvBool)(0 != 0)); // Hal field -- bL2CleanFbPull - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bL2CleanFbPull = ((NvBool)(0 == 0)); } @@ -245,7 +245,7 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStateDestroy__ = &kmemsysStateDestroy_IMPL; // Hal function -- kmemsysGetFbNumaInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; } @@ -259,14 +259,103 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GP102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GA102; } // default else { - pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_5baef9; + } + + // Hal function -- kmemsysCacheOp + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; + } + else if (0) + { + } + + // Hal function -- kmemsysDoCacheOp + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; + } + else if (0) + { + } + + // Hal function -- kmemsysReadL2SysmemInvalidateReg + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; + } + + // Hal function -- kmemsysWriteL2SysmemInvalidateReg + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; + } + + // Hal function -- kmemsysReadL2PeermemInvalidateReg + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; + } + + // Hal function -- kmemsysWriteL2PeermemInvalidateReg + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; } // Hal function -- kmemsysInitFlushSysmemBuffer @@ -279,12 +368,13 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GH100; } else if (0) { @@ -300,7 +390,7 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x007003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | AD102 | AD103 | AD104 */ { pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; } @@ -308,8 +398,9 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; } else if (0) { @@ -343,7 +434,7 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; } @@ -371,6 +462,16 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } } + // Hal function -- kmemsysSwizzIdToVmmuSegmentsRange + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelMemorySystem_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 816412e97..714f26cdc 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -203,11 +203,18 @@ struct KernelMemorySystem { void (*__kmemsysStateDestroy__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysGetFbNumaInfo__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *, NvS32 *); NV_STATUS (*__kmemsysReadUsableFbSize__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *); + NV_STATUS (*__kmemsysCacheOp__)(OBJGPU *, struct KernelMemorySystem *, PMEMORY_DESCRIPTOR, FB_CACHE_MEMTYPE, FB_CACHE_OP); + NV_STATUS (*__kmemsysDoCacheOp__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32, PRMTIMEOUT); + NvU32 (*__kmemsysReadL2SysmemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *); + void (*__kmemsysWriteL2SysmemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NvU32 (*__kmemsysReadL2PeermemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *); + void (*__kmemsysWriteL2PeermemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysInitFlushSysmemBuffer__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysProgramSysmemFlushBuffer__)(OBJGPU *, struct KernelMemorySystem *); NvBool (*__kmemsysIsPagePLCable__)(OBJGPU *, struct KernelMemorySystem *, NvU64, NvU64); NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *); + NV_STATUS (*__kmemsysSwizzIdToVmmuSegmentsRange__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32); NV_STATUS (*__kmemsysReconcileTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); @@ -280,6 +287,18 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) #define kmemsysReadUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) kmemsysReadUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) #define kmemsysReadUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize) kmemsysReadUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) +#define kmemsysCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, operation) +#define kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, operation) +#define kmemsysDoCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) kmemsysDoCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) +#define kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) kmemsysDoCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) +#define kmemsysReadL2SysmemInvalidateReg(pGpu, pKernelMemorySystem) kmemsysReadL2SysmemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysReadL2SysmemInvalidateReg_HAL(pGpu, pKernelMemorySystem) kmemsysReadL2SysmemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysWriteL2SysmemInvalidateReg(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2SysmemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem, arg0) +#define kmemsysWriteL2SysmemInvalidateReg_HAL(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2SysmemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem, arg0) +#define kmemsysReadL2PeermemInvalidateReg(pGpu, pKernelMemorySystem) kmemsysReadL2PeermemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysReadL2PeermemInvalidateReg_HAL(pGpu, pKernelMemorySystem) kmemsysReadL2PeermemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysWriteL2PeermemInvalidateReg(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2PeermemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem, arg0) +#define kmemsysWriteL2PeermemInvalidateReg_HAL(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2PeermemInvalidateReg_DISPATCH(pGpu, pKernelMemorySystem, arg0) #define kmemsysInitFlushSysmemBuffer(pGpu, pKernelMemorySystem) kmemsysInitFlushSysmemBuffer_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysInitFlushSysmemBuffer_HAL(pGpu, pKernelMemorySystem) kmemsysInitFlushSysmemBuffer_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysProgramSysmemFlushBuffer(pGpu, pKernelMemorySystem) kmemsysProgramSysmemFlushBuffer_DISPATCH(pGpu, pKernelMemorySystem) @@ -290,6 +309,8 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysReadMIGMemoryCfg_HAL(pGpu, pKernelMemorySystem) kmemsysReadMIGMemoryCfg_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysInitMIGMemoryPartitionTable(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) +#define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) #define kmemsysReconcileTunableState(pGpu, pEngstate, pTunableState) kmemsysReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -319,82 +340,6 @@ static inline NV_STATUS kmemsysGetUsableFbSize(OBJGPU *pGpu, struct KernelMemory #define kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize) kmemsysGetUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) -NV_STATUS kmemsysCacheOp_GM200(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NV_STATUS kmemsysCacheOp(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp_GM200(pGpu, pKernelMemorySystem, arg0, arg1, operation) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, operation) - -NV_STATUS kmemsysDoCacheOp_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NV_STATUS kmemsysDoCacheOp(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysDoCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) kmemsysDoCacheOp_GM107(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) kmemsysDoCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) - -NvU32 kmemsysReadL2SysmemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NvU32 kmemsysReadL2SysmemInvalidateReg(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return 0; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysReadL2SysmemInvalidateReg(pGpu, pKernelMemorySystem) kmemsysReadL2SysmemInvalidateReg_TU102(pGpu, pKernelMemorySystem) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysReadL2SysmemInvalidateReg_HAL(pGpu, pKernelMemorySystem) kmemsysReadL2SysmemInvalidateReg(pGpu, pKernelMemorySystem) - -void kmemsysWriteL2SysmemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline void kmemsysWriteL2SysmemInvalidateReg(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysWriteL2SysmemInvalidateReg(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2SysmemInvalidateReg_TU102(pGpu, pKernelMemorySystem, arg0) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysWriteL2SysmemInvalidateReg_HAL(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2SysmemInvalidateReg(pGpu, pKernelMemorySystem, arg0) - -NvU32 kmemsysReadL2PeermemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NvU32 kmemsysReadL2PeermemInvalidateReg(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return 0; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysReadL2PeermemInvalidateReg(pGpu, pKernelMemorySystem) kmemsysReadL2PeermemInvalidateReg_TU102(pGpu, pKernelMemorySystem) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysReadL2PeermemInvalidateReg_HAL(pGpu, pKernelMemorySystem) kmemsysReadL2PeermemInvalidateReg(pGpu, pKernelMemorySystem) - -void kmemsysWriteL2PeermemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline void kmemsysWriteL2PeermemInvalidateReg(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysWriteL2PeermemInvalidateReg(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2PeermemInvalidateReg_TU102(pGpu, pKernelMemorySystem, arg0) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysWriteL2PeermemInvalidateReg_HAL(pGpu, pKernelMemorySystem, arg0) kmemsysWriteL2PeermemInvalidateReg(pGpu, pKernelMemorySystem, arg0) - static inline void kmemsysAssertSysmemFlushBufferValid_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return; } @@ -507,19 +452,6 @@ static inline void kmemsysFreeComprResources(OBJGPU *pGpu, struct KernelMemorySy #define kmemsysFreeComprResources_HAL(pGpu, pKernelMemorySystem, hwResId) kmemsysFreeComprResources(pGpu, pKernelMemorySystem, hwResId) -NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU32 vmmuSegmentSize, NvU32 totalVmmuSegments); - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU32 vmmuSegmentSize, NvU32 totalVmmuSegments) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_GA100(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) - NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); #ifdef __nvoc_kern_mem_sys_h_disabled @@ -579,6 +511,70 @@ static inline NV_STATUS kmemsysReadUsableFbSize_DISPATCH(OBJGPU *pGpu, struct Ke return pKernelMemorySystem->__kmemsysReadUsableFbSize__(pGpu, pKernelMemorySystem, pFbSize); } +NV_STATUS kmemsysCacheOp_GM200(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); + +NV_STATUS kmemsysCacheOp_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); + +static inline NV_STATUS kmemsysCacheOp_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation) { + return NV_OK; +} + +static inline NV_STATUS kmemsysCacheOp_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation) { + return pKernelMemorySystem->__kmemsysCacheOp__(pGpu, pKernelMemorySystem, arg0, arg1, operation); +} + +NV_STATUS kmemsysDoCacheOp_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3); + +NV_STATUS kmemsysDoCacheOp_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3); + +static inline NV_STATUS kmemsysDoCacheOp_46f6a7(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kmemsysDoCacheOp_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3) { + return pKernelMemorySystem->__kmemsysDoCacheOp__(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3); +} + +NvU32 kmemsysReadL2SysmemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysReadL2SysmemInvalidateReg_68b109(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + NV_ASSERT_OR_RETURN_PRECOMP(0, -1); +} + +static inline NvU32 kmemsysReadL2SysmemInvalidateReg_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysReadL2SysmemInvalidateReg__(pGpu, pKernelMemorySystem); +} + +void kmemsysWriteL2SysmemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0); + +static inline void kmemsysWriteL2SysmemInvalidateReg_f2d351(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kmemsysWriteL2SysmemInvalidateReg_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { + pKernelMemorySystem->__kmemsysWriteL2SysmemInvalidateReg__(pGpu, pKernelMemorySystem, arg0); +} + +NvU32 kmemsysReadL2PeermemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysReadL2PeermemInvalidateReg_68b109(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + NV_ASSERT_OR_RETURN_PRECOMP(0, -1); +} + +static inline NvU32 kmemsysReadL2PeermemInvalidateReg_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysReadL2PeermemInvalidateReg__(pGpu, pKernelMemorySystem); +} + +void kmemsysWriteL2PeermemInvalidateReg_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0); + +static inline void kmemsysWriteL2PeermemInvalidateReg_f2d351(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kmemsysWriteL2PeermemInvalidateReg_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0) { + pKernelMemorySystem->__kmemsysWriteL2PeermemInvalidateReg__(pGpu, pKernelMemorySystem, arg0); +} + static inline NV_STATUS kmemsysInitFlushSysmemBuffer_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return NV_OK; } @@ -587,6 +583,8 @@ NV_STATUS kmemsysInitFlushSysmemBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySy NV_STATUS kmemsysInitFlushSysmemBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +NV_STATUS kmemsysInitFlushSysmemBuffer_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + static inline NV_STATUS kmemsysInitFlushSysmemBuffer_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return pKernelMemorySystem->__kmemsysInitFlushSysmemBuffer__(pGpu, pKernelMemorySystem); } @@ -599,6 +597,8 @@ void kmemsysProgramSysmemFlushBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySyst void kmemsysProgramSysmemFlushBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +void kmemsysProgramSysmemFlushBuffer_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + static inline void kmemsysProgramSysmemFlushBuffer_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { pKernelMemorySystem->__kmemsysProgramSysmemFlushBuffer__(pGpu, pKernelMemorySystem); } @@ -639,6 +639,14 @@ static inline NV_STATUS kmemsysInitMIGMemoryPartitionTable_DISPATCH(OBJGPU *pGpu return pKernelMemorySystem->__kmemsysInitMIGMemoryPartitionTable__(pGpu, pKernelMemorySystem); } +NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU32 vmmuSegmentSize, NvU32 totalVmmuSegments); + +NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU32 vmmuSegmentSize, NvU32 totalVmmuSegments); + +static inline NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU32 vmmuSegmentSize, NvU32 totalVmmuSegments) { + return pKernelMemorySystem->__kmemsysSwizzIdToVmmuSegmentsRange__(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments); +} + static inline NV_STATUS kmemsysReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { return pEngstate->__kmemsysReconcileTunableState__(pGpu, pEngstate, pTunableState); } diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index fb802d79d..f3f65a252 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index e4f926e9d..d503a910d 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -171,7 +171,7 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF, ((NvBool)(0 == 0))); } @@ -182,7 +182,7 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN, ((NvBool)(0 == 0))); } @@ -193,8 +193,9 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->setProperty(pThis, PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI, ((NvBool)(0 != 0))); } // default else @@ -223,7 +224,7 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944, ((NvBool)(0 == 0))); } @@ -292,19 +293,229 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; } + // Hal function -- kbifGetXveStatusBits + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; + } + else if (0) + { + } + + // Hal function -- kbifClearXveStatus + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; + } + else if (0) + { + } + + // Hal function -- kbifGetXveAerBits + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; + } + else if (0) + { + } + + // Hal function -- kbifClearXveAer + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; + } + else if (0) + { + } + + // Hal function -- kbifGetPcieConfigAccessTestRegisters + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; + } + } + + // Hal function -- kbifVerifyPcieConfigAccessTestRegisters + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_46f6a7; + } + } + + // Hal function -- kbifRearmMSI + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; + } + else if (0) + { + } + + // Hal function -- kbifIsMSIEnabledInHW + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; + } + else if (0) + { + } + + // Hal function -- kbifIsMSIXEnabledInHW + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; + } + else if (0) + { + } + // Hal function -- kbifIsPciIoAccessEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; } + // Hal function -- kbifIs3dController + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; + } + else if (0) + { + } + + // Hal function -- kbifExecC73War + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; + } + + // Hal function -- kbifEnableExtendedTagSupport + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; + } + // default + else + { + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_b3696a; + } + } + + // Hal function -- kbifPcieConfigEnableRelaxedOrdering + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; + } + else if (0) + { + } + } + + // Hal function -- kbifPcieConfigDisableRelaxedOrdering + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; + } + else if (0) + { + } + } + // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace if (0) { @@ -322,16 +533,82 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } } + // Hal function -- kbifEnableNoSnoop + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; + } + else if (0) + { + } + else if (0) + { + } + } + // Hal function -- kbifApplyWARBug3208922 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; } + // Hal function -- kbifProbePcieReqAtomicCaps + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; + } + // default + else + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; + } + } + + // Hal function -- kbifGetPciConfigSpacePriMirror + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GH100; + } + // default + else + { + } + + // Hal function -- kbifGetBusOptionsAddr + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; + } + else if (0) + { + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBif_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index a1a88dd29..0b29f90f4 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -93,9 +93,27 @@ struct KernelBif { NV_STATUS (*__kbifStateLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifStateUnload__)(struct OBJGPU *, struct KernelBif *, NvU32); + NV_STATUS (*__kbifGetXveStatusBits__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); + NV_STATUS (*__kbifClearXveStatus__)(struct OBJGPU *, struct KernelBif *, NvU32 *); + NV_STATUS (*__kbifGetXveAerBits__)(struct OBJGPU *, struct KernelBif *, NvU32 *); + NV_STATUS (*__kbifClearXveAer__)(struct OBJGPU *, struct KernelBif *, NvU32); + void (*__kbifGetPcieConfigAccessTestRegisters__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); + NV_STATUS (*__kbifVerifyPcieConfigAccessTestRegisters__)(struct OBJGPU *, struct KernelBif *, NvU32, NvU32); + void (*__kbifRearmMSI__)(struct OBJGPU *, struct KernelBif *); + NvBool (*__kbifIsMSIEnabledInHW__)(struct OBJGPU *, struct KernelBif *); + NvBool (*__kbifIsMSIXEnabledInHW__)(struct OBJGPU *, struct KernelBif *); NvBool (*__kbifIsPciIoAccessEnabled__)(struct OBJGPU *, struct KernelBif *); + NvBool (*__kbifIs3dController__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifExecC73War__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifEnableExtendedTagSupport__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifPcieConfigEnableRelaxedOrdering__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifPcieConfigDisableRelaxedOrdering__)(struct OBJGPU *, struct KernelBif *); void (*__kbifInitRelaxedOrderingFromEmulatedConfigSpace__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifEnableNoSnoop__)(struct OBJGPU *, struct KernelBif *, NvBool); void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifProbePcieReqAtomicCaps__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); + NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); NV_STATUS (*__kbifReconcileTunableState__)(POBJGPU, struct KernelBif *, void *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); @@ -131,6 +149,7 @@ struct KernelBif { NvU32 forceP2PType; NvBool peerMappingOverride; NvBool EnteredRecoverySinceErrorsLastChecked; + NvU32 osPcieAtomicsOpMask; }; #ifndef __NVOC_CLASS_KernelBif_TYPEDEF__ @@ -199,12 +218,48 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifStatePostLoad_HAL(pGpu, pKernelBif, arg0) kbifStatePostLoad_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload_HAL(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifGetXveStatusBits(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_DISPATCH(pGpu, pKernelBif, pBits, pStatus) +#define kbifGetXveStatusBits_HAL(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_DISPATCH(pGpu, pKernelBif, pBits, pStatus) +#define kbifClearXveStatus(pGpu, pKernelBif, pStatus) kbifClearXveStatus_DISPATCH(pGpu, pKernelBif, pStatus) +#define kbifClearXveStatus_HAL(pGpu, pKernelBif, pStatus) kbifClearXveStatus_DISPATCH(pGpu, pKernelBif, pStatus) +#define kbifGetXveAerBits(pGpu, pKernelBif, pBits) kbifGetXveAerBits_DISPATCH(pGpu, pKernelBif, pBits) +#define kbifGetXveAerBits_HAL(pGpu, pKernelBif, pBits) kbifGetXveAerBits_DISPATCH(pGpu, pKernelBif, pBits) +#define kbifClearXveAer(pGpu, pKernelBif, bits) kbifClearXveAer_DISPATCH(pGpu, pKernelBif, bits) +#define kbifClearXveAer_HAL(pGpu, pKernelBif, bits) kbifClearXveAer_DISPATCH(pGpu, pKernelBif, bits) +#define kbifGetPcieConfigAccessTestRegisters(pGpu, pKernelBif, pciStart, pcieStart) kbifGetPcieConfigAccessTestRegisters_DISPATCH(pGpu, pKernelBif, pciStart, pcieStart) +#define kbifGetPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, pciStart, pcieStart) kbifGetPcieConfigAccessTestRegisters_DISPATCH(pGpu, pKernelBif, pciStart, pcieStart) +#define kbifVerifyPcieConfigAccessTestRegisters(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) kbifVerifyPcieConfigAccessTestRegisters_DISPATCH(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) +#define kbifVerifyPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) kbifVerifyPcieConfigAccessTestRegisters_DISPATCH(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) +#define kbifRearmMSI(pGpu, pKernelBif) kbifRearmMSI_DISPATCH(pGpu, pKernelBif) +#define kbifRearmMSI_HAL(pGpu, pKernelBif) kbifRearmMSI_DISPATCH(pGpu, pKernelBif) +#define kbifIsMSIEnabledInHW(pGpu, pKernelBif) kbifIsMSIEnabledInHW_DISPATCH(pGpu, pKernelBif) +#define kbifIsMSIEnabledInHW_HAL(pGpu, pKernelBif) kbifIsMSIEnabledInHW_DISPATCH(pGpu, pKernelBif) +#define kbifIsMSIXEnabledInHW(pGpu, pKernelBif) kbifIsMSIXEnabledInHW_DISPATCH(pGpu, pKernelBif) +#define kbifIsMSIXEnabledInHW_HAL(pGpu, pKernelBif) kbifIsMSIXEnabledInHW_DISPATCH(pGpu, pKernelBif) #define kbifIsPciIoAccessEnabled(pGpu, pKernelBif) kbifIsPciIoAccessEnabled_DISPATCH(pGpu, pKernelBif) #define kbifIsPciIoAccessEnabled_HAL(pGpu, pKernelBif) kbifIsPciIoAccessEnabled_DISPATCH(pGpu, pKernelBif) +#define kbifIs3dController(pGpu, pKernelBif) kbifIs3dController_DISPATCH(pGpu, pKernelBif) +#define kbifIs3dController_HAL(pGpu, pKernelBif) kbifIs3dController_DISPATCH(pGpu, pKernelBif) +#define kbifExecC73War(pGpu, pKernelBif) kbifExecC73War_DISPATCH(pGpu, pKernelBif) +#define kbifExecC73War_HAL(pGpu, pKernelBif) kbifExecC73War_DISPATCH(pGpu, pKernelBif) +#define kbifEnableExtendedTagSupport(pGpu, pKernelBif) kbifEnableExtendedTagSupport_DISPATCH(pGpu, pKernelBif) +#define kbifEnableExtendedTagSupport_HAL(pGpu, pKernelBif) kbifEnableExtendedTagSupport_DISPATCH(pGpu, pKernelBif) +#define kbifPcieConfigEnableRelaxedOrdering(pGpu, pKernelBif) kbifPcieConfigEnableRelaxedOrdering_DISPATCH(pGpu, pKernelBif) +#define kbifPcieConfigEnableRelaxedOrdering_HAL(pGpu, pKernelBif) kbifPcieConfigEnableRelaxedOrdering_DISPATCH(pGpu, pKernelBif) +#define kbifPcieConfigDisableRelaxedOrdering(pGpu, pKernelBif) kbifPcieConfigDisableRelaxedOrdering_DISPATCH(pGpu, pKernelBif) +#define kbifPcieConfigDisableRelaxedOrdering_HAL(pGpu, pKernelBif) kbifPcieConfigDisableRelaxedOrdering_DISPATCH(pGpu, pKernelBif) #define kbifInitRelaxedOrderingFromEmulatedConfigSpace(pGpu, pBif) kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(pGpu, pBif) #define kbifInitRelaxedOrderingFromEmulatedConfigSpace_HAL(pGpu, pBif) kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(pGpu, pBif) +#define kbifEnableNoSnoop(pGpu, pKernelBif, bEnable) kbifEnableNoSnoop_DISPATCH(pGpu, pKernelBif, bEnable) +#define kbifEnableNoSnoop_HAL(pGpu, pKernelBif, bEnable) kbifEnableNoSnoop_DISPATCH(pGpu, pKernelBif, bEnable) #define kbifApplyWARBug3208922(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) #define kbifApplyWARBug3208922_HAL(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) +#define kbifProbePcieReqAtomicCaps(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) +#define kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) +#define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) +#define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) +#define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) +#define kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) #define kbifReconcileTunableState(pGpu, pEngstate, pTunableState) kbifReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -259,285 +314,255 @@ static inline void kbifClearConfigErrors(struct OBJGPU *pGpu, struct KernelBif * #define kbifClearConfigErrors_HAL(pGpu, pKernelBif, arg0, arg1) kbifClearConfigErrors(pGpu, pKernelBif, arg0, arg1) -NV_STATUS kbifGetXveStatusBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); +void kbifDisableP2PTransactions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetXveStatusBits(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) { +static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetXveStatusBits(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_GM107(pGpu, pKernelBif, pBits, pStatus) +#define kbifDisableP2PTransactions(pGpu, pKernelBif) kbifDisableP2PTransactions_TU102(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetXveStatusBits_HAL(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits(pGpu, pKernelBif, pBits, pStatus) +#define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) -NV_STATUS kbifClearXveStatus_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus); +NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifClearXveStatus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0) { + return pKernelBif->__kbifConstructEngine__(pGpu, pKernelBif, arg0); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifClearXveStatus(pGpu, pKernelBif, pStatus) kbifClearXveStatus_GM107(pGpu, pKernelBif, pStatus) -#endif //__nvoc_kernel_bif_h_disabled - -#define kbifClearXveStatus_HAL(pGpu, pKernelBif, pStatus) kbifClearXveStatus(pGpu, pKernelBif, pStatus) -NV_STATUS kbifGetXveAerBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits); +NV_STATUS kbifStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetXveAerBits(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifStateInitLocked__(pGpu, pKernelBif); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifGetXveAerBits(pGpu, pKernelBif, pBits) kbifGetXveAerBits_GM107(pGpu, pKernelBif, pBits) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifGetXveAerBits_HAL(pGpu, pKernelBif, pBits) kbifGetXveAerBits(pGpu, pKernelBif, pBits) +static inline NV_STATUS kbifStateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return NV_OK; +} -NV_STATUS kbifClearXveAer_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits); +NV_STATUS kbifStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifClearXveAer(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return pKernelBif->__kbifStateLoad__(pGpu, pKernelBif, arg0); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifClearXveAer(pGpu, pKernelBif, bits) kbifClearXveAer_GM107(pGpu, pKernelBif, bits) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifClearXveAer_HAL(pGpu, pKernelBif, bits) kbifClearXveAer(pGpu, pKernelBif, bits) +static inline NV_STATUS kbifStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return NV_OK; +} -void kbifGetPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart); +NV_STATUS kbifStatePostLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifGetPcieConfigAccessTestRegisters(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline NV_STATUS kbifStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return pKernelBif->__kbifStatePostLoad__(pGpu, pKernelBif, arg0); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifGetPcieConfigAccessTestRegisters(pGpu, pKernelBif, pciStart, pcieStart) kbifGetPcieConfigAccessTestRegisters_GM107(pGpu, pKernelBif, pciStart, pcieStart) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifGetPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, pciStart, pcieStart) kbifGetPcieConfigAccessTestRegisters(pGpu, pKernelBif, pciStart, pcieStart) +static inline NV_STATUS kbifStateUnload_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return NV_OK; +} -NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr); +NV_STATUS kbifStateUnload_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return pKernelBif->__kbifStateUnload__(pGpu, pKernelBif, arg0); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifVerifyPcieConfigAccessTestRegisters(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) kbifVerifyPcieConfigAccessTestRegisters_GM107(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifVerifyPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) kbifVerifyPcieConfigAccessTestRegisters(pGpu, pKernelBif, nvXveId, nvXveVccapHdr) +NV_STATUS kbifGetXveStatusBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); -void kbifRearmMSI_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifGetXveStatusBits_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifRearmMSI(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline NV_STATUS kbifGetXveStatusBits_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) { + return NV_OK; } -#else //__nvoc_kernel_bif_h_disabled -#define kbifRearmMSI(pGpu, pKernelBif) kbifRearmMSI_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifRearmMSI_HAL(pGpu, pKernelBif) kbifRearmMSI(pGpu, pKernelBif) +static inline NV_STATUS kbifGetXveStatusBits_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) { + return pKernelBif->__kbifGetXveStatusBits__(pGpu, pKernelBif, pBits, pStatus); +} -NvBool kbifIsMSIEnabledInHW_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifClearXveStatus_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NvBool kbifIsMSIEnabledInHW(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_FALSE; +NV_STATUS kbifClearXveStatus_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus); + +static inline NV_STATUS kbifClearXveStatus_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus) { + return NV_OK; } -#else //__nvoc_kernel_bif_h_disabled -#define kbifIsMSIEnabledInHW(pGpu, pKernelBif) kbifIsMSIEnabledInHW_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifIsMSIEnabledInHW_HAL(pGpu, pKernelBif) kbifIsMSIEnabledInHW(pGpu, pKernelBif) +static inline NV_STATUS kbifClearXveStatus_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus) { + return pKernelBif->__kbifClearXveStatus__(pGpu, pKernelBif, pStatus); +} -NvBool kbifIsMSIXEnabledInHW_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifGetXveAerBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NvBool kbifIsMSIXEnabledInHW(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_FALSE; +NV_STATUS kbifGetXveAerBits_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits); + +static inline NV_STATUS kbifGetXveAerBits_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits) { + return NV_OK; } -#else //__nvoc_kernel_bif_h_disabled -#define kbifIsMSIXEnabledInHW(pGpu, pKernelBif) kbifIsMSIXEnabledInHW_TU102(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifIsMSIXEnabledInHW_HAL(pGpu, pKernelBif) kbifIsMSIXEnabledInHW(pGpu, pKernelBif) +static inline NV_STATUS kbifGetXveAerBits_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits) { + return pKernelBif->__kbifGetXveAerBits__(pGpu, pKernelBif, pBits); +} -NvBool kbifIs3dController_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifClearXveAer_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NvBool kbifIs3dController(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_bif_h_disabled -#define kbifIs3dController(pGpu, pKernelBif) kbifIs3dController_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled +NV_STATUS kbifClearXveAer_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits); -#define kbifIs3dController_HAL(pGpu, pKernelBif) kbifIs3dController(pGpu, pKernelBif) +static inline NV_STATUS kbifClearXveAer_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits) { + return NV_OK; +} -void kbifExecC73War_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +static inline NV_STATUS kbifClearXveAer_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits) { + return pKernelBif->__kbifClearXveAer__(pGpu, pKernelBif, bits); +} -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifExecC73War(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline void kbifGetPcieConfigAccessTestRegisters_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { + NV_ASSERT_PRECOMP(0); + return; } -#else //__nvoc_kernel_bif_h_disabled -#define kbifExecC73War(pGpu, pKernelBif) kbifExecC73War_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifExecC73War_HAL(pGpu, pKernelBif) kbifExecC73War(pGpu, pKernelBif) +void kbifGetPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart); -static inline void kbifEnableExtendedTagSupport_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { +static inline void kbifGetPcieConfigAccessTestRegisters_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { return; } -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifEnableExtendedTagSupport(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline void kbifGetPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { + pKernelBif->__kbifGetPcieConfigAccessTestRegisters__(pGpu, pKernelBif, pciStart, pcieStart); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifEnableExtendedTagSupport(pGpu, pKernelBif) kbifEnableExtendedTagSupport_b3696a(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifEnableExtendedTagSupport_HAL(pGpu, pKernelBif) kbifEnableExtendedTagSupport(pGpu, pKernelBif) +static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_92bfc3(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} -void kbifPcieConfigEnableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr); -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifPcieConfigEnableRelaxedOrdering(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { + return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_kernel_bif_h_disabled -#define kbifPcieConfigEnableRelaxedOrdering(pGpu, pKernelBif) kbifPcieConfigEnableRelaxedOrdering_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifPcieConfigEnableRelaxedOrdering_HAL(pGpu, pKernelBif) kbifPcieConfigEnableRelaxedOrdering(pGpu, pKernelBif) +static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { + return pKernelBif->__kbifVerifyPcieConfigAccessTestRegisters__(pGpu, pKernelBif, nvXveId, nvXveVccapHdr); +} -void kbifPcieConfigDisableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +void kbifRearmMSI_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifPcieConfigDisableRelaxedOrdering(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline void kbifRearmMSI_f2d351(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_PRECOMP(0); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifPcieConfigDisableRelaxedOrdering(pGpu, pKernelBif) kbifPcieConfigDisableRelaxedOrdering_GM107(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifPcieConfigDisableRelaxedOrdering_HAL(pGpu, pKernelBif) kbifPcieConfigDisableRelaxedOrdering(pGpu, pKernelBif) - -NV_STATUS kbifEnableNoSnoop_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable); +static inline void kbifRearmMSI_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifEnableNoSnoop(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline void kbifRearmMSI_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifRearmMSI__(pGpu, pKernelBif); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifEnableNoSnoop(pGpu, pKernelBif, bEnable) kbifEnableNoSnoop_GM107(pGpu, pKernelBif, bEnable) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifEnableNoSnoop_HAL(pGpu, pKernelBif, bEnable) kbifEnableNoSnoop(pGpu, pKernelBif, bEnable) +NvBool kbifIsMSIEnabledInHW_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -void kbifDisableP2PTransactions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NvBool kbifIsMSIEnabledInHW_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -#ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +static inline NvBool kbifIsMSIEnabledInHW_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return ((NvBool)(0 != 0)); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifDisableP2PTransactions(pGpu, pKernelBif) kbifDisableP2PTransactions_TU102(pGpu, pKernelBif) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) +static inline NvBool kbifIsMSIEnabledInHW_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifIsMSIEnabledInHW__(pGpu, pKernelBif); +} -NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); +NvBool kbifIsMSIXEnabledInHW_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetPciConfigSpacePriMirror(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +NvBool kbifIsMSIXEnabledInHW_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvBool kbifIsMSIXEnabledInHW_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return ((NvBool)(0 != 0)); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_GM107(pGpu, pKernelBif, pMirrorBase, pMirrorSize) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) +static inline NvBool kbifIsMSIXEnabledInHW_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifIsMSIXEnabledInHW__(pGpu, pKernelBif); +} -NV_STATUS kbifGetBusOptionsAddr_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg); +NvBool kbifIsPciIoAccessEnabled_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -#ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetBusOptionsAddr(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg) { - NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NvBool kbifIsPciIoAccessEnabled_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return ((NvBool)(0 != 0)); } -#else //__nvoc_kernel_bif_h_disabled -#define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_GM107(pGpu, pKernelBif, options, addrReg) -#endif //__nvoc_kernel_bif_h_disabled -#define kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) +static inline NvBool kbifIsPciIoAccessEnabled_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifIsPciIoAccessEnabled__(pGpu, pKernelBif); +} -NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); +NvBool kbifIs3dController_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline NV_STATUS kbifConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0) { - return pKernelBif->__kbifConstructEngine__(pGpu, pKernelBif, arg0); -} +NvBool kbifIs3dController_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -NV_STATUS kbifStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +static inline NvBool kbifIs3dController_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return ((NvBool)(0 != 0)); +} -static inline NV_STATUS kbifStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return pKernelBif->__kbifStateInitLocked__(pGpu, pKernelBif); +static inline NvBool kbifIs3dController_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifIs3dController__(pGpu, pKernelBif); } -static inline NV_STATUS kbifStateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; +void kbifExecC73War_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifExecC73War_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; } -NV_STATUS kbifStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); +static inline void kbifExecC73War_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifExecC73War__(pGpu, pKernelBif); +} -static inline NV_STATUS kbifStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return pKernelBif->__kbifStateLoad__(pGpu, pKernelBif, arg0); +static inline void kbifEnableExtendedTagSupport_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_PRECOMP(0); + return; } -static inline NV_STATUS kbifStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; +void kbifEnableExtendedTagSupport_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifEnableExtendedTagSupport_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; } -NV_STATUS kbifStatePostLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); +static inline void kbifEnableExtendedTagSupport_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifEnableExtendedTagSupport__(pGpu, pKernelBif); +} -static inline NV_STATUS kbifStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return pKernelBif->__kbifStatePostLoad__(pGpu, pKernelBif, arg0); +static inline void kbifPcieConfigEnableRelaxedOrdering_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_PRECOMP(0); + return; } -static inline NV_STATUS kbifStateUnload_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; +void kbifPcieConfigEnableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +void kbifPcieConfigEnableRelaxedOrdering_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifPcieConfigEnableRelaxedOrdering_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; } -NV_STATUS kbifStateUnload_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); +static inline void kbifPcieConfigEnableRelaxedOrdering_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifPcieConfigEnableRelaxedOrdering__(pGpu, pKernelBif); +} -static inline NV_STATUS kbifStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return pKernelBif->__kbifStateUnload__(pGpu, pKernelBif, arg0); +static inline void kbifPcieConfigDisableRelaxedOrdering_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_PRECOMP(0); + return; } -NvBool kbifIsPciIoAccessEnabled_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +void kbifPcieConfigDisableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline NvBool kbifIsPciIoAccessEnabled_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return ((NvBool)(0 != 0)); +void kbifPcieConfigDisableRelaxedOrdering_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifPcieConfigDisableRelaxedOrdering_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; } -static inline NvBool kbifIsPciIoAccessEnabled_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return pKernelBif->__kbifIsPciIoAccessEnabled__(pGpu, pKernelBif); +static inline void kbifPcieConfigDisableRelaxedOrdering_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifPcieConfigDisableRelaxedOrdering__(pGpu, pKernelBif); } static inline void kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a(struct OBJGPU *pGpu, struct KernelBif *pBif) { @@ -550,6 +575,27 @@ static inline void kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(struc pBif->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__(pGpu, pBif); } +static inline NV_STATUS kbifEnableNoSnoop_92bfc3(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kbifEnableNoSnoop_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable); + +NV_STATUS kbifEnableNoSnoop_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable); + +static inline NV_STATUS kbifEnableNoSnoop_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { + return NV_OK; +} + +static inline NV_STATUS kbifEnableNoSnoop_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifEnableNoSnoop_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { + return pKernelBif->__kbifEnableNoSnoop__(pGpu, pKernelBif, bEnable); +} + void kbifApplyWARBug3208922_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); static inline void kbifApplyWARBug3208922_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { @@ -560,6 +606,40 @@ static inline void kbifApplyWARBug3208922_DISPATCH(struct OBJGPU *pGpu, struct K pKernelBif->__kbifApplyWARBug3208922__(pGpu, pKernelBif); } +static inline void kbifProbePcieReqAtomicCaps_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} + +void kbifProbePcieReqAtomicCaps_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifProbePcieReqAtomicCaps_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifProbePcieReqAtomicCaps__(pGpu, pKernelBif); +} + +NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); + +NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); + +static inline NV_STATUS kbifGetPciConfigSpacePriMirror_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifGetPciConfigSpacePriMirror_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize) { + return pKernelBif->__kbifGetPciConfigSpacePriMirror__(pGpu, pKernelBif, pMirrorBase, pMirrorSize); +} + +NV_STATUS kbifGetBusOptionsAddr_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg); + +NV_STATUS kbifGetBusOptionsAddr_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg); + +static inline NV_STATUS kbifGetBusOptionsAddr_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifGetBusOptionsAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg) { + return pKernelBif->__kbifGetBusOptionsAddr__(pGpu, pKernelBif, options, addrReg); +} + static inline NV_STATUS kbifReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { return pEngstate->__kbifReconcileTunableState__(pGpu, pEngstate, pTunableState); } diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c new file mode 100644 index 000000000..2736c7110 --- /dev/null +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c @@ -0,0 +1,383 @@ +#define NVOC_KERNEL_CCU_API_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_ccu_api_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x3abed3 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcuApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_KernelCcuApi(KernelCcuApi*); +void __nvoc_init_funcTable_KernelCcuApi(KernelCcuApi*); +NV_STATUS __nvoc_ctor_KernelCcuApi(KernelCcuApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_KernelCcuApi(KernelCcuApi*); +void __nvoc_dtor_KernelCcuApi(KernelCcuApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcuApi; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_KernelCcuApi = { + /*pClassDef=*/ &__nvoc_class_def_KernelCcuApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelCcuApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcuApi_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcuApi, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelCcuApi = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_KernelCcuApi_KernelCcuApi, + &__nvoc_rtti_KernelCcuApi_GpuResource, + &__nvoc_rtti_KernelCcuApi_RmResource, + &__nvoc_rtti_KernelCcuApi_RmResourceCommon, + &__nvoc_rtti_KernelCcuApi_RsResource, + &__nvoc_rtti_KernelCcuApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcuApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelCcuApi), + /*classId=*/ classId(KernelCcuApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelCcuApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelCcuApi, + /*pCastInfo=*/ &__nvoc_castinfo_KernelCcuApi, + /*pExportInfo=*/ &__nvoc_export_info_KernelCcuApi +}; + +static NV_STATUS __nvoc_thunk_KernelCcuApi_gpuresMap(struct GpuResource *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return kccuapiMap((struct KernelCcuApi *)(((unsigned char *)pKernelCcuApi) - __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_KernelCcuApi_gpuresUnmap(struct GpuResource *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return kccuapiUnmap((struct KernelCcuApi *)(((unsigned char *)pKernelCcuApi) - __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_KernelCcuApi_gpuresGetMapAddrSpace(struct GpuResource *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return kccuapiGetMapAddrSpace((struct KernelCcuApi *)(((unsigned char *)pKernelCcuApi) - __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NV_STATUS __nvoc_thunk_KernelCcuApi_rmresGetMemoryMappingDescriptor(struct RmResource *pKernelCcuApi, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return kccuapiGetMemoryMappingDescriptor((struct KernelCcuApi *)(((unsigned char *)pKernelCcuApi) - __nvoc_rtti_KernelCcuApi_RmResource.offset), ppMemDesc); +} + +static NvBool __nvoc_thunk_GpuResource_kccuapiShareCallback(struct KernelCcuApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kccuapiControl(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiGetMemInterMapParams(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlFilter(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_kccuapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pReference); +} + +static NvU32 __nvoc_thunk_RsResource_kccuapiGetRefCount(struct KernelCcuApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiMapTo(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiControl_Prologue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kccuapiGetRegBaseOffsetAndSize(struct KernelCcuApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kccuapiInternalControlForward(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), command, pParams, size); +} + +static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiUnmapFrom(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_kccuapiControl_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlLookup(struct KernelCcuApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams, ppEntry); +} + +static NvBool __nvoc_thunk_RmResource_kccuapiAccessCallback(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCcuApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kccuapiCtrlCmdSubscribe_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcbca0101u, + /*paramSize=*/ sizeof(NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelCcuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kccuapiCtrlCmdSubscribe" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kccuapiCtrlCmdUnsubscribe_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcbca0102u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_KernelCcuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kccuapiCtrlCmdUnsubscribe" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcuApi = +{ + /*numEntries=*/ 2, + /*pExportEntries=*/ __nvoc_exported_method_def_KernelCcuApi +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_KernelCcuApi(KernelCcuApi *pThis) { + __nvoc_kccuapiDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelCcuApi(KernelCcuApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_KernelCcuApi(KernelCcuApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_KernelCcuApi_fail_GpuResource; + __nvoc_init_dataField_KernelCcuApi(pThis); + + status = __nvoc_kccuapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_KernelCcuApi_fail__init; + goto __nvoc_ctor_KernelCcuApi_exit; // Success + +__nvoc_ctor_KernelCcuApi_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_KernelCcuApi_fail_GpuResource: +__nvoc_ctor_KernelCcuApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__kccuapiMap__ = &kccuapiMap_IMPL; + + pThis->__kccuapiUnmap__ = &kccuapiUnmap_IMPL; + + pThis->__kccuapiGetMapAddrSpace__ = &kccuapiGetMapAddrSpace_IMPL; + + pThis->__kccuapiGetMemoryMappingDescriptor__ = &kccuapiGetMemoryMappingDescriptor_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kccuapiCtrlCmdSubscribe__ = &kccuapiCtrlCmdSubscribe_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kccuapiCtrlCmdUnsubscribe__ = &kccuapiCtrlCmdUnsubscribe_IMPL; +#endif + + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_KernelCcuApi_gpuresMap; + + pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_KernelCcuApi_gpuresUnmap; + + pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_KernelCcuApi_gpuresGetMapAddrSpace; + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__rmresGetMemoryMappingDescriptor__ = &__nvoc_thunk_KernelCcuApi_rmresGetMemoryMappingDescriptor; + + pThis->__kccuapiShareCallback__ = &__nvoc_thunk_GpuResource_kccuapiShareCallback; + + pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; + + pThis->__kccuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kccuapiGetMemInterMapParams; + + pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; + + pThis->__kccuapiControlFilter__ = &__nvoc_thunk_RsResource_kccuapiControlFilter; + + pThis->__kccuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kccuapiAddAdditionalDependants; + + pThis->__kccuapiGetRefCount__ = &__nvoc_thunk_RsResource_kccuapiGetRefCount; + + pThis->__kccuapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap; + + pThis->__kccuapiMapTo__ = &__nvoc_thunk_RsResource_kccuapiMapTo; + + pThis->__kccuapiControl_Prologue__ = &__nvoc_thunk_RmResource_kccuapiControl_Prologue; + + pThis->__kccuapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kccuapiGetRegBaseOffsetAndSize; + + pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; + + pThis->__kccuapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kccuapiInternalControlForward; + + pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; + + pThis->__kccuapiUnmapFrom__ = &__nvoc_thunk_RsResource_kccuapiUnmapFrom; + + pThis->__kccuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControl_Epilogue; + + pThis->__kccuapiControlLookup__ = &__nvoc_thunk_RsResource_kccuapiControlLookup; + + pThis->__kccuapiAccessCallback__ = &__nvoc_thunk_RmResource_kccuapiAccessCallback; +} + +void __nvoc_init_funcTable_KernelCcuApi(KernelCcuApi *pThis) { + __nvoc_init_funcTable_KernelCcuApi_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_KernelCcuApi(KernelCcuApi *pThis) { + pThis->__nvoc_pbase_KernelCcuApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_KernelCcuApi(pThis); +} + +NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + KernelCcuApi *pThis; + + pThis = portMemAllocNonPaged(sizeof(KernelCcuApi)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelCcuApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcuApi); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_KernelCcuApi(pThis); + status = __nvoc_ctor_KernelCcuApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_KernelCcuApi_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelCcuApi_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_KernelCcuApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h new file mode 100644 index 000000000..366a914c2 --- /dev/null +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h @@ -0,0 +1,258 @@ +#ifndef _G_KERNEL_CCU_API_NVOC_H_ +#define _G_KERNEL_CCU_API_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_ccu_api_nvoc.h" + +#ifndef KERNEL_CCU_API_H +#define KERNEL_CCU_API_H + +#include "gpu/gpu_resource.h" +#include "ctrl/ctrlcbca.h" + +/****************************************************************************\ + * * + * Kernel Ccu Api class header. * + * * + ****************************************************************************/ + +#ifdef NVOC_KERNEL_CCU_API_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelCcuApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct KernelCcuApi *__nvoc_pbase_KernelCcuApi; + NV_STATUS (*__kccuapiMap__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NV_STATUS (*__kccuapiUnmap__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kccuapiGetMapAddrSpace__)(struct KernelCcuApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__kccuapiGetMemoryMappingDescriptor__)(struct KernelCcuApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kccuapiCtrlCmdSubscribe__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS *); + NV_STATUS (*__kccuapiCtrlCmdUnsubscribe__)(struct KernelCcuApi *); + NvBool (*__kccuapiShareCallback__)(struct KernelCcuApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__kccuapiAddAdditionalDependants__)(struct RsClient *, struct KernelCcuApi *, RsResourceRef *); + NvU32 (*__kccuapiGetRefCount__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiCheckMemInterUnmap__)(struct KernelCcuApi *, NvBool); + NV_STATUS (*__kccuapiMapTo__)(struct KernelCcuApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kccuapiControl_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiGetRegBaseOffsetAndSize__)(struct KernelCcuApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiInternalControlForward__)(struct KernelCcuApi *, NvU32, void *, NvU32); + void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiUnmapFrom__)(struct KernelCcuApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kccuapiControl_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiControlLookup__)(struct KernelCcuApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvBool (*__kccuapiAccessCallback__)(struct KernelCcuApi *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +#define __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +typedef struct KernelCcuApi KernelCcuApi; +#endif /* __NVOC_CLASS_KernelCcuApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCcuApi +#define __nvoc_class_id_KernelCcuApi 0x3abed3 +#endif /* __nvoc_class_id_KernelCcuApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcuApi; + +#define __staticCast_KernelCcuApi(pThis) \ + ((pThis)->__nvoc_pbase_KernelCcuApi) + +#ifdef __nvoc_kernel_ccu_api_h_disabled +#define __dynamicCast_KernelCcuApi(pThis) ((KernelCcuApi*)NULL) +#else //__nvoc_kernel_ccu_api_h_disabled +#define __dynamicCast_KernelCcuApi(pThis) \ + ((KernelCcuApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelCcuApi))) +#endif //__nvoc_kernel_ccu_api_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_KernelCcuApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_KernelCcuApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define kccuapiMap(pKernelCcuApi, pCallContext, pParams, pCpuMapping) kccuapiMap_DISPATCH(pKernelCcuApi, pCallContext, pParams, pCpuMapping) +#define kccuapiUnmap(pKernelCcuApi, pCallContext, pCpuMapping) kccuapiUnmap_DISPATCH(pKernelCcuApi, pCallContext, pCpuMapping) +#define kccuapiGetMapAddrSpace(pKernelCcuApi, pCallContext, mapFlags, pAddrSpace) kccuapiGetMapAddrSpace_DISPATCH(pKernelCcuApi, pCallContext, mapFlags, pAddrSpace) +#define kccuapiGetMemoryMappingDescriptor(pKernelCcuApi, ppMemDesc) kccuapiGetMemoryMappingDescriptor_DISPATCH(pKernelCcuApi, ppMemDesc) +#define kccuapiCtrlCmdSubscribe(pKernelCcuApi, pParams) kccuapiCtrlCmdSubscribe_DISPATCH(pKernelCcuApi, pParams) +#define kccuapiCtrlCmdUnsubscribe(pKernelCcuApi) kccuapiCtrlCmdUnsubscribe_DISPATCH(pKernelCcuApi) +#define kccuapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kccuapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiAddAdditionalDependants(pClient, pResource, pReference) kccuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define kccuapiGetRefCount(pResource) kccuapiGetRefCount_DISPATCH(pResource) +#define kccuapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kccuapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kccuapiMapTo(pResource, pParams) kccuapiMapTo_DISPATCH(pResource, pParams) +#define kccuapiControl_Prologue(pResource, pCallContext, pParams) kccuapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kccuapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) +#define kccuapiInternalControlForward(pGpuResource, command, pParams, size) kccuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) +#define kccuapiUnmapFrom(pResource, pParams) kccuapiUnmapFrom_DISPATCH(pResource, pParams) +#define kccuapiControl_Epilogue(pResource, pCallContext, pParams) kccuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiControlLookup(pResource, pParams, ppEntry) kccuapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kccuapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kccuapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS kccuapiMap_IMPL(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); + +static inline NV_STATUS kccuapiMap_DISPATCH(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pKernelCcuApi->__kccuapiMap__(pKernelCcuApi, pCallContext, pParams, pCpuMapping); +} + +NV_STATUS kccuapiUnmap_IMPL(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping); + +static inline NV_STATUS kccuapiUnmap_DISPATCH(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pKernelCcuApi->__kccuapiUnmap__(pKernelCcuApi, pCallContext, pCpuMapping); +} + +NV_STATUS kccuapiGetMapAddrSpace_IMPL(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); + +static inline NV_STATUS kccuapiGetMapAddrSpace_DISPATCH(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pKernelCcuApi->__kccuapiGetMapAddrSpace__(pKernelCcuApi, pCallContext, mapFlags, pAddrSpace); +} + +NV_STATUS kccuapiGetMemoryMappingDescriptor_IMPL(struct KernelCcuApi *pKernelCcuApi, struct MEMORY_DESCRIPTOR **ppMemDesc); + +static inline NV_STATUS kccuapiGetMemoryMappingDescriptor_DISPATCH(struct KernelCcuApi *pKernelCcuApi, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pKernelCcuApi->__kccuapiGetMemoryMappingDescriptor__(pKernelCcuApi, ppMemDesc); +} + +NV_STATUS kccuapiCtrlCmdSubscribe_IMPL(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS *pParams); + +static inline NV_STATUS kccuapiCtrlCmdSubscribe_DISPATCH(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS *pParams) { + return pKernelCcuApi->__kccuapiCtrlCmdSubscribe__(pKernelCcuApi, pParams); +} + +NV_STATUS kccuapiCtrlCmdUnsubscribe_IMPL(struct KernelCcuApi *pKernelCcuApi); + +static inline NV_STATUS kccuapiCtrlCmdUnsubscribe_DISPATCH(struct KernelCcuApi *pKernelCcuApi) { + return pKernelCcuApi->__kccuapiCtrlCmdUnsubscribe__(pKernelCcuApi); +} + +static inline NvBool kccuapiShareCallback_DISPATCH(struct KernelCcuApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__kccuapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS kccuapiControl_DISPATCH(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kccuapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiGetMemInterMapParams_DISPATCH(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kccuapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { + return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kccuapiControlFilter_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline void kccuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + pResource->__kccuapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NvU32 kccuapiGetRefCount_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiGetRefCount__(pResource); +} + +static inline NV_STATUS kccuapiCheckMemInterUnmap_DISPATCH(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kccuapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS kccuapiMapTo_DISPATCH(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kccuapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS kccuapiControl_Prologue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiGetRegBaseOffsetAndSize_DISPATCH(struct KernelCcuApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__kccuapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiCanCopy__(pResource); +} + +static inline NV_STATUS kccuapiInternalControlForward_DISPATCH(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__kccuapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { + pResource->__kccuapiPreDestruct__(pResource); +} + +static inline NV_STATUS kccuapiUnmapFrom_DISPATCH(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__kccuapiUnmapFrom__(pResource, pParams); +} + +static inline void kccuapiControl_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kccuapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiControlLookup_DISPATCH(struct KernelCcuApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__kccuapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvBool kccuapiAccessCallback_DISPATCH(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__kccuapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS kccuapiConstruct_IMPL(struct KernelCcuApi *arg_pKernelCcuApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); +#define __nvoc_kccuapiConstruct(arg_pKernelCcuApi, arg_pCallContext, arg_pParams) kccuapiConstruct_IMPL(arg_pKernelCcuApi, arg_pCallContext, arg_pParams) +void kccuapiDestruct_IMPL(struct KernelCcuApi *pKernelCcuApi); +#define __nvoc_kccuapiDestruct(pKernelCcuApi) kccuapiDestruct_IMPL(pKernelCcuApi) +#undef PRIVATE_FIELD + +#endif // KERNEL_CCU_API_H + + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERNEL_CCU_API_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.c b/src/nvidia/generated/g_kernel_ccu_nvoc.c new file mode 100644 index 000000000..b9f2cf4c9 --- /dev/null +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.c @@ -0,0 +1,307 @@ +#define NVOC_KERNEL_CCU_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_ccu_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x5d5b68 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcu; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; + +void __nvoc_init_KernelCcu(KernelCcu*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelCcu(KernelCcu*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelCcu(KernelCcu*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelCcu(KernelCcu*, RmHalspecOwner* ); +void __nvoc_dtor_KernelCcu(KernelCcu*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcu; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcu_KernelCcu = { + /*pClassDef=*/ &__nvoc_class_def_KernelCcu, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelCcu, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcu_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcu, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCcu_OBJENGSTATE = { + /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCcu, __nvoc_base_OBJENGSTATE), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelCcu = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_KernelCcu_KernelCcu, + &__nvoc_rtti_KernelCcu_OBJENGSTATE, + &__nvoc_rtti_KernelCcu_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcu = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelCcu), + /*classId=*/ classId(KernelCcu), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelCcu", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelCcu, + /*pCastInfo=*/ &__nvoc_castinfo_KernelCcu, + /*pExportInfo=*/ &__nvoc_export_info_KernelCcu +}; + +static NV_STATUS __nvoc_thunk_KernelCcu_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pKernelCcu, ENGDESCRIPTOR engDesc) { + return kccuConstructEngine(pGpu, (struct KernelCcu *)(((unsigned char *)pKernelCcu) - __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), engDesc); +} + +static NV_STATUS __nvoc_thunk_KernelCcu_engstateStateLoad(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 flags) { + return kccuStateLoad(arg0, (struct KernelCcu *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_KernelCcu_engstateStateUnload(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 flags) { + return kccuStateUnload(arg0, (struct KernelCcu *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStateInitLocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePreLoad(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePostUnload(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); +} + +static void __nvoc_thunk_OBJENGSTATE_kccuStateDestroy(POBJGPU pGpu, struct KernelCcu *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePreUnload(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStateInitUnlocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_OBJENGSTATE_kccuInitMissing(POBJGPU pGpu, struct KernelCcu *pEngstate) { + engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePreInitLocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePreInitUnlocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuGetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuCompareTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { + return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunables1, pTunables2); +} + +static void __nvoc_thunk_OBJENGSTATE_kccuFreeTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePostLoad(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuAllocTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { + return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), ppTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuSetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_kccuIsPresent(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcu = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_KernelCcu(KernelCcu *pThis) { + __nvoc_kccuDestruct(pThis); + __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + if (status != NV_OK) goto __nvoc_ctor_KernelCcu_fail_OBJENGSTATE; + __nvoc_init_dataField_KernelCcu(pThis, pRmhalspecowner); + goto __nvoc_ctor_KernelCcu_exit; // Success + +__nvoc_ctor_KernelCcu_fail_OBJENGSTATE: +__nvoc_ctor_KernelCcu_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + // Hal function -- kccuConstructEngine + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; + } + else if (0) + { + } + + pThis->__kccuStateLoad__ = &kccuStateLoad_IMPL; + + pThis->__kccuStateUnload__ = &kccuStateUnload_IMPL; + + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelCcu_engstateConstructEngine; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCcu_engstateStateLoad; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCcu_engstateStateUnload; + + pThis->__kccuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState; + + pThis->__kccuStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStateInitLocked; + + pThis->__kccuStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreLoad; + + pThis->__kccuStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePostUnload; + + pThis->__kccuStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kccuStateDestroy; + + pThis->__kccuStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreUnload; + + pThis->__kccuStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStateInitUnlocked; + + pThis->__kccuInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kccuInitMissing; + + pThis->__kccuStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreInitLocked; + + pThis->__kccuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreInitUnlocked; + + pThis->__kccuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuGetTunableState; + + pThis->__kccuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuCompareTunableState; + + pThis->__kccuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuFreeTunableState; + + pThis->__kccuStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePostLoad; + + pThis->__kccuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuAllocTunableState; + + pThis->__kccuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuSetTunableState; + + pThis->__kccuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kccuIsPresent; +} + +void __nvoc_init_funcTable_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelCcu_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_KernelCcu = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; + pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_funcTable_KernelCcu(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + KernelCcu *pThis; + RmHalspecOwner *pRmhalspecowner; + + pThis = portMemAllocNonPaged(sizeof(KernelCcu)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelCcu)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcu); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_KernelCcu(pThis, pRmhalspecowner); + status = __nvoc_ctor_KernelCcu(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_KernelCcu_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelCcu_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_KernelCcu(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.h b/src/nvidia/generated/g_kernel_ccu_nvoc.h new file mode 100644 index 000000000..3e729adea --- /dev/null +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.h @@ -0,0 +1,311 @@ +#ifndef _G_KERNEL_CCU_NVOC_H_ +#define _G_KERNEL_CCU_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_ccu_nvoc.h" + +#ifndef KERNEL_CCU_H +#define KERNEL_CCU_H + +/****************************************************************************** +* +* Kernel CCU module header +* This file contains functions managing CCU core on CPU RM +* +******************************************************************************/ + +#include "gpu/gpu.h" +#include "gpu/eng_state.h" +#include "rmapi/rmapi.h" +#include "objtmr.h" + +/*! + * KernelCcu is a logical abstraction of the GPU Ccu Engine. The + * Public API of the Ccu Engine is exposed through this object, and any + * interfaces which do not manage the underlying Ccu can be managed by + * this object. + */ + +#define CCU_PER_GPU_COUNTER_Q_SIZE (16384) +#define CCU_TIMESTAMP_SIZE (sizeof(NvU64)) +#define CCU_TIMEOUT_100MSECS (100000000) +#define CCU_MIG_INST_COUNTER_Q_SIZE (2048) + +#define CCU_DEV_SHRBUF_ID (0) +#define CCU_MIG_SHRBUF_ID_START (1) + +#define CCU_DEV_SHRBUF_COUNT (1) +#define CCU_SHRBUF_COUNT_MAX (GPUMGR_MAX_GPU_INSTANCES + CCU_DEV_SHRBUF_COUNT) +#define CCU_MIG_SWIZZID_SIZE (sizeof(NvU8)) +#define CCU_MIG_INVALID_SWIZZID (0xFF) + +#define CCU_GPU_SHARED_BUFFER_SIZE_MAX (CCU_PER_GPU_COUNTER_Q_SIZE + (2 * CCU_TIMESTAMP_SIZE) + CCU_MIG_SWIZZID_SIZE) // 16K counter block + head & tail timestamp size + mig-SwizzId size +#define CCU_MIG_INST_SHARED_BUFFER_SIZE_MAX (CCU_MIG_INST_COUNTER_Q_SIZE + (2 * CCU_TIMESTAMP_SIZE) + CCU_MIG_SWIZZID_SIZE) // 2K counter block + head & tail timestamp size + mig-SwizzId size + +typedef struct +{ + NvP64 addr; // Kernel address + NvP64 priv; // Private page count +} SHARED_BUFFER_MAP_INFO; + +typedef struct +{ + /* shared buffer info */ + NvU64 *pHeadTimeStamp; // Timestamp before the start of counter block + NvU64 *pTailTimeStamp; // Timestamp at the end of counter block + NvU8 *pSwizzId; // Mig inst swizz id + NvP64 pCounterBlock; // Counter block start address + NvU32 counterBlockSize; // Counter block size +} CCU_SHRBUF_INFO; + +typedef struct +{ + CCU_SHRBUF_INFO *pCounterDstInfo; // Counter shared buffer info + SHARED_BUFFER_MAP_INFO *pKernelMapInfo; // Shared buffer kernel map info +} CCU_SHRBUF; + +#ifdef NVOC_KERNEL_CCU_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelCcu { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelCcu *__nvoc_pbase_KernelCcu; + NV_STATUS (*__kccuConstructEngine__)(OBJGPU *, struct KernelCcu *, ENGDESCRIPTOR); + NV_STATUS (*__kccuStateLoad__)(OBJGPU *, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuStateUnload__)(OBJGPU *, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuReconcileTunableState__)(POBJGPU, struct KernelCcu *, void *); + NV_STATUS (*__kccuStateInitLocked__)(POBJGPU, struct KernelCcu *); + NV_STATUS (*__kccuStatePreLoad__)(POBJGPU, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuStatePostUnload__)(POBJGPU, struct KernelCcu *, NvU32); + void (*__kccuStateDestroy__)(POBJGPU, struct KernelCcu *); + NV_STATUS (*__kccuStatePreUnload__)(POBJGPU, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuStateInitUnlocked__)(POBJGPU, struct KernelCcu *); + void (*__kccuInitMissing__)(POBJGPU, struct KernelCcu *); + NV_STATUS (*__kccuStatePreInitLocked__)(POBJGPU, struct KernelCcu *); + NV_STATUS (*__kccuStatePreInitUnlocked__)(POBJGPU, struct KernelCcu *); + NV_STATUS (*__kccuGetTunableState__)(POBJGPU, struct KernelCcu *, void *); + NV_STATUS (*__kccuCompareTunableState__)(POBJGPU, struct KernelCcu *, void *, void *); + void (*__kccuFreeTunableState__)(POBJGPU, struct KernelCcu *, void *); + NV_STATUS (*__kccuStatePostLoad__)(POBJGPU, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuAllocTunableState__)(POBJGPU, struct KernelCcu *, void **); + NV_STATUS (*__kccuSetTunableState__)(POBJGPU, struct KernelCcu *, void *); + NvBool (*__kccuIsPresent__)(POBJGPU, struct KernelCcu *); + MEMORY_DESCRIPTOR *pMemDesc[9]; + CCU_SHRBUF shrBuf[9]; +}; + +#ifndef __NVOC_CLASS_KernelCcu_TYPEDEF__ +#define __NVOC_CLASS_KernelCcu_TYPEDEF__ +typedef struct KernelCcu KernelCcu; +#endif /* __NVOC_CLASS_KernelCcu_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCcu +#define __nvoc_class_id_KernelCcu 0x5d5b68 +#endif /* __nvoc_class_id_KernelCcu */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCcu; + +#define __staticCast_KernelCcu(pThis) \ + ((pThis)->__nvoc_pbase_KernelCcu) + +#ifdef __nvoc_kernel_ccu_h_disabled +#define __dynamicCast_KernelCcu(pThis) ((KernelCcu*)NULL) +#else //__nvoc_kernel_ccu_h_disabled +#define __dynamicCast_KernelCcu(pThis) \ + ((KernelCcu*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelCcu))) +#endif //__nvoc_kernel_ccu_h_disabled + +#define PDB_PROP_KCCU_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_KCCU_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING + +NV_STATUS __nvoc_objCreateDynamic_KernelCcu(KernelCcu**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); +#define __objCreate_KernelCcu(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelCcu((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define kccuConstructEngine(pGpu, pKernelCcu, engDesc) kccuConstructEngine_DISPATCH(pGpu, pKernelCcu, engDesc) +#define kccuConstructEngine_HAL(pGpu, pKernelCcu, engDesc) kccuConstructEngine_DISPATCH(pGpu, pKernelCcu, engDesc) +#define kccuStateLoad(arg0, arg1, flags) kccuStateLoad_DISPATCH(arg0, arg1, flags) +#define kccuStateUnload(arg0, arg1, flags) kccuStateUnload_DISPATCH(arg0, arg1, flags) +#define kccuReconcileTunableState(pGpu, pEngstate, pTunableState) kccuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kccuStateInitLocked(pGpu, pEngstate) kccuStateInitLocked_DISPATCH(pGpu, pEngstate) +#define kccuStatePreLoad(pGpu, pEngstate, arg0) kccuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kccuStatePostUnload(pGpu, pEngstate, arg0) kccuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kccuStateDestroy(pGpu, pEngstate) kccuStateDestroy_DISPATCH(pGpu, pEngstate) +#define kccuStatePreUnload(pGpu, pEngstate, arg0) kccuStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kccuStateInitUnlocked(pGpu, pEngstate) kccuStateInitUnlocked_DISPATCH(pGpu, pEngstate) +#define kccuInitMissing(pGpu, pEngstate) kccuInitMissing_DISPATCH(pGpu, pEngstate) +#define kccuStatePreInitLocked(pGpu, pEngstate) kccuStatePreInitLocked_DISPATCH(pGpu, pEngstate) +#define kccuStatePreInitUnlocked(pGpu, pEngstate) kccuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define kccuGetTunableState(pGpu, pEngstate, pTunableState) kccuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kccuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kccuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) +#define kccuFreeTunableState(pGpu, pEngstate, pTunableState) kccuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kccuStatePostLoad(pGpu, pEngstate, arg0) kccuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kccuAllocTunableState(pGpu, pEngstate, ppTunableState) kccuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) +#define kccuSetTunableState(pGpu, pEngstate, pTunableState) kccuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kccuIsPresent(pGpu, pEngstate) kccuIsPresent_DISPATCH(pGpu, pEngstate) +void kccuDestruct_IMPL(struct KernelCcu *arg0); + +#define __nvoc_kccuDestruct(arg0) kccuDestruct_IMPL(arg0) +NV_STATUS kccuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc); + +static inline NV_STATUS kccuConstructEngine_46f6a7(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kccuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc) { + return pKernelCcu->__kccuConstructEngine__(pGpu, pKernelCcu, engDesc); +} + +NV_STATUS kccuStateLoad_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 flags); + +static inline NV_STATUS kccuStateLoad_DISPATCH(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 flags) { + return arg1->__kccuStateLoad__(arg0, arg1, flags); +} + +NV_STATUS kccuStateUnload_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 flags); + +static inline NV_STATUS kccuStateUnload_DISPATCH(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 flags) { + return arg1->__kccuStateUnload__(arg0, arg1, flags); +} + +static inline NV_STATUS kccuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return pEngstate->__kccuReconcileTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kccuStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return pEngstate->__kccuStateInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kccuStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return pEngstate->__kccuStatePreLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kccuStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return pEngstate->__kccuStatePostUnload__(pGpu, pEngstate, arg0); +} + +static inline void kccuStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + pEngstate->__kccuStateDestroy__(pGpu, pEngstate); +} + +static inline NV_STATUS kccuStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return pEngstate->__kccuStatePreUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kccuStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return pEngstate->__kccuStateInitUnlocked__(pGpu, pEngstate); +} + +static inline void kccuInitMissing_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + pEngstate->__kccuInitMissing__(pGpu, pEngstate); +} + +static inline NV_STATUS kccuStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return pEngstate->__kccuStatePreInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kccuStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return pEngstate->__kccuStatePreInitUnlocked__(pGpu, pEngstate); +} + +static inline NV_STATUS kccuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return pEngstate->__kccuGetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kccuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { + return pEngstate->__kccuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +} + +static inline void kccuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + pEngstate->__kccuFreeTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS kccuStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { + return pEngstate->__kccuStatePostLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS kccuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { + return pEngstate->__kccuAllocTunableState__(pGpu, pEngstate, ppTunableState); +} + +static inline NV_STATUS kccuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { + return pEngstate->__kccuSetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NvBool kccuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { + return pEngstate->__kccuIsPresent__(pGpu, pEngstate); +} + +NV_STATUS kccuMemDescGetForSwizzId_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, MEMORY_DESCRIPTOR **arg2); +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuMemDescGetForSwizzId(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, MEMORY_DESCRIPTOR **arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuMemDescGetForSwizzId(arg0, arg1, swizzId, arg2) kccuMemDescGetForSwizzId_IMPL(arg0, arg1, swizzId, arg2) +#endif //__nvoc_kernel_ccu_h_disabled + +NV_STATUS kccuMemDescGetForShrBufId_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrbufId, MEMORY_DESCRIPTOR **arg2); +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuMemDescGetForShrBufId(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrbufId, MEMORY_DESCRIPTOR **arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuMemDescGetForShrBufId(arg0, arg1, shrbufId, arg2) kccuMemDescGetForShrBufId_IMPL(arg0, arg1, shrbufId, arg2) +#endif //__nvoc_kernel_ccu_h_disabled + +NvU32 kccuCounterBlockSizeGet_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bDevCounter); +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NvU32 kccuCounterBlockSizeGet(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bDevCounter) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return 0; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuCounterBlockSizeGet(arg0, arg1, bDevCounter) kccuCounterBlockSizeGet_IMPL(arg0, arg1, bDevCounter) +#endif //__nvoc_kernel_ccu_h_disabled + +#undef PRIVATE_FIELD + + +#endif // KERNEL_CCU_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERNEL_CCU_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index 2b4de2af9..653c8fe6f 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -232,7 +232,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL; // Hal function -- kceIsPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceIsPresent__ = &kceIsPresent_IMPL; } @@ -244,7 +244,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceStateLoad__ = &kceStateLoad_GP100; } @@ -253,14 +253,13 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR } // Hal function -- kceStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceStateUnload__ = &kceStateUnload_GP100; } // default else { - pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; } pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; @@ -278,7 +277,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100; } @@ -291,13 +290,13 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52; } // Hal function -- kceIsCurrentMaxTopology - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; } @@ -314,7 +313,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetGrceConfigSize1__ = &kceGetGrceConfigSize1_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceGetGrceConfigSize1__ = &kceGetGrceConfigSize1_GA100; } @@ -337,15 +336,16 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; } else if (0) { } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100; } else if (0) { @@ -358,34 +358,65 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR } // Hal function -- kceGetMappings - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceGetMappings__ = &kceGetMappings_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceGetMappings__ = &kceGetMappings_GH100; + } + else if (0) + { + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetMappings__ = &kceGetMappings_46f6a7; } + // Hal function -- kceMapPceLceForC2C + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7; + } + + // Hal function -- kceMapPceLceForGRCE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a; + } + // Hal function -- kceMapPceLceForSysmemLinks if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7; } // Hal function -- kceMapPceLceForNvlinkPeers - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100; + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_46f6a7; @@ -396,31 +427,38 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee; } // Hal function -- kceMapAsyncLceDefault - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100; + } + else if (0) + { + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7; } // Hal function -- kceGetNvlinkPeerSupportedLceMask - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; } @@ -434,7 +472,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; } @@ -443,14 +481,18 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_4a4dee; } - // Hal function -- kceIsGen4orHigherSupported + // Hal function -- kceIsGenXorHigherSupported if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - pThis->__kceIsGen4orHigherSupported__ = &kceIsGen4orHigherSupported_GA100; + pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { - pThis->__kceIsGen4orHigherSupported__ = &kceIsGen4orHigherSupported_cbe027; + pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027; } // Hal function -- kceApplyGen4orHigherMapping @@ -458,7 +500,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a; } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index 0e3074e0f..cc19f5271 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -43,6 +43,52 @@ extern "C" { #include "kernel/gpu/intr/intr_service.h" #include "gpu/ce/kernel_ce_shared.h" +#define MAX_CE_CNT 18 + +/* + * sysmemLinks + * Represents the number of sysmem links detected + * This affects how many PCEs LCE0(sysmem read CE) + * and LCE1(sysmem write CE) should be mapped to + * maxLinksPerPeer + * Represents the maximum number of peer links + * between this GPU and all its peers. This affects + * how many PCEs LCE3(P2P CE) should be mapped to + * numPeers + * Represents the number of Peer GPUs discovered so far + * bSymmetric + * Represents whether the topology detected so far + * is symmetric i.e. has same number of links to all + * peers connected through nvlink. This affects how + * many PCEs to assign to LCEs3-5 (nvlink P2P CEs) + * bSwitchConfig + * Represents whether the config listed is intended + * for use with nvswitch systems + * pceLceMap + * Value of NV_CE_PCE2LCE_CONFIG0 register with the + * above values for sysmemLinks, maxLinksPerPeer, + * numLinks and bSymmetric + * grceConfig + * Value of NV_CE_GRCE_CONFIG register with the + * above values for sysmemLinks, maxLinksPerPeer, + * numLinks and bSymmetric + * exposeCeMask + * Mask of CEs to expose to clients for the above + * above values for sysmemLinks, maxLinksPerPeer, + * numLinks and bSymmetric + */ +typedef struct NVLINK_CE_AUTO_CONFIG_TABLE +{ + NvU32 sysmemLinks; + NvU32 maxLinksPerPeer; + NvU32 numPeers; + NvBool bSymmetric; + NvBool bSwitchConfig; + NvU32 pceLceMap[MAX_CE_CNT]; + NvU32 grceConfig[MAX_CE_CNT]; + NvU32 exposeCeMask; +} NVLINK_CE_AUTO_CONFIG_TABLE; + // // Kernel Copy Engine // This class provides Kernel-RM interface and state tracking for Copy Engine. @@ -53,9 +99,6 @@ extern "C" { #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif -struct NVLINK_CE_AUTO_CONFIG_TABLE; - - struct KernelCE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -76,13 +119,15 @@ struct KernelCE { NvU32 (*__kceGetGrceConfigSize1__)(struct KernelCE *); NvU32 (*__kceGetPce2lceConfigSize1__)(struct KernelCE *); NV_STATUS (*__kceGetMappings__)(OBJGPU *, struct KernelCE *, NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *, NvU32 *); + NV_STATUS (*__kceMapPceLceForC2C__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); + void (*__kceMapPceLceForGRCE__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kceMapPceLceForSysmemLinks__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kceMapPceLceForNvlinkPeers__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvU32 (*__kceGetSysmemSupportedLceMask__)(OBJGPU *, struct KernelCE *); NV_STATUS (*__kceMapAsyncLceDefault__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *, NvU32); NvU32 (*__kceGetNvlinkPeerSupportedLceMask__)(OBJGPU *, struct KernelCE *, NvU32); NvU32 (*__kceGetGrceSupportedLceMask__)(OBJGPU *, struct KernelCE *); - NvBool (*__kceIsGen4orHigherSupported__)(OBJGPU *, struct KernelCE *); + NvBool (*__kceIsGenXorHigherSupported__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceApplyGen4orHigherMapping__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32, NvU32); NV_STATUS (*__kceReconcileTunableState__)(POBJGPU, struct KernelCE *, void *); NV_STATUS (*__kceStateInitLocked__)(POBJGPU, struct KernelCE *); @@ -105,6 +150,7 @@ struct KernelCE { NvU32 publicID; NvBool bStubbed; NvU32 nvlinkPeerMask; + NvU32 nvlinkNumPeers; NvBool bIsAutoConfigEnabled; NvBool bUseGen4Mapping; struct IO_APERTURE aperture; @@ -161,6 +207,10 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceGetPce2lceConfigSize1_HAL(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetMappings(pGpu, pCe, arg0, arg1, arg2, arg3) kceGetMappings_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceGetMappings_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceGetMappings_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) +#define kceMapPceLceForC2C(pGpu, pKCe, arg0, arg1, arg2) kceMapPceLceForC2C_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) +#define kceMapPceLceForC2C_HAL(pGpu, pKCe, arg0, arg1, arg2) kceMapPceLceForC2C_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) +#define kceMapPceLceForGRCE(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceMapPceLceForGRCE_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) +#define kceMapPceLceForGRCE_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceMapPceLceForGRCE_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) #define kceMapPceLceForSysmemLinks(pGpu, pCe, arg0, arg1, arg2, arg3) kceMapPceLceForSysmemLinks_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceMapPceLceForSysmemLinks_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceMapPceLceForSysmemLinks_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceMapPceLceForNvlinkPeers(pGpu, pCe, arg0, arg1, arg2) kceMapPceLceForNvlinkPeers_DISPATCH(pGpu, pCe, arg0, arg1, arg2) @@ -173,8 +223,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pCe, arg0) kceGetNvlinkPeerSupportedLceMask_DISPATCH(pGpu, pCe, arg0) #define kceGetGrceSupportedLceMask(pGpu, pCe) kceGetGrceSupportedLceMask_DISPATCH(pGpu, pCe) #define kceGetGrceSupportedLceMask_HAL(pGpu, pCe) kceGetGrceSupportedLceMask_DISPATCH(pGpu, pCe) -#define kceIsGen4orHigherSupported(pGpu, pCe) kceIsGen4orHigherSupported_DISPATCH(pGpu, pCe) -#define kceIsGen4orHigherSupported_HAL(pGpu, pCe) kceIsGen4orHigherSupported_DISPATCH(pGpu, pCe) +#define kceIsGenXorHigherSupported(pGpu, pCe, checkGen) kceIsGenXorHigherSupported_DISPATCH(pGpu, pCe, checkGen) +#define kceIsGenXorHigherSupported_HAL(pGpu, pCe, checkGen) kceIsGenXorHigherSupported_DISPATCH(pGpu, pCe, checkGen) #define kceApplyGen4orHigherMapping(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceApplyGen4orHigherMapping_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceReconcileTunableState(pGpu, pEngstate, pTunableState) kceReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) @@ -409,6 +459,8 @@ NvU32 kceGetPce2lceConfigSize1_GA100(struct KernelCE *arg0); NvU32 kceGetPce2lceConfigSize1_GA102(struct KernelCE *arg0); +NvU32 kceGetPce2lceConfigSize1_GH100(struct KernelCE *arg0); + static inline NvU32 kceGetPce2lceConfigSize1_4a4dee(struct KernelCE *arg0) { return 0; } @@ -419,6 +471,8 @@ static inline NvU32 kceGetPce2lceConfigSize1_DISPATCH(struct KernelCE *arg0) { NV_STATUS kceGetMappings_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NVLINK_TOPOLOGY_PARAMS *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3); +NV_STATUS kceGetMappings_GH100(OBJGPU *pGpu, struct KernelCE *pCe, NVLINK_TOPOLOGY_PARAMS *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3); + static inline NV_STATUS kceGetMappings_46f6a7(OBJGPU *pGpu, struct KernelCE *pCe, NVLINK_TOPOLOGY_PARAMS *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3) { return NV_ERR_NOT_SUPPORTED; } @@ -427,6 +481,26 @@ static inline NV_STATUS kceGetMappings_DISPATCH(OBJGPU *pGpu, struct KernelCE *p return pCe->__kceGetMappings__(pGpu, pCe, arg0, arg1, arg2, arg3); } +NV_STATUS kceMapPceLceForC2C_GH100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); + +static inline NV_STATUS kceMapPceLceForC2C_46f6a7(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kceMapPceLceForC2C_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { + return pKCe->__kceMapPceLceForC2C__(pGpu, pKCe, arg0, arg1, arg2); +} + +void kceMapPceLceForGRCE_GH100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 arg4); + +static inline void kceMapPceLceForGRCE_b3696a(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 arg4) { + return; +} + +static inline void kceMapPceLceForGRCE_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 arg4) { + pKCe->__kceMapPceLceForGRCE__(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4); +} + NV_STATUS kceMapPceLceForSysmemLinks_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 arg3); NV_STATUS kceMapPceLceForSysmemLinks_GA102(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 arg3); @@ -441,6 +515,8 @@ static inline NV_STATUS kceMapPceLceForSysmemLinks_DISPATCH(OBJGPU *pGpu, struct NV_STATUS kceMapPceLceForNvlinkPeers_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); +NV_STATUS kceMapPceLceForNvlinkPeers_GH100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); + static inline NV_STATUS kceMapPceLceForNvlinkPeers_46f6a7(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { return NV_ERR_NOT_SUPPORTED; } @@ -463,6 +539,8 @@ static inline NvU32 kceGetSysmemSupportedLceMask_DISPATCH(OBJGPU *pGpu, struct K NV_STATUS kceMapAsyncLceDefault_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 arg3); +NV_STATUS kceMapAsyncLceDefault_GH100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 arg3); + static inline NV_STATUS kceMapAsyncLceDefault_46f6a7(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2, NvU32 arg3) { return NV_ERR_NOT_SUPPORTED; } @@ -495,14 +573,16 @@ static inline NvU32 kceGetGrceSupportedLceMask_DISPATCH(OBJGPU *pGpu, struct Ker return pCe->__kceGetGrceSupportedLceMask__(pGpu, pCe); } -NvBool kceIsGen4orHigherSupported_GA100(OBJGPU *pGpu, struct KernelCE *pCe); +NvBool kceIsGenXorHigherSupported_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 checkGen); + +NvBool kceIsGenXorHigherSupported_GH100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 checkGen); -static inline NvBool kceIsGen4orHigherSupported_cbe027(OBJGPU *pGpu, struct KernelCE *pCe) { +static inline NvBool kceIsGenXorHigherSupported_cbe027(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 checkGen) { return ((NvBool)(0 == 0)); } -static inline NvBool kceIsGen4orHigherSupported_DISPATCH(OBJGPU *pGpu, struct KernelCE *pCe) { - return pCe->__kceIsGen4orHigherSupported__(pGpu, pCe); +static inline NvBool kceIsGenXorHigherSupported_DISPATCH(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 checkGen) { + return pCe->__kceIsGenXorHigherSupported__(pGpu, pCe, checkGen); } void kceApplyGen4orHigherMapping_GA100(OBJGPU *pGpu, struct KernelCE *pCe, NvU32 *arg0, NvU32 *arg1, NvU32 arg2, NvU32 arg3); diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index 30e98129d..1b6accfe9 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -751,6 +751,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [35] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdSaveEngineCtxData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb06f0111u, + /*paramSize=*/ sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlCmdSaveEngineCtxData" +#endif + }, + { /* [36] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdRestoreEngineCtxData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) + /*flags=*/ 0x2204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb06f0112u, + /*paramSize=*/ sizeof(NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlCmdRestoreEngineCtxData" +#endif + }, + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -765,7 +795,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidC06F" #endif }, - { /* [36] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -780,7 +810,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelC06F" #endif }, - { /* [37] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -795,7 +825,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleC06F" #endif }, - { /* [38] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -810,7 +840,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBindC06F" #endif }, - { /* [39] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -825,7 +855,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidC36F" #endif }, - { /* [40] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -840,7 +870,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelC36F" #endif }, - { /* [41] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -855,7 +885,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleC36F" #endif }, - { /* [42] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -870,7 +900,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBindC36F" #endif }, - { /* [43] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -885,7 +915,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpfifoGetWorkSubmitToken" #endif }, - { /* [44] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -900,7 +930,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer" #endif }, - { /* [45] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -920,7 +950,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelChannel = { - /*numEntries=*/ 46, + /*numEntries=*/ 48, /*pExportEntries=*/ __nvoc_exported_method_def_KernelChannel }; @@ -992,17 +1022,31 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCheckMemInterUnmap__ = &kchannelCheckMemInterUnmap_IMPL; + // Hal function -- kchannelCreateUserMemDesc + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; + } + else if (0) + { + } + // Hal function -- kchannelIsUserdAddrSizeValid if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; } else if (0) { @@ -1128,6 +1172,14 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdSetChannelHwState__ = &kchannelCtrlCmdSetChannelHwState_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__kchannelCtrlCmdSaveEngineCtxData__ = &kchannelCtrlCmdSaveEngineCtxData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) + pThis->__kchannelCtrlCmdRestoreEngineCtxData__ = &kchannelCtrlCmdRestoreEngineCtxData_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlCmdGetClassEngineidC06F__ = &kchannelCtrlCmdGetClassEngineidC06F_6a9a13; #endif diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index b52d1791b..b6a27e0d8 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -210,6 +210,7 @@ struct KernelChannel { NV_STATUS (*__kchannelGetMapAddrSpace__)(struct KernelChannel *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__kchannelGetMemInterMapParams__)(struct KernelChannel *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kchannelCheckMemInterUnmap__)(struct KernelChannel *, NvBool); + NV_STATUS (*__kchannelCreateUserMemDesc__)(struct OBJGPU *, struct KernelChannel *); NvBool (*__kchannelIsUserdAddrSizeValid__)(struct KernelChannel *, NvU32, NvU32); NV_STATUS (*__kchannelCtrlCmdResetIsolatedChannel__)(struct KernelChannel *, NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGetClassEngineid__)(struct KernelChannel *, NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS *); @@ -241,6 +242,8 @@ struct KernelChannel { NV_STATUS (*__kchannelCtrlCmdGetEngineCtxState__)(struct KernelChannel *, NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGetChannelHwState__)(struct KernelChannel *, NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS *); NV_STATUS (*__kchannelCtrlCmdSetChannelHwState__)(struct KernelChannel *, NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS *); + NV_STATUS (*__kchannelCtrlCmdSaveEngineCtxData__)(struct KernelChannel *, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *); + NV_STATUS (*__kchannelCtrlCmdRestoreEngineCtxData__)(struct KernelChannel *, NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGetClassEngineidC06F__)(struct KernelChannel *, NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS *); NV_STATUS (*__kchannelCtrlCmdResetChannelC06F__)(struct KernelChannel *, NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGpFifoScheduleC06F__)(struct KernelChannel *, NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS *); @@ -352,6 +355,8 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelGetMapAddrSpace(pKernelChannel, pCallContext, mapFlags, pAddrSpace) kchannelGetMapAddrSpace_DISPATCH(pKernelChannel, pCallContext, mapFlags, pAddrSpace) #define kchannelGetMemInterMapParams(pKernelChannel, pParams) kchannelGetMemInterMapParams_DISPATCH(pKernelChannel, pParams) #define kchannelCheckMemInterUnmap(pKernelChannel, bSubdeviceHandleProvided) kchannelCheckMemInterUnmap_DISPATCH(pKernelChannel, bSubdeviceHandleProvided) +#define kchannelCreateUserMemDesc(pGpu, arg0) kchannelCreateUserMemDesc_DISPATCH(pGpu, arg0) +#define kchannelCreateUserMemDesc_HAL(pGpu, arg0) kchannelCreateUserMemDesc_DISPATCH(pGpu, arg0) #define kchannelIsUserdAddrSizeValid(pKernelChannel, userdAddrLo, userdAddrHi) kchannelIsUserdAddrSizeValid_DISPATCH(pKernelChannel, userdAddrLo, userdAddrHi) #define kchannelIsUserdAddrSizeValid_HAL(pKernelChannel, userdAddrLo, userdAddrHi) kchannelIsUserdAddrSizeValid_DISPATCH(pKernelChannel, userdAddrLo, userdAddrHi) #define kchannelCtrlCmdResetIsolatedChannel(pKernelChannel, pResetParams) kchannelCtrlCmdResetIsolatedChannel_DISPATCH(pKernelChannel, pResetParams) @@ -384,6 +389,8 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelCtrlCmdGetEngineCtxState(pKernelChannel, pCtxStateParams) kchannelCtrlCmdGetEngineCtxState_DISPATCH(pKernelChannel, pCtxStateParams) #define kchannelCtrlCmdGetChannelHwState(pKernelChannel, pParams) kchannelCtrlCmdGetChannelHwState_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlCmdSetChannelHwState(pKernelChannel, pParams) kchannelCtrlCmdSetChannelHwState_DISPATCH(pKernelChannel, pParams) +#define kchannelCtrlCmdSaveEngineCtxData(pKernelChannel, pCtxBuffParams) kchannelCtrlCmdSaveEngineCtxData_DISPATCH(pKernelChannel, pCtxBuffParams) +#define kchannelCtrlCmdRestoreEngineCtxData(pKernelChannel, pCtxBuffParams) kchannelCtrlCmdRestoreEngineCtxData_DISPATCH(pKernelChannel, pCtxBuffParams) #define kchannelCtrlCmdGetClassEngineidC06F(pKernelChannel, pParams) kchannelCtrlCmdGetClassEngineidC06F_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlCmdResetChannelC06F(pKernelChannel, pResetChannelParams) kchannelCtrlCmdResetChannelC06F_DISPATCH(pKernelChannel, pResetChannelParams) #define kchannelCtrlCmdGpFifoScheduleC06F(pKernelChannel, pSchedParams) kchannelCtrlCmdGpFifoScheduleC06F_DISPATCH(pKernelChannel, pSchedParams) @@ -593,19 +600,6 @@ static inline NV_STATUS kchannelDestroyUserdMemDesc(struct OBJGPU *pGpu, struct #define kchannelDestroyUserdMemDesc_HAL(pGpu, arg0) kchannelDestroyUserdMemDesc(pGpu, arg0) -NV_STATUS kchannelCreateUserMemDesc_GM107(struct OBJGPU *pGpu, struct KernelChannel *arg0); - -#ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelCreateUserMemDesc(struct OBJGPU *pGpu, struct KernelChannel *arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_channel_h_disabled -#define kchannelCreateUserMemDesc(pGpu, arg0) kchannelCreateUserMemDesc_GM107(pGpu, arg0) -#endif //__nvoc_kernel_channel_h_disabled - -#define kchannelCreateUserMemDesc_HAL(pGpu, arg0) kchannelCreateUserMemDesc(pGpu, arg0) - NV_STATUS kchannelGetEngine_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 *engDesc); #ifdef __nvoc_kernel_channel_h_disabled @@ -720,10 +714,24 @@ static inline NV_STATUS kchannelCheckMemInterUnmap_DISPATCH(struct KernelChannel return pKernelChannel->__kchannelCheckMemInterUnmap__(pKernelChannel, bSubdeviceHandleProvided); } +NV_STATUS kchannelCreateUserMemDesc_GM107(struct OBJGPU *pGpu, struct KernelChannel *arg0); + +NV_STATUS kchannelCreateUserMemDesc_GA10B(struct OBJGPU *pGpu, struct KernelChannel *arg0); + +static inline NV_STATUS kchannelCreateUserMemDesc_56cd7a(struct OBJGPU *pGpu, struct KernelChannel *arg0) { + return NV_OK; +} + +static inline NV_STATUS kchannelCreateUserMemDesc_DISPATCH(struct OBJGPU *pGpu, struct KernelChannel *arg0) { + return arg0->__kchannelCreateUserMemDesc__(pGpu, arg0); +} + NvBool kchannelIsUserdAddrSizeValid_GV100(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi); NvBool kchannelIsUserdAddrSizeValid_GA100(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi); +NvBool kchannelIsUserdAddrSizeValid_GH100(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi); + static inline NvBool kchannelIsUserdAddrSizeValid_cbe027(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi) { return ((NvBool)(0 == 0)); } @@ -938,6 +946,18 @@ static inline NV_STATUS kchannelCtrlCmdSetChannelHwState_DISPATCH(struct KernelC return pKernelChannel->__kchannelCtrlCmdSetChannelHwState__(pKernelChannel, pParams); } +NV_STATUS kchannelCtrlCmdSaveEngineCtxData_IMPL(struct KernelChannel *pKernelChannel, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *pCtxBuffParams); + +static inline NV_STATUS kchannelCtrlCmdSaveEngineCtxData_DISPATCH(struct KernelChannel *pKernelChannel, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *pCtxBuffParams) { + return pKernelChannel->__kchannelCtrlCmdSaveEngineCtxData__(pKernelChannel, pCtxBuffParams); +} + +NV_STATUS kchannelCtrlCmdRestoreEngineCtxData_IMPL(struct KernelChannel *pKernelChannel, NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS *pCtxBuffParams); + +static inline NV_STATUS kchannelCtrlCmdRestoreEngineCtxData_DISPATCH(struct KernelChannel *pKernelChannel, NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS *pCtxBuffParams) { + return pKernelChannel->__kchannelCtrlCmdRestoreEngineCtxData__(pKernelChannel, pCtxBuffParams); +} + static inline NV_STATUS kchannelCtrlCmdGetClassEngineidC06F_6a9a13(struct KernelChannel *pKernelChannel, NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS *pParams) { return kchannelCtrlCmdGetClassEngineid(pKernelChannel, pParams); } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index 3cb763058..e50affe99 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -33,6 +33,10 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_KernelFalcon = { }, }; +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// kflcnResetHw +// kflcnIsEngineInReset const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon = { /*classInfo=*/ { @@ -100,7 +104,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; } @@ -115,7 +119,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO // Hal function -- kflcnRiscvProgramBcr if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; } @@ -131,7 +135,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO // Hal function -- kflcnSwitchToFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; } @@ -166,7 +170,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO // Hal function -- kflcnWaitForResetToFinish if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; } @@ -191,7 +195,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; } @@ -206,7 +210,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO // Hal function -- kflcnIntrRetrigger if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; } @@ -226,7 +230,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; } @@ -245,7 +249,7 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; } @@ -280,9 +284,9 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; void __nvoc_init_GenericKernelFalcon(GenericKernelFalcon*, RmHalspecOwner* ); -void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon*, RmHalspecOwner* ); +void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon*); NV_STATUS __nvoc_ctor_GenericKernelFalcon(GenericKernelFalcon*, RmHalspecOwner* , struct OBJGPU * arg_pGpu, KernelFalconEngineConfig * arg_pFalconConfig); -void __nvoc_init_dataField_GenericKernelFalcon(GenericKernelFalcon*, RmHalspecOwner* ); +void __nvoc_init_dataField_GenericKernelFalcon(GenericKernelFalcon*); void __nvoc_dtor_GenericKernelFalcon(GenericKernelFalcon*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_GenericKernelFalcon; @@ -375,13 +379,8 @@ void __nvoc_dtor_GenericKernelFalcon(GenericKernelFalcon *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_GenericKernelFalcon(GenericKernelFalcon *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); @@ -395,7 +394,7 @@ NV_STATUS __nvoc_ctor_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecO if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail_IntrService; status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail_Object; - __nvoc_init_dataField_GenericKernelFalcon(pThis, pRmhalspecowner); + __nvoc_init_dataField_GenericKernelFalcon(pThis); status = __nvoc_gkflcnConstruct(pThis, arg_pGpu, arg_pFalconConfig); if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail__init; @@ -413,13 +412,8 @@ NV_STATUS __nvoc_ctor_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecO return status; } -static void __nvoc_init_funcTable_GenericKernelFalcon_1(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_GenericKernelFalcon_1(GenericKernelFalcon *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); pThis->__gkflcnResetHw__ = &gkflcnResetHw_IMPL; @@ -442,8 +436,8 @@ static void __nvoc_init_funcTable_GenericKernelFalcon_1(GenericKernelFalcon *pTh pThis->__gkflcnServiceInterrupt__ = &__nvoc_thunk_IntrService_gkflcnServiceInterrupt; } -void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_GenericKernelFalcon_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon *pThis) { + __nvoc_init_funcTable_GenericKernelFalcon_1(pThis); } void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); @@ -457,7 +451,7 @@ void __nvoc_init_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); __nvoc_init_Object(&pThis->__nvoc_base_Object, pRmhalspecowner); - __nvoc_init_funcTable_GenericKernelFalcon(pThis, pRmhalspecowner); + __nvoc_init_funcTable_GenericKernelFalcon(pThis); } NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KernelFalconEngineConfig * arg_pFalconConfig) { diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index 85d681e3d..ce971af9b 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -502,18 +502,6 @@ NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon**, Dynamic*, #define gkflcnServiceNotificationInterrupt(arg0, arg1, arg2) gkflcnServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define gkflcnClearInterrupt(pGpu, pIntrService, pParams) gkflcnClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define gkflcnServiceInterrupt(pGpu, pIntrService, pParams) gkflcnServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void gkflcnNonstallIntrCheckAndClear_TU102(struct OBJGPU *arg0, struct GenericKernelFalcon *pKernelFlcn, struct THREAD_STATE_NODE *arg1); - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void gkflcnNonstallIntrCheckAndClear(struct OBJGPU *arg0, struct GenericKernelFalcon *pKernelFlcn, struct THREAD_STATE_NODE *arg1) { - NV_ASSERT_FAILED_PRECOMP("GenericKernelFalcon was disabled!"); -} -#else //__nvoc_kernel_falcon_h_disabled -#define gkflcnNonstallIntrCheckAndClear(arg0, pKernelFlcn, arg1) gkflcnNonstallIntrCheckAndClear_TU102(arg0, pKernelFlcn, arg1) -#endif //__nvoc_kernel_falcon_h_disabled - -#define gkflcnNonstallIntrCheckAndClear_HAL(arg0, pKernelFlcn, arg1) gkflcnNonstallIntrCheckAndClear(arg0, pKernelFlcn, arg1) - NV_STATUS gkflcnResetHw_IMPL(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn); static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn) { diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index 06b2344bb..b3df44baf 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -172,7 +172,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bUseChidHeap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bUseChidHeap = ((NvBool)(0 == 0)); } @@ -186,7 +186,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals pThis->bUsePerRunlistChram = ((NvBool)(0 != 0)); // Hal field -- bIsPerRunlistChramSupportedInHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bIsPerRunlistChramSupportedInHw = ((NvBool)(0 == 0)); } @@ -197,7 +197,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bHostEngineExpansion - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bHostEngineExpansion = ((NvBool)(0 == 0)); } @@ -218,7 +218,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bSubcontextSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bSubcontextSupported = ((NvBool)(0 == 0)); } @@ -229,7 +229,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bMixedInstmemApertureDefAllowed - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bMixedInstmemApertureDefAllowed = ((NvBool)(0 == 0)); } @@ -240,7 +240,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bIsZombieSubctxWarEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bIsZombieSubctxWarEnabled = ((NvBool)(0 == 0)); } @@ -251,7 +251,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bIsSchedSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bIsSchedSupported = ((NvBool)(0 == 0)); } @@ -295,7 +295,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoStateDestroy__ = &kfifoStateDestroy_IMPL; // Hal function -- kfifoStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; } @@ -307,7 +307,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner } // Hal function -- kfifoStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; } @@ -315,12 +315,43 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { } + // Hal function -- kfifoCheckChannelAllocAddrSpaces + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoCheckChannelAllocAddrSpaces__ = &kfifoCheckChannelAllocAddrSpaces_GH100; + } + // default + else + { + pThis->__kfifoCheckChannelAllocAddrSpaces__ = &kfifoCheckChannelAllocAddrSpaces_56cd7a; + } + + // Hal function -- kfifoGetMmioUsermodeOffset + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_474d46; + } + + // Hal function -- kfifoGetMmioUsermodeSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_474d46; + } + // Hal function -- kfifoChannelGroupGetLocalMaxSubcontext if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GA100; } @@ -331,6 +362,17 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { } + // Hal function -- kfifoGetCtxBufferMapFlags + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetCtxBufferMapFlags__ = &kfifoGetCtxBufferMapFlags_GH100; + } + // default + else + { + pThis->__kfifoGetCtxBufferMapFlags__ = &kfifoGetCtxBufferMapFlags_b3696a; + } + // Hal function -- kfifoEngineInfoXlate if (0) { @@ -339,7 +381,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GA100; } @@ -358,7 +400,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_GA100; } @@ -374,7 +416,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_GA100; } @@ -382,6 +424,22 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { } + // Hal function -- kfifoGetMaxNumRunlists + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kfifoGetMaxNumRunlists__ = &kfifoGetMaxNumRunlists_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetMaxNumRunlists__ = &kfifoGetMaxNumRunlists_GH100; + } + else if (0) + { + } + else if (0) + { + } + // Hal function -- kfifoRunlistGetBaseShift if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -391,7 +449,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA102; } @@ -404,7 +462,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } @@ -417,7 +475,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GA100; } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index b0c853d69..08dbfa10e 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -388,7 +388,7 @@ MAKE_LIST(FifoSchedulingHandlerEntryList, FifoSchedulingHandlerEntry); #define INST_BLOCK_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 #define INST_BLOCK_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 -// Macro to verify HW/class defines are compatible +// Macro to verify HW and class defines are compatible #define VERIFY_INST_BLOCK_APERTURE(vid, coh, ncoh) \ ct_assert((vid) == INST_BLOCK_APERTURE_VIDEO_MEMORY); \ ct_assert((coh) == INST_BLOCK_APERTURE_SYSTEM_COHERENT_MEMORY); \ @@ -413,10 +413,15 @@ struct KernelFifo { void (*__kfifoStateDestroy__)(struct OBJGPU *, struct KernelFifo *); NV_STATUS (*__kfifoStatePostLoad__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreUnload__)(struct OBJGPU *, struct KernelFifo *, NvU32); + NV_STATUS (*__kfifoCheckChannelAllocAddrSpaces__)(struct KernelFifo *, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE); + NvU64 (*__kfifoGetMmioUsermodeOffset__)(struct OBJGPU *, struct KernelFifo *, NvBool); + NvU64 (*__kfifoGetMmioUsermodeSize__)(struct OBJGPU *, struct KernelFifo *, NvBool); NvU32 (*__kfifoChannelGroupGetLocalMaxSubcontext__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannelGroup *, NvBool); + void (*__kfifoGetCtxBufferMapFlags__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32 *); NV_STATUS (*__kfifoEngineInfoXlate__)(struct OBJGPU *, struct KernelFifo *, ENGINE_INFO_TYPE, NvU32, ENGINE_INFO_TYPE, NvU32 *); NV_STATUS (*__kfifoGenerateWorkSubmitToken__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannel *, NvU32 *, NvBool); NV_STATUS (*__kfifoUpdateUsermodeDoorbell__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32); + NvU32 (*__kfifoGetMaxNumRunlists__)(struct OBJGPU *, struct KernelFifo *); NvU32 (*__kfifoRunlistGetBaseShift__)(struct KernelFifo *); NvU32 (*__kfifoGetMaxCeChannelGroups__)(struct OBJGPU *, struct KernelFifo *); void (*__kfifoSetupUserD__)(struct KernelFifo *, NvU8 *); @@ -504,14 +509,24 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoStatePostLoad_HAL(pGpu, pKernelFifo, flags) kfifoStatePostLoad_DISPATCH(pGpu, pKernelFifo, flags) #define kfifoStatePreUnload(pGpu, pKernelFifo, flags) kfifoStatePreUnload_DISPATCH(pGpu, pKernelFifo, flags) #define kfifoStatePreUnload_HAL(pGpu, pKernelFifo, flags) kfifoStatePreUnload_DISPATCH(pGpu, pKernelFifo, flags) +#define kfifoCheckChannelAllocAddrSpaces(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) +#define kfifoCheckChannelAllocAddrSpaces_HAL(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) +#define kfifoGetMmioUsermodeOffset(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetMmioUsermodeSize(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) #define kfifoChannelGroupGetLocalMaxSubcontext(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) #define kfifoChannelGroupGetLocalMaxSubcontext_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) +#define kfifoGetCtxBufferMapFlags(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags_DISPATCH(pGpu, pKernelFifo, engine, pFlags) +#define kfifoGetCtxBufferMapFlags_HAL(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags_DISPATCH(pGpu, pKernelFifo, engine, pFlags) #define kfifoEngineInfoXlate(pGpu, pKernelFifo, inType, inVal, outType, pOutVal) kfifoEngineInfoXlate_DISPATCH(pGpu, pKernelFifo, inType, inVal, outType, pOutVal) #define kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, inType, inVal, outType, pOutVal) kfifoEngineInfoXlate_DISPATCH(pGpu, pKernelFifo, inType, inVal, outType, pOutVal) #define kfifoGenerateWorkSubmitToken(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) kfifoGenerateWorkSubmitToken_DISPATCH(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) #define kfifoGenerateWorkSubmitToken_HAL(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) kfifoGenerateWorkSubmitToken_DISPATCH(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) #define kfifoUpdateUsermodeDoorbell(arg0, arg1, workSubmitToken, runlisId) kfifoUpdateUsermodeDoorbell_DISPATCH(arg0, arg1, workSubmitToken, runlisId) #define kfifoUpdateUsermodeDoorbell_HAL(arg0, arg1, workSubmitToken, runlisId) kfifoUpdateUsermodeDoorbell_DISPATCH(arg0, arg1, workSubmitToken, runlisId) +#define kfifoGetMaxNumRunlists(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_DISPATCH(pGpu, pKernelFifo) +#define kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_DISPATCH(pGpu, pKernelFifo) #define kfifoRunlistGetBaseShift(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoRunlistGetBaseShift_HAL(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoGetMaxCeChannelGroups(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) @@ -718,21 +733,6 @@ static inline NV_STATUS kfifoChannelGetFifoContextMemDesc(struct OBJGPU *pGpu, s #define kfifoChannelGetFifoContextMemDesc_HAL(pGpu, pKernelFifo, pKernelChannel, engState, ppMemdesc) kfifoChannelGetFifoContextMemDesc(pGpu, pKernelFifo, pKernelChannel, engState, ppMemdesc) -static inline NV_STATUS kfifoCheckChannelAllocAddrSpaces_56cd7a(struct KernelFifo *pKernelFifo, NV_ADDRESS_SPACE userdAddrSpace, NV_ADDRESS_SPACE pushBuffAddrSpace, NV_ADDRESS_SPACE gpFifoAddrSpace) { - return NV_OK; -} - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoCheckChannelAllocAddrSpaces(struct KernelFifo *pKernelFifo, NV_ADDRESS_SPACE userdAddrSpace, NV_ADDRESS_SPACE pushBuffAddrSpace, NV_ADDRESS_SPACE gpFifoAddrSpace) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoCheckChannelAllocAddrSpaces(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_56cd7a(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoCheckChannelAllocAddrSpaces_HAL(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) - NV_STATUS kfifoConvertInstToKernelChannel_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, INST_BLOCK_DESC *arg0, struct KernelChannel **arg1); #ifdef __nvoc_kernel_fifo_h_disabled @@ -746,36 +746,6 @@ static inline NV_STATUS kfifoConvertInstToKernelChannel(struct OBJGPU *pGpu, str #define kfifoConvertInstToKernelChannel_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoConvertInstToKernelChannel(pGpu, pKernelFifo, arg0, arg1) -static inline NvU64 kfifoGetMmioUsermodeOffset_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU64 kfifoGetMmioUsermodeOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return 0; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetMmioUsermodeOffset(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_474d46(pGpu, pKernelFifo, arg0) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset(pGpu, pKernelFifo, arg0) - -static inline NvU64 kfifoGetMmioUsermodeSize_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU64 kfifoGetMmioUsermodeSize(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return 0; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetMmioUsermodeSize(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_474d46(pGpu, pKernelFifo, arg0) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize(pGpu, pKernelFifo, arg0) - NV_STATUS kfifoGetUsermodeMapInfo_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *arg0, NvU32 *arg1); #ifdef __nvoc_kernel_fifo_h_disabled @@ -843,20 +813,6 @@ static inline NvU32 kfifoGetMaxChannelGroupSize(struct KernelFifo *pKernelFifo) #define kfifoGetMaxChannelGroupSize_HAL(pKernelFifo) kfifoGetMaxChannelGroupSize(pKernelFifo) -static inline void kfifoGetCtxBufferMapFlags_b3696a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engine, NvU32 *pFlags) { - return; -} - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline void kfifoGetCtxBufferMapFlags(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engine, NvU32 *pFlags) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetCtxBufferMapFlags(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags_b3696a(pGpu, pKernelFifo, engine, pFlags) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetCtxBufferMapFlags_HAL(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags(pGpu, pKernelFifo, engine, pFlags) - static inline NV_STATUS kfifoAddObject_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct ChannelDescendant *pObject) { return NV_OK; } @@ -996,19 +952,6 @@ static inline const char *kfifoGetEngineName(struct KernelFifo *pKernelFifo, ENG #define kfifoGetEngineName_HAL(pKernelFifo, inType, inVal) kfifoGetEngineName(pKernelFifo, inType, inVal) -NvU32 kfifoGetMaxNumRunlists_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU32 kfifoGetMaxNumRunlists(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return 0; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetMaxNumRunlists(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_GM107(pGpu, pKernelFifo) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo) kfifoGetMaxNumRunlists(pGpu, pKernelFifo) - NV_STATUS kfifoGetEnginePbdmaIds_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE type, NvU32 val, NvU32 **ppPbdmaIds, NvU32 *pNumPbdmas); #ifdef __nvoc_kernel_fifo_h_disabled @@ -1288,6 +1231,36 @@ static inline NV_STATUS kfifoStatePreUnload_DISPATCH(struct OBJGPU *pGpu, struct return pKernelFifo->__kfifoStatePreUnload__(pGpu, pKernelFifo, flags); } +NV_STATUS kfifoCheckChannelAllocAddrSpaces_GH100(struct KernelFifo *pKernelFifo, NV_ADDRESS_SPACE userdAddrSpace, NV_ADDRESS_SPACE pushBuffAddrSpace, NV_ADDRESS_SPACE gpFifoAddrSpace); + +static inline NV_STATUS kfifoCheckChannelAllocAddrSpaces_56cd7a(struct KernelFifo *pKernelFifo, NV_ADDRESS_SPACE userdAddrSpace, NV_ADDRESS_SPACE pushBuffAddrSpace, NV_ADDRESS_SPACE gpFifoAddrSpace) { + return NV_OK; +} + +static inline NV_STATUS kfifoCheckChannelAllocAddrSpaces_DISPATCH(struct KernelFifo *pKernelFifo, NV_ADDRESS_SPACE userdAddrSpace, NV_ADDRESS_SPACE pushBuffAddrSpace, NV_ADDRESS_SPACE gpFifoAddrSpace) { + return pKernelFifo->__kfifoCheckChannelAllocAddrSpaces__(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace); +} + +NvU64 kfifoGetMmioUsermodeOffset_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); + +static inline NvU64 kfifoGetMmioUsermodeOffset_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU64 kfifoGetMmioUsermodeOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { + return pKernelFifo->__kfifoGetMmioUsermodeOffset__(pGpu, pKernelFifo, arg0); +} + +NvU64 kfifoGetMmioUsermodeSize_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); + +static inline NvU64 kfifoGetMmioUsermodeSize_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU64 kfifoGetMmioUsermodeSize_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { + return pKernelFifo->__kfifoGetMmioUsermodeSize__(pGpu, pKernelFifo, arg0); +} + NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1); NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1); @@ -1300,6 +1273,16 @@ static inline NvU32 kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(struct OBJGP return pKernelFifo->__kfifoChannelGroupGetLocalMaxSubcontext__(pGpu, pKernelFifo, arg0, arg1); } +void kfifoGetCtxBufferMapFlags_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engine, NvU32 *pFlags); + +static inline void kfifoGetCtxBufferMapFlags_b3696a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engine, NvU32 *pFlags) { + return; +} + +static inline void kfifoGetCtxBufferMapFlags_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engine, NvU32 *pFlags) { + pKernelFifo->__kfifoGetCtxBufferMapFlags__(pGpu, pKernelFifo, engine, pFlags); +} + NV_STATUS kfifoEngineInfoXlate_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal, ENGINE_INFO_TYPE outType, NvU32 *pOutVal); NV_STATUS kfifoEngineInfoXlate_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal, ENGINE_INFO_TYPE outType, NvU32 *pOutVal); @@ -1336,6 +1319,18 @@ static inline NV_STATUS kfifoUpdateUsermodeDoorbell_DISPATCH(struct OBJGPU *arg0 return arg1->__kfifoUpdateUsermodeDoorbell__(arg0, arg1, workSubmitToken, runlisId); } +NvU32 kfifoGetMaxNumRunlists_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + +NvU32 kfifoGetMaxNumRunlists_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + +static inline NvU32 kfifoGetMaxNumRunlists_4a4dee(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return 0; +} + +static inline NvU32 kfifoGetMaxNumRunlists_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return pKernelFifo->__kfifoGetMaxNumRunlists__(pGpu, pKernelFifo); +} + NvU32 kfifoRunlistGetBaseShift_GM107(struct KernelFifo *pKernelFifo); NvU32 kfifoRunlistGetBaseShift_GA100(struct KernelFifo *pKernelFifo); @@ -1434,7 +1429,7 @@ static inline NvBool kfifoIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFifo *pE return pEngstate->__kfifoIsPresent__(pGpu, pEngstate); } -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice) { +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice, NvU32 flags) { return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index 1ac0db926..bd2b2e4bf 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -199,7 +199,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bCtxswLoggingSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bCtxswLoggingSupported = ((NvBool)(0 == 0)); } @@ -219,7 +219,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bPerSubcontextContextHeaderSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bPerSubcontextContextHeaderSupported = ((NvBool)(0 == 0)); } @@ -230,7 +230,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bSetContextBuffersGPUPrivileged - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bSetContextBuffersGPUPrivileged = ((NvBool)(0 == 0)); } @@ -241,7 +241,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bUcodeSupportsPrivAccessMap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bUcodeSupportsPrivAccessMap = ((NvBool)(0 == 0)); } @@ -252,7 +252,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bRtvCbSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bRtvCbSupported = ((NvBool)(0 == 0)); } @@ -315,7 +315,7 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL; // Hal function -- kgraphicsClearInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; } @@ -324,7 +324,7 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals } // Hal function -- kgraphicsServiceInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index 35bf576d0..610d24215 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -216,6 +216,17 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + // Hal field -- bPartitionedFmc + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->bPartitionedFmc = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bPartitionedFmc = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); @@ -267,7 +278,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; } @@ -286,7 +297,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; } @@ -298,6 +309,44 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { } + // Hal function -- kgspAllocBootArgs + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; + } + else if (0) + { + } + } + else if (0) + { + } + + // Hal function -- kgspFreeBootArgs + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; + } + else if (0) + { + } + } + else if (0) + { + } + // Hal function -- kgspBootstrapRiscvOSEarly if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -305,10 +354,14 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; + } else if (0) { } @@ -324,7 +377,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; } @@ -351,9 +404,67 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; + } else if (0) { } + } + else if (0) + { + } + + // Hal function -- kgspGetBinArchiveGspRmCcGfwDebugSigned + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmCcGfwDebugSigned__ = &kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmCcGfwDebugSigned__ = &kgspGetBinArchiveGspRmCcGfwDebugSigned_80f438; + } + } + else if (0) + { + } + + // Hal function -- kgspGetBinArchiveGspRmCcGfwProdSigned + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmCcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmCcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcGfwProdSigned_80f438; + } + } + else if (0) + { + } + + // Hal function -- kgspCalculateFbLayout + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; + } else if (0) { } @@ -362,6 +473,26 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { } + // Hal function -- kgspGetNonWprHeapSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; + } + // default + else + { + } + } + else if (0) + { + } + // Hal function -- kgspExecuteSequencerCommand if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -369,7 +500,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; } @@ -388,7 +519,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; } @@ -403,12 +534,13 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * // Hal function -- kgspResetHw if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgspResetHw__ = &kgspResetHw_TU102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kgspResetHw__ = &kgspResetHw_GH100; } else if (0) { @@ -421,7 +553,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * // Hal function -- kgspIsEngineInReset if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kgspIsEngineInReset__ = &kgspIsEngineInReset_TU102; } @@ -436,11 +568,11 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * // Hal function -- kgspGetFrtsSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; } @@ -449,14 +581,33 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { } + // Hal function -- kgspExtractVbiosFromRom + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; + } + else if (0) + { + } + } + else if (0) + { + } + // Hal function -- kgspExecuteFwsecFrts if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; } @@ -465,6 +616,57 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { } + // Hal function -- kgspExecuteFwsecSb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; + } + else if (0) + { + } + } + else if (0) + { + } + + // Hal function -- kgspExecuteBooterLoad + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; + } + } + else if (0) + { + } + + // Hal function -- kgspExecuteBooterUnloadIfNeeded + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; + } + } + else if (0) + { + } + // Hal function -- kgspExecuteHsFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -472,10 +674,30 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; + } + } + else if (0) + { + } + + // Hal function -- kgspWaitForGfwBootOk + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; + } else if (0) { } @@ -503,8 +725,13 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; } } else if (0) @@ -530,8 +757,13 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; } } else if (0) @@ -557,10 +789,34 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_ab7237; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_20361c; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_5f1986; + } + // default + else + { + } + } + else if (0) + { + } + + // Hal function -- kgspSetupGspFmcArgs + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; + } // default else { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_9e2234; + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } } else if (0) diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 0657f317c..9f26a8887 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -58,6 +58,7 @@ extern "C" { * Forward declarations */ typedef struct SimAccessBuffer SimAccessBuffer; +typedef struct GSP_CC_BOOT_PARAMS GSP_CC_BOOT_PARAMS; /*! * Structure for VBIOS image for early FRTS. @@ -244,19 +245,31 @@ struct KernelGsp { NvU32 (*__kgspServiceInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceServiceInterruptArguments *); void (*__kgspConfigureFalcon__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspIsDebugModeEnabled__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspAllocBootArgs__)(struct OBJGPU *, struct KernelGsp *); + void (*__kgspFreeBootArgs__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspBootstrapRiscvOSEarly__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspGetGspRmBootUcodeStorage__)(struct OBJGPU *, struct KernelGsp *, BINDATA_STORAGE **, BINDATA_STORAGE **); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmBoot__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcGfwDebugSigned__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcGfwProdSigned__)(struct KernelGsp *); + NV_STATUS (*__kgspCalculateFbLayout__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + NvU32 (*__kgspGetNonWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp *, NvU32); NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspIsEngineInReset__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **); NV_STATUS (*__kgspExecuteFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64); + NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *); + NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64); + NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); + NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); const char *(*__kgspGetSignatureSectionName__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); void (*__kgspFreeTunableState__)(POBJGPU, struct KernelGsp *, void *); NV_STATUS (*__kgspCompareTunableState__)(POBJGPU, struct KernelGsp *, void *, void *); @@ -285,6 +298,9 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pWprMetaDescriptor; GspFwWprMeta *pWprMeta; NvP64 pWprMetaMappingPriv; + MEMORY_DESCRIPTOR *pGspFmcArgumentsDescriptor; + GSP_CC_BOOT_PARAMS *pGspFmcArgumentsCached; + NvP64 pGspFmcArgumentsMappingPriv; MEMORY_DESCRIPTOR *pLibosInitArgumentsDescriptor; LibosMemoryRegionInitArgument *pLibosInitArgumentsCached; NvP64 pLibosInitArgumentsMappingPriv; @@ -301,11 +317,14 @@ struct KernelGsp { LIBOS_LOG_DECODE logDecode; RM_LIBOS_LOG_MEM rmLibosLogMem[2]; void *pLogElf; + NvBool bLibosLogsPollingEnabled; + NvBool bXid119Printed; NvBool bInInit; MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf; SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; GspStaticConfigInfo gspStaticInfo; + NvBool bPartitionedFmc; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -345,12 +364,24 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspConfigureFalcon_HAL(pGpu, pKernelGsp) kgspConfigureFalcon_DISPATCH(pGpu, pKernelGsp) #define kgspIsDebugModeEnabled(pGpu, pKernelGsp) kgspIsDebugModeEnabled_DISPATCH(pGpu, pKernelGsp) #define kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp) kgspIsDebugModeEnabled_DISPATCH(pGpu, pKernelGsp) +#define kgspAllocBootArgs(pGpu, pKernelGsp) kgspAllocBootArgs_DISPATCH(pGpu, pKernelGsp) +#define kgspAllocBootArgs_HAL(pGpu, pKernelGsp) kgspAllocBootArgs_DISPATCH(pGpu, pKernelGsp) +#define kgspFreeBootArgs(pGpu, pKernelGsp) kgspFreeBootArgs_DISPATCH(pGpu, pKernelGsp) +#define kgspFreeBootArgs_HAL(pGpu, pKernelGsp) kgspFreeBootArgs_DISPATCH(pGpu, pKernelGsp) #define kgspBootstrapRiscvOSEarly(pGpu, pKernelGsp, pGspFw) kgspBootstrapRiscvOSEarly_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw) kgspBootstrapRiscvOSEarly_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspGetGspRmBootUcodeStorage(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetGspRmBootUcodeStorage_HAL(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetBinArchiveGspRmBoot(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmBoot_HAL(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcGfwDebugSigned(pKernelGsp) kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcGfwDebugSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspGetNonWprHeapSize(pGpu, pKernelGsp) kgspGetNonWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetNonWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetNonWprHeapSize_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteSequencerCommand(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize) kgspExecuteSequencerCommand_DISPATCH(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize) #define kgspExecuteSequencerCommand_HAL(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize) kgspExecuteSequencerCommand_DISPATCH(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize) #define kgspReadUcodeFuseVersion(pGpu, pKernelGsp, ucodeId) kgspReadUcodeFuseVersion_DISPATCH(pGpu, pKernelGsp, ucodeId) @@ -361,16 +392,28 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspIsEngineInReset_HAL(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize_HAL(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) +#define kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) +#define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) #define kgspExecuteFwsecFrts(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) #define kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) +#define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) +#define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) +#define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) +#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) +#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) +#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteHsFalcon(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) +#define kgspWaitForGfwBootOk(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) +#define kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) #define kgspGetBinArchiveBooterLoadUcode(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetSignatureSectionName(pGpu, pKernelGsp) kgspGetSignatureSectionName_DISPATCH(pGpu, pKernelGsp) #define kgspGetSignatureSectionName_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionName_DISPATCH(pGpu, pKernelGsp) +#define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspStateDestroy(pGpu, pEngstate) kgspStateDestroy_DISPATCH(pGpu, pEngstate) #define kgspFreeTunableState(pGpu, pEngstate, pTunableState) kgspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) @@ -392,31 +435,6 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspStatePostLoad(pGpu, pEngstate, arg0) kgspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspAllocTunableState(pGpu, pEngstate, ppTunableState) kgspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define kgspSetTunableState(pGpu, pEngstate, pTunableState) kgspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -NV_STATUS kgspAllocBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspAllocBootArgs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspAllocBootArgs(pGpu, pKernelGsp) kgspAllocBootArgs_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspAllocBootArgs_HAL(pGpu, pKernelGsp) kgspAllocBootArgs(pGpu, pKernelGsp) - -void kgspFreeBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline void kgspFreeBootArgs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspFreeBootArgs(pGpu, pKernelGsp) kgspFreeBootArgs_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspFreeBootArgs_HAL(pGpu, pKernelGsp) kgspFreeBootArgs(pGpu, pKernelGsp) - void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -442,34 +460,6 @@ static inline NV_STATUS kgspSetCmdQueueHead(struct OBJGPU *pGpu, struct KernelGs #define kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead(pGpu, pKernelGsp, queueIdx, value) -NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspCalculateFbLayout(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_TU102(pGpu, pKernelGsp, pGspFw) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) - -static inline NvU32 kgspGetNonWprHeapSize_ed6b8b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return 1048576; -} - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NvU32 kgspGetNonWprHeapSize(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return 0; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspGetNonWprHeapSize(pGpu, pKernelGsp) kgspGetNonWprHeapSize_ed6b8b(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspGetNonWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetNonWprHeapSize(pGpu, pKernelGsp) - void kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -495,71 +485,6 @@ static inline NvU32 kgspService(struct OBJGPU *pGpu, struct KernelGsp *pKernelGs #define kgspService_HAL(pGpu, pKernelGsp) kgspService(pGpu, pKernelGsp) -NV_STATUS kgspExtractVbiosFromRom_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspExtractVbiosFromRom(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_TU102(pGpu, pKernelGsp, ppVbiosImg) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) - -NV_STATUS kgspExecuteFwsecSb_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspExecuteFwsecSb(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_TU102(pGpu, pKernelGsp, pFwsecUcode) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) - -NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspExecuteBooterLoad(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_TU102(pGpu, pKernelGsp, gspFwWprMetaOffset) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) - -NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) - -NV_STATUS kgspWaitForGfwBootOk_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspWaitForGfwBootOk(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspWaitForGfwBootOk(pGpu, pKernelGsp) kgspWaitForGfwBootOk_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp) kgspWaitForGfwBootOk(pGpu, pKernelGsp) - NV_STATUS kgspWaitForProcessorSuspend_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -615,10 +540,36 @@ static inline NvBool kgspIsDebugModeEnabled_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspIsDebugModeEnabled__(pGpu, pKernelGsp); } +NV_STATUS kgspAllocBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +NV_STATUS kgspAllocBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspAllocBootArgs_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspAllocBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspAllocBootArgs__(pGpu, pKernelGsp); +} + +void kgspFreeBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +void kgspFreeBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline void kgspFreeBootArgs_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kgspFreeBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + pKernelGsp->__kgspFreeBootArgs__(pGpu, pKernelGsp); +} + NV_STATUS kgspBootstrapRiscvOSEarly_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); NV_STATUS kgspBootstrapRiscvOSEarly_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); +NV_STATUS kgspBootstrapRiscvOSEarly_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + static inline NV_STATUS kgspBootstrapRiscvOSEarly_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } @@ -645,6 +596,10 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA100(struct KernelGsp *pKerne const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA102(struct KernelGsp *pKernelGsp); +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKernelGsp); + +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKernelGsp); + static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_80f438(struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); } @@ -653,6 +608,54 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_DISPATCH(struct return pKernelGsp->__kgspGetBinArchiveGspRmBoot__(pKernelGsp); } +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmCcGfwDebugSigned__(pKernelGsp); +} + +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmCcGfwProdSigned__(pKernelGsp); +} + +NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +NV_STATUS kgspCalculateFbLayout_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +static inline NV_STATUS kgspCalculateFbLayout_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspCalculateFbLayout_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + return pKernelGsp->__kgspCalculateFbLayout__(pGpu, pKernelGsp, pGspFw); +} + +static inline NvU32 kgspGetNonWprHeapSize_ed6b8b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 1048576; +} + +static inline NvU32 kgspGetNonWprHeapSize_d505ea(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 2097152; +} + +static inline NvU32 kgspGetNonWprHeapSize_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NvU32 kgspGetNonWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetNonWprHeapSize__(pGpu, pKernelGsp); +} + NV_STATUS kgspExecuteSequencerCommand_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize); NV_STATUS kgspExecuteSequencerCommand_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize); @@ -681,6 +684,8 @@ static inline NvU32 kgspReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struc NV_STATUS kgspResetHw_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +NV_STATUS kgspResetHw_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + static inline NV_STATUS kgspResetHw_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } @@ -713,6 +718,20 @@ static inline NvU32 kgspGetFrtsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelG return pKernelGsp->__kgspGetFrtsSize__(pGpu, pKernelGsp); } +NV_STATUS kgspExtractVbiosFromRom_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg); + +static inline NV_STATUS kgspExtractVbiosFromRom_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgspExtractVbiosFromRom_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExtractVbiosFromRom_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { + return pKernelGsp->__kgspExtractVbiosFromRom__(pGpu, pKernelGsp, ppVbiosImg); +} + NV_STATUS kgspExecuteFwsecFrts_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset); static inline NV_STATUS kgspExecuteFwsecFrts_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset) { @@ -723,6 +742,40 @@ static inline NV_STATUS kgspExecuteFwsecFrts_DISPATCH(struct OBJGPU *pGpu, struc return pKernelGsp->__kgspExecuteFwsecFrts__(pGpu, pKernelGsp, pFwsecUcode, frtsOffset); } +NV_STATUS kgspExecuteFwsecSb_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode); + +static inline NV_STATUS kgspExecuteFwsecSb_ac1694(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { + return NV_OK; +} + +static inline NV_STATUS kgspExecuteFwsecSb_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExecuteFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { + return pKernelGsp->__kgspExecuteFwsecSb__(pGpu, pKernelGsp, pFwsecUcode); +} + +NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); + +static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExecuteBooterLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { + return pKernelGsp->__kgspExecuteBooterLoad__(pGpu, pKernelGsp, gspFwWprMetaOffset); +} + +NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspExecuteBooterUnloadIfNeeded__(pGpu, pKernelGsp); +} + NV_STATUS kgspExecuteHsFalcon_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFlcnUcode, struct KernelFalcon *pKernelFlcn, NvU32 *pMailbox0, NvU32 *pMailbox1); NV_STATUS kgspExecuteHsFalcon_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFlcnUcode, struct KernelFalcon *pKernelFlcn, NvU32 *pMailbox0, NvU32 *pMailbox1); @@ -735,6 +788,18 @@ static inline NV_STATUS kgspExecuteHsFalcon_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspExecuteHsFalcon__(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1); } +NV_STATUS kgspWaitForGfwBootOk_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +NV_STATUS kgspWaitForGfwBootOk_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspWaitForGfwBootOk_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspWaitForGfwBootOk_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspWaitForGfwBootOk__(pGpu, pKernelGsp); +} + const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU102(struct KernelGsp *pKernelGsp); const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU116(struct KernelGsp *pKernelGsp); @@ -743,6 +808,8 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA100(struct KernelGsp * const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA102(struct KernelGsp *pKernelGsp); +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_AD102(struct KernelGsp *pKernelGsp); + static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_80f438(struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); } @@ -759,6 +826,8 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA100(struct KernelGsp const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA102(struct KernelGsp *pKernelGsp); +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_AD102(struct KernelGsp *pKernelGsp); + static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_80f438(struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); } @@ -783,6 +852,14 @@ static inline const char *kgspGetSignatureSectionName_ab7237(struct OBJGPU *pGpu return ".fwsignature_tu11x"; } +static inline const char *kgspGetSignatureSectionName_20361c(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return ".fwsignature_ad10x"; +} + +static inline const char *kgspGetSignatureSectionName_5f1986(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return ".fwsignature_gh100"; +} + static inline const char *kgspGetSignatureSectionName_9e2234(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return ((void *)0); } @@ -795,6 +872,16 @@ static inline const char *kgspGetSignatureSectionName_DISPATCH(struct OBJGPU *pG return pKernelGsp->__kgspGetSignatureSectionName__(pGpu, pKernelGsp); } +NV_STATUS kgspSetupGspFmcArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +static inline NV_STATUS kgspSetupGspFmcArgs_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspSetupGspFmcArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + return pKernelGsp->__kgspSetupGspFmcArgs__(pGpu, pKernelGsp, pGspFw); +} + static inline void kgspStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { pEngstate->__kgspStateDestroy__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index bfcfc7e58..0390b7d35 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -116,11 +116,11 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner // Hal function -- kheadProcessVblankCallbacks if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; } @@ -132,11 +132,11 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner // Hal function -- kheadResetPendingVblank if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_v04_00_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; } @@ -151,11 +151,11 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner // Hal function -- kheadResetPendingVblankForKernel if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_v04_00_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_e426af; } @@ -170,11 +170,11 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner // Hal function -- kheadReadPendingVblank if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_v04_00_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_92bfc3; } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c index c44d95525..a00a5dde0 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c @@ -180,7 +180,7 @@ void __nvoc_init_dataField_KernelIoctrl(KernelIoctrl *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KIOCTRL_MINION_AVAILABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KIOCTRL_MINION_AVAILABLE, ((NvBool)(0 == 0))); } @@ -225,7 +225,7 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; } @@ -241,7 +241,7 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index d4925015b..97d92c8f5 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.c b/src/nvidia/generated/g_kernel_mc_nvoc.c index f0796a788..4b53d808d 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.c +++ b/src/nvidia/generated/g_kernel_mc_nvoc.c @@ -70,12 +70,12 @@ static NV_STATUS __nvoc_thunk_KernelMc_engstateStateInitLocked(struct OBJGPU *pG return kmcStateInitLocked(pGpu, (struct KernelMc *)(((unsigned char *)pKernelMc) - __nvoc_rtti_KernelMc_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); +static NV_STATUS __nvoc_thunk_KernelMc_engstateStateLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelMc, NvU32 arg0) { + return kmcStateLoad(pGpu, (struct KernelMc *)(((unsigned char *)pKernelMc) - __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStateLoad(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { + return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStateUnload(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { @@ -191,12 +191,14 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR pThis->__kmcStateInitLocked__ = &kmcStateInitLocked_IMPL; + pThis->__kmcStateLoad__ = &kmcStateLoad_IMPL; + // Hal function -- kmcWritePmcEnableReg if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GA100; } @@ -209,7 +211,7 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GA100; } @@ -219,9 +221,9 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelMc_engstateStateInitLocked; - pThis->__kmcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelMc_engstateStateLoad; - pThis->__kmcStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmcStateLoad; + pThis->__kmcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState; pThis->__kmcStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kmcStateUnload; diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index 451d20220..8ff0c1ae6 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,6 +44,13 @@ extern "C" { #include "gpu/eng_state.h" #include "gpu/gpu_halspec.h" +// Latency Timer Control determines how we set or dont set the PCI latency timer. +typedef struct LATENCY_TIMER_CONTROL +{ + NvBool DontModifyTimerValue; // Dont touch the timer value at all. + NvU32 LatencyTimerValue; // Requested value for PCI latency timer. +} LATENCY_TIMER_CONTROL; + #ifdef NVOC_KERNEL_MC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -56,10 +63,10 @@ struct KernelMc { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelMc *__nvoc_pbase_KernelMc; NV_STATUS (*__kmcStateInitLocked__)(struct OBJGPU *, struct KernelMc *); + NV_STATUS (*__kmcStateLoad__)(struct OBJGPU *, struct KernelMc *, NvU32); NV_STATUS (*__kmcWritePmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvU32, NvBool, NvBool); NvU32 (*__kmcReadPmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvBool); NV_STATUS (*__kmcReconcileTunableState__)(POBJGPU, struct KernelMc *, void *); - NV_STATUS (*__kmcStateLoad__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStateUnload__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePreLoad__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePostUnload__)(POBJGPU, struct KernelMc *, NvU32); @@ -77,6 +84,7 @@ struct KernelMc { NV_STATUS (*__kmcSetTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcConstructEngine__)(POBJGPU, struct KernelMc *, ENGDESCRIPTOR); NvBool (*__kmcIsPresent__)(POBJGPU, struct KernelMc *); + LATENCY_TIMER_CONTROL LatencyTimerControl; }; #ifndef __NVOC_CLASS_KernelMc_TYPEDEF__ @@ -110,12 +118,12 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc**, Dynamic*, NvU32); __nvoc_objCreate_KernelMc((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kmcStateInitLocked(pGpu, pKernelMc) kmcStateInitLocked_DISPATCH(pGpu, pKernelMc) +#define kmcStateLoad(pGpu, pKernelMc, arg0) kmcStateLoad_DISPATCH(pGpu, pKernelMc, arg0) #define kmcWritePmcEnableReg(pGpu, pKernelMc, arg0, arg1, arg2) kmcWritePmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0, arg1, arg2) #define kmcWritePmcEnableReg_HAL(pGpu, pKernelMc, arg0, arg1, arg2) kmcWritePmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0, arg1, arg2) #define kmcReadPmcEnableReg(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) #define kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) #define kmcReconcileTunableState(pGpu, pEngstate, pTunableState) kmcReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmcStateLoad(pGpu, pEngstate, arg0) kmcStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmcStateUnload(pGpu, pEngstate, arg0) kmcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePreLoad(pGpu, pEngstate, arg0) kmcStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePostUnload(pGpu, pEngstate, arg0) kmcStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -165,6 +173,12 @@ static inline NV_STATUS kmcStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct return pKernelMc->__kmcStateInitLocked__(pGpu, pKernelMc); } +NV_STATUS kmcStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0); + +static inline NV_STATUS kmcStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0) { + return pKernelMc->__kmcStateLoad__(pGpu, pKernelMc, arg0); +} + NV_STATUS kmcWritePmcEnableReg_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2); NV_STATUS kmcWritePmcEnableReg_GA100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2); @@ -193,10 +207,6 @@ static inline NV_STATUS kmcReconcileTunableState_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kmcReconcileTunableState__(pGpu, pEngstate, pTunableState); } -static inline NV_STATUS kmcStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { - return pEngstate->__kmcStateLoad__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kmcStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return pEngstate->__kmcStateUnload__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c index 02fe216cf..82589addb 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c @@ -205,14 +205,14 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__kmigmgrStateUnload__ = &kmigmgrStateUnload_IMPL; // Hal function -- kmigmgrCreateGPUInstanceCheck - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_GA100; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_46f6a7; } @@ -227,7 +227,8 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + // default + else { pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; } @@ -241,10 +242,15 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm else if (0) { } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmigmgrIsGPUInstanceCombinationValid__ = &kmigmgrIsGPUInstanceCombinationValid_GH100; + } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + // default + else { pThis->__kmigmgrIsGPUInstanceCombinationValid__ = &kmigmgrIsGPUInstanceCombinationValid_491d52; } @@ -254,39 +260,41 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_GH100; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + // default + else { pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_491d52; } // Hal function -- kmigmgrIsMemoryPartitioningRequested - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_GA100; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_491d52; } // Hal function -- kmigmgrIsMemoryPartitioningNeeded - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_GA100; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_491d52; } @@ -297,14 +305,14 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; } else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index 848856803..b28a3b51a 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -138,6 +138,11 @@ typedef struct MIG_RESOURCE_ALLOCATION * Bitvector of local engine IDs associated with this instance. */ ENGTYPE_BIT_VECTOR localEngines; + + /*! + * Virtualized GPC Count + */ + NvU32 virtualGpcCount; } MIG_RESOURCE_ALLOCATION; typedef struct MIG_COMPUTE_INSTANCE @@ -383,6 +388,11 @@ typedef struct KERNEL_MIG_MANAGER_STATIC_INFO /*! Per swizzId FB memory page ranges */ NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS *pSwizzIdFbMemPageRanges; + /*! Compute instance profiles */ + NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *pCIProfiles; + + /*! Skyline info used to determine GPU and compute instance resources available */ + NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS *pSkylineInfo; } KERNEL_MIG_MANAGER_STATIC_INFO; /*! @@ -691,6 +701,8 @@ static inline NvBool kmigmgrIsDevinitMIGBitSet_DISPATCH(OBJGPU *arg0, struct Ker NvBool kmigmgrIsGPUInstanceCombinationValid_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag); +NvBool kmigmgrIsGPUInstanceCombinationValid_GH100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag); + static inline NvBool kmigmgrIsGPUInstanceCombinationValid_491d52(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag) { return ((NvBool)(0 != 0)); } @@ -701,6 +713,8 @@ static inline NvBool kmigmgrIsGPUInstanceCombinationValid_DISPATCH(OBJGPU *arg0, NvBool kmigmgrIsGPUInstanceFlagValid_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag); +NvBool kmigmgrIsGPUInstanceFlagValid_GH100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag); + static inline NvBool kmigmgrIsGPUInstanceFlagValid_491d52(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpuInstanceFlag) { return ((NvBool)(0 != 0)); } diff --git a/src/nvidia/generated/g_kernel_nvdec_nvoc.c b/src/nvidia/generated/g_kernel_nvdec_nvoc.c deleted file mode 100644 index 905d3d4d3..000000000 --- a/src/nvidia/generated/g_kernel_nvdec_nvoc.c +++ /dev/null @@ -1,470 +0,0 @@ -#define NVOC_KERNEL_NVDEC_H_PRIVATE_ACCESS_ALLOWED -#include "nvoc/runtime.h" -#include "nvoc/rtti.h" -#include "nvtypes.h" -#include "nvport/nvport.h" -#include "nvport/inline/util_valist.h" -#include "utils/nvassert.h" -#include "g_kernel_nvdec_nvoc.h" - -#ifdef DEBUG -char __nvoc_class_id_uniqueness_check_0xaba9df = 1; -#endif - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvdec; - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; - -void __nvoc_init_KernelNvdec(KernelNvdec*, RmHalspecOwner* ); -void __nvoc_init_funcTable_KernelNvdec(KernelNvdec*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_KernelNvdec(KernelNvdec*, RmHalspecOwner* ); -void __nvoc_init_dataField_KernelNvdec(KernelNvdec*, RmHalspecOwner* ); -void __nvoc_dtor_KernelNvdec(KernelNvdec*); -extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelNvdec; - -static const struct NVOC_RTTI __nvoc_rtti_KernelNvdec_KernelNvdec = { - /*pClassDef=*/ &__nvoc_class_def_KernelNvdec, - /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelNvdec, - /*offset=*/ 0, -}; - -static const struct NVOC_RTTI __nvoc_rtti_KernelNvdec_Object = { - /*pClassDef=*/ &__nvoc_class_def_Object, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(KernelNvdec, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), -}; - -static const struct NVOC_RTTI __nvoc_rtti_KernelNvdec_OBJENGSTATE = { - /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(KernelNvdec, __nvoc_base_OBJENGSTATE), -}; - -static const struct NVOC_RTTI __nvoc_rtti_KernelNvdec_KernelFalcon = { - /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(KernelNvdec, __nvoc_base_KernelFalcon), -}; - -static const struct NVOC_RTTI __nvoc_rtti_KernelNvdec_IntrService = { - /*pClassDef=*/ &__nvoc_class_def_IntrService, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(KernelNvdec, __nvoc_base_IntrService), -}; - -static const struct NVOC_CASTINFO __nvoc_castinfo_KernelNvdec = { - /*numRelatives=*/ 5, - /*relatives=*/ { - &__nvoc_rtti_KernelNvdec_KernelNvdec, - &__nvoc_rtti_KernelNvdec_IntrService, - &__nvoc_rtti_KernelNvdec_KernelFalcon, - &__nvoc_rtti_KernelNvdec_OBJENGSTATE, - &__nvoc_rtti_KernelNvdec_Object, - }, -}; - -const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvdec = -{ - /*classInfo=*/ { - /*size=*/ sizeof(KernelNvdec), - /*classId=*/ classId(KernelNvdec), - /*providerId=*/ &__nvoc_rtti_provider, -#if NV_PRINTF_STRINGS_ALLOWED - /*name=*/ "KernelNvdec", -#endif - }, - /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelNvdec, - /*pCastInfo=*/ &__nvoc_castinfo_KernelNvdec, - /*pExportInfo=*/ &__nvoc_export_info_KernelNvdec -}; - -static NV_STATUS __nvoc_thunk_KernelNvdec_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelNvdec, ENGDESCRIPTOR arg0) { - return knvdecConstructEngine(pGpu, (struct KernelNvdec *)(((unsigned char *)pKernelNvdec) - __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_KernelNvdec_kflcnResetHw(struct OBJGPU *pGpu, struct KernelFalcon *pKernelNvdec) { - return knvdecResetHw(pGpu, (struct KernelNvdec *)(((unsigned char *)pKernelNvdec) - __nvoc_rtti_KernelNvdec_KernelFalcon.offset)); -} - -static NvBool __nvoc_thunk_KernelNvdec_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelNvdec) { - return knvdecIsEngineInReset(pGpu, (struct KernelNvdec *)(((unsigned char *)pKernelNvdec) - __nvoc_rtti_KernelNvdec_KernelFalcon.offset)); -} - -static void __nvoc_thunk_KernelNvdec_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[155]) { - knvdecRegisterIntrService(arg0, (struct KernelNvdec *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvdec_IntrService.offset), arg2); -} - -static NV_STATUS __nvoc_thunk_KernelNvdec_intrservServiceNotificationInterrupt(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { - return knvdecServiceNotificationInterrupt(arg0, (struct KernelNvdec *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvdec_IntrService.offset), arg2); -} - -static void __nvoc_thunk_OBJENGSTATE_knvdecStateDestroy(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static void __nvoc_thunk_OBJENGSTATE_knvdecFreeTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecCompareTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static NvBool __nvoc_thunk_IntrService_knvdecClearInterrupt(struct OBJGPU *pGpu, struct KernelNvdec *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelNvdec_IntrService.offset), pParams); -} - -static NvBool __nvoc_thunk_OBJENGSTATE_knvdecIsPresent(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static NvU32 __nvoc_thunk_IntrService_knvdecServiceInterrupt(struct OBJGPU *pGpu, struct KernelNvdec *pIntrService, IntrServiceServiceInterruptArguments *pParams) { - return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelNvdec_IntrService.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecReconcileTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStateLoad(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStateUnload(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStateInitLocked(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePreLoad(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePostUnload(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePreUnload(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStateInitUnlocked(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static void __nvoc_thunk_OBJENGSTATE_knvdecInitMissing(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePreInitLocked(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePreInitUnlocked(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecGetTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecStatePostLoad(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecAllocTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvdecSetTunableState(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvdec_OBJENGSTATE.offset), pTunableState); -} - -const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelNvdec = -{ - /*numEntries=*/ 0, - /*pExportEntries=*/ 0 -}; - -void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_dtor_KernelFalcon(KernelFalcon*); -void __nvoc_dtor_IntrService(IntrService*); -void __nvoc_dtor_KernelNvdec(KernelNvdec *pThis) { - __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_dtor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon); - __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); - PORT_UNREFERENCED_VARIABLE(pThis); -} - -void __nvoc_init_dataField_KernelNvdec(KernelNvdec *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); -} - -NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_IntrService(IntrService* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_KernelNvdec(KernelNvdec *pThis, RmHalspecOwner *pRmhalspecowner) { - NV_STATUS status = NV_OK; - status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_ctor_KernelNvdec_fail_OBJENGSTATE; - status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_ctor_KernelNvdec_fail_KernelFalcon; - status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_ctor_KernelNvdec_fail_IntrService; - __nvoc_init_dataField_KernelNvdec(pThis, pRmhalspecowner); - goto __nvoc_ctor_KernelNvdec_exit; // Success - -__nvoc_ctor_KernelNvdec_fail_IntrService: - __nvoc_dtor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon); -__nvoc_ctor_KernelNvdec_fail_KernelFalcon: - __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); -__nvoc_ctor_KernelNvdec_fail_OBJENGSTATE: -__nvoc_ctor_KernelNvdec_exit: - - return status; -} - -static void __nvoc_init_funcTable_KernelNvdec_1(KernelNvdec *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - - // Hal function -- knvdecConstructEngine - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__knvdecConstructEngine__ = &knvdecConstructEngine_IMPL; - } - else if (0) - { - } - - // Hal function -- knvdecConfigureFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__knvdecConfigureFalcon__ = &knvdecConfigureFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__knvdecConfigureFalcon__ = &knvdecConfigureFalcon_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__knvdecConfigureFalcon__ = &knvdecConfigureFalcon_GA102; - } - else if (0) - { - } - } - else if (0) - { - } - - // Hal function -- knvdecResetHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__knvdecResetHw__ = &knvdecResetHw_ac1694; - } - else if (0) - { - } - } - else if (0) - { - } - - pThis->__knvdecIsEngineInReset__ = &knvdecIsEngineInReset_167f46; - - // Hal function -- knvdecIsEngineDisabled - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__knvdecIsEngineDisabled__ = &knvdecIsEngineDisabled_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__knvdecIsEngineDisabled__ = &knvdecIsEngineDisabled_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__knvdecIsEngineDisabled__ = &knvdecIsEngineDisabled_GA102; - } - else if (0) - { - } - } - else if (0) - { - } - - // Hal function -- knvdecReadUcodeFuseVersion - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__knvdecReadUcodeFuseVersion__ = &knvdecReadUcodeFuseVersion_b2b553; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__knvdecReadUcodeFuseVersion__ = &knvdecReadUcodeFuseVersion_GA100; - } - else if (0) - { - } - } - else if (0) - { - } - - pThis->__knvdecRegisterIntrService__ = &knvdecRegisterIntrService_IMPL; - - pThis->__knvdecServiceNotificationInterrupt__ = &knvdecServiceNotificationInterrupt_IMPL; - - pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvdec_engstateConstructEngine; - - pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelNvdec_kflcnResetHw; - - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_KernelNvdec_kflcnIsEngineInReset; - - pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelNvdec_intrservRegisterIntrService; - - pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelNvdec_intrservServiceNotificationInterrupt; - - pThis->__knvdecStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_knvdecStateDestroy; - - pThis->__knvdecFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecFreeTunableState; - - pThis->__knvdecCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecCompareTunableState; - - pThis->__knvdecClearInterrupt__ = &__nvoc_thunk_IntrService_knvdecClearInterrupt; - - pThis->__knvdecIsPresent__ = &__nvoc_thunk_OBJENGSTATE_knvdecIsPresent; - - pThis->__knvdecServiceInterrupt__ = &__nvoc_thunk_IntrService_knvdecServiceInterrupt; - - pThis->__knvdecReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecReconcileTunableState; - - pThis->__knvdecStateLoad__ = &__nvoc_thunk_OBJENGSTATE_knvdecStateLoad; - - pThis->__knvdecStateUnload__ = &__nvoc_thunk_OBJENGSTATE_knvdecStateUnload; - - pThis->__knvdecStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_knvdecStateInitLocked; - - pThis->__knvdecStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePreLoad; - - pThis->__knvdecStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePostUnload; - - pThis->__knvdecStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePreUnload; - - pThis->__knvdecStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_knvdecStateInitUnlocked; - - pThis->__knvdecInitMissing__ = &__nvoc_thunk_OBJENGSTATE_knvdecInitMissing; - - pThis->__knvdecStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePreInitLocked; - - pThis->__knvdecStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePreInitUnlocked; - - pThis->__knvdecGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecGetTunableState; - - pThis->__knvdecStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_knvdecStatePostLoad; - - pThis->__knvdecAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecAllocTunableState; - - pThis->__knvdecSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvdecSetTunableState; -} - -void __nvoc_init_funcTable_KernelNvdec(KernelNvdec *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_KernelNvdec_1(pThis, pRmhalspecowner); -} - -void __nvoc_init_OBJENGSTATE(OBJENGSTATE*, RmHalspecOwner* ); -void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); -void __nvoc_init_IntrService(IntrService*, RmHalspecOwner* ); -void __nvoc_init_KernelNvdec(KernelNvdec *pThis, RmHalspecOwner *pRmhalspecowner) { - pThis->__nvoc_pbase_KernelNvdec = pThis; - pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; - pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; - pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; - pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; - __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); - __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); - __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); - __nvoc_init_funcTable_KernelNvdec(pThis, pRmhalspecowner); -} - -NV_STATUS __nvoc_objCreate_KernelNvdec(KernelNvdec **ppThis, Dynamic *pParent, NvU32 createFlags) { - NV_STATUS status; - Object *pParentObj; - KernelNvdec *pThis; - RmHalspecOwner *pRmhalspecowner; - - pThis = portMemAllocNonPaged(sizeof(KernelNvdec)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; - - portMemSet(pThis, 0, sizeof(KernelNvdec)); - - __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelNvdec); - - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) - { - pParentObj = dynamicCast(pParent, Object); - objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); - } - else - { - pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; - } - - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_KernelNvdec(pThis, pRmhalspecowner); - status = __nvoc_ctor_KernelNvdec(pThis, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_objCreate_KernelNvdec_cleanup; - - *ppThis = pThis; - return NV_OK; - -__nvoc_objCreate_KernelNvdec_cleanup: - // do not call destructors here since the constructor already called them - portMemFree(pThis); - return status; -} - -NV_STATUS __nvoc_objCreateDynamic_KernelNvdec(KernelNvdec **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { - NV_STATUS status; - - status = __nvoc_objCreate_KernelNvdec(ppThis, pParent, createFlags); - - return status; -} - diff --git a/src/nvidia/generated/g_kernel_nvdec_nvoc.h b/src/nvidia/generated/g_kernel_nvdec_nvoc.h deleted file mode 100644 index e9fff46c4..000000000 --- a/src/nvidia/generated/g_kernel_nvdec_nvoc.h +++ /dev/null @@ -1,341 +0,0 @@ -#ifndef _G_KERNEL_NVDEC_NVOC_H_ -#define _G_KERNEL_NVDEC_NVOC_H_ -#include "nvoc/runtime.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "g_kernel_nvdec_nvoc.h" - -#ifndef KERNEL_NVDEC_H -#define KERNEL_NVDEC_H - -#include "core/core.h" -#include "gpu/eng_state.h" -#include "gpu/falcon/kernel_falcon.h" -#include "gpu/gpu.h" - -#ifdef NVOC_KERNEL_NVDEC_H_PRIVATE_ACCESS_ALLOWED -#define PRIVATE_FIELD(x) x -#else -#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) -#endif -struct KernelNvdec { - const struct NVOC_RTTI *__nvoc_rtti; - struct OBJENGSTATE __nvoc_base_OBJENGSTATE; - struct KernelFalcon __nvoc_base_KernelFalcon; - struct IntrService __nvoc_base_IntrService; - struct Object *__nvoc_pbase_Object; - struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; - struct KernelFalcon *__nvoc_pbase_KernelFalcon; - struct IntrService *__nvoc_pbase_IntrService; - struct KernelNvdec *__nvoc_pbase_KernelNvdec; - NV_STATUS (*__knvdecConstructEngine__)(struct OBJGPU *, struct KernelNvdec *, ENGDESCRIPTOR); - void (*__knvdecConfigureFalcon__)(struct OBJGPU *, struct KernelNvdec *); - NV_STATUS (*__knvdecResetHw__)(struct OBJGPU *, struct KernelNvdec *); - NvBool (*__knvdecIsEngineInReset__)(struct OBJGPU *, struct KernelNvdec *); - NvBool (*__knvdecIsEngineDisabled__)(struct OBJGPU *, struct KernelNvdec *); - NvU32 (*__knvdecReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelNvdec *, NvU32); - void (*__knvdecRegisterIntrService__)(struct OBJGPU *, struct KernelNvdec *, IntrServiceRecord *); - NV_STATUS (*__knvdecServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelNvdec *, IntrServiceServiceNotificationInterruptArguments *); - void (*__knvdecStateDestroy__)(POBJGPU, struct KernelNvdec *); - void (*__knvdecFreeTunableState__)(POBJGPU, struct KernelNvdec *, void *); - NV_STATUS (*__knvdecCompareTunableState__)(POBJGPU, struct KernelNvdec *, void *, void *); - NvBool (*__knvdecClearInterrupt__)(struct OBJGPU *, struct KernelNvdec *, IntrServiceClearInterruptArguments *); - NvBool (*__knvdecIsPresent__)(POBJGPU, struct KernelNvdec *); - NvU32 (*__knvdecServiceInterrupt__)(struct OBJGPU *, struct KernelNvdec *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__knvdecReconcileTunableState__)(POBJGPU, struct KernelNvdec *, void *); - NV_STATUS (*__knvdecStateLoad__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecStateUnload__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecStateInitLocked__)(POBJGPU, struct KernelNvdec *); - NV_STATUS (*__knvdecStatePreLoad__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecStatePostUnload__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecStatePreUnload__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecStateInitUnlocked__)(POBJGPU, struct KernelNvdec *); - void (*__knvdecInitMissing__)(POBJGPU, struct KernelNvdec *); - NV_STATUS (*__knvdecStatePreInitLocked__)(POBJGPU, struct KernelNvdec *); - NV_STATUS (*__knvdecStatePreInitUnlocked__)(POBJGPU, struct KernelNvdec *); - NV_STATUS (*__knvdecGetTunableState__)(POBJGPU, struct KernelNvdec *, void *); - NV_STATUS (*__knvdecStatePostLoad__)(POBJGPU, struct KernelNvdec *, NvU32); - NV_STATUS (*__knvdecAllocTunableState__)(POBJGPU, struct KernelNvdec *, void **); - NV_STATUS (*__knvdecSetTunableState__)(POBJGPU, struct KernelNvdec *, void *); -}; - -#ifndef __NVOC_CLASS_KernelNvdec_TYPEDEF__ -#define __NVOC_CLASS_KernelNvdec_TYPEDEF__ -typedef struct KernelNvdec KernelNvdec; -#endif /* __NVOC_CLASS_KernelNvdec_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelNvdec -#define __nvoc_class_id_KernelNvdec 0xaba9df -#endif /* __nvoc_class_id_KernelNvdec */ - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvdec; - -#define __staticCast_KernelNvdec(pThis) \ - ((pThis)->__nvoc_pbase_KernelNvdec) - -#ifdef __nvoc_kernel_nvdec_h_disabled -#define __dynamicCast_KernelNvdec(pThis) ((KernelNvdec*)NULL) -#else //__nvoc_kernel_nvdec_h_disabled -#define __dynamicCast_KernelNvdec(pThis) \ - ((KernelNvdec*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelNvdec))) -#endif //__nvoc_kernel_nvdec_h_disabled - -#define PDB_PROP_KNVDEC_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. -#define PDB_PROP_KNVDEC_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING - -NV_STATUS __nvoc_objCreateDynamic_KernelNvdec(KernelNvdec**, Dynamic*, NvU32, va_list); - -NV_STATUS __nvoc_objCreate_KernelNvdec(KernelNvdec**, Dynamic*, NvU32); -#define __objCreate_KernelNvdec(ppNewObj, pParent, createFlags) \ - __nvoc_objCreate_KernelNvdec((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) - -#define knvdecConstructEngine(pGpu, pKernelNvdec, arg0) knvdecConstructEngine_DISPATCH(pGpu, pKernelNvdec, arg0) -#define knvdecConstructEngine_HAL(pGpu, pKernelNvdec, arg0) knvdecConstructEngine_DISPATCH(pGpu, pKernelNvdec, arg0) -#define knvdecConfigureFalcon(pGpu, pKernelNvdec) knvdecConfigureFalcon_DISPATCH(pGpu, pKernelNvdec) -#define knvdecConfigureFalcon_HAL(pGpu, pKernelNvdec) knvdecConfigureFalcon_DISPATCH(pGpu, pKernelNvdec) -#define knvdecResetHw(pGpu, pKernelNvdec) knvdecResetHw_DISPATCH(pGpu, pKernelNvdec) -#define knvdecResetHw_HAL(pGpu, pKernelNvdec) knvdecResetHw_DISPATCH(pGpu, pKernelNvdec) -#define knvdecIsEngineInReset(pGpu, pKernelNvdec) knvdecIsEngineInReset_DISPATCH(pGpu, pKernelNvdec) -#define knvdecIsEngineDisabled(pGpu, pKernelNvdec) knvdecIsEngineDisabled_DISPATCH(pGpu, pKernelNvdec) -#define knvdecIsEngineDisabled_HAL(pGpu, pKernelNvdec) knvdecIsEngineDisabled_DISPATCH(pGpu, pKernelNvdec) -#define knvdecReadUcodeFuseVersion(pGpu, pKernelNvdec, ucodeId) knvdecReadUcodeFuseVersion_DISPATCH(pGpu, pKernelNvdec, ucodeId) -#define knvdecReadUcodeFuseVersion_HAL(pGpu, pKernelNvdec, ucodeId) knvdecReadUcodeFuseVersion_DISPATCH(pGpu, pKernelNvdec, ucodeId) -#define knvdecRegisterIntrService(arg0, arg1, arg2) knvdecRegisterIntrService_DISPATCH(arg0, arg1, arg2) -#define knvdecServiceNotificationInterrupt(arg0, arg1, arg2) knvdecServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) -#define knvdecStateDestroy(pGpu, pEngstate) knvdecStateDestroy_DISPATCH(pGpu, pEngstate) -#define knvdecFreeTunableState(pGpu, pEngstate, pTunableState) knvdecFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvdecCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) knvdecCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define knvdecClearInterrupt(pGpu, pIntrService, pParams) knvdecClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define knvdecIsPresent(pGpu, pEngstate) knvdecIsPresent_DISPATCH(pGpu, pEngstate) -#define knvdecServiceInterrupt(pGpu, pIntrService, pParams) knvdecServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define knvdecReconcileTunableState(pGpu, pEngstate, pTunableState) knvdecReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvdecStateLoad(pGpu, pEngstate, arg0) knvdecStateLoad_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecStateUnload(pGpu, pEngstate, arg0) knvdecStateUnload_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecStateInitLocked(pGpu, pEngstate) knvdecStateInitLocked_DISPATCH(pGpu, pEngstate) -#define knvdecStatePreLoad(pGpu, pEngstate, arg0) knvdecStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecStatePostUnload(pGpu, pEngstate, arg0) knvdecStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecStatePreUnload(pGpu, pEngstate, arg0) knvdecStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecStateInitUnlocked(pGpu, pEngstate) knvdecStateInitUnlocked_DISPATCH(pGpu, pEngstate) -#define knvdecInitMissing(pGpu, pEngstate) knvdecInitMissing_DISPATCH(pGpu, pEngstate) -#define knvdecStatePreInitLocked(pGpu, pEngstate) knvdecStatePreInitLocked_DISPATCH(pGpu, pEngstate) -#define knvdecStatePreInitUnlocked(pGpu, pEngstate) knvdecStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define knvdecGetTunableState(pGpu, pEngstate, pTunableState) knvdecGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvdecStatePostLoad(pGpu, pEngstate, arg0) knvdecStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define knvdecAllocTunableState(pGpu, pEngstate, ppTunableState) knvdecAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define knvdecSetTunableState(pGpu, pEngstate, pTunableState) knvdecSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -void knvdecNonstallIntrCheckAndClear_TU102(struct OBJGPU *arg0, struct KernelNvdec *arg1, struct THREAD_STATE_NODE *arg2); - -#ifdef __nvoc_kernel_nvdec_h_disabled -static inline void knvdecNonstallIntrCheckAndClear(struct OBJGPU *arg0, struct KernelNvdec *arg1, struct THREAD_STATE_NODE *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelNvdec was disabled!"); -} -#else //__nvoc_kernel_nvdec_h_disabled -#define knvdecNonstallIntrCheckAndClear(arg0, arg1, arg2) knvdecNonstallIntrCheckAndClear_TU102(arg0, arg1, arg2) -#endif //__nvoc_kernel_nvdec_h_disabled - -#define knvdecNonstallIntrCheckAndClear_HAL(arg0, arg1, arg2) knvdecNonstallIntrCheckAndClear(arg0, arg1, arg2) - -NV_STATUS knvdecConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, ENGDESCRIPTOR arg0); - -static inline NV_STATUS knvdecConstructEngine_395e98(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, ENGDESCRIPTOR arg0) { - return NV_ERR_NOT_SUPPORTED; -} - -static inline NV_STATUS knvdecConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, ENGDESCRIPTOR arg0) { - return pKernelNvdec->__knvdecConstructEngine__(pGpu, pKernelNvdec, arg0); -} - -void knvdecConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -void knvdecConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -void knvdecConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -static inline void knvdecConfigureFalcon_f2d351(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - NV_ASSERT_PRECOMP(0); -} - -static inline void knvdecConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - pKernelNvdec->__knvdecConfigureFalcon__(pGpu, pKernelNvdec); -} - -static inline NV_STATUS knvdecResetHw_ac1694(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - return NV_OK; -} - -static inline NV_STATUS knvdecResetHw_5baef9(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -static inline NV_STATUS knvdecResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - return pKernelNvdec->__knvdecResetHw__(pGpu, pKernelNvdec); -} - -static inline NvBool knvdecIsEngineInReset_167f46(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); - return ((NvBool)(0 != 0)); -} - -static inline NvBool knvdecIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - return pKernelNvdec->__knvdecIsEngineInReset__(pGpu, pKernelNvdec); -} - -NvBool knvdecIsEngineDisabled_TU102(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -NvBool knvdecIsEngineDisabled_GA100(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -NvBool knvdecIsEngineDisabled_GA102(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec); - -static inline NvBool knvdecIsEngineDisabled_108313(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} - -static inline NvBool knvdecIsEngineDisabled_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec) { - return pKernelNvdec->__knvdecIsEngineDisabled__(pGpu, pKernelNvdec); -} - -static inline NvU32 knvdecReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, NvU32 ucodeId) { - return 0; -} - -NvU32 knvdecReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, NvU32 ucodeId); - -static inline NvU32 knvdecReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, NvU32 ucodeId) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - -static inline NvU32 knvdecReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pKernelNvdec, NvU32 ucodeId) { - return pKernelNvdec->__knvdecReadUcodeFuseVersion__(pGpu, pKernelNvdec, ucodeId); -} - -void knvdecRegisterIntrService_IMPL(struct OBJGPU *arg0, struct KernelNvdec *arg1, IntrServiceRecord arg2[155]); - -static inline void knvdecRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct KernelNvdec *arg1, IntrServiceRecord arg2[155]) { - arg1->__knvdecRegisterIntrService__(arg0, arg1, arg2); -} - -NV_STATUS knvdecServiceNotificationInterrupt_IMPL(struct OBJGPU *arg0, struct KernelNvdec *arg1, IntrServiceServiceNotificationInterruptArguments *arg2); - -static inline NV_STATUS knvdecServiceNotificationInterrupt_DISPATCH(struct OBJGPU *arg0, struct KernelNvdec *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { - return arg1->__knvdecServiceNotificationInterrupt__(arg0, arg1, arg2); -} - -static inline void knvdecStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - pEngstate->__knvdecStateDestroy__(pGpu, pEngstate); -} - -static inline void knvdecFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - pEngstate->__knvdecFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvdecCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__knvdecCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline NvBool knvdecClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return pIntrService->__knvdecClearInterrupt__(pGpu, pIntrService, pParams); -} - -static inline NvBool knvdecIsPresent_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return pEngstate->__knvdecIsPresent__(pGpu, pEngstate); -} - -static inline NvU32 knvdecServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelNvdec *pIntrService, IntrServiceServiceInterruptArguments *pParams) { - return pIntrService->__knvdecServiceInterrupt__(pGpu, pIntrService, pParams); -} - -static inline NV_STATUS knvdecReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return pEngstate->__knvdecReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvdecStateLoad_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStateLoad__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecStateUnload_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStateUnload__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return pEngstate->__knvdecStateInitLocked__(pGpu, pEngstate); -} - -static inline NV_STATUS knvdecStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStatePreLoad__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStatePostUnload__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStatePreUnload__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return pEngstate->__knvdecStateInitUnlocked__(pGpu, pEngstate); -} - -static inline void knvdecInitMissing_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - pEngstate->__knvdecInitMissing__(pGpu, pEngstate); -} - -static inline NV_STATUS knvdecStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return pEngstate->__knvdecStatePreInitLocked__(pGpu, pEngstate); -} - -static inline NV_STATUS knvdecStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate) { - return pEngstate->__knvdecStatePreInitUnlocked__(pGpu, pEngstate); -} - -static inline NV_STATUS knvdecGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return pEngstate->__knvdecGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvdecStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, NvU32 arg0) { - return pEngstate->__knvdecStatePostLoad__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS knvdecAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void **ppTunableState) { - return pEngstate->__knvdecAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS knvdecSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvdec *pEngstate, void *pTunableState) { - return pEngstate->__knvdecSetTunableState__(pGpu, pEngstate, pTunableState); -} - -#undef PRIVATE_FIELD - - -#endif // KERNEL_NVDEC_H - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _G_KERNEL_NVDEC_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index 35a8261e6..fe162b07d 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -182,7 +182,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_ENABLED, ((NvBool)(0 == 0))); } @@ -193,7 +193,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED, ((NvBool)(0 == 0))); } @@ -203,8 +203,30 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT, ((NvBool)(0 != 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT, ((NvBool)(0 == 0))); + } + + // NVOC Property Hal field -- PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK, ((NvBool)(0 != 0))); + } + // NVOC Property Hal field -- PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING, ((NvBool)(0 == 0))); } @@ -215,7 +237,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED, ((NvBool)(0 == 0))); } @@ -226,7 +248,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD, ((NvBool)(0 == 0))); } @@ -237,7 +259,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN, ((NvBool)(0 == 0))); } @@ -272,8 +294,19 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm // NVOC Property Hal field -- PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING pThis->setProperty(pThis, PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING, ((NvBool)(0 != 0))); + // NVOC Property Hal field -- PDB_PROP_KNVLINK_MINION_GFW_BOOT + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_MINION_GFW_BOOT, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KNVLINK_MINION_GFW_BOOT, ((NvBool)(0 != 0))); + } + // NVOC Property Hal field -- PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED, ((NvBool)(0 != 0))); } @@ -335,10 +368,14 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; + } // default else { @@ -355,11 +392,11 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ { pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; } @@ -375,7 +412,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; } @@ -394,7 +431,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; } @@ -416,7 +453,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO else if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; } @@ -436,7 +473,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; } @@ -452,7 +489,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; } @@ -468,7 +505,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; } @@ -484,7 +521,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; } @@ -500,7 +537,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; } @@ -516,7 +553,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; } @@ -535,7 +572,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO if (0) { } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; } @@ -555,12 +592,76 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO { pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; } } + // Hal function -- knvlinkIsAliSupported + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; + } + } + + // Hal function -- knvlinkPostSetupNvlinkPeer + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; + } + } + + // Hal function -- knvlinkDiscoverPostRxDetLinks + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; + } + } + + // Hal function -- knvlinkIsFloorSweepingNeeded + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; + } + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvlink_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelNvlink_engstateStatePreInitLocked; diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 02bf0afcb..798f33f2f 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -75,9 +75,10 @@ typedef struct _def_knvlink_conn_info #define NVLINK_VERSION_22 0x00000004 #define NVLINK_VERSION_30 0x00000005 #define NVLINK_VERSION_31 0x00000006 +#define NVLINK_VERSION_40 0x00000007 // Maximum links the GPU NVLink SW can currently support -#define NVLINK_MAX_LINKS_SW 12 +#define NVLINK_MAX_LINKS_SW 18 // Maximum IOCTRLs supported in SW #define NVLINK_MAX_IOCTRLS_SW 3 @@ -214,6 +215,10 @@ struct KernelNvlink { void (*__knvlinkSetupPeerMapping__)(OBJGPU *, struct KernelNvlink *, OBJGPU *, NvU32); NV_STATUS (*__knvlinkProgramLinkSpeed__)(OBJGPU *, struct KernelNvlink *); NvBool (*__knvlinkPoweredUpForD3__)(OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkIsAliSupported__)(OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkReconcileTunableState__)(POBJGPU, struct KernelNvlink *, void *); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); @@ -231,6 +236,8 @@ struct KernelNvlink { NvBool PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED; + NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT; + NvBool PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK; NvBool PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING; NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED; NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD; @@ -238,6 +245,9 @@ struct KernelNvlink { NvBool PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6; NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE; NvBool PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING; + NvBool PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING; + NvBool PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING; + NvBool PDB_PROP_KNVLINK_MINION_GFW_BOOT; NvBool PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED; struct KernelIoctrl *pKernelIoctrl[3]; NvU32 ioctrlMask; @@ -261,7 +271,7 @@ struct KernelNvlink { NvU32 bridgedLinks; NvU32 enabledLinks; NvU32 initializedLinks; - KNVLINK_RM_LINK nvlinkLinks[12]; + KNVLINK_RM_LINK nvlinkLinks[18]; NvU32 postRxDetLinkMask; NvU32 disconnectedLinkMask; NvU32 sysmemLinkMask; @@ -276,10 +286,13 @@ struct KernelNvlink { NvBool bForceEnableCoreLibRtlsims; NvBool bEnableTrainingAtLoad; NvBool bEnableSafeModeAtLoad; + NvBool bEnableAli; + NvBool bFloorSwept; + NvBool bLinkTrainingDebugSpew; NvBool bDisableSingleLaneMode; NvBool bDisableL2Mode; NvU32 nvlinkLinkSpeed; - NvU32 errorRecoveries[12]; + NvU32 errorRecoveries[18]; NvBool bNvswitchProxy; NvU64 fabricBaseAddr; }; @@ -305,24 +318,34 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink; ((KernelNvlink*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelNvlink))) #endif //__nvoc_kernel_nvlink_h_disabled -#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_CAST -#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED +#define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_CAST +#define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_NAME PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING +#define PDB_PROP_KNVLINK_MINION_GFW_BOOT_BASE_CAST +#define PDB_PROP_KNVLINK_MINION_GFW_BOOT_BASE_NAME PDB_PROP_KNVLINK_MINION_GFW_BOOT +#define PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK_BASE_CAST +#define PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK_BASE_NAME PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED_BASE_CAST #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED_BASE_NAME PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED +#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_CAST +#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED +#define PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING_BASE_CAST +#define PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING_BASE_NAME PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING #define PDB_PROP_KNVLINK_ENABLED_BASE_CAST #define PDB_PROP_KNVLINK_ENABLED_BASE_NAME PDB_PROP_KNVLINK_ENABLED +#define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT_BASE_CAST +#define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT_BASE_NAME PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT #define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED_BASE_CAST #define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED_BASE_NAME PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED +#define PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING_BASE_CAST +#define PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING_BASE_NAME PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING #define PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED_BASE_CAST #define PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED #define PDB_PROP_KNVLINK_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KNVLINK_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING -#define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_CAST -#define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_NAME PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_CAST -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_CAST #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_NAME PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 +#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_CAST +#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_CAST #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_NAME PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD #define PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_CAST @@ -371,6 +394,14 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkProgramLinkSpeed_HAL(pGpu, pKernelNvlink) knvlinkProgramLinkSpeed_DISPATCH(pGpu, pKernelNvlink) #define knvlinkPoweredUpForD3(pGpu, pKernelNvlink) knvlinkPoweredUpForD3_DISPATCH(pGpu, pKernelNvlink) #define knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink) knvlinkPoweredUpForD3_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkIsAliSupported(pGpu, pKernelNvlink) knvlinkIsAliSupported_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkIsAliSupported_HAL(pGpu, pKernelNvlink) knvlinkIsAliSupported_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkPostSetupNvlinkPeer(pGpu, pKernelNvlink) knvlinkPostSetupNvlinkPeer_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkPostSetupNvlinkPeer_HAL(pGpu, pKernelNvlink) knvlinkPostSetupNvlinkPeer_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkDiscoverPostRxDetLinks(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) +#define knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) +#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkReconcileTunableState(pGpu, pEngstate, pTunableState) knvlinkReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define knvlinkStateInitLocked(pGpu, pEngstate) knvlinkStateInitLocked_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreLoad(pGpu, pEngstate, arg0) knvlinkStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -590,18 +621,18 @@ static inline NV_STATUS knvlinkCoreRemoveLink(OBJGPU *pGpu, struct KernelNvlink #define knvlinkCoreRemoveLink_HAL(pGpu, pKernelNvlink, arg0) knvlinkCoreRemoveLink(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink) knvlinkCoreShutdownDeviceLinks_IMPL(pGpu, pKernelNvlink) +#define knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, bForcePowerDown) knvlinkCoreShutdownDeviceLinks_IMPL(pGpu, pKernelNvlink, bForcePowerDown) #endif //__nvoc_kernel_nvlink_h_disabled -#define knvlinkCoreShutdownDeviceLinks_HAL(pGpu, pKernelNvlink) knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink) +#define knvlinkCoreShutdownDeviceLinks_HAL(pGpu, pKernelNvlink, bForcePowerDown) knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, bForcePowerDown) NV_STATUS knvlinkCoreResetDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); @@ -837,18 +868,18 @@ static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(OBJGPU *pGpu, struct Kern #define knvlinkGetPeersNvlinkMaskFromHshub_HAL(pGpu, pKernelNvlink) knvlinkGetPeersNvlinkMaskFromHshub(pGpu, pKernelNvlink) -NV_STATUS knvlinkPrepareForXVEReset_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkPrepareForXVEReset_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkPrepareForXVEReset(pGpu, pKernelNvlink) knvlinkPrepareForXVEReset_IMPL(pGpu, pKernelNvlink) +#define knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, bForcePowerDown) knvlinkPrepareForXVEReset_IMPL(pGpu, pKernelNvlink, bForcePowerDown) #endif //__nvoc_kernel_nvlink_h_disabled -#define knvlinkPrepareForXVEReset_HAL(pGpu, pKernelNvlink) knvlinkPrepareForXVEReset(pGpu, pKernelNvlink) +#define knvlinkPrepareForXVEReset_HAL(pGpu, pKernelNvlink, bForcePowerDown) knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, bForcePowerDown) NV_STATUS knvlinkEnterExitSleep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); @@ -1043,6 +1074,19 @@ static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(OBJGPU *pGpu, struct Kern #define knvlinkSetUniqueFlaBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFlaBaseAddress(pGpu, pKernelNvlink, arg0) +NV_STATUS knvlinkFloorSweep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks); + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkFloorSweep(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) knvlinkFloorSweep_IMPL(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkFloorSweep_HAL(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) + static inline NvU64 knvlinkGetUniqueFabricBaseAddress_72249a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->fabricBaseAddr; } @@ -1097,20 +1141,31 @@ static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(OBJGPU *pGpu, s #define knvlinkApplyNvswitchDegradedModeSettings_HAL(pGpu, pKernelNvlink, switchLinkMasks) knvlinkApplyNvswitchDegradedModeSettings(pGpu, pKernelNvlink, switchLinkMasks) -static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { - return NV_ERR_NOT_SUPPORTED; +NvU32 knvlinkGetNumActiveLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return 0; } +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink) knvlinkGetNumActiveLinksPerIoctrl_IMPL(pGpu, pKernelNvlink) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkGetNumActiveLinksPerIoctrl_HAL(pGpu, pKernelNvlink) knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink) + +NvU32 knvlinkGetTotalNumLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkDiscoverPostRxDetLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NvU32 knvlinkGetTotalNumLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return 0; } #else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkDiscoverPostRxDetLinks(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_46f6a7(pGpu, pKernelNvlink, pPeerGpu) +#define knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink) knvlinkGetTotalNumLinksPerIoctrl_IMPL(pGpu, pKernelNvlink) #endif //__nvoc_kernel_nvlink_h_disabled -#define knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks(pGpu, pKernelNvlink, pPeerGpu) +#define knvlinkGetTotalNumLinksPerIoctrl_HAL(pGpu, pKernelNvlink) knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink) NV_STATUS knvlinkConstructEngine_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, ENGDESCRIPTOR arg2); @@ -1160,6 +1215,8 @@ static inline NV_STATUS knvlinkValidateFabricBaseAddress_56cd7a(OBJGPU *pGpu, st NV_STATUS knvlinkValidateFabricBaseAddress_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkValidateFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); + static inline NV_STATUS knvlinkValidateFabricBaseAddress_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { return NV_ERR_NOT_SUPPORTED; } @@ -1300,6 +1357,50 @@ static inline NvBool knvlinkPoweredUpForD3_DISPATCH(OBJGPU *pGpu, struct KernelN return pKernelNvlink->__knvlinkPoweredUpForD3__(pGpu, pKernelNvlink); } +static inline NV_STATUS knvlinkIsAliSupported_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return NV_OK; +} + +NV_STATUS knvlinkIsAliSupported_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline NV_STATUS knvlinkIsAliSupported_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkIsAliSupported__(pGpu, pKernelNvlink); +} + +static inline NV_STATUS knvlinkPostSetupNvlinkPeer_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return NV_OK; +} + +NV_STATUS knvlinkPostSetupNvlinkPeer_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline NV_STATUS knvlinkPostSetupNvlinkPeer_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkPostSetupNvlinkPeer__(pGpu, pKernelNvlink); +} + +static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { + return NV_OK; +} + +NV_STATUS knvlinkDiscoverPostRxDetLinks_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); + +static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { + return pKernelNvlink->__knvlinkDiscoverPostRxDetLinks__(pGpu, pKernelNvlink, pPeerGpu); +} + +static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return ((NvBool)(0 != 0)); +} + +NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); + +static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); +} + static inline NV_STATUS knvlinkReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { return pEngstate->__knvlinkReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -1418,6 +1519,7 @@ NvlStatus knvlinkCoreSetRxSublinkDetectCallback (nvlink_link *link, NvU32 NvlStatus knvlinkCoreGetRxSublinkDetectCallback (nvlink_link *link); void knvlinkCoreTrainingCompleteCallback (nvlink_link *link); void knvlinkCoreGetUphyLoadCallback (nvlink_link *link, NvBool *bUnlocked); +NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link); #endif diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index 5dae6ee3b..45019018d 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -242,12 +242,13 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_f2d351; } } else if (0) @@ -257,12 +258,13 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner // Hal function -- ksec2ResetHw if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__ksec2ResetHw__ = &ksec2ResetHw_5baef9; } } else if (0) @@ -272,12 +274,13 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner // Hal function -- ksec2IsEngineInReset if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ { pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_TU102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_108313; } } else if (0) @@ -291,7 +294,7 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; } @@ -303,6 +306,38 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { } + // Hal function -- ksec2GetBinArchiveBlUcode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08700000UL) )) /* ChipHal: AD102 | AD103 | AD104 | GH100 */ + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; + } + } + else if (0) + { + } + + // Hal function -- ksec2GetGenericBlUcode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08700000UL) )) /* ChipHal: AD102 | AD103 | AD104 | GH100 */ + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; + } + } + else if (0) + { + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelSec2_kflcnResetHw; diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index ccac76c6b..19bff7b64 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -62,6 +62,8 @@ struct KernelSec2 { NV_STATUS (*__ksec2ResetHw__)(struct OBJGPU *, struct KernelSec2 *); NvBool (*__ksec2IsEngineInReset__)(struct OBJGPU *, struct KernelSec2 *); NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32); + const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *); + NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **); NV_STATUS (*__ksec2ReconcileTunableState__)(POBJGPU, struct KernelSec2 *, void *); NV_STATUS (*__ksec2StateLoad__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32); @@ -125,6 +127,10 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2IsEngineInReset_HAL(pGpu, pKernelSec2) ksec2IsEngineInReset_DISPATCH(pGpu, pKernelSec2) #define ksec2ReadUcodeFuseVersion(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) #define ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) +#define ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2) +#define ksec2GetBinArchiveBlUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2) +#define ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) +#define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) #define ksec2ReconcileTunableState(pGpu, pEngstate, pTunableState) ksec2ReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2StateLoad(pGpu, pEngstate, arg0) ksec2StateLoad_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -144,32 +150,6 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2AllocTunableState(pGpu, pEngstate, ppTunableState) ksec2AllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define ksec2SetTunableState(pGpu, pEngstate, pTunableState) ksec2SetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate) -const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); - -#ifdef __nvoc_kernel_sec2_h_disabled -static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_FAILED_PRECOMP("KernelSec2 was disabled!"); - return NULL; -} -#else //__nvoc_kernel_sec2_h_disabled -#define ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_TU102(pGpu, pKernelSec2) -#endif //__nvoc_kernel_sec2_h_disabled - -#define ksec2GetBinArchiveBlUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) - -NV_STATUS ksec2GetGenericBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg); - -#ifdef __nvoc_kernel_sec2_h_disabled -static inline NV_STATUS ksec2GetGenericBlUcode(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg) { - NV_ASSERT_FAILED_PRECOMP("KernelSec2 was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_sec2_h_disabled -#define ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_TU102(pGpu, pKernelSec2, ppDesc, ppImg) -#endif //__nvoc_kernel_sec2_h_disabled - -#define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) - NV_STATUS ksec2ConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0); static inline NV_STATUS ksec2ConstructEngine_395e98(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) { @@ -228,6 +208,26 @@ static inline NvU32 ksec2ReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, stru return pKernelSec2->__ksec2ReadUcodeFuseVersion__(pGpu, pKernelSec2, ucodeId); } +const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); + +static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_80f438(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + return pKernelSec2->__ksec2GetBinArchiveBlUcode__(pGpu, pKernelSec2); +} + +NV_STATUS ksec2GetGenericBlUcode_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg); + +static inline NV_STATUS ksec2GetGenericBlUcode_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS ksec2GetGenericBlUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, const RM_FLCN_BL_DESC **ppDesc, const NvU8 **ppImg) { + return pKernelSec2->__ksec2GetGenericBlUcode__(pGpu, pKernelSec2, ppDesc, ppImg); +} + static inline NV_STATUS ksec2ReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { return pEngstate->__ksec2ReconcileTunableState__(pGpu, pEngstate, pTunableState); } diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index 558f42925..b7aac63d4 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -1059,6 +1059,12 @@ void memdescUnmapInternal(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags // #define MEMDESC_FLAGS_REGISTERED_TO_GSP NVBIT64(42) +// +// If this flag is set then it indicates that the memory associated with +// this descriptor was allocated from local EGM. +// +#define MEMDESC_FLAGS_ALLOC_FROM_EGM NVBIT64(43) + // // Indicates that this memdesc is tracking client sysmem allocation as // against RM internal sysmem allocation diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index a2b5d3c83..6807d38af 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -90,7 +90,6 @@ struct MemoryFabric { NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memoryfabricMap__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memoryfabricAccessCallback__)(struct MemoryFabric *, struct RsClient *, void *, RsAccessRight); - NvU32 flags; }; #ifndef __NVOC_CLASS_MemoryFabric_TYPEDEF__ @@ -268,6 +267,21 @@ static inline NvBool memoryfabricCanExport(struct MemoryFabric *pMemoryFabric) { #undef PRIVATE_FIELD +typedef struct +{ + // + // TODO: Only sticky non-partial mappings are supported currently, so all + // the fabric addrs are mapped to the single vidmem memory object. However, + // when partial mappings are supported, we will need a per-fabric memdesc + // tree to track the mappings for multiple vidmem memory objects. + // + NvHandle hDupedVidmem; + + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + + NvU32 allocFlags; +} FABRIC_MEMDESC_DATA; + #endif /* _MEMORYFABRIC_H_ */ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index b4d4aa746..38be567d1 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -172,7 +172,7 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bFbRegionsSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bFbRegionsSupported = ((NvBool)(0 == 0)); } @@ -183,7 +183,7 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p } // Hal field -- bPmaEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bPmaEnabled = ((NvBool)(0 == 0)); } @@ -194,7 +194,7 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p } // Hal field -- bClientPageTablesPmaManaged - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bClientPageTablesPmaManaged = ((NvBool)(0 == 0)); } @@ -255,10 +255,21 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bBug2301372IncreaseRmReserveMemoryWar = ((NvBool)(0 != 0)); } + // Hal field -- bBug3620359IncreaseRmReserveMemoryWar + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + { + pThis->bBug3620359IncreaseRmReserveMemoryWar = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bBug3620359IncreaseRmReserveMemoryWar = ((NvBool)(0 != 0)); + } + pThis->bEnableDynamicPageOfflining = ((NvBool)(0 != 0)); // Hal field -- bVgpuPmaSupport - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bVgpuPmaSupport = ((NvBool)(0 == 0)); } @@ -268,10 +279,8 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bVgpuPmaSupport = ((NvBool)(0 != 0)); } - pThis->bSupportCCProtectedMemoryAlloc = ((NvBool)(0 != 0)); - // Hal field -- bAllowNoncontiguousAllocation - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bAllowNoncontiguousAllocation = ((NvBool)(0 == 0)); } @@ -282,7 +291,7 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p } // Hal field -- bScrubOnFreeEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->bScrubOnFreeEnabled = ((NvBool)(0 == 0)); } @@ -293,8 +302,9 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p } // Hal field -- bFastScrubberEnabled - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->bFastScrubberEnabled = ((NvBool)(0 == 0)); } // default else @@ -343,12 +353,22 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStateDestroy__ = &memmgrStateDestroy_IMPL; + // Hal function -- memmgrMemUtilsCheckMemoryFastScrubEnable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_491d52; + } + // Hal function -- memmgrAllocDetermineAlignment if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GA100; } @@ -376,12 +396,13 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0800fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ { + pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_AD102; } else if (0) { @@ -392,7 +413,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GA100; } @@ -400,8 +421,44 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { } + // Hal function -- memmgrGetPteKindBl + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; + } + + // Hal function -- memmgrGetPteKindPitch + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; + } + + // Hal function -- memmgrChooseKindCompressC + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; + } + else if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; + } + // Hal function -- memmgrGetFlaKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; } @@ -415,7 +472,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_13cd8d; } @@ -436,7 +493,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_e133c0; } @@ -446,7 +503,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_56cd7a; } @@ -456,13 +513,13 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_56cd7a; } // Hal function -- memmgrGetDisablePlcKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; } @@ -476,7 +533,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; } @@ -490,7 +547,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GA100; } diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index 262e3b321..c7e65aebe 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -399,9 +399,13 @@ struct MemoryManager { NV_STATUS (*__memmgrStatePreUnload__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateUnload__)(OBJGPU *, struct MemoryManager *, NvU32); void (*__memmgrStateDestroy__)(OBJGPU *, struct MemoryManager *); + NvBool (*__memmgrMemUtilsCheckMemoryFastScrubEnable__)(OBJGPU *, struct MemoryManager *, NvU32, NvBool, RmPhysAddr, NvU32, NV_ADDRESS_SPACE); NV_STATUS (*__memmgrAllocDetermineAlignment__)(OBJGPU *, struct MemoryManager *, NvU64 *, NvU64 *, NvU64, NvU32, NvU32, NvU32, NvU64); NvU64 (*__memmgrGetMaxContextSize__)(OBJGPU *, struct MemoryManager *); void (*__memmgrScrubRegistryOverrides__)(OBJGPU *, struct MemoryManager *); + NvU32 (*__memmgrGetPteKindBl__)(OBJGPU *, struct MemoryManager *); + NvU32 (*__memmgrGetPteKindPitch__)(OBJGPU *, struct MemoryManager *); + NvU32 (*__memmgrChooseKindCompressC__)(OBJGPU *, struct MemoryManager *, FB_ALLOC_PAGE_FORMAT *); NV_STATUS (*__memmgrGetFlaKind__)(OBJGPU *, struct MemoryManager *, NvU32 *); NvU32 (*__memmgrDetermineComptag__)(OBJGPU *, struct MemoryManager *, RmPhysAddr); NV_STATUS (*__memmgrCheckReservedMemorySize__)(OBJGPU *, struct MemoryManager *); @@ -444,10 +448,10 @@ struct MemoryManager { NvBool bSysmemCompressionSupportDef; NvBool bBug1698088IncreaseRmReserveMemoryWar; NvBool bBug2301372IncreaseRmReserveMemoryWar; + NvBool bBug3620359IncreaseRmReserveMemoryWar; NvBool bEnableFbsrFileMode; NvBool bEnableDynamicPageOfflining; NvBool bVgpuPmaSupport; - NvBool bSupportCCProtectedMemoryAlloc; NvBool bAllowNoncontiguousAllocation; NvBool bEccInterleavedVidmemScrub; NvBool bScrubberInitialized; @@ -525,12 +529,20 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrStatePreUnload(pGpu, pMemoryManager, arg0) memmgrStatePreUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateUnload(pGpu, pMemoryManager, arg0) memmgrStateUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateDestroy(pGpu, pMemoryManager) memmgrStateDestroy_DISPATCH(pGpu, pMemoryManager) +#define memmgrMemUtilsCheckMemoryFastScrubEnable(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) +#define memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) #define memmgrAllocDetermineAlignment(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) memmgrAllocDetermineAlignment_DISPATCH(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) #define memmgrAllocDetermineAlignment_HAL(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) memmgrAllocDetermineAlignment_DISPATCH(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) #define memmgrGetMaxContextSize(pGpu, pMemoryManager) memmgrGetMaxContextSize_DISPATCH(pGpu, pMemoryManager) #define memmgrGetMaxContextSize_HAL(pGpu, pMemoryManager) memmgrGetMaxContextSize_DISPATCH(pGpu, pMemoryManager) #define memmgrScrubRegistryOverrides(pGpu, pMemoryManager) memmgrScrubRegistryOverrides_DISPATCH(pGpu, pMemoryManager) #define memmgrScrubRegistryOverrides_HAL(pGpu, pMemoryManager) memmgrScrubRegistryOverrides_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetPteKindBl(pGpu, pMemoryManager) memmgrGetPteKindBl_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetPteKindBl_HAL(pGpu, pMemoryManager) memmgrGetPteKindBl_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetPteKindPitch(pGpu, pMemoryManager) memmgrGetPteKindPitch_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetPteKindPitch_HAL(pGpu, pMemoryManager) memmgrGetPteKindPitch_DISPATCH(pGpu, pMemoryManager) +#define memmgrChooseKindCompressC(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrChooseKindCompressC_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind_HAL(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) @@ -1183,32 +1195,6 @@ static inline NvBool memmgrIsKindBlocklinear(struct MemoryManager *pMemoryManage #define memmgrIsKindBlocklinear_HAL(pMemoryManager, arg0) memmgrIsKindBlocklinear(pMemoryManager, arg0) -NvU32 memmgrGetPteKindBl_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrGetPteKindBl(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetPteKindBl(pGpu, pMemoryManager) memmgrGetPteKindBl_GM107(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetPteKindBl_HAL(pGpu, pMemoryManager) memmgrGetPteKindBl(pGpu, pMemoryManager) - -NvU32 memmgrGetPteKindPitch_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrGetPteKindPitch(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetPteKindPitch(pGpu, pMemoryManager) memmgrGetPteKindPitch_GM107(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetPteKindPitch_HAL(pGpu, pMemoryManager) memmgrGetPteKindPitch(pGpu, pMemoryManager) - NvU32 memmgrChooseKindZ_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0); #ifdef __nvoc_mem_mgr_h_disabled @@ -1235,19 +1221,6 @@ static inline NvU32 memmgrChooseKindCompressZ(OBJGPU *pGpu, struct MemoryManager #define memmgrChooseKindCompressZ_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressZ(pGpu, pMemoryManager, arg0) -NvU32 memmgrChooseKindCompressC_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrChooseKindCompressC(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrChooseKindCompressC(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_GP100(pGpu, pMemoryManager, arg0) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrChooseKindCompressC_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC(pGpu, pMemoryManager, arg0) - static inline NvU32 memmgrChooseKindCompressCForMS2_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { return 0; } @@ -1682,6 +1655,16 @@ static inline void memmgrStateDestroy_DISPATCH(OBJGPU *pGpu, struct MemoryManage pMemoryManager->__memmgrStateDestroy__(pGpu, pMemoryManager); } +NvBool memmgrMemUtilsCheckMemoryFastScrubEnable_GH100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvBool arg1, RmPhysAddr arg2, NvU32 arg3, NV_ADDRESS_SPACE arg4); + +static inline NvBool memmgrMemUtilsCheckMemoryFastScrubEnable_491d52(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvBool arg1, RmPhysAddr arg2, NvU32 arg3, NV_ADDRESS_SPACE arg4) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvBool arg1, RmPhysAddr arg2, NvU32 arg3, NV_ADDRESS_SPACE arg4) { + return pMemoryManager->__memmgrMemUtilsCheckMemoryFastScrubEnable__(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4); +} + NV_STATUS memmgrAllocDetermineAlignment_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment); NV_STATUS memmgrAllocDetermineAlignment_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment); @@ -1702,6 +1685,8 @@ NvU64 memmgrGetMaxContextSize_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryM NvU64 memmgrGetMaxContextSize_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +NvU64 memmgrGetMaxContextSize_AD102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + static inline NvU64 memmgrGetMaxContextSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return 0; } @@ -1722,6 +1707,36 @@ static inline void memmgrScrubRegistryOverrides_DISPATCH(OBJGPU *pGpu, struct Me pMemoryManager->__memmgrScrubRegistryOverrides__(pGpu, pMemoryManager); } +NvU32 memmgrGetPteKindBl_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetPteKindBl_474d46(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 memmgrGetPteKindBl_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetPteKindBl__(pGpu, pMemoryManager); +} + +NvU32 memmgrGetPteKindPitch_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetPteKindPitch_474d46(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 memmgrGetPteKindPitch_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetPteKindPitch__(pGpu, pMemoryManager); +} + +NvU32 memmgrChooseKindCompressC_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0); + +static inline NvU32 memmgrChooseKindCompressC_474d46(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 memmgrChooseKindCompressC_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0) { + return pMemoryManager->__memmgrChooseKindCompressC__(pGpu, pMemoryManager, arg0); +} + NV_STATUS memmgrGetFlaKind_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *arg0); static inline NV_STATUS memmgrGetFlaKind_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *arg0) { @@ -1930,14 +1945,6 @@ static inline NvBool memmgrIsPmaAddrTree(struct MemoryManager *pMemoryManager) { return pMemoryManager->bPmaAddrTree; } -static inline NvBool memmgrIsMemoryProtectionEnabledInSw(struct MemoryManager *pMemoryManager) { - return pMemoryManager->bSupportCCProtectedMemoryAlloc; -} - -static inline void memmgrSetMemoryProtectionInSw(struct MemoryManager *pMemoryManager, NvU32 val) { - pMemoryManager->bSupportCCProtectedMemoryAlloc = !!val; -} - static inline NvU64 memmgrGetRsvdMemoryBase(struct MemoryManager *pMemoryManager) { return pMemoryManager->rsvdMemoryBase; } diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index dc5ffa1c4..048f225b6 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -1474,6 +1474,18 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, + { 0x2331, 0x16d3, 0x10DE, "GRID H100-1-10C" }, + { 0x2331, 0x16d4, 0x10DE, "GRID H100-2-20C" }, + { 0x2331, 0x16d5, 0x10DE, "GRID H100-3-40C" }, + { 0x2331, 0x16d6, 0x10DE, "GRID H100-4-40C" }, + { 0x2331, 0x16d7, 0x10DE, "GRID H100-7-80C" }, + { 0x2331, 0x16d8, 0x10DE, "GRID H100-4C" }, + { 0x2331, 0x16d9, 0x10DE, "GRID H100-8C" }, + { 0x2331, 0x16da, 0x10DE, "GRID H100-10C" }, + { 0x2331, 0x16db, 0x10DE, "GRID H100-16C" }, + { 0x2331, 0x16dc, 0x10DE, "GRID H100-20C" }, + { 0x2331, 0x16dd, 0x10DE, "GRID H100-40C" }, + { 0x2331, 0x16de, 0x10DE, "GRID H100-80C" }, { 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" }, { 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" }, { 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" }, diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index 3d7776b68..8697633b6 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -226,7 +226,7 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS, ((NvBool)(0 == 0))); } @@ -237,7 +237,7 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner } // NVOC Property Hal field -- PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE, ((NvBool)(0 == 0))); } @@ -260,8 +260,9 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner pThis->setProperty(pThis, PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS, (0)); // NVOC Property Hal field -- PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->setProperty(pThis, PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL, ((NvBool)(0 == 0))); } // default else @@ -325,7 +326,7 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal { pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_GA100; } @@ -347,6 +348,87 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStateDestroy__ = &tmrStateDestroy_IMPL; + // Hal function -- tmrSetCurrentTime + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; + } + else if (0) + { + } + } + + // Hal function -- tmrGetTimeEx + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; + } + else if (0) + { + } + } + + // Hal function -- tmrSetCountdownIntrDisable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; + } + // default + else + { + } + + // Hal function -- tmrSetCountdown + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; + } + else if (0) + { + } + + // Hal function -- tmrGrTickFreqChange + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; + } + // Hal function -- tmrGetGpuPtimerOffset if (0) { @@ -358,7 +440,7 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_GA100; } @@ -377,8 +459,9 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal else if (0) { #if 0 - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ { + pThis->__tmrGetPhysicalIntrVectors__ = &tmrGetPhysicalIntrVectors_GH100; } // default else diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 5493ee175..1002c1e9c 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -198,6 +198,11 @@ struct OBJTMR { NV_STATUS (*__tmrStateLoad__)(OBJGPU *, struct OBJTMR *, NvU32); NV_STATUS (*__tmrStateUnload__)(OBJGPU *, struct OBJTMR *, NvU32); void (*__tmrStateDestroy__)(OBJGPU *, struct OBJTMR *); + NV_STATUS (*__tmrSetCurrentTime__)(OBJGPU *, struct OBJTMR *); + NvU64 (*__tmrGetTimeEx__)(OBJGPU *, struct OBJTMR *, struct THREAD_STATE_NODE *); + NV_STATUS (*__tmrSetCountdownIntrDisable__)(OBJGPU *, struct OBJTMR *); + NV_STATUS (*__tmrSetCountdown__)(OBJGPU *, struct OBJTMR *, NvU32, NvU32, struct THREAD_STATE_NODE *); + NV_STATUS (*__tmrGrTickFreqChange__)(OBJGPU *, struct OBJTMR *, NvBool); NV_STATUS (*__tmrGetGpuPtimerOffset__)(OBJGPU *, struct OBJTMR *, NvU32 *, NvU32 *); NV_STATUS (*__tmrGetPhysicalIntrVectors__)(OBJGPU *, struct OBJTMR *, NvU32, NvU32 *, NvU32 *, NvU32 *); void (*__tmrFreeTunableState__)(POBJGPU, struct OBJTMR *, void *); @@ -294,6 +299,16 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32); #define tmrStateLoad(pGpu, pTmr, arg0) tmrStateLoad_DISPATCH(pGpu, pTmr, arg0) #define tmrStateUnload(pGpu, pTmr, arg0) tmrStateUnload_DISPATCH(pGpu, pTmr, arg0) #define tmrStateDestroy(pGpu, pTmr) tmrStateDestroy_DISPATCH(pGpu, pTmr) +#define tmrSetCurrentTime(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr) +#define tmrSetCurrentTime_HAL(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr) +#define tmrGetTimeEx(pGpu, pTmr, arg0) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg0) +#define tmrGetTimeEx_HAL(pGpu, pTmr, arg0) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg0) +#define tmrSetCountdownIntrDisable(pGpu, pTmr) tmrSetCountdownIntrDisable_DISPATCH(pGpu, pTmr) +#define tmrSetCountdownIntrDisable_HAL(pGpu, pTmr) tmrSetCountdownIntrDisable_DISPATCH(pGpu, pTmr) +#define tmrSetCountdown(pGpu, pTmr, arg0, arg1, arg2) tmrSetCountdown_DISPATCH(pGpu, pTmr, arg0, arg1, arg2) +#define tmrSetCountdown_HAL(pGpu, pTmr, arg0, arg1, arg2) tmrSetCountdown_DISPATCH(pGpu, pTmr, arg0, arg1, arg2) +#define tmrGrTickFreqChange(pGpu, pTmr, arg0) tmrGrTickFreqChange_DISPATCH(pGpu, pTmr, arg0) +#define tmrGrTickFreqChange_HAL(pGpu, pTmr, arg0) tmrGrTickFreqChange_DISPATCH(pGpu, pTmr, arg0) #define tmrGetGpuPtimerOffset(pGpu, pTmr, arg0, arg1) tmrGetGpuPtimerOffset_DISPATCH(pGpu, pTmr, arg0, arg1) #define tmrGetGpuPtimerOffset_HAL(pGpu, pTmr, arg0, arg1) tmrGetGpuPtimerOffset_DISPATCH(pGpu, pTmr, arg0, arg1) #define tmrGetPhysicalIntrVectors(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) tmrGetPhysicalIntrVectors_DISPATCH(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) @@ -353,19 +368,6 @@ static inline NV_STATUS tmrDelay(struct OBJTMR *pTmr, NvU32 arg0) { #define tmrDelay_HAL(pTmr, arg0) tmrDelay(pTmr, arg0) -NV_STATUS tmrSetCurrentTime_GV100(OBJGPU *pGpu, struct OBJTMR *pTmr); - -#ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrSetCurrentTime(OBJGPU *pGpu, struct OBJTMR *pTmr) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_objtmr_h_disabled -#define tmrSetCurrentTime(pGpu, pTmr) tmrSetCurrentTime_GV100(pGpu, pTmr) -#endif //__nvoc_objtmr_h_disabled - -#define tmrSetCurrentTime_HAL(pGpu, pTmr) tmrSetCurrentTime(pGpu, pTmr) - static inline NV_STATUS tmrSetAlarmIntrDisable_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { return NV_OK; } @@ -457,19 +459,6 @@ static inline NvU64 tmrGetTime(OBJGPU *pGpu, struct OBJTMR *pTmr) { #define tmrGetTime_HAL(pGpu, pTmr) tmrGetTime(pGpu, pTmr) -NvU64 tmrGetTimeEx_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); - -#ifdef __nvoc_objtmr_h_disabled -static inline NvU64 tmrGetTimeEx(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return 0; -} -#else //__nvoc_objtmr_h_disabled -#define tmrGetTimeEx(pGpu, pTmr, arg0) tmrGetTimeEx_GM107(pGpu, pTmr, arg0) -#endif //__nvoc_objtmr_h_disabled - -#define tmrGetTimeEx_HAL(pGpu, pTmr, arg0) tmrGetTimeEx(pGpu, pTmr, arg0) - NvU32 tmrReadTimeLoReg_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); #ifdef __nvoc_objtmr_h_disabled @@ -526,19 +515,6 @@ static inline NvBool tmrGetAlarmPending(OBJGPU *pGpu, struct OBJTMR *pTmr, struc #define tmrGetAlarmPending_HAL(pGpu, pTmr, arg0) tmrGetAlarmPending(pGpu, pTmr, arg0) -NV_STATUS tmrSetCountdownIntrDisable_GM200(OBJGPU *pGpu, struct OBJTMR *pTmr); - -#ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrSetCountdownIntrDisable(OBJGPU *pGpu, struct OBJTMR *pTmr) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_objtmr_h_disabled -#define tmrSetCountdownIntrDisable(pGpu, pTmr) tmrSetCountdownIntrDisable_GM200(pGpu, pTmr) -#endif //__nvoc_objtmr_h_disabled - -#define tmrSetCountdownIntrDisable_HAL(pGpu, pTmr) tmrSetCountdownIntrDisable(pGpu, pTmr) - NV_STATUS tmrSetCountdownIntrEnable_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr); #ifdef __nvoc_objtmr_h_disabled @@ -580,19 +556,6 @@ static inline NvBool tmrGetCountdownPending(OBJGPU *pGpu, struct OBJTMR *pTmr, s #define tmrGetCountdownPending_HAL(pGpu, pTmr, arg0) tmrGetCountdownPending(pGpu, pTmr, arg0) -NV_STATUS tmrSetCountdown_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); - -#ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrSetCountdown(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_objtmr_h_disabled -#define tmrSetCountdown(pGpu, pTmr, arg0, arg1, arg2) tmrSetCountdown_TU102(pGpu, pTmr, arg0, arg1, arg2) -#endif //__nvoc_objtmr_h_disabled - -#define tmrSetCountdown_HAL(pGpu, pTmr, arg0, arg1, arg2) tmrSetCountdown(pGpu, pTmr, arg0, arg1, arg2) - NV_STATUS tmrGetTimerBar0MapInfo_PTIMER(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *arg0, NvU32 *arg1); #ifdef __nvoc_objtmr_h_disabled @@ -606,19 +569,6 @@ static inline NV_STATUS tmrGetTimerBar0MapInfo(OBJGPU *pGpu, struct OBJTMR *pTmr #define tmrGetTimerBar0MapInfo_HAL(pGpu, pTmr, arg0, arg1) tmrGetTimerBar0MapInfo(pGpu, pTmr, arg0, arg1) -NV_STATUS tmrGrTickFreqChange_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, NvBool arg0); - -#ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrGrTickFreqChange(OBJGPU *pGpu, struct OBJTMR *pTmr, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_objtmr_h_disabled -#define tmrGrTickFreqChange(pGpu, pTmr, arg0) tmrGrTickFreqChange_GM107(pGpu, pTmr, arg0) -#endif //__nvoc_objtmr_h_disabled - -#define tmrGrTickFreqChange_HAL(pGpu, pTmr, arg0) tmrGrTickFreqChange(pGpu, pTmr, arg0) - static inline NvU32 tmrGetUtilsClkScaleFactor_4a4dee(OBJGPU *pGpu, struct OBJTMR *pTmr) { return 0; } @@ -800,6 +750,70 @@ static inline void tmrStateDestroy_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { pTmr->__tmrStateDestroy__(pGpu, pTmr); } +static inline NV_STATUS tmrSetCurrentTime_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_OK; +} + +NV_STATUS tmrSetCurrentTime_GV100(OBJGPU *pGpu, struct OBJTMR *pTmr); + +NV_STATUS tmrSetCurrentTime_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NV_STATUS tmrSetCurrentTime_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS tmrSetCurrentTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return pTmr->__tmrSetCurrentTime__(pGpu, pTmr); +} + +static inline NvU64 tmrGetTimeEx_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { + return osGetTimestamp(); +} + +NvU64 tmrGetTimeEx_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + +NvU64 tmrGetTimeEx_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + +static inline NvU64 tmrGetTimeEx_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { + return pTmr->__tmrGetTimeEx__(pGpu, pTmr, arg0); +} + +NV_STATUS tmrSetCountdownIntrDisable_GM200(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NV_STATUS tmrSetCountdownIntrDisable_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_OK; +} + +static inline NV_STATUS tmrSetCountdownIntrDisable_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS tmrSetCountdownIntrDisable_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return pTmr->__tmrSetCountdownIntrDisable__(pGpu, pTmr); +} + +NV_STATUS tmrSetCountdown_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +NV_STATUS tmrSetCountdown_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +static inline NV_STATUS tmrSetCountdown_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS tmrSetCountdown_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { + return pTmr->__tmrSetCountdown__(pGpu, pTmr, arg0, arg1, arg2); +} + +NV_STATUS tmrGrTickFreqChange_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, NvBool arg0); + +static inline NV_STATUS tmrGrTickFreqChange_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvBool arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS tmrGrTickFreqChange_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvBool arg0) { + return pTmr->__tmrGrTickFreqChange__(pGpu, pTmr, arg0); +} + NV_STATUS tmrGetGpuPtimerOffset_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1); NV_STATUS tmrGetGpuPtimerOffset_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1); @@ -820,6 +834,8 @@ static inline NV_STATUS tmrGetPhysicalIntrVectors_46f6a7(OBJGPU *pGpu, struct OB return NV_ERR_NOT_SUPPORTED; } +NV_STATUS tmrGetPhysicalIntrVectors_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount); + static inline NV_STATUS tmrGetPhysicalIntrVectors_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { return pTmr->__tmrGetPhysicalIntrVectors__(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount); } diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 16f314d7d..0ee6be853 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -53,6 +53,7 @@ extern "C" { /* ------------------------ OS Includes ------------------------------------- */ #include "os/nv_memory_type.h" #include "os/capability.h" +#include "os/os_fixed_mode_timings_props.h" /* ------------------------ Forward Declarations ---------------------------- */ @@ -306,6 +307,8 @@ typedef NV_STATUS OSDelay(NvU32); typedef NV_STATUS OSDelayUs(NvU32); typedef NV_STATUS OSDelayNs(NvU32); typedef void OSSpinLoop(void); +typedef NvU64 OSGetMaxUserVa(void); +typedef NvU32 OSGetCpuVaAddrShift(void); typedef NvU32 OSGetCurrentProcess(void); typedef void OSGetCurrentProcessName(char *, NvU32); typedef NvU32 OSGetCurrentPasid(void); @@ -763,11 +766,10 @@ NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osIovaMap(PIOVAMAPPING pIovaMapping); void osIovaUnmap(PIOVAMAPPING pIovaMapping); NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu, - NvU32 *pAddr, + NvU64 *pAddr, NvU32 *pAddrWidth, NvU32 *pMask, NvU32 *pMaskWidth, - NvU32 *pGranularity, NvBool bIsPeer, NvU32 peerIndex); NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu, @@ -875,6 +877,9 @@ NV_STATUS osGetSyncpointAperture(OS_GPU_INFO *pOsGpuInfo, NvU64 *limit, NvU32 *offset); NV_STATUS osTegraI2CGetBusState(OS_GPU_INFO *pOsGpuInfo, NvU32 port, NvS32 *scl, NvS32 *sda); +NV_STATUS osTegraSocParseFixedModeTimings(OS_GPU_INFO *pOsGpuInfo, + NvU32 dcbIndex, + OS_FIXED_MODE_TIMINGS *pFixedModeTimings); NV_STATUS osGetVersion(NvU32 *pMajorVer, NvU32 *pMinorVer, @@ -1030,6 +1035,23 @@ NV_STATUS osTegraSocGpioSetPinInterrupt(OS_GPU_INFO *pArg1, NvU32 arg2, NvU32 arg3); +NV_STATUS osTegraSocDsiParsePanelProps(OS_GPU_INFO *pArg1, + void *pArg2); + +NvBool osTegraSocIsDsiPanelConnected(OS_GPU_INFO *pArg1); + +NV_STATUS osTegraSocDsiPanelEnable(OS_GPU_INFO *pArg1, + void *pArg2); + +NV_STATUS osTegraSocDsiPanelReset(OS_GPU_INFO *pArg1, + void *pArg2); + +void osTegraSocDsiPanelDisable(OS_GPU_INFO *pArg1, + void *pArg2); + +void osTegraSocDsiPanelCleanup(OS_GPU_INFO *pArg1, + void *pArg2); + NV_STATUS osTegraSocResetMipiCal(OS_GPU_INFO *pArg1); NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1, @@ -1126,6 +1148,8 @@ NV_STATUS osVerifySystemEnvironment(OBJGPU *pGpu); NV_STATUS osSanityTestIsr(OBJGPU *pGpu); +NV_STATUS osConfigurePcieReqAtomics(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask); + NvBool osDmabufIsSupported(void); static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu) @@ -1157,6 +1181,11 @@ static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu) #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1) #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2) +NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, + NvU64 size, NvU32 *pNumaNodeId); +void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, + NvU64 size, NvU32 numaNodeId); + // Os 1Hz timer callback functions NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr); NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr); @@ -1180,7 +1209,6 @@ NvU32 vgpuDevReadReg032( void osInitSystemStaticConfig(SYS_STATIC_CONFIG *); -NvU32 osGetReleaseAssertBehavior(void); void osDbgBugCheckOnAssert(void); NvBool osBugCheckOnTimeoutEnabled(void); @@ -1212,6 +1240,8 @@ OSGetMaximumCoreCount osGetMaximumCoreCount; OSGetCurrentProcessorNumber osGetCurrentProcessorNumber; OSGetVersionDump osGetVersionDump; +OSGetMaxUserVa osGetMaxUserVa; +OSGetCpuVaAddrShift osGetCpuVaAddrShift; OSMemAddFilter osMemAddFilter; OSMemRemoveFilter osMemRemoveFilter; OSMemGetFilter osMemGetFilter; diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 23135b7ff..5f4395e92 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -323,12 +323,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [9] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdExecRegops_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) - /*flags=*/ 0x230u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc010au, /*paramSize=*/ sizeof(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS), @@ -530,7 +530,7 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__profilerBaseCtrlCmdExecRegops__ = &profilerBaseCtrlCmdExecRegops_IMPL; #endif diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index 1c6bf0a90..ac9fb1624 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -39,6 +39,8 @@ extern "C" { #ifndef RESOURCE_FWD_DECLS_H #define RESOURCE_FWD_DECLS_H +#include "rmconfig.h" + // Base classes struct ChannelDescendant; @@ -546,6 +548,18 @@ typedef struct I2cApi I2cApi; #endif /* __nvoc_class_id_I2cApi */ +struct KernelCcuApi; + +#ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +#define __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +typedef struct KernelCcuApi KernelCcuApi; +#endif /* __NVOC_CLASS_KernelCcuApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCcuApi +#define __nvoc_class_id_KernelCcuApi 0x3abed3 +#endif /* __nvoc_class_id_KernelCcuApi */ + + struct KernelChannel; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ diff --git a/src/nvidia/generated/g_resource_nvoc.c b/src/nvidia/generated/g_resource_nvoc.c index eee007e5a..9547f8d99 100644 --- a/src/nvidia/generated/g_resource_nvoc.c +++ b/src/nvidia/generated/g_resource_nvoc.c @@ -33,6 +33,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_RmResourceCommon = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_rmconfig_private.h b/src/nvidia/generated/g_rmconfig_private.h index 0abaf0a37..64c5df2a2 100644 --- a/src/nvidia/generated/g_rmconfig_private.h +++ b/src/nvidia/generated/g_rmconfig_private.h @@ -8,7 +8,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_private.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _G_RMCFG_PRIVATE_H_ @@ -242,7 +242,7 @@ #define IsGA107orBetter(pGpu) rmcfg_IsGA107orBetter(pGpu) #define IsGA10B(pGpu) ((0) && (pGpu)) -#define IsGA10BorBetter(pGpu) ((0) && (pGpu)) +#define IsGA10BorBetter(pGpu) rmcfg_IsGA10BorBetter(pGpu) // Any GA10X chip? #define IsGA10X(pGpu) rmcfg_IsGA10X(pGpu) @@ -251,11 +251,35 @@ // GA10XF #define IsGA102F(pGpu) ((0) && (pGpu)) -#define IsGA102ForBetter(pGpu) ((0) && (pGpu)) +#define IsGA102ForBetter(pGpu) rmcfg_IsGA102ForBetter(pGpu) // Any GA10XF chip? #define IsGA10XF(pGpu) (0 && (pGpu)) -#define IsGA10XForBetter(pGpu) (0 && (pGpu)) +#define IsGA10XForBetter(pGpu) rmcfg_IsGA10XForBetter(pGpu) + + +// AD10X +#define IsAD102(pGpu) rmcfg_IsAD102(pGpu) +#define IsAD102orBetter(pGpu) rmcfg_IsAD102orBetter(pGpu) + +#define IsAD103(pGpu) rmcfg_IsAD103(pGpu) +#define IsAD103orBetter(pGpu) rmcfg_IsAD103orBetter(pGpu) + +#define IsAD104(pGpu) rmcfg_IsAD104(pGpu) +#define IsAD104orBetter(pGpu) rmcfg_IsAD104orBetter(pGpu) + +// Any AD10X chip? +#define IsAD10X(pGpu) rmcfg_IsAD10X(pGpu) +#define IsAD10XorBetter(pGpu) rmcfg_IsAD10XorBetter(pGpu) + + +// GH10X +#define IsGH100(pGpu) rmcfg_IsGH100(pGpu) +#define IsGH100orBetter(pGpu) rmcfg_IsGH100orBetter(pGpu) + +// Any GH10X chip? +#define IsGH10X(pGpu) rmcfg_IsGH10X(pGpu) +#define IsGH10XorBetter(pGpu) rmcfg_IsGH10XorBetter(pGpu) // T12X @@ -462,6 +486,36 @@ #define IsDFPGA(pGpu) (0 && (pGpu)) +// Any dADA chip? +#define IsdADA(pGpu) rmcfg_IsdADA(pGpu) +#define IsdADAorBetter(pGpu) rmcfg_IsdADAorBetter(pGpu) + + +// Any ADA chip? +#define IsADA(pGpu) (IsADA_CLASSIC_GPUS(pGpu) || IsADA_TEGRA_BIG_GPUS(pGpu)) +#define IsADAorBetter(pGpu) (IsADA_CLASSIC_GPUSorBetter(pGpu) || IsADA_TEGRA_BIG_GPUSorBetter(pGpu)) + + +// Any ADA_CLASSIC_GPUS chip? +#define IsADA_CLASSIC_GPUS(pGpu) rmcfg_IsADA_CLASSIC_GPUS(pGpu) +#define IsADA_CLASSIC_GPUSorBetter(pGpu) rmcfg_IsADA_CLASSIC_GPUSorBetter(pGpu) + + +// Any dHOPPER chip? +#define IsdHOPPER(pGpu) rmcfg_IsdHOPPER(pGpu) +#define IsdHOPPERorBetter(pGpu) rmcfg_IsdHOPPERorBetter(pGpu) + + +// Any HOPPER chip? +#define IsHOPPER(pGpu) (IsHOPPER_CLASSIC_GPUS(pGpu) || IsHOPPER_TEGRA_BIG_GPUS(pGpu)) +#define IsHOPPERorBetter(pGpu) (IsHOPPER_CLASSIC_GPUSorBetter(pGpu) || IsHOPPER_TEGRA_BIG_GPUSorBetter(pGpu)) + + +// Any HOPPER_CLASSIC_GPUS chip? +#define IsHOPPER_CLASSIC_GPUS(pGpu) rmcfg_IsHOPPER_CLASSIC_GPUS(pGpu) +#define IsHOPPER_CLASSIC_GPUSorBetter(pGpu) rmcfg_IsHOPPER_CLASSIC_GPUSorBetter(pGpu) + + // Any TEGRA_BIG_GPUS chip? #define IsTEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) #define IsTEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) @@ -689,7 +743,4 @@ -// ARCH test -#define RMCFG_IS_ARCH(arch) RMCFG_FEATURE_ARCH_##arch - #endif // _G_RMCFG_PRIVATE_H_ diff --git a/src/nvidia/generated/g_rmconfig_util.c b/src/nvidia/generated/g_rmconfig_util.c index d9d1b9b78..4407d9342 100644 --- a/src/nvidia/generated/g_rmconfig_util.c +++ b/src/nvidia/generated/g_rmconfig_util.c @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_util.c // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #include "gpu/gpu.h" @@ -131,6 +131,11 @@ NvBool rmcfg_IsGA107orBetter(POBJGPU pGpu) return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_GA107, GPU_NO_MASK_REVISION, GPU_NO_REVISION); } +NvBool rmcfg_IsGA10BorBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_GA10B, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + NvBool rmcfg_IsGA10X(POBJGPU pGpu) { return IsGA100(pGpu) || IsGA102(pGpu) || IsGA103(pGpu) || IsGA104(pGpu) || IsGA106(pGpu) || IsGA107(pGpu); @@ -141,9 +146,79 @@ NvBool rmcfg_IsGA10XorBetter(POBJGPU pGpu) return IsGA100orBetter(pGpu); } +NvBool rmcfg_IsGA102ForBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_GA102F, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsGA10XForBetter(POBJGPU pGpu) +{ + return IsAD102orBetter(pGpu); +} + +NvBool rmcfg_IsAD102(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_AD102, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD102orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD102, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD103(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_AD103, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD103orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD103, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD104(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_AD104, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD104orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD104, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD10X(POBJGPU pGpu) +{ + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); +} + +NvBool rmcfg_IsAD10XorBetter(POBJGPU pGpu) +{ + return IsAD102orBetter(pGpu); +} + +NvBool rmcfg_IsGH100(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_GH100, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsGH100orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_GH100, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsGH10X(POBJGPU pGpu) +{ + return IsGH100(pGpu); +} + +NvBool rmcfg_IsGH10XorBetter(POBJGPU pGpu) +{ + return IsGH100orBetter(pGpu); +} + NvBool rmcfg_IsDISPLAYLESS(POBJGPU pGpu) { - return IsGA100(pGpu); + return IsGA100(pGpu) || IsGH100(pGpu); } NvBool rmcfg_IsdTURING(POBJGPU pGpu) @@ -176,6 +251,46 @@ NvBool rmcfg_IsAMPERE_CLASSIC_GPUSorBetter(POBJGPU pGpu) return IsGA100orBetter(pGpu); } +NvBool rmcfg_IsdADA(POBJGPU pGpu) +{ + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); +} + +NvBool rmcfg_IsdADAorBetter(POBJGPU pGpu) +{ + return IsAD102orBetter(pGpu); +} + +NvBool rmcfg_IsADA_CLASSIC_GPUS(POBJGPU pGpu) +{ + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); +} + +NvBool rmcfg_IsADA_CLASSIC_GPUSorBetter(POBJGPU pGpu) +{ + return IsAD102orBetter(pGpu); +} + +NvBool rmcfg_IsdHOPPER(POBJGPU pGpu) +{ + return IsGH100(pGpu); +} + +NvBool rmcfg_IsdHOPPERorBetter(POBJGPU pGpu) +{ + return IsGH100orBetter(pGpu); +} + +NvBool rmcfg_IsHOPPER_CLASSIC_GPUS(POBJGPU pGpu) +{ + return IsGH100(pGpu); +} + +NvBool rmcfg_IsHOPPER_CLASSIC_GPUSorBetter(POBJGPU pGpu) +{ + return IsGH100orBetter(pGpu); +} + // NVOC class ID uniqueness checks diff --git a/src/nvidia/generated/g_rmconfig_util.h b/src/nvidia/generated/g_rmconfig_util.h index 9122e89f1..599b551de 100644 --- a/src/nvidia/generated/g_rmconfig_util.h +++ b/src/nvidia/generated/g_rmconfig_util.h @@ -7,7 +7,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_util.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _G_RMCFG_UTIL_H_ @@ -40,8 +40,23 @@ NvBool rmcfg_IsGA106(POBJGPU pGpu); NvBool rmcfg_IsGA106orBetter(POBJGPU pGpu); NvBool rmcfg_IsGA107(POBJGPU pGpu); NvBool rmcfg_IsGA107orBetter(POBJGPU pGpu); +NvBool rmcfg_IsGA10BorBetter(POBJGPU pGpu); NvBool rmcfg_IsGA10X(POBJGPU pGpu); NvBool rmcfg_IsGA10XorBetter(POBJGPU pGpu); +NvBool rmcfg_IsGA102ForBetter(POBJGPU pGpu); +NvBool rmcfg_IsGA10XForBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD102(POBJGPU pGpu); +NvBool rmcfg_IsAD102orBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD103(POBJGPU pGpu); +NvBool rmcfg_IsAD103orBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD104(POBJGPU pGpu); +NvBool rmcfg_IsAD104orBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD10X(POBJGPU pGpu); +NvBool rmcfg_IsAD10XorBetter(POBJGPU pGpu); +NvBool rmcfg_IsGH100(POBJGPU pGpu); +NvBool rmcfg_IsGH100orBetter(POBJGPU pGpu); +NvBool rmcfg_IsGH10X(POBJGPU pGpu); +NvBool rmcfg_IsGH10XorBetter(POBJGPU pGpu); NvBool rmcfg_IsDISPLAYLESS(POBJGPU pGpu); NvBool rmcfg_IsdTURING(POBJGPU pGpu); NvBool rmcfg_IsTURING_CLASSIC_GPUS(POBJGPU pGpu); @@ -49,6 +64,14 @@ NvBool rmcfg_IsdAMPERE(POBJGPU pGpu); NvBool rmcfg_IsdAMPEREorBetter(POBJGPU pGpu); NvBool rmcfg_IsAMPERE_CLASSIC_GPUS(POBJGPU pGpu); NvBool rmcfg_IsAMPERE_CLASSIC_GPUSorBetter(POBJGPU pGpu); +NvBool rmcfg_IsdADA(POBJGPU pGpu); +NvBool rmcfg_IsdADAorBetter(POBJGPU pGpu); +NvBool rmcfg_IsADA_CLASSIC_GPUS(POBJGPU pGpu); +NvBool rmcfg_IsADA_CLASSIC_GPUSorBetter(POBJGPU pGpu); +NvBool rmcfg_IsdHOPPER(POBJGPU pGpu); +NvBool rmcfg_IsdHOPPERorBetter(POBJGPU pGpu); +NvBool rmcfg_IsHOPPER_CLASSIC_GPUS(POBJGPU pGpu); +NvBool rmcfg_IsHOPPER_CLASSIC_GPUSorBetter(POBJGPU pGpu); #endif // _G_RMCFG_UTIL_H_ diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index 2203526b6..dfb60389f 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -393,6 +393,15 @@ typedef struct rpc_perf_bridgeless_info_update_v17_00 typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; +typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 +{ + NvU32 sysmemPfnBitmapRing; + NvU32 sysmemPfnBitmapRingHi; + NvU32 sysmemPfnBitmap; +} rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; + +typedef rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 rpc_set_sysmem_dirty_page_tracking_buffer_v; + #endif @@ -1679,6 +1688,35 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRing), + .name = "sysmemPfnBitmapRing" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRingHi), + .name = "sysmemPfnBitmapRingHi" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmap), + .name = "sysmemPfnBitmap" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 = { + .name = "rpc_set_sysmem_dirty_page_tracking_buffer", + .header_length = NV_SIZEOF32(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), + .fdesc = vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 +}; +#endif + #endif #ifdef RPC_DEBUG_PRINT_FUNCTIONS @@ -1994,6 +2032,13 @@ vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 +vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) +{ + return &vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; +} +#endif + #endif @@ -2076,6 +2121,8 @@ typedef union rpc_generic_union { rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v; rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00; rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v; + rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; + rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; } rpc_generic_union; #endif diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index 663c9877d..47d85d346 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -15,58 +15,58 @@ // RPC:VGPU_PF_REG_READ32 RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_v15_00; -RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:DUMP_PROTOBUF_COMPONENT RpcDumpProtobufComponent rpcDumpProtobufComponent_v18_12; -RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:ALLOC_MEMORY RpcAllocMemory rpcAllocMemory_v13_01; -RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:GPU_EXEC_REG_OPS RpcGpuExecRegOps rpcGpuExecRegOps_v12_01; -RpcGpuExecRegOps rpcGpuExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcGpuExecRegOps rpcGpuExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:RMFS_INIT RpcRmfsInit rpcRmfsInit_v15_00; -RpcRmfsInit rpcRmfsInit_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcRmfsInit rpcRmfsInit_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:UNSET_PAGE_DIRECTORY RpcUnsetPageDirectory rpcUnsetPageDirectory_v03_00; RpcUnsetPageDirectory rpcUnsetPageDirectory_v1E_05; -RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:GET_GSP_STATIC_INFO RpcGetGspStaticInfo rpcGetGspStaticInfo_v14_00; -RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:GSP_SET_SYSTEM_INFO RpcGspSetSystemInfo rpcGspSetSystemInfo_v17_00; -RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:RMFS_CLEANUP RpcRmfsCleanup rpcRmfsCleanup_v15_00; -RpcRmfsCleanup rpcRmfsCleanup_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcRmfsCleanup rpcRmfsCleanup_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:SET_PAGE_DIRECTORY RpcSetPageDirectory rpcSetPageDirectory_v03_00; RpcSetPageDirectory rpcSetPageDirectory_v1E_05; -RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:UNLOADING_GUEST_DRIVER RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v03_00; RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v1F_07; -RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:SET_REGISTRY RpcSetRegistry rpcSetRegistry_v17_00; -RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:RMFS_CLOSE_QUEUE RpcRmfsCloseQueue rpcRmfsCloseQueue_v15_00; -RpcRmfsCloseQueue rpcRmfsCloseQueue_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcRmfsCloseQueue rpcRmfsCloseQueue_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:GET_STATIC_INFO RpcGetStaticInfo rpcGetStaticInfo_v17_05; @@ -80,27 +80,29 @@ RpcGetStaticInfo rpcGetStaticInfo_v18_16; RpcGetStaticInfo rpcGetStaticInfo_v19_00; RpcGetStaticInfo rpcGetStaticInfo_v1A_00; RpcGetStaticInfo rpcGetStaticInfo_v1A_05; -RpcGetStaticInfo rpcGetStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcGetStaticInfo rpcGetStaticInfo_v20_01; +RpcGetStaticInfo rpcGetStaticInfo_v20_04; +RpcGetStaticInfo rpcGetStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:IDLE_CHANNELS RpcIdleChannels rpcIdleChannels_v03_00; -RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:UPDATE_BAR_PDE RpcUpdateBarPde rpcUpdateBarPde_v15_00; -RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:MAP_MEMORY_DMA RpcMapMemoryDma rpcMapMemoryDma_v03_00; -RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:UNMAP_MEMORY_DMA RpcUnmapMemoryDma rpcUnmapMemoryDma_v03_00; -RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // RPC:RMFS_TEST RpcRmfsTest rpcRmfsTest_v15_00; -RpcRmfsTest rpcRmfsTest_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +RpcRmfsTest rpcRmfsTest_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X @@ -2112,6 +2114,91 @@ static void rpc_iGrp_ipVersions_Install_v1F_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInf #endif // } +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v20_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v20_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v20_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v20_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v20_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + @@ -2180,8 +2267,12 @@ static NV_STATUS rpc_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v19_00; if (IsIPVersionInRange(pRpc, 0x1A000000, 0x1A04FFFF)) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_00; - if (IsIPVersionInRange(pRpc, 0x1A050000, 0xFFFFFFFF)) + if (IsIPVersionInRange(pRpc, 0x1A050000, 0x2000FFFF)) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_05; + if (IsIPVersionInRange(pRpc, 0x20010000, 0x2003FFFF)) + pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_01; + if (IsIPVersionInRange(pRpc, 0x20040000, 0xFFFFFFFF)) + pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_04; if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) pRpcHal->rpcIdleChannels = rpcIdleChannels_v03_00; if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) @@ -2577,6 +2668,21 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_0F[] = { { 0x1F0F0000, 0xFFFFFFFF, }, // }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_00[] = { + { 0x20000000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_01[] = { + { 0x20010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_02[] = { + { 0x20020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_03[] = { + { 0x20030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_04[] = { + { 0x20040000, 0xFFFFFFFF, }, // + }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, } @@ -2699,6 +2805,11 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v1F_0D), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0E), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0F), // + _RPC_HAL_IGRP_ENTRY_INIT(v20_00), // + _RPC_HAL_IGRP_ENTRY_INIT(v20_01), // + _RPC_HAL_IGRP_ENTRY_INIT(v20_02), // + _RPC_HAL_IGRP_ENTRY_INIT(v20_03), // + _RPC_HAL_IGRP_ENTRY_INIT(v20_04), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT @@ -2871,6 +2982,98 @@ static void rpcHalIfacesSetup_GA107(RPC_HAL_IFACES *pRpcHal) #endif // GA10X or GA107 +#if defined(RMCFG_HAL_SETUP_AD102) + +static void rpcHalIfacesSetup_AD102(RPC_HAL_IFACES *pRpcHal) +{ + + // AD102's RPC hal interface function pointer block + static const RPC_HAL_IFACES rpcHalIfacesInitStruct_AD102 = + { + rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcAllocMemory_STUB, // rpcAllocMemory + rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps + rpcRmfsInit_STUB, // rpcRmfsInit + rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory + rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo + rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcSetRegistry_STUB, // rpcSetRegistry + rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue + rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcIdleChannels_STUB, // rpcIdleChannels + rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcMapMemoryDma_STUB, // rpcMapMemoryDma + rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma + rpcRmfsTest_STUB, // rpcRmfsTest + rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo + + }; // rpcHalIfacesInitStruct_AD102 + + // init AD102's RPC function ptrs using the init struct above + *pRpcHal = rpcHalIfacesInitStruct_AD102; +} + +#endif // AD10X or AD102 + +#if defined(RMCFG_HAL_SETUP_AD103) + +static void rpcHalIfacesSetup_AD103(RPC_HAL_IFACES *pRpcHal) +{ + rpcHalIfacesSetup_AD102(pRpcHal); // AD103 interfaces identical to AD102 +} + +#endif // AD10X or AD103 + +#if defined(RMCFG_HAL_SETUP_AD104) + +static void rpcHalIfacesSetup_AD104(RPC_HAL_IFACES *pRpcHal) +{ + rpcHalIfacesSetup_AD102(pRpcHal); // AD104 interfaces identical to AD102 +} + +#endif // AD10X or AD104 + +#if defined(RMCFG_HAL_SETUP_GH100) + +static void rpcHalIfacesSetup_GH100(RPC_HAL_IFACES *pRpcHal) +{ + + // GH100's RPC hal interface function pointer block + static const RPC_HAL_IFACES rpcHalIfacesInitStruct_GH100 = + { + rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcAllocMemory_STUB, // rpcAllocMemory + rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps + rpcRmfsInit_STUB, // rpcRmfsInit + rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory + rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo + rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcSetRegistry_STUB, // rpcSetRegistry + rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue + rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcIdleChannels_STUB, // rpcIdleChannels + rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcMapMemoryDma_STUB, // rpcMapMemoryDma + rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma + rpcRmfsTest_STUB, // rpcRmfsTest + rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo + + }; // rpcHalIfacesInitStruct_GH100 + + // init GH100's RPC function ptrs using the init struct above + *pRpcHal = rpcHalIfacesInitStruct_GH100; +} + +#endif // GH10X or GH100 + diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index 53601c8ff..6f022d8bb 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -231,7 +231,7 @@ typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E NvU32 bufSize; NvU32 count; NvU32 tracker; - NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL]; + NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E]; } NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E; typedef NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v; diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index d521d30e1..c4b06b8ad 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -991,21 +991,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [51] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuInterruptFunction_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800171u, - /*paramSize=*/ sizeof(NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdGpuInterruptFunction" -#endif - }, - { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1020,7 +1005,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuQueryFunctionStatus" #endif }, - { /* [53] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1035,7 +1020,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetPartitions" #endif }, - { /* [54] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1050,7 +1035,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPartitions" #endif }, - { /* [55] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1065,7 +1050,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuReportNonReplayableFault" #endif }, - { /* [56] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1080,7 +1065,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetEngineRunlistPriBase" #endif }, - { /* [57] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1095,7 +1080,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetHwEngineId" #endif }, - { /* [58] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1110,7 +1095,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetNvfbcSwSessionStats" #endif }, - { /* [59] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1125,7 +1110,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo" #endif }, - { /* [60] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1140,7 +1125,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPartitionCapacity" #endif }, - { /* [61] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1155,7 +1140,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetCachedInfo" #endif }, - { /* [62] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1170,7 +1155,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetPartitioningMode" #endif }, - { /* [63] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1185,7 +1170,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuDescribePartitions" #endif }, - { /* [64] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1200,7 +1185,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetMaxSupportedPageSize" #endif }, - { /* [65] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1215,7 +1200,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetActivePartitionIds" #endif }, - { /* [66] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1230,7 +1215,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPids" #endif }, - { /* [67] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1245,7 +1230,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPidInfo" #endif }, - { /* [68] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1260,7 +1245,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetComputePolicyConfig" #endif }, - { /* [69] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1275,7 +1260,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputePolicyConfig" #endif }, - { /* [70] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1290,7 +1275,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdValidateMemMapRequest" #endif }, - { /* [71] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1303,6 +1288,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdGpuGetEngineLoadTimes" +#endif + }, + { /* [71] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetComputeProfiles_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001a2u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetComputeProfiles" #endif }, { /* [72] */ @@ -1516,12 +1516,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [86] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdI2cReadReg_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) - /*flags=*/ 0x230u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800603u, /*paramSize=*/ sizeof(NV2080_CTRL_I2C_RW_REG_PARAMS), @@ -1531,12 +1531,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [87] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdI2cWriteReg_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) - /*flags=*/ 0x230u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800604u, /*paramSize=*/ sizeof(NV2080_CTRL_I2C_RW_REG_PARAMS), @@ -2853,6 +2853,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic { /* [175] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCcuMap_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ab3u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdCcuMap" +#endif + }, + { /* [176] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCcuUnmap_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ab4u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdCcuUnmap" +#endif + }, + { /* [177] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetPcieP2pCaps_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) @@ -2865,7 +2895,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [176] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2880,7 +2910,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [177] */ + { /* [179] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + /*flags=*/ 0x2600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800abau, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" +#endif + }, + { /* [180] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad8u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" +#endif + }, + { /* [181] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad9u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" +#endif + }, + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2888,14 +2963,14 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800abau, + /*methodId=*/ 0x20800adau, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [178] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2910,7 +2985,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [179] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2925,7 +3000,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [180] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2940,7 +3015,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [181] */ + { /* [186] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2955,7 +3030,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [182] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2970,7 +3045,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [183] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2985,7 +3060,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [184] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3000,7 +3075,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [185] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3015,13 +3090,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [186] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) + { /* [191] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*flags=*/ 0x2200u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801112u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS), @@ -3030,7 +3105,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [187] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3045,7 +3120,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [188] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3060,7 +3135,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [189] */ + { /* [194] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3075,7 +3150,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [190] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3090,7 +3165,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [191] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3105,7 +3180,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [192] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3120,7 +3195,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [193] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3135,7 +3210,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [194] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3150,7 +3225,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [195] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3165,7 +3240,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [196] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3180,7 +3255,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [197] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3195,7 +3270,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [198] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3210,7 +3285,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [199] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3225,7 +3300,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [200] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3240,7 +3315,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [201] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3255,7 +3330,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [202] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3270,7 +3345,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [203] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3285,7 +3360,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [204] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3300,7 +3375,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [205] */ + { /* [210] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3315,7 +3390,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [206] */ + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3330,7 +3405,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [207] */ + { /* [212] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3345,7 +3420,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [208] */ + { /* [213] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3360,7 +3435,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [209] */ + { /* [214] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3375,7 +3450,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [210] */ + { /* [215] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3390,7 +3465,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [211] */ + { /* [216] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3405,7 +3480,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [212] */ + { /* [217] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3420,7 +3495,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [213] */ + { /* [218] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3435,7 +3510,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [214] */ + { /* [219] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3450,7 +3525,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [215] */ + { /* [220] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3465,7 +3540,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [216] */ + { /* [221] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3480,7 +3555,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [217] */ + { /* [222] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3495,7 +3570,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [218] */ + { /* [223] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3510,7 +3585,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [219] */ + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3525,7 +3600,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [220] */ + { /* [225] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3540,7 +3615,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [221] */ + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3555,7 +3630,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [222] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3570,7 +3645,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [223] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3585,7 +3660,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [224] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3600,7 +3675,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [225] */ + { /* [230] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3615,7 +3690,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [226] */ + { /* [231] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3630,7 +3705,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [227] */ + { /* [232] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3645,7 +3720,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [228] */ + { /* [233] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3660,7 +3735,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [229] */ + { /* [234] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3675,7 +3750,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [230] */ + { /* [235] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801239u, + /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" +#endif + }, + { /* [236] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3690,7 +3780,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [231] */ + { /* [237] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3705,7 +3795,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [232] */ + { /* [238] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3720,7 +3810,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [233] */ + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3735,7 +3825,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [234] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3750,7 +3840,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [235] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3765,7 +3855,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [236] */ + { /* [242] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3780,7 +3870,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [237] */ + { /* [243] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3795,7 +3885,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [238] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3810,7 +3900,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [239] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3825,7 +3915,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [240] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3840,7 +3930,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [241] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3855,7 +3945,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [242] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3870,7 +3960,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [243] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3885,7 +3975,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [244] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3900,7 +3990,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [245] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3915,7 +4005,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [246] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3930,7 +4020,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [247] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3945,7 +4035,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [248] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3960,7 +4050,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [249] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3975,7 +4065,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [250] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,7 +4080,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [251] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4005,7 +4095,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [252] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4020,7 +4110,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [253] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4035,7 +4125,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [254] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4050,7 +4140,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [255] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4065,7 +4155,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [256] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4080,7 +4170,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [257] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4095,7 +4185,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [258] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4110,7 +4200,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [259] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4125,7 +4215,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [260] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4140,7 +4230,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [261] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4155,7 +4245,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [262] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4170,7 +4260,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [263] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4185,7 +4275,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [264] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4200,7 +4290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [265] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4215,7 +4305,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [266] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4230,7 +4320,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [267] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4245,7 +4335,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [268] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4260,7 +4350,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [269] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4275,7 +4365,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [270] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4290,7 +4380,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [271] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4305,7 +4395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [272] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4320,7 +4410,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [273] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4335,7 +4425,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [274] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4350,7 +4440,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [275] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4365,7 +4455,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [276] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4380,7 +4470,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [277] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4395,7 +4485,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [278] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4410,7 +4500,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [279] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4425,7 +4515,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [280] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4440,7 +4530,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [281] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4455,7 +4545,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [282] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4470,7 +4560,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [283] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4485,7 +4575,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [284] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4500,7 +4590,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [285] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4515,7 +4605,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [286] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4530,7 +4620,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [287] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4545,7 +4635,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [288] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4560,7 +4650,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [289] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4575,7 +4665,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [290] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4590,7 +4680,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [291] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4605,7 +4695,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [292] */ + { /* [298] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + /*flags=*/ 0x6210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801829u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" +#endif + }, + { /* [299] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + /*flags=*/ 0x6210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080182au, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" +#endif + }, + { /* [300] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetC2CInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080182bu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" +#endif + }, + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4620,7 +4755,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [293] */ + { /* [302] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080182du, + /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" +#endif + }, + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4635,7 +4785,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [294] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4650,7 +4800,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [295] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4665,7 +4815,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [296] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4680,7 +4830,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [297] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4695,7 +4845,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [298] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4710,7 +4860,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [299] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4725,7 +4875,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [300] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4740,7 +4890,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [301] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4755,7 +4905,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [302] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4770,7 +4920,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [303] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4785,7 +4935,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [304] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4800,7 +4950,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [305] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4815,7 +4965,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [306] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4830,7 +4980,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [307] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4845,7 +4995,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [308] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4860,7 +5010,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [309] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4875,7 +5025,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [310] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4890,7 +5040,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [311] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4905,7 +5055,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [312] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4920,7 +5070,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [313] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4935,7 +5085,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [314] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4950,7 +5100,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [315] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4965,7 +5115,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [316] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4980,7 +5130,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [317] */ + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4995,7 +5145,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [318] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5010,7 +5160,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [319] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5025,7 +5175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [320] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5040,7 +5190,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [321] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5055,7 +5205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [322] */ + { /* [332] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5070,7 +5220,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [323] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5085,7 +5235,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [324] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5100,7 +5250,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [325] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5115,7 +5265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [326] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5130,7 +5280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [327] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5145,7 +5295,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [328] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5160,7 +5310,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [329] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5175,7 +5325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [330] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5190,7 +5340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [331] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5205,7 +5355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [332] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5220,7 +5370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [333] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5235,7 +5385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [334] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5250,7 +5400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [335] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5265,7 +5415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [336] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5280,7 +5430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [337] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5295,7 +5445,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [338] */ + { /* [348] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkGetAliEnabled_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080301au, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" +#endif + }, + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5310,7 +5475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [339] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5325,7 +5490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [340] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5340,7 +5505,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [341] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5355,7 +5520,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [342] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5370,7 +5535,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [343] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5385,7 +5550,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [344] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5400,7 +5565,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [345] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5415,7 +5580,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [346] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5430,7 +5595,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [347] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5445,7 +5610,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [348] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5460,7 +5625,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [349] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5475,7 +5640,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [350] */ + { /* [361] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPreLinkTrainAli_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803027u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" +#endif + }, + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5490,7 +5670,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [351] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5505,7 +5685,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [352] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5520,7 +5700,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [353] */ + { /* [365] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkLinkTrainAli_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080302bu, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" +#endif + }, + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5535,7 +5730,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [354] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5550,7 +5745,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [355] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5565,7 +5760,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [356] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5580,7 +5775,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [357] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5595,7 +5790,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [358] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5610,7 +5805,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [359] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5625,7 +5820,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [360] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5640,7 +5835,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [361] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5655,7 +5850,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [362] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5670,7 +5865,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [363] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5685,7 +5880,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [364] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5700,7 +5895,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [365] */ + { /* [378] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5715,7 +5910,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [366] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5730,7 +5925,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [367] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5745,7 +5940,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [368] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5760,112 +5955,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [369] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetDmemUsage_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803101u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" -#endif - }, - { /* [370] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationMap_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803112u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationMap" -#endif - }, - { /* [371] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationUnmap_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803113u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationUnmap" -#endif - }, - { /* [372] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803114u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationGetInfo" -#endif - }, - { /* [373] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationGetControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803115u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationGetControl" -#endif - }, - { /* [374] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [382] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationSetControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkEomControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20803116u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS), + /*methodId=*/ 0x2080303cu, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationSetControl" + /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [375] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnInstrumentationRecalibrate_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetDmemUsage_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20803117u, - /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS), + /*methodId=*/ 0x20803101u, + /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationRecalibrate" + /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [376] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5880,7 +6000,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [377] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5895,7 +6015,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [378] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5910,7 +6030,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [379] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5925,7 +6045,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [380] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5940,7 +6060,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [381] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5955,7 +6075,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [382] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5970,7 +6090,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [383] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5985,7 +6105,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [384] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6000,7 +6120,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [385] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6015,7 +6135,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [386] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6030,7 +6150,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [387] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6045,7 +6165,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [388] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6060,7 +6180,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [389] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6075,7 +6195,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [390] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6090,7 +6210,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [391] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6105,7 +6225,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [392] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6120,7 +6240,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [393] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6135,7 +6255,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [394] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6150,7 +6270,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [395] */ + { /* [403] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6170,7 +6290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 396, + /*numEntries=*/ 404, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -6378,6 +6498,22 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetEomStatus__ = &subdeviceCtrlCmdBusGetEomStatus_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + pThis->__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__ = &subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdBusGetC2CInfo__ = &subdeviceCtrlCmdBusGetC2CInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdBusGetC2CErrorInfo__ = &subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif @@ -6426,6 +6562,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkCoreCallback__ = &subdeviceCtrlCmdNvlinkCoreCallback_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdNvlinkGetAliEnabled__ = &subdeviceCtrlCmdNvlinkGetAliEnabled_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdNvlinkSetLoopbackMode__ = &subdeviceCtrlCmdNvlinkSetLoopbackMode_IMPL; #endif @@ -6474,6 +6614,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkEnableLinksPostTopology__ = &subdeviceCtrlCmdNvlinkEnableLinksPostTopology_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdNvlinkPreLinkTrainAli__ = &subdeviceCtrlCmdNvlinkPreLinkTrainAli_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdNvlinkGetRefreshCounters__ = &subdeviceCtrlCmdNvlinkGetRefreshCounters_IMPL; #endif @@ -6486,6 +6630,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet__ = &subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdNvlinkLinkTrainAli__ = &subdeviceCtrlCmdNvlinkLinkTrainAli_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo__ = &subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo_IMPL; #endif @@ -6550,6 +6698,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__ = &subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdNvlinkEomControl__ = &subdeviceCtrlCmdNvlinkEomControl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadBuffer__ = &subdeviceCtrlCmdI2cReadBuffer_IMPL; #endif @@ -6558,11 +6710,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdI2cWriteBuffer__ = &subdeviceCtrlCmdI2cWriteBuffer_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadReg__ = &subdeviceCtrlCmdI2cReadReg_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x230u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cWriteReg__ = &subdeviceCtrlCmdI2cWriteReg_IMPL; #endif @@ -6790,7 +6942,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoGetUserdLocation__ = &subdeviceCtrlCmdFifoGetUserdLocation_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) pThis->__subdeviceCtrlCmdFifoGetDeviceInfoTable__ = &subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL; #endif @@ -6974,6 +7126,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetZcullMask__ = &subdeviceCtrlCmdKGrGetZcullMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo__ = &subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL; #endif @@ -7230,10 +7386,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetPidInfo__ = &subdeviceCtrlCmdGpuGetPidInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - pThis->__subdeviceCtrlCmdGpuInterruptFunction__ = &subdeviceCtrlCmdGpuInterruptFunction_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuQueryFunctionStatus__ = &subdeviceCtrlCmdGpuQueryFunctionStatus_IMPL; #endif @@ -7241,6 +7393,15 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdGpuReportNonReplayableFault__ = &subdeviceCtrlCmdGpuReportNonReplayableFault_IMPL; #endif +} + +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__subdeviceCtrlCmdGpuGetEngineFaultInfo__ = &subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL; @@ -7273,15 +7434,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) pThis->__subdeviceCtrlCmdGpuGetEngineLoadTimes__ = &subdeviceCtrlCmdGpuGetEngineLoadTimes_IMPL; #endif -} - -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdEventSetTrigger__ = &subdeviceCtrlCmdEventSetTrigger_IMPL; @@ -7427,30 +7579,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlcnGetDmemUsage__ = &subdeviceCtrlCmdFlcnGetDmemUsage_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationMap__ = &subdeviceCtrlCmdFlcnInstrumentationMap_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationUnmap__ = &subdeviceCtrlCmdFlcnInstrumentationUnmap_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationGetInfo__ = &subdeviceCtrlCmdFlcnInstrumentationGetInfo_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationGetControl__ = &subdeviceCtrlCmdFlcnInstrumentationGetControl_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationSetControl__ = &subdeviceCtrlCmdFlcnInstrumentationSetControl_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdFlcnInstrumentationRecalibrate__ = &subdeviceCtrlCmdFlcnInstrumentationRecalibrate_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdFlcnGetEngineArch__ = &subdeviceCtrlCmdFlcnGetEngineArch_IMPL; #endif @@ -7539,6 +7667,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetPartitions__ = &subdeviceCtrlCmdGpuGetPartitions_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGpuGetComputeProfiles__ = &subdeviceCtrlCmdGpuGetComputeProfiles_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) pThis->__subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles__ = &subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles_IMPL; #endif @@ -7551,6 +7683,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges__ = &subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + pThis->__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__ = &subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) pThis->__subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance__ = &subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_IMPL; #endif @@ -7811,6 +7947,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__ = &subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalGetPcieP2pCaps__ = &subdeviceCtrlCmdInternalGetPcieP2pCaps_IMPL; #endif @@ -7823,6 +7967,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGetAvailableHshubMask__ = &subdeviceCtrlCmdGetAvailableHshubMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdCcuMap__ = &subdeviceCtrlCmdCcuMap_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdCcuUnmap__ = &subdeviceCtrlCmdCcuUnmap_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resPreDestruct__ = &__nvoc_thunk_Subdevice_resPreDestruct; pThis->__nvoc_base_GpuResource.__gpuresInternalControlForward__ = &__nvoc_thunk_Subdevice_gpuresInternalControlForward; diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 9e2990df0..3192cccf9 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -171,6 +171,10 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdBusSetEomParameters__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetUphyDlnCfgSpace__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetEomStatus__)(struct Subdevice *, NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetC2CInfo__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetC2CErrorInfo__)(struct Subdevice *, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusSysmemAccess__)(struct Subdevice *, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkCaps__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkStatus__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *); @@ -183,6 +187,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkGetLpCounters__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableNvlinkPeer__)(struct Subdevice *, NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkCoreCallback__)(struct Subdevice *, NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkGetAliEnabled__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkSetLoopbackMode__)(struct Subdevice *, NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid__)(struct Subdevice *, NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkUpdateHshubMux__)(struct Subdevice *, NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS *); @@ -195,9 +200,11 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkUpdatePeerLinkMask__)(struct Subdevice *, NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkUpdateLinkConnection__)(struct Subdevice *, NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableLinksPostTopology__)(struct Subdevice *, NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkPreLinkTrainAli__)(struct Subdevice *, NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetRefreshCounters__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkClearRefreshCounters__)(struct Subdevice *, NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkLinkTrainAli__)(struct Subdevice *, NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkProgramLinkSpeed__)(struct Subdevice *, NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS *); @@ -214,6 +221,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo__)(struct Subdevice *, NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableLinks__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__)(struct Subdevice *, NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkEomControl__)(struct Subdevice *, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadReg__)(struct Subdevice *, NV2080_CTRL_I2C_RW_REG_PARAMS *); @@ -320,6 +328,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdKGrGetNumTpcsForGpc__)(struct Subdevice *, NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetGpcTileMap__)(struct Subdevice *, NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetZcullMask__)(struct Subdevice *, NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrInternalStaticGetInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrInternalStaticGetCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *); @@ -384,7 +393,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetVprInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPids__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PIDS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPidInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PID_INFO_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdGpuInterruptFunction__)(struct Subdevice *, NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryFunctionStatus__)(struct Subdevice *, NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuReportNonReplayableFault__)(struct Subdevice *, NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineFaultInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS *); @@ -431,12 +439,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdCeGetCePceMask__)(struct Subdevice *, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeUpdatePceLceMappings__)(struct Subdevice *, NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetDmemUsage__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationMap__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationUnmap__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationGetInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationGetControl__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationSetControl__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFlcnInstrumentationRecalibrate__)(struct Subdevice *, NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetEngineArch__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerQueueInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerControlGet__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS *); @@ -459,9 +461,11 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGrmgrGetGrFsInfo__)(struct Subdevice *, NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetPartitions__)(struct Subdevice *, NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPartitions__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetComputeProfiles__)(struct Subdevice *, NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *); @@ -527,9 +531,13 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdHshubNextHshubId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetPcieP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetAvailableHshubMask__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *); NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); @@ -652,6 +660,10 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBusSetEomParameters(pSubdevice, pParams) subdeviceCtrlCmdBusSetEomParameters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetUphyDlnCfgSpace(pSubdevice, pParams) subdeviceCtrlCmdBusGetUphyDlnCfgSpace_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetEomStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetEomStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetC2CErrorInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSysmemAccess(pSubdevice, pParams) subdeviceCtrlCmdBusSysmemAccess_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetNvlinkCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetNvlinkStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkStatus_DISPATCH(pSubdevice, pParams) @@ -664,6 +676,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkGetLpCounters(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetLpCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEnableNvlinkPeer(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEnableNvlinkPeer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkCoreCallback(pSubdevice, pParams) subdeviceCtrlCmdNvlinkCoreCallback_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkGetAliEnabled(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetAliEnabled_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkSetLoopbackMode(pSubdevice, pParams) subdeviceCtrlCmdNvlinkSetLoopbackMode_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid(pSubdevice, pParams) subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkUpdateHshubMux(pSubdevice, pParams) subdeviceCtrlCmdNvlinkUpdateHshubMux_DISPATCH(pSubdevice, pParams) @@ -676,9 +689,11 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkUpdatePeerLinkMask(pSubdevice, pParams) subdeviceCtrlCmdNvlinkUpdatePeerLinkMask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkUpdateLinkConnection(pSubdevice, pParams) subdeviceCtrlCmdNvlinkUpdateLinkConnection_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEnableLinksPostTopology(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEnableLinksPostTopology_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkPreLinkTrainAli(pSubdevice, pParams) subdeviceCtrlCmdNvlinkPreLinkTrainAli_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetRefreshCounters(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetRefreshCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkClearRefreshCounters(pSubdevice, pParams) subdeviceCtrlCmdNvlinkClearRefreshCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkLinkTrainAli(pSubdevice, pParams) subdeviceCtrlCmdNvlinkLinkTrainAli_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkProgramLinkSpeed(pSubdevice, pParams) subdeviceCtrlCmdNvlinkProgramLinkSpeed_DISPATCH(pSubdevice, pParams) @@ -695,6 +710,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo(pSubdevice, pParams) subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEnableLinks(pSubdevice) subdeviceCtrlCmdNvlinkEnableLinks_DISPATCH(pSubdevice) #define subdeviceCtrlCmdNvlinkProcessInitDisabledLinks(pSubdevice, pParams) subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkEomControl(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEomControl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdI2cReadBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cReadReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadReg_DISPATCH(pSubdevice, pI2cParams) @@ -801,6 +817,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdKGrGetNumTpcsForGpc(pSubdevice, pParams) subdeviceCtrlCmdKGrGetNumTpcsForGpc_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetGpcTileMap(pSubdevice, pParams) subdeviceCtrlCmdKGrGetGpcTileMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetZcullMask(pSubdevice, pParams) subdeviceCtrlCmdKGrGetZcullMask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo(pSubdevice, pParams) subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrInternalStaticGetInfo(pSubdevice, pParams) subdeviceCtrlCmdKGrInternalStaticGetInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrInternalStaticGetCaps(pSubdevice, pParams) subdeviceCtrlCmdKGrInternalStaticGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder(pSubdevice, pParams) subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder_DISPATCH(pSubdevice, pParams) @@ -865,7 +882,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetVprInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetVprInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPids(pSubdevice, pGetPidsParams) subdeviceCtrlCmdGpuGetPids_DISPATCH(pSubdevice, pGetPidsParams) #define subdeviceCtrlCmdGpuGetPidInfo(pSubdevice, pGetPidInfoParams) subdeviceCtrlCmdGpuGetPidInfo_DISPATCH(pSubdevice, pGetPidInfoParams) -#define subdeviceCtrlCmdGpuInterruptFunction(pSubdevice, pParams) subdeviceCtrlCmdGpuInterruptFunction_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuQueryFunctionStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryFunctionStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuReportNonReplayableFault(pSubdevice, pParams) subdeviceCtrlCmdGpuReportNonReplayableFault_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetEngineFaultInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineFaultInfo_DISPATCH(pSubdevice, pParams) @@ -912,12 +928,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdCeGetCePceMask(pSubdevice, pCePceMaskParams) subdeviceCtrlCmdCeGetCePceMask_DISPATCH(pSubdevice, pCePceMaskParams) #define subdeviceCtrlCmdCeUpdatePceLceMappings(pSubdevice, pCeUpdatePceLceMappingsParams) subdeviceCtrlCmdCeUpdatePceLceMappings_DISPATCH(pSubdevice, pCeUpdatePceLceMappingsParams) #define subdeviceCtrlCmdFlcnGetDmemUsage(pSubdevice, pFlcnDmemUsageParams) subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(pSubdevice, pFlcnDmemUsageParams) -#define subdeviceCtrlCmdFlcnInstrumentationMap(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationMap_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFlcnInstrumentationUnmap(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationUnmap_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFlcnInstrumentationGetInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationGetInfo_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFlcnInstrumentationGetControl(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationGetControl_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFlcnInstrumentationSetControl(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationSetControl_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFlcnInstrumentationRecalibrate(pSubdevice, pParams) subdeviceCtrlCmdFlcnInstrumentationRecalibrate_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnGetEngineArch(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetEngineArch_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnUstreamerQueueInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerQueueInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnUstreamerControlGet(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerControlGet_DISPATCH(pSubdevice, pParams) @@ -940,9 +950,11 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGrmgrGetGrFsInfo(pSubdevice, pParams) subdeviceCtrlCmdGrmgrGetGrFsInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetPartitions(pSubdevice, pParams) subdeviceCtrlCmdGpuSetPartitions_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPartitions(pSubdevice, pParams) subdeviceCtrlCmdGpuGetPartitions_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetComputeProfiles(pSubdevice, pParams) subdeviceCtrlCmdGpuGetComputeProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixGc6BlockerRefCnt(pSubdevice, pParams) subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(pSubdevice, pParams) @@ -1008,9 +1020,13 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdHshubNextHshubId(pSubdevice, pParams) subdeviceCtrlCmdHshubNextHshubId_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr(pSubdevice) subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetPcieP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetCoherentFbApertureSize(pSubdevice, pParams) subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetAvailableHshubMask(pSubdevice, pParams) subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdCcuUnmap(pSubdevice) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice) #define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) #define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -1301,6 +1317,30 @@ static inline NV_STATUS subdeviceCtrlCmdBusGetEomStatus_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdBusGetEomStatus__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdBusGetC2CInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetC2CInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetC2CErrorInfo__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdBusSysmemAccess_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdBusSysmemAccess_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *pParams) { @@ -1373,6 +1413,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkCoreCallback_DISPATCH(struct Subde return pSubdevice->__subdeviceCtrlCmdNvlinkCoreCallback__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkGetAliEnabled_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkGetAliEnabled_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkGetAliEnabled__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkSetLoopbackMode_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkSetLoopbackMode_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS *pParams) { @@ -1445,6 +1491,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkEnableLinksPostTopology_DISPATCH(s return pSubdevice->__subdeviceCtrlCmdNvlinkEnableLinksPostTopology__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkPreLinkTrainAli_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkPreLinkTrainAli_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkPreLinkTrainAli__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkGetRefreshCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkGetRefreshCounters_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS *pParams) { @@ -1463,6 +1515,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_DISPATCH(stru return pSubdevice->__subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkLinkTrainAli_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkLinkTrainAli_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkLinkTrainAli__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS *pParams) { @@ -1559,6 +1617,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH( return pSubdevice->__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkEomControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkEomControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkEomControl__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); static inline NV_STATUS subdeviceCtrlCmdI2cReadBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams) { @@ -2201,6 +2265,12 @@ static inline NV_STATUS subdeviceCtrlCmdKGrGetZcullMask_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdKGrGetZcullMask__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdKGrInternalStaticGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *pParams) { @@ -2585,12 +2655,6 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetPidInfo_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdGpuGetPidInfo__(pSubdevice, pGetPidInfoParams); } -NV_STATUS subdeviceCtrlCmdGpuInterruptFunction_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdGpuInterruptFunction_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdGpuInterruptFunction__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdGpuQueryFunctionStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuQueryFunctionStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS *pParams) { @@ -2867,42 +2931,6 @@ static inline NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(struct Subdevi return pSubdevice->__subdeviceCtrlCmdFlcnGetDmemUsage__(pSubdevice, pFlcnDmemUsageParams); } -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationMap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationMap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationMap__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationUnmap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationUnmap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationUnmap__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationGetInfo__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationGetControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationGetControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationGetControl__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationSetControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationSetControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationSetControl__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdFlcnInstrumentationRecalibrate_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdFlcnInstrumentationRecalibrate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdFlcnInstrumentationRecalibrate__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdFlcnGetEngineArch_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdFlcnGetEngineArch_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *pParams) { @@ -3035,6 +3063,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetPartitions_DISPATCH(struct Subdevi return pSubdevice->__subdeviceCtrlCmdGpuGetPartitions__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetComputeProfiles_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetComputeProfiles_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetComputeProfiles__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS *pParams) { @@ -3053,6 +3087,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPage return pSubdevice->__subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *pParams) { @@ -3443,6 +3483,18 @@ static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_D return pSubdevice->__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalGetPcieP2pCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *pParams) { @@ -3461,6 +3513,18 @@ static inline NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdGetAvailableHshubMask__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdCcuMap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdCcuMap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdCcuMap__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdCcuUnmap_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdCcuUnmap_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdCcuUnmap__(pSubdevice); +} + static inline NvBool subdeviceShareCallback_DISPATCH(struct Subdevice *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__subdeviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index 01bdecb06..1f9a36670 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -70,9 +70,6 @@ extern "C" { #define IsMobile(p) 0 -#define RM_ASSERT_BEHAVIOR_BUGCHECK_RELEASE (0x41) -#define RM_ASSERT_BEHAVIOR_BUGCHECK_DEVELOP (0x42) - // // OS defines (Windows flavor can be added later on) // Unix flavor need to be sync with defines in file "nv.h" @@ -385,7 +382,6 @@ struct OBJSYS { NvBool PDB_PROP_SYS_DEBUGGER_DISABLED; NvBool PDB_PROP_SYS_PRIORITY_BOOST; NvU32 PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US; - NvBool PDB_PROP_SYS_BSOD_ON_ASSERT; NvBool PDB_PROP_SYS_BUGCHECK_ON_TIMEOUT; NvU32 apiLockMask; NvU32 apiLockModuleMask; @@ -458,8 +454,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS; #define PDB_PROP_SYS_NVIF_INIT_DONE_BASE_NAME PDB_PROP_SYS_NVIF_INIT_DONE #define PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT_BASE_CAST #define PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT_BASE_NAME PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT -#define PDB_PROP_SYS_BSOD_ON_ASSERT_BASE_CAST -#define PDB_PROP_SYS_BSOD_ON_ASSERT_BASE_NAME PDB_PROP_SYS_BSOD_ON_ASSERT #define PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS_BASE_CAST #define PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS_BASE_NAME PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS #define PDB_PROP_SYS_PRIMARY_VBIOS_STATE_SAVED_BASE_CAST diff --git a/src/nvidia/generated/g_traceable_nvoc.c b/src/nvidia/generated/g_traceable_nvoc.c index f00b9ffb1..5d4d94ae6 100644 --- a/src/nvidia/generated/g_traceable_nvoc.c +++ b/src/nvidia/generated/g_traceable_nvoc.c @@ -33,6 +33,7 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_OBJTRACEABLE = { }, }; +// Not instantiable because it's not derived from class "Object" const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index 1692c5871..c97a6d4c9 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -225,6 +225,19 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + // Hal function -- usrmodeConstructHal + if (0) + { + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + { + pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GH100; + } + pThis->__usrmodeCanCopy__ = &usrmodeCanCopy_IMPL; pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_UserModeApi_resCanCopy; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index cda3262e4..c63b107ba 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -39,6 +39,11 @@ extern "C" { #include "gpu/gpu.h" #include "nvoc/utility.h" +/*! + * RM internal class representing USERMODE_A classes. We inherit Memory here instead of GpuResource + * because GpuResource can only map regmem, whereas for HOPPER+, we will need to map sysmem with an + * effective address space of fbmem if the user requests the GMMU/BAR1 mapping for the VF pages. + */ #ifdef NVOC_USERMODE_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -53,6 +58,7 @@ struct UserModeApi { struct RmResource *__nvoc_pbase_RmResource; struct Memory *__nvoc_pbase_Memory; struct UserModeApi *__nvoc_pbase_UserModeApi; + NV_STATUS (*__usrmodeConstructHal__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NvBool (*__usrmodeCanCopy__)(struct UserModeApi *); NV_STATUS (*__usrmodeCheckMemInterUnmap__)(struct UserModeApi *, NvBool); NV_STATUS (*__usrmodeControl__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -104,6 +110,8 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define __objCreate_UserModeApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_UserModeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) +#define usrmodeConstructHal(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) +#define usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) #define usrmodeCanCopy(pUserModeApi) usrmodeCanCopy_DISPATCH(pUserModeApi) #define usrmodeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) usrmodeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define usrmodeControl(pMemory, pCallContext, pParams) usrmodeControl_DISPATCH(pMemory, pCallContext, pParams) @@ -125,18 +133,17 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeMap(pMemory, pCallContext, pParams, pCpuMapping) usrmodeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define usrmodeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) usrmodeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); - -#ifdef __nvoc_usermode_api_h_disabled -static inline NV_STATUS usrmodeConstructHal(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - NV_ASSERT_FAILED_PRECOMP("UserModeApi was disabled!"); +static inline NV_STATUS usrmodeConstructHal_46f6a7(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_usermode_api_h_disabled -#define usrmodeConstructHal(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_GV100(pUserModeApi, pCallContext, pParams) -#endif //__nvoc_usermode_api_h_disabled -#define usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams) usrmodeConstructHal(pUserModeApi, pCallContext, pParams) +NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +NV_STATUS usrmodeConstructHal_GH100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS usrmodeConstructHal_DISPATCH(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pUserModeApi->__usrmodeConstructHal__(pUserModeApi, pCallContext, pParams); +} NvBool usrmodeCanCopy_IMPL(struct UserModeApi *pUserModeApi); diff --git a/src/nvidia/generated/g_vaspace_nvoc.c b/src/nvidia/generated/g_vaspace_nvoc.c index 2c4bed253..a0ff813f9 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.c +++ b/src/nvidia/generated/g_vaspace_nvoc.c @@ -42,6 +42,12 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_OBJVASPACE = { }, }; +// Not instantiable because it's an abstract class with following pure virtual functions: +// vaspaceConstruct_ +// vaspaceAlloc +// vaspaceFree +// vaspaceApplyDefaultAlignment +// vaspaceGetVasInfo const struct NVOC_CLASS_DEF __nvoc_class_def_OBJVASPACE = { /*classInfo=*/ { diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c index f54c9890f..bed57b17e 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c @@ -172,7 +172,7 @@ void __nvoc_init_dataField_VirtMemAllocator(VirtMemAllocator *pThis, RmHalspecOw PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_DMA_ENFORCE_32BIT_POINTER - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_DMA_ENFORCE_32BIT_POINTER, ((NvBool)(0 == 0))); } @@ -193,7 +193,7 @@ void __nvoc_init_dataField_VirtMemAllocator(VirtMemAllocator *pThis, RmHalspecOw } // NVOC Property Hal field -- PDB_PROP_DMA_IS_SUPPORTED_SPARSE_VIRTUAL - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_DMA_IS_SUPPORTED_SPARSE_VIRTUAL, ((NvBool)(0 == 0))); } @@ -254,8 +254,30 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm pThis->__dmaStateInitLocked__ = &dmaStateInitLocked_IMPL; + // Hal function -- dmaAllocBar1P2PMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__dmaAllocBar1P2PMapping__ = &dmaAllocBar1P2PMapping_GH100; + } + // default + else + { + pThis->__dmaAllocBar1P2PMapping__ = &dmaAllocBar1P2PMapping_46f6a7; + } + + // Hal function -- dmaFreeBar1P2PMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + { + pThis->__dmaFreeBar1P2PMapping__ = &dmaFreeBar1P2PMapping_GH100; + } + // default + else + { + pThis->__dmaFreeBar1P2PMapping__ = &dmaFreeBar1P2PMapping_b3696a; + } + // Hal function -- dmaStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ { pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; } diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index 8770f1185..5613cc94d 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -101,6 +101,8 @@ struct VirtMemAllocator { struct VirtMemAllocator *__nvoc_pbase_VirtMemAllocator; NV_STATUS (*__dmaConstructEngine__)(struct OBJGPU *, struct VirtMemAllocator *, ENGDESCRIPTOR); NV_STATUS (*__dmaStateInitLocked__)(struct OBJGPU *, struct VirtMemAllocator *); + NV_STATUS (*__dmaAllocBar1P2PMapping__)(struct OBJGPU *, struct VirtMemAllocator *, DMA_BAR1P2P_MAPPING_PRARAMS *); + void (*__dmaFreeBar1P2PMapping__)(struct VirtMemAllocator *, CLI_DMA_MAPPING_INFO *); NV_STATUS (*__dmaStatePostLoad__)(struct OBJGPU *, struct VirtMemAllocator *, NvU32); NV_STATUS (*__dmaReconcileTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); NV_STATUS (*__dmaStateLoad__)(POBJGPU, struct VirtMemAllocator *, NvU32); @@ -180,6 +182,10 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator**, Dynamic*, NvU32) #define dmaConstructEngine(pGpu, pDma, arg0) dmaConstructEngine_DISPATCH(pGpu, pDma, arg0) #define dmaStateInitLocked(pGpu, pDma) dmaStateInitLocked_DISPATCH(pGpu, pDma) +#define dmaAllocBar1P2PMapping(pGpu, pDma, params) dmaAllocBar1P2PMapping_DISPATCH(pGpu, pDma, params) +#define dmaAllocBar1P2PMapping_HAL(pGpu, pDma, params) dmaAllocBar1P2PMapping_DISPATCH(pGpu, pDma, params) +#define dmaFreeBar1P2PMapping(pDma, arg0) dmaFreeBar1P2PMapping_DISPATCH(pDma, arg0) +#define dmaFreeBar1P2PMapping_HAL(pDma, arg0) dmaFreeBar1P2PMapping_DISPATCH(pDma, arg0) #define dmaStatePostLoad(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) #define dmaStatePostLoad_HAL(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) #define dmaReconcileTunableState(pGpu, pEngstate, pTunableState) dmaReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) @@ -267,35 +273,6 @@ static inline NV_STATUS dmaFreeMapping(struct OBJGPU *pGpu, struct VirtMemAlloca #define dmaFreeMapping_HAL(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) dmaFreeMapping(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) -static inline NV_STATUS dmaAllocBar1P2PMapping_46f6a7(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, DMA_BAR1P2P_MAPPING_PRARAMS *params) { - return NV_ERR_NOT_SUPPORTED; -} - -#ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NV_STATUS dmaAllocBar1P2PMapping(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, DMA_BAR1P2P_MAPPING_PRARAMS *params) { - NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_virt_mem_allocator_h_disabled -#define dmaAllocBar1P2PMapping(pGpu, pDma, params) dmaAllocBar1P2PMapping_46f6a7(pGpu, pDma, params) -#endif //__nvoc_virt_mem_allocator_h_disabled - -#define dmaAllocBar1P2PMapping_HAL(pGpu, pDma, params) dmaAllocBar1P2PMapping(pGpu, pDma, params) - -static inline void dmaFreeBar1P2PMapping_b3696a(struct VirtMemAllocator *pDma, CLI_DMA_MAPPING_INFO *arg0) { - return; -} - -#ifdef __nvoc_virt_mem_allocator_h_disabled -static inline void dmaFreeBar1P2PMapping(struct VirtMemAllocator *pDma, CLI_DMA_MAPPING_INFO *arg0) { - NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); -} -#else //__nvoc_virt_mem_allocator_h_disabled -#define dmaFreeBar1P2PMapping(pDma, arg0) dmaFreeBar1P2PMapping_b3696a(pDma, arg0) -#endif //__nvoc_virt_mem_allocator_h_disabled - -#define dmaFreeBar1P2PMapping_HAL(pDma, arg0) dmaFreeBar1P2PMapping(pDma, arg0) - NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse); #ifdef __nvoc_virt_mem_allocator_h_disabled @@ -400,6 +377,26 @@ static inline NV_STATUS dmaStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct return pDma->__dmaStateInitLocked__(pGpu, pDma); } +NV_STATUS dmaAllocBar1P2PMapping_GH100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, DMA_BAR1P2P_MAPPING_PRARAMS *params); + +static inline NV_STATUS dmaAllocBar1P2PMapping_46f6a7(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, DMA_BAR1P2P_MAPPING_PRARAMS *params) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS dmaAllocBar1P2PMapping_DISPATCH(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, DMA_BAR1P2P_MAPPING_PRARAMS *params) { + return pDma->__dmaAllocBar1P2PMapping__(pGpu, pDma, params); +} + +void dmaFreeBar1P2PMapping_GH100(struct VirtMemAllocator *pDma, CLI_DMA_MAPPING_INFO *arg0); + +static inline void dmaFreeBar1P2PMapping_b3696a(struct VirtMemAllocator *pDma, CLI_DMA_MAPPING_INFO *arg0) { + return; +} + +static inline void dmaFreeBar1P2PMapping_DISPATCH(struct VirtMemAllocator *pDma, CLI_DMA_MAPPING_INFO *arg0) { + pDma->__dmaFreeBar1P2PMapping__(pDma, arg0); +} + NV_STATUS dmaStatePostLoad_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, NvU32 arg0); static inline NV_STATUS dmaStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, NvU32 arg0) { diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 9af1bc5fa..1bb27cb29 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107 +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X // #ifndef _RMCFG_H_ @@ -29,6 +29,8 @@ #define RMCFG_CHIP_TU10X 1 #define RMCFG_CHIP_GA10X 1 #define RMCFG_CHIP_GA10XF 0 +#define RMCFG_CHIP_AD10X 1 +#define RMCFG_CHIP_GH10X 1 #define RMCFG_CHIP_T12X 0 #define RMCFG_CHIP_T13X 0 #define RMCFG_CHIP_T21X 0 @@ -58,6 +60,8 @@ #define RMCFG_CHIP_GV100 0 +#define RMCFG_CHIP_GV11B 0 + #define RMCFG_CHIP_TU102 1 #define RMCFG_CHIP_TU104 1 #define RMCFG_CHIP_TU106 1 @@ -74,6 +78,14 @@ #define RMCFG_CHIP_GA102F 0 +#define RMCFG_CHIP_AD102 1 +#define RMCFG_CHIP_AD103 1 +#define RMCFG_CHIP_AD104 1 + +#define RMCFG_CHIP_GH100 1 + +#define RMCFG_CHIP_T194 0 + #define RMCFG_CHIP_T234 0 #define RMCFG_CHIP_T234D 0 @@ -107,13 +119,11 @@ #define RMCFG_CHIP_GK110C 0 #define RMCFG_CHIP_GK208 0 #define RMCFG_CHIP_GK208S 0 -#define RMCFG_CHIP_GV11B 0 #define RMCFG_CHIP_T001_FERMI_NOT_EXIST 0 #define RMCFG_CHIP_T124 0 #define RMCFG_CHIP_T132 0 #define RMCFG_CHIP_T210 0 #define RMCFG_CHIP_T186 0 -#define RMCFG_CHIP_T194 0 #define RMCFG_CHIP_T002_TURING_NOT_EXIST 0 @@ -157,6 +167,14 @@ #define RMCFG_CHIP_TEGRA_DGPU_AMPERE 0 #define RMCFG_CHIP_TEGRA_DGPU 0 #define RMCFG_CHIP_DFPGA 0 +#define RMCFG_CHIP_dADA 1 +#define RMCFG_CHIP_DADA 1 +#define RMCFG_CHIP_ADA 1 +#define RMCFG_CHIP_ADA_CLASSIC_GPUS 1 +#define RMCFG_CHIP_dHOPPER 1 +#define RMCFG_CHIP_DHOPPER 1 +#define RMCFG_CHIP_HOPPER 1 +#define RMCFG_CHIP_HOPPER_CLASSIC_GPUS 1 #define RMCFG_CHIP_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_FERMI_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_TEGRA 0 @@ -339,15 +357,18 @@ #define RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_TURING_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_AMPERE_CHANNEL_GPFIFO_A 1 +#define RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_NV04_SOFTWARE_TEST 1 #define RMCFG_CLASS_NV4_SOFTWARE_TEST 1 // aka NV04_SOFTWARE_TEST #define RMCFG_CLASS_VOLTA_USERMODE_A 1 #define RMCFG_CLASS_TURING_USERMODE_A 1 #define RMCFG_CLASS_AMPERE_USERMODE_A 1 +#define RMCFG_CLASS_HOPPER_USERMODE_A 1 #define RMCFG_CLASS_NVC371_DISP_SF_USER 1 #define RMCFG_CLASS_NVC372_DISPLAY_SW 1 #define RMCFG_CLASS_NVC573_DISP_CAPABILITIES 1 #define RMCFG_CLASS_NVC673_DISP_CAPABILITIES 1 +#define RMCFG_CLASS_NVC773_DISP_CAPABILITIES 1 #define RMCFG_CLASS_NV04_DISPLAY_COMMON 1 #define RMCFG_CLASS_NV50_DEFERRED_API_CLASS 1 #define RMCFG_CLASS_MPS_COMPUTE 1 @@ -362,6 +383,9 @@ #define RMCFG_CLASS_NVC67B_WINDOW_IMM_CHANNEL_DMA 1 #define RMCFG_CLASS_NVC67D_CORE_CHANNEL_DMA 1 #define RMCFG_CLASS_NVC67E_WINDOW_CHANNEL_DMA 1 +#define RMCFG_CLASS_NVC770_DISPLAY 1 +#define RMCFG_CLASS_NVC771_DISP_SF_USER 1 +#define RMCFG_CLASS_NVC77D_CORE_CHANNEL_DMA 1 #define RMCFG_CLASS_NV9010_VBLANK_CALLBACK 1 #define RMCFG_CLASS_GF100_PROFILER 1 // Profiler Client Support #define RMCFG_CLASS_MAXWELL_PROFILER 1 // Base Profiler Class @@ -377,15 +401,22 @@ #define RMCFG_CLASS_FERMI_TWOD_A 1 // FERMI Graphics 2D #define RMCFG_CLASS_FERMI_VASPACE_A 1 // FERMI virtual address space #define RMCFG_CLASS_GF100_HDACODEC 1 +#define RMCFG_CLASS_NVB8B0_VIDEO_DECODER 1 // Decoder Class for Hopper #define RMCFG_CLASS_NVC4B0_VIDEO_DECODER 1 // Decoder Class for Turing #define RMCFG_CLASS_NVC6B0_VIDEO_DECODER 1 // Decoder Class for Ampere #define RMCFG_CLASS_NVC7B0_VIDEO_DECODER 1 // Decoder Class for Ampere +#define RMCFG_CLASS_NVC9B0_VIDEO_DECODER 1 // Decoder Class for Ada #define RMCFG_CLASS_NVC4B7_VIDEO_ENCODER 1 #define RMCFG_CLASS_NVB4B7_VIDEO_ENCODER 1 #define RMCFG_CLASS_NVC7B7_VIDEO_ENCODER 1 +#define RMCFG_CLASS_NVC9B7_VIDEO_ENCODER 1 +#define RMCFG_CLASS_NVB8D1_VIDEO_NVJPG 1 #define RMCFG_CLASS_NVC4D1_VIDEO_NVJPG 1 +#define RMCFG_CLASS_NVC9D1_VIDEO_NVJPG 1 +#define RMCFG_CLASS_NVB8FA_VIDEO_OFA 1 #define RMCFG_CLASS_NVC6FA_VIDEO_OFA 1 #define RMCFG_CLASS_NVC7FA_VIDEO_OFA 1 +#define RMCFG_CLASS_NVC9FA_VIDEO_OFA 1 #define RMCFG_CLASS_KEPLER_INLINE_TO_MEMORY_B 1 // Kepler inline to memory #define RMCFG_CLASS_FERMI_CONTEXT_SHARE_A 1 // Context Share class #define RMCFG_CLASS_KEPLER_CHANNEL_GROUP_A 1 // Channel Group Class @@ -393,6 +424,7 @@ #define RMCFG_CLASS_TURING_DMA_COPY_A 1 #define RMCFG_CLASS_AMPERE_DMA_COPY_A 1 #define RMCFG_CLASS_AMPERE_DMA_COPY_B 1 +#define RMCFG_CLASS_HOPPER_DMA_COPY_A 1 #define RMCFG_CLASS_MAXWELL_DMA_COPY_A 1 #define RMCFG_CLASS_ACCESS_COUNTER_NOTIFY_BUFFER 1 // Access Cntr Buffer for Gr #define RMCFG_CLASS_MMU_FAULT_BUFFER 1 // Volta Fault Buffer for Gr @@ -402,11 +434,15 @@ #define RMCFG_CLASS_AMPERE_COMPUTE_A 1 // AmpereComputeA (Graphics Compute) #define RMCFG_CLASS_AMPERE_B 1 // AmpereB (Graphics) #define RMCFG_CLASS_AMPERE_COMPUTE_B 1 // AmpereComputeB (Graphics Compute) +#define RMCFG_CLASS_ADA_A 1 // AdaA (Graphics) +#define RMCFG_CLASS_ADA_COMPUTE_A 1 // AdaComputeA (Graphics Compute) #define RMCFG_CLASS_AMPERE_SMC_PARTITION_REF 1 // Ampere SMC Partition Subscription #define RMCFG_CLASS_AMPERE_SMC_EXEC_PARTITION_REF 1 // Ampere SMC Execution Partition Subscription #define RMCFG_CLASS_AMPERE_SMC_CONFIG_SESSION 1 // Ampere SMC config session subscription #define RMCFG_CLASS_NV0092_RG_LINE_CALLBACK 1 // RG line callback functions #define RMCFG_CLASS_AMPERE_SMC_MONITOR_SESSION 1 // Ampere SMC monitor session subscription +#define RMCFG_CLASS_HOPPER_A 1 // HopperA (Graphics) +#define RMCFG_CLASS_HOPPER_COMPUTE_A 1 // HopperComputeA (Graphics Compute) #define RMCFG_CLASS_NV40_DEBUG_BUFFER 1 #define RMCFG_CLASS_GT200_DEBUGGER 1 // CUDA Debugger support #define RMCFG_CLASS_NV40_I2C 1 // I2C operations @@ -414,6 +450,7 @@ #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD +#define RMCFG_CLASS_NV_COUNTER_COLLECTION_UNIT 1 // Counter Collection Unit Class @@ -504,7 +541,7 @@ #define RMCFG_MODULE_ISOHUB 0 // Display's memory read interface #define RMCFG_MODULE_BSP 0 // Bit Stream Processor/NVDEC #define RMCFG_MODULE_NVDEC 0 // aka BSP -#define RMCFG_MODULE_KERNEL_NVDEC 1 // NVDEC on Kernel(CPU) RM. Used for booting Falcon cores. +#define RMCFG_MODULE_KERNEL_NVDEC 1 #define RMCFG_MODULE_CIPHER 0 #define RMCFG_MODULE_CE 0 // Copy Engine #define RMCFG_MODULE_KERNEL_CE 1 // Kernel Copy Engine @@ -582,6 +619,7 @@ #define RMCFG_MODULE_KERNEL_NVLINK 1 // Nvlink on Kernel(CPU) RM #define RMCFG_MODULE_IOCTRL 0 // NVLINK Ioctrl #define RMCFG_MODULE_HSHUB 0 // High Speed Hub +#define RMCFG_MODULE_HSHUBMANAGER 0 // High Speed Hub Manager #define RMCFG_MODULE_KERNEL_HSHUB 1 // High Speed Hub on Kernel(CPU) RM #define RMCFG_MODULE_KERNEL_HSHUB 1 // High Speed Hub on Kernel(CPU) RM #define RMCFG_MODULE_GPUMON 1 // GPU Monitoring @@ -592,6 +630,7 @@ #define RMCFG_MODULE_RPCSTRUCTURECOPY 0 // RPC structure copying for VGPU #define RMCFG_MODULE_NVJPG 0 // Video JPEG (NVJPG) Engine #define RMCFG_MODULE_KERNEL_NVJPG 1 +#define RMCFG_MODULE_KERNEL_FSP 1 // FSP on Kernel(CPU) RM #define RMCFG_MODULE_GSP 0 // GPU system processor #define RMCFG_MODULE_KERNEL_GSP 1 // GSP on Kernel(CPU) RM. Used for booting RM on GSP. #define RMCFG_MODULE_OFA 0 // Optical Flow Accelarator @@ -605,6 +644,7 @@ #define RMCFG_MODULE_DISPMACRO 0 // DispMacro RM infrastructure for IED removal from VBIOS #define RMCFG_MODULE_DISP_MGR 0 // Lid- and dock-related disp code for NOTEBOOK #define RMCFG_MODULE_PLATFORM 1 // Object for platform related features +#define RMCFG_MODULE_KERNEL_CCU 1 // Counter Collection Unit Kernel(CPU) RM diff --git a/src/nvidia/inc/kernel/core/prelude.h b/src/nvidia/inc/kernel/core/prelude.h index d6bdbe88a..38b30a236 100644 --- a/src/nvidia/inc/kernel/core/prelude.h +++ b/src/nvidia/inc/kernel/core/prelude.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,7 +40,6 @@ /* ------------------------ RM library and utils ---------------------------- */ #include "nvport/nvport.h" #include "nvoc/runtime.h" -#include "nvoc/utility.h" #include "core/printf.h" #include "core/strict.h" #include "utils/nvassert.h" diff --git a/src/nvidia/inc/kernel/core/printf.h b/src/nvidia/inc/kernel/core/printf.h index 28d3a388e..d4db22684 100644 --- a/src/nvidia/inc/kernel/core/printf.h +++ b/src/nvidia/inc/kernel/core/printf.h @@ -302,59 +302,6 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length); #endif -//******************************************************************************** -// -// NVRM_TRACE support -// low-overhead runtime state capture -// to enable, define USE_NVRM_TRACE (retail or debug builds) -// -//******************************************************************************** - -#ifdef USE_NVRM_TRACE - -NvU32 NVRM_TRACE_INIT(void); -NvU32 NVRM_TRACE_DISABLE(void); -void NVRM_TRACE_ENABLE(void); -void NVRM_TRACE_DUMP(void); -void NVRM_TRACE(NvU32); -void NVRM_TRACEV(NvU32 *,NvU32); -void NVRM_TRACE1(NvU32); -void NVRM_TRACE2(NvU32, NvU32); -void NVRM_TRACE3(NvU32, NvU32, NvU32); -void NVRM_TRACE4(NvU32, NvU32, NvU32, NvU32); -void NVRM_TRACE5(NvU32, NvU32, NvU32, NvU32, NvU32); - -// versions of reg read/write that log to trace buffer -//NvU32 NVRM_TRACE_REG_RD32(OBJGPU *, NvU32); -//void NVRM_TRACE_REG_WR32(OBJGPU *, NvU32, NvU32); - -// fifolog format looks like: -// 31:28 = unique file number -// 27:4 = file line number -// 1:0 = fifo state bits (bit1 = puller, bit0 = reassign) -#define FIFOLOG(fn,fa,fb) NVRM_TRACE2('FIFO', ((fn << 28) | (__LINE__ << 4) | \ - ((fa & 0x1) ? 1 : 0) << 1 | \ - ((fb & 0x1) ? 1 : 0)) ) - -#else // ! USE_NVRM_TRACE - -#define NVRM_TRACE_INIT() -#define NVRM_TRACE_DISABLE() 0 -#define NVRM_TRACE_ENABLE() -#define NVRM_TRACE_DUMP() -#define NVRM_TRACE(c0) -#define NVRM_TRACE1(c0) -#define NVRM_TRACE2(c0, c1) -#define NVRM_TRACE3(c0, c1, c2) -#define NVRM_TRACE4(c0, c1, c2, c3) -#define NVRM_TRACE5(c0, c1, c2, c3, c4) -#define FIFOLOG(a,b,c) - -#endif // ! USE_NVRM_TRACE - -#define NVRM_TRACE_ERROR(code, status) NVRM_TRACE3('EEEE', (code), (status)) -#define NVRM_TRACE_API(code, p0, p1, p2) NVRM_TRACE5('API ', (code), (p0), (p1), (p2)) - void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist); void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...); diff --git a/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h b/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h new file mode 100644 index 000000000..ff7d3ad43 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h @@ -0,0 +1,3 @@ + +#include "g_kernel_ccu_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h b/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h new file mode 100644 index 000000000..66c6abb84 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h @@ -0,0 +1,3 @@ + +#include "g_kernel_ccu_api_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h index 0136475a1..354641061 100644 --- a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h +++ b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h @@ -24,52 +24,6 @@ #ifndef KERNEL_CE_GV100_PRIVATE_H #define KERNEL_CE_GV100_PRIVATE_H -#define MAX_CE_CNT 15 - -/* - * sysmemLinks - * Represents the number of sysmem links detected - * This affects how many PCEs LCE0(sysmem read CE) - * and LCE1(sysmem write CE) should be mapped to - * maxLinksPerPeer - * Represents the maximum number of peer links - * between this GPU and all its peers. This affects - * how many PCEs LCE3(P2P CE) should be mapped to - * numPeers - * Represents the number of Peer GPUs discovered so far - * bSymmetric - * Represents whether the topology detected so far - * is symmetric i.e. has same number of links to all - * peers connected through nvlink. This affects how - * many PCEs to assign to LCEs3-5 (nvlink P2P CEs) - * bSwitchConfig - * Represents whether the config listed is intended - * for use with nvswitch systems - * pceLceMap - * Value of NV_CE_PCE2LCE_CONFIG0 register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * grceConfig - * Value of NV_CE_GRCE_CONFIG register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * exposeCeMask - * Mask of CEs to expose to clients for the above - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - */ -typedef struct NVLINK_CE_AUTO_CONFIG_TABLE -{ - NvU32 sysmemLinks; - NvU32 maxLinksPerPeer; - NvU32 numPeers; - NvBool bSymmetric; - NvBool bSwitchConfig; - NvU32 pceLceMap[MAX_CE_CNT]; - NvU32 grceConfig[MAX_CE_CNT]; - NvU32 exposeCeMask; -} NVLINK_CE_AUTO_CONFIG_TABLE; - // // General convention decided on between HW and SW: // - CE2 is for SYSMEM reads diff --git a/src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h b/src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h new file mode 100644 index 000000000..1d387bc87 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h @@ -0,0 +1,3 @@ + +#include "g_kern_fsp_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h b/src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h new file mode 100644 index 000000000..ddefae29a --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define FSP_OK (0x00U) +#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU) +#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU) +#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U) +#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U) diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 6c86a6e28..30757c54c 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -90,6 +90,9 @@ #if GPU_CHILD_MODULE(FBFLCN) GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, NV_FALSE, pFbflcn ) #endif +#if GPU_CHILD_MODULE(HSHUBMANAGER) + GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr ) +#endif #if GPU_CHILD_MODULE(HSHUB) GPU_CHILD_MULTI_INST ( OBJHSHUB, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub ) #endif @@ -120,9 +123,6 @@ #if GPU_CHILD_MODULE(KERNEL_GMMU) GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, NV_FALSE, pKernelGmmu ) #endif -#if GPU_CHILD_MODULE(KERNEL_NVDEC) - GPU_CHILD_SINGLE_INST( KernelNvdec, GPU_GET_KERNEL_NVDEC, 1, NV_FALSE, NV_FALSE, pKernelNvdec ) -#endif #if GPU_CHILD_MODULE(KERNEL_SEC2) GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, NV_FALSE, pKernelSec2 ) #endif @@ -291,9 +291,15 @@ #if GPU_CHILD_MODULE(GSP) GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, NV_FALSE, pGsp ) #endif +#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP) + GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, NV_FALSE, pKernelFsp ) +#endif #if GPU_CHILD_MODULE(OFA) GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, NV_FALSE, pOfa ) #endif +#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU) + GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, NV_FALSE, pKernelCcu ) +#endif // Undefine the entry macros to simplify call sites #undef GPU_CHILD diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index 47abb8e23..e7767480d 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -35,6 +35,7 @@ #include "ctrl/ctrl2080/ctrl2080bios.h" #include "ctrl/ctrl2080/ctrl2080fb.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrla083.h" #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT @@ -109,8 +110,8 @@ typedef struct GspStaticConfigInfo_t NvBool bClRootportNeedsNosnoopWAR; - VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; - VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; + NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; + NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; NvU64 displaylessMaxPixels; // Client handle for internal RMAPI control. @@ -121,6 +122,8 @@ typedef struct GspStaticConfigInfo_t // Subdevice handle for internal RMAPI control. NvHandle hInternalSubdevice; + + NvBool bAtsSupported; } GspStaticConfigInfo; // Pushed from CPU-RM to GSP-RM @@ -133,6 +136,7 @@ typedef struct GspSystemInfo NvU64 simAccessBufPhysAddr; NvU64 pcieAtomicsOpMask; NvU64 consoleMemSize; + NvU64 maxUserVa; NvU32 pciConfigMirrorBase; NvU32 pciConfigMirrorSize; NvU8 oorArch; diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index a87345adf..e4c616b0a 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -81,13 +81,14 @@ #define MC_ENGINE_IDX_NVJPG 42 #define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG #define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG -#define MC_ENGINE_IDX_RESERVED43 43 -#define MC_ENGINE_IDX_RESERVED44 44 -#define MC_ENGINE_IDX_RESERVED45 45 -#define MC_ENGINE_IDX_RESERVED46 46 -#define MC_ENGINE_IDX_RESERVED47 47 -#define MC_ENGINE_IDX_RESERVED48 48 -#define MC_ENGINE_IDX_RESERVED49 49 +#define MC_ENGINE_IDX_NVJPEG1 43 +#define MC_ENGINE_IDX_NVJPEG2 44 +#define MC_ENGINE_IDX_NVJPEG3 45 +#define MC_ENGINE_IDX_NVJPEG4 46 +#define MC_ENGINE_IDX_NVJPEG5 47 +#define MC_ENGINE_IDX_NVJPEG6 48 +#define MC_ENGINE_IDX_NVJPEG7 49 + #define MC_ENGINE_IDX_REPLAYABLE_FAULT 50 #define MC_ENGINE_IDX_ACCESS_CNTR 51 #define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52 @@ -101,9 +102,9 @@ #define MC_ENGINE_IDX_NVDEC2 58 #define MC_ENGINE_IDX_NVDEC3 59 #define MC_ENGINE_IDX_NVDEC4 60 -#define MC_ENGINE_IDX_RESERVED61 61 -#define MC_ENGINE_IDX_RESERVED62 62 -#define MC_ENGINE_IDX_RESERVED63 63 +#define MC_ENGINE_IDX_NVDEC5 61 +#define MC_ENGINE_IDX_NVDEC6 62 +#define MC_ENGINE_IDX_NVDEC7 63 #define MC_ENGINE_IDX_CPU_DOORBELL 64 #define MC_ENGINE_IDX_PRIV_DOORBELL 65 #define MC_ENGINE_IDX_MMU_ECC_ERROR 66 diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index c2a4e29cd..9c6933689 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -45,6 +45,12 @@ #include "addrtree.h" #include "nvmisc.h" +#if defined(SRT_BUILD) +#define RMCFG_MODULE_x 1 +#else +#include "rmconfig.h" +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h b/src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h deleted file mode 100644 index 3f3847994..000000000 --- a/src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h +++ /dev/null @@ -1,3 +0,0 @@ - -#include "g_kernel_nvdec_nvoc.h" - diff --git a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h new file mode 100644 index 000000000..e60275949 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_MAP, + RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL)) + NV_STATUS subdeviceCtrlCmdCcuMap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams); + + RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP, + RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL)) + NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice); + diff --git a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h index 63e492887..03f383669 100644 --- a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h +++ b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h @@ -198,4 +198,15 @@ NvBool rmMemPoolIsScrubSkipped(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInf */ NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU32*); -#endif //_RM_POOL_ALLOC_H_ +/*! + * @brief Indicate that pool should be allocated in protected video memory in + * case memory protection is enabled + * + * @param[in] pMemReserveInfo Pointer to the RM_POOL_ALLOC_MEM_RESERVE_INFO data + * @param[in] bProtected Allocate in protected memory + * + * @return + */ +void rmMemPoolAllocateProtectedMemory(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvBool bProtected); + +#endif //_RM_POOL_ALLOC_ diff --git a/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h b/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h new file mode 100644 index 000000000..5b0e98905 --- /dev/null +++ b/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OS_FIXED_MODE_TIMINGS_PROPS_H_ +#define _OS_FIXED_MODE_TIMINGS_PROPS_H_ + +#include "gpu/disp/kern_disp_max.h" +#include "nvtypes.h" + +typedef struct +{ + NvU16 hActive; + NvU16 hFrontPorch; + NvU16 hSyncWidth; + NvU16 hBackPorch; + + NvU16 vActive; + NvU16 vFrontPorch; + NvU16 vSyncWidth; + NvU16 vBackPorch; + + NvU32 pclkKHz; + NvU32 rrx1k; +} OS_MODE_TIMING; + +typedef struct +{ + OS_MODE_TIMING timingsPerStream[OBJ_MAX_HEADS]; + NvU8 numTimings; +} OS_FIXED_MODE_TIMINGS; + +#endif diff --git a/src/nvidia/inc/kernel/platform/acpi_common.h b/src/nvidia/inc/kernel/platform/acpi_common.h index 37d55b7f3..2b46703d8 100644 --- a/src/nvidia/inc/kernel/platform/acpi_common.h +++ b/src/nvidia/inc/kernel/platform/acpi_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ void cacheDsmSupportedFunction(OBJGPU *, ACPI_DSM_FUNCTION, NvU32, NvU32 *, NvU3 NV_STATUS checkDsmCall(OBJGPU *, ACPI_DSM_FUNCTION *, NvU32 *, NvU32 *, NvU16 *); void acpiDsmInit(OBJGPU *); NV_STATUS getLicenseKey(OBJGPU *, NvU32, NvU32 *, NvU16 *); +void uncacheDsmFuncStatus(OBJGPU *, ACPI_DSM_FUNCTION, NvU32); // useful macros #if NV_PRINTF_ENABLED diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index eb6aa382b..e95f57638 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -132,28 +132,141 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC !RMCFG_FEATURE_PHYSICAL_RM \ ) -// per-rmcontrol flags values +// +// 'FLAGS' Attribute +// ----------------- +// +// RMCTRL_FLAGS is used to specify per-command state. +// + #define RMCTRL_FLAGS_NONE 0x000000000 -#define RMCTRL_FLAGS_NO_STATIC 0x000000000 // internal to chip-config. TODO -- delete -#define RMCTRL_FLAGS_ONLY_IF_CMD_DEFINED 0x000000000 // internal to chip-config. TODO -- delete + +// +// If the KERNEL_PRIVILEGED flag is specified, the call will only be allowed +// for kernel mode callers (such as other kernel drivers) using a privileged +// kernel RM client (CliCheckIsKernelClient() returning true). Otherwise, +// NV_ERR_INSUFFICIENT_PERMISSIONS is returned. +// #define RMCTRL_FLAGS_KERNEL_PRIVILEGED 0x000000000 + +// +// The resman rmcontrol handler will not grab the "gpus lock" +// before executing the implementing function. +// +// Please be sure you know what you're doing before using this! +// #define RMCTRL_FLAGS_NO_GPUS_LOCK 0x000000001 + +// +// Indicate to resman that this rmcontrol does not access any gpu +// resources and can therefore run even when the gpu is powered down. +// +// Please be sure you know what you're doing before using this! +// #define RMCTRL_FLAGS_NO_GPUS_ACCESS 0x000000002 + +// +// If the PRIVILEGED flag is specified, the call will only be allowed for +// a) user contexts with admin privleges (osIsAdministrator() returning true), or +// b) kernel mode callers, such as other kernel drivers. +// Otherwise, NV_ERR_INSUFFICIENT_PERMISSIONS is returned. +// #define RMCTRL_FLAGS_PRIVILEGED 0x000000004 -#define RMCTRL_FLAGS_HACK_USED_ON_MULTIPLE_CLASSES 0x000000008 + +// +// If the NON_PRIVILEGED flag is specified, the call will be allowed from any +// client. +// #define RMCTRL_FLAGS_NON_PRIVILEGED 0x000000010 -#define RMCTRL_FLAGS_BIG_PAYLOAD 0x000000020 + +// +// The resman rmcontrol handler will grab the per-device lock instead +// of the "gpus lock" before executing the implementing function. +// +// Please be sure you know what you're doing before using this! +// #define RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY 0x000000040 + +// +// This flag is equivalent to PRIVILEGED when the RM access rights +// implementation is disabled. Otherwise, it has no effect. +// +// The purpose of this flag is to aid in the transition to the access rights +// system, so that access rights can be used for control calls that were +// previously PRIVILEGED. Once access rights are enabled, this flag will no +// longer be necessary. +// #define RMCTRL_FLAGS_PRIVILEGED_IF_RS_ACCESS_DISABLED 0x000000100 // for Resserv Access Rights migration + +// +// This flag specifies that the control shall be directly forwarded to the +// physical object if called on the CPU-RM kernel. +// #define RMCTRL_FLAGS_ROUTE_TO_PHYSICAL 0x000000200 + +// +// If the INTERNAL flag is specified, the call will only be allowed +// to be issued from RM itself. Otherwise, NV_ERR_NOT_SUPPORTED is returned. +// #define RMCTRL_FLAGS_INTERNAL 0x000000400 + +// +// If the API_LOCK_READONLY flag is specified, the call will acquire the +// read-only API lock and may run concurrently with other operations that have +// also taken the read-only API lock. This flag is ignored if read-only API +// locking is disabled in RM. +// #define RMCTRL_FLAGS_API_LOCK_READONLY 0x000000800 + +// +// If the :GPU_LOCK_READONLY flag is specified, the call will acquire a +// read-only GPU lock and may run concurrently with other operations that have +// also taken a read-only GPU lock. This flag is ignored if read-only GPU +// locking is disabled in RM. +// #define RMCTRL_FLAGS_GPU_LOCK_READONLY 0x000001000 + +// +// This flag specifies that the control shall be directly forwarded to the +// the VGPU host if called from a guest (where IS_VIRTUAL() is true) +// #define RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST 0x000002000 + +// +// This flag specifies that the control output does not depend on the input +// parameters and can be cached on the receiving end. +// The cache is transparent and may not exist on all platforms. +// #define RMCTRL_FLAGS_CACHEABLE 0x000004000 + +// +// This flag specifies that the control parameters will be +// copied out back to the caller even if the control call fails. +// #define RMCTRL_FLAGS_COPYOUT_ON_ERROR 0x000008000 + +// ?? #define RMCTRL_FLAGS_ALLOW_WITHOUT_SYSMEM_ACCESS 0x000010000 + +// +// 'ACCESS_RIGHTS' Attribute +// ------------------------ +// +// Used to specify a set of access rights that the client must hold on the +// target resource to execute this control call. Note that this can only check +// access rights on the target object; for other objects, such as those +// specified by handles in parameter structs, checks must be done manually. +// +// The definition of each access right and its meaning is provided in the +// README located at drivers/common/shared/accessrights/README. The prefix +// "RS_ACCESS" is appended to each entry in the control call definition; +// for example, :NICE -> RS_ACCESS_NICE. +// +// This attribute only has an effect when the RM access rights implementation +// is enabled; see g_bRsAccessEnabled. +// + #endif // _CONTROL_H_ diff --git a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h index 2116d66fa..c298257dd 100644 --- a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h +++ b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -126,6 +126,7 @@ NV_STATUS nvGpuOpsQueryCesCaps(struct gpuDevice *device, NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace, NvU64 srcAddress, struct gpuAddressSpace *dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress); NV_STATUS nvGpuOpsDupMemory(struct gpuDevice *device, diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index fca7b7029..f36e283b5 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -191,6 +191,10 @@ struct _RM_API NV_STATUS (*MapToCpuWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, NvU64 offset, NvU64 length, NvP64 *ppCpuVirtAddr, NvU32 flags, API_SECURITY_INFO *pSecInfo); + // Map memory v2. Pass in flags as a pointer for in/out access + NV_STATUS (*MapToCpuWithSecInfoV2)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, + NvU64 offset, NvU64 length, NvP64 *ppCpuVirtAddr, NvU32 *flags, API_SECURITY_INFO *pSecInfo); + // Unmap memory with default security attributes and local pointers (no NvP64) NV_STATUS (*UnmapFromCpu)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, void *pLinearAddress, NvU32 flags, NvU32 ProcessId); diff --git a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h index b26218cb6..e513fc411 100644 --- a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h +++ b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h @@ -196,10 +196,15 @@ typedef struct GMMU_COMPR_INFO GMMU_COMPR_INFO; */ #define GMMU_FMT_VERSION_2 2 +/*! + * 6-level (57b VA) format supported on Hopper+. + */ +#define GMMU_FMT_VERSION_3 3 + /*! * Maximum number of MMU versions supported. */ -#define GMMU_FMT_MAX_VERSION_COUNT 2 +#define GMMU_FMT_MAX_VERSION_COUNT 3 /*! * Array of format version numbers for enumeration utility. diff --git a/src/nvidia/inc/libraries/nvport/debug.h b/src/nvidia/inc/libraries/nvport/debug.h index fe7a94d7a..1390774e2 100644 --- a/src/nvidia/inc/libraries/nvport/debug.h +++ b/src/nvidia/inc/libraries/nvport/debug.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -278,6 +278,8 @@ PORT_DEBUG_INLINE void portDbgExPrintfLevel(NvU32 level, const char *format, ... #include "nvport/inline/debug_qnx.h" #elif NVOS_IS_DCECORE #include "nvport/inline/debug_dcecore.h" +#elif defined(GSP_PLUGIN_BUILD) +#include "nvport/inline/debug_vgpu_gsp.h" #else #if PORT_IS_KERNEL_BUILD diff --git a/src/nvidia/inc/physical/gpu/disp/disp.h b/src/nvidia/inc/physical/gpu/disp/disp.h deleted file mode 100644 index 6fa6d14ac..000000000 --- a/src/nvidia/inc/physical/gpu/disp/disp.h +++ /dev/null @@ -1,3 +0,0 @@ - -#include "g_disp_nvoc.h" - diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c index 1107f5d84..d66faaf31 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c @@ -32,6 +32,7 @@ #include "ctrl/ctrl2080/ctrl2080perf.h" // NV2080_CTRL_CMD_PERF_* #include "ctrl/ctrl0080/ctrl0080perf.h" // NV0080_CTRL_CMD_PERF_GET_CAPS #include "ctrl/ctrl0080/ctrl0080bsp.h" // NV0080_CTRL_CMD_BSP_GET_CAPS +#include "ctrl/ctrl0073/ctrl0073dp.h" // NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES // // TODO - deprecation shim shouldn't depend on RM internals @@ -61,6 +62,7 @@ static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_BIOS_GET_INFO)(API_SECURITY_INFO static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_BUS_GET_INFO)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); static NV_STATUS V2_CONVERTER(_NV0080_CTRL_CMD_BSP_GET_CAPS)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_GPU_GET_INFO)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); +static NV_STATUS V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); typedef struct { @@ -77,6 +79,7 @@ static const RmDeprecatedControlEntry rmDeprecatedControlTable[] = { NV2080_CTRL_CMD_BUS_GET_INFO, V2_CONVERTER(_NV2080_CTRL_CMD_BUS_GET_INFO), NV_FALSE}, { NV0080_CTRL_CMD_BSP_GET_CAPS, V2_CONVERTER(_NV0080_CTRL_CMD_BSP_GET_CAPS), NV_FALSE}, { NV2080_CTRL_CMD_GPU_GET_INFO, V2_CONVERTER(_NV2080_CTRL_CMD_GPU_GET_INFO), NV_FALSE}, + { NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES, V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES), NV_FALSE}, { 0, NULL, NV_FALSE } }; @@ -638,3 +641,102 @@ static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_GPU_GET_INFO) NV_TRUE // Command GETs info, do copy-out ); } + +static NV_STATUS V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES) +( + API_SECURITY_INFO *pSecInfo, + DEPRECATED_CONTEXT *pContextInternal, + NVOS54_PARAMETERS *pArgs +) +{ + NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *pParams = NULL; + NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS *pParams2 = NULL; + NV_STATUS status; + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + NV_PRINTF(LEVEL_ERROR, "No memory for pParams\n"); + return NV_ERR_NO_MEMORY; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + RmCopyUserForDeprecatedApi(RMAPI_DEPRECATED_COPYIN, + RMAPI_DEPRECATED_BUFFER_EMPLACE, + pArgs->params, + sizeof(*pParams), + (void**)&pParams, + pSecInfo->paramLocation == PARAM_LOCATION_USER), + done); + + pParams2 = portMemAllocNonPaged(sizeof(*pParams2)); + if (pParams2 == NULL) + { + NV_PRINTF(LEVEL_ERROR, "No memory for pParams2\n"); + status = NV_ERR_NO_MEMORY; + goto done; + } + + NVMISC_MEMSET(pParams2, 0, sizeof(*pParams2)); + + pParams2->subDeviceInstance = pParams->subDeviceInstance; + pParams2->displayId = pParams->displayId; + pParams2->bEnableMSA = pParams->bEnableMSA; + pParams2->bStereoPhaseInverse = pParams->bStereoPhaseInverse; + pParams2->bCacheMsaOverrideForNextModeset = pParams->bCacheMsaOverrideForNextModeset; + pParams2->featureMask = pParams->featureMask; + pParams2->featureValues = pParams->featureValues; + + if (pParams->pFeatureDebugValues != NULL) + { + pParams2->bDebugValues = NV_TRUE; + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + RmCopyUserForDeprecatedApi(RMAPI_DEPRECATED_COPYIN, + RMAPI_DEPRECATED_BUFFER_EMPLACE, + pParams->pFeatureDebugValues, + sizeof(pParams2->featureDebugValues), + (void**)&pParams2->featureDebugValues, + pSecInfo->paramLocation != PARAM_LOCATION_KERNEL), + done); + } + status = pContextInternal->RmControl(pContextInternal, pArgs->hClient, + pArgs->hObject, + NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2, + pParams2, + sizeof(NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS)); + if (status == NV_OK) + { + if (pParams->pFeatureDebugValues != NULL) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + RmCopyUserForDeprecatedApi(RMAPI_DEPRECATED_COPYOUT, + RMAPI_DEPRECATED_BUFFER_EMPLACE, + pParams->pFeatureDebugValues, + sizeof(pParams2->featureDebugValues), + (void**)&pParams2->featureDebugValues, + pSecInfo->paramLocation != PARAM_LOCATION_KERNEL), + done); + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + RmCopyUserForDeprecatedApi(RMAPI_DEPRECATED_COPYOUT, + RMAPI_DEPRECATED_BUFFER_EMPLACE, + pArgs->params, + sizeof(*pParams), + (void**)&pParams, + pSecInfo->paramLocation == PARAM_LOCATION_USER), + done); + } + +done: + if (pParams2 != NULL) + { + portMemFree(pParams2); + } + if (pParams != NULL) + { + portMemFree(pParams); + } + + return status; +} diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c index 024a27495..1e9110813 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c @@ -28,6 +28,7 @@ #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE #include "nvos.h" + NV_STATUS RmDeprecatedGetHandleParent ( diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index c0df2d4d0..dd114310f 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -217,12 +217,6 @@ typedef struct UvmGpuChannelInstanceInfo_tag // Out: Type of the engine the channel is bound to NvU32 channelEngineType; - // Out: Channel handle required to ring the doorbell - NvU32 workSubmissionToken; - - // Out: Address of the doorbell - volatile NvU32 *workSubmissionOffset; - // Out: Channel handle to be used in the CLEAR_FAULTED method NvU32 clearFaultedToken; @@ -231,6 +225,10 @@ typedef struct UvmGpuChannelInstanceInfo_tag // Ampere+ GPUs volatile NvU32 *pChramChannelRegister; + // Out: Address of the Runlist PRI Base Register required to ring the + // doorbell after clearing the faulted bit. + volatile NvU32 *pRunlistPRIBaseRegister; + // Out: SMC engine id to which the GR channel is bound, or zero if the GPU // does not support SMC or it is a CE channel NvU32 smcEngineId; @@ -372,6 +370,8 @@ typedef enum UVM_LINK_TYPE_NVLINK_1, UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, + UVM_LINK_TYPE_NVLINK_4, + UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag @@ -429,11 +429,9 @@ typedef struct UvmGpuAddressSpaceInfo_tag typedef struct UvmGpuAllocInfo_tag { - NvU64 rangeBegin; // Allocation will be made between - NvU64 rangeEnd; // rangeBegin & rangeEnd both included NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M - NvU64 alignment; // Alignment of allocation + NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory @@ -568,6 +566,8 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; + // Out: AMD SEV (Secure Encrypted Virtualization) is enabled + NvBool sevEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index 4c22a6e81..480940a3c 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1997-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1997-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -787,44 +787,15 @@ // 1 - Increases RM reserved space // 0 - (default) Keeps RM reserved space as it is. -#define NV_REG_STR_BUG_1698088_WAR "RMBug1698088War" -#define NV_REG_STR_BUG_1698088_WAR_ENABLE 0x00000001 -#define NV_REG_STR_BUG_1698088_WAR_DISABLE 0x00000000 -#define NV_REG_STR_BUG_1698088_WAR_DEFAULT NV_REG_STR_BUG_1698088_WAR_DISABLE - -// -// TYPE DWORD -// This regkey can be used to ignore upper memory on GM20X and later. If there -// is upper memory but this regkey is set to _YES, then RM will only expose the -// lower memory to clients. -// -// DEFAULT - Use the default setting of upper memory on GM20X-and-later. -// YES - Ignore upper memory on GM20X-and-later. -// -#define NV_REG_STR_RM_IGNORE_UPPER_MEMORY "RMIgnoreUpperMemory" -#define NV_REG_STR_RM_IGNORE_UPPER_MEMORY_DEFAULT (0x00000000) -#define NV_REG_STR_RM_IGNORE_UPPER_MEMORY_YES (0x00000001) - -#define NV_REG_STR_RM_NO_ECC_FB_SCRUB "RMNoECCFBScrub" - #define NV_REG_STR_RM_DISABLE_SCRUB_ON_FREE "RMDisableScrubOnFree" // Type DWORD // Encoding 0 (default) - Scrub on free // 1 - Disable Scrub on Free -#define NV_REG_STR_RM_INIT_SCRUB "RMInitScrub" -// Type DWORD -// Encoding 1 - Scrub Fb during rminit irrespective of ECC capability - -#define NV_REG_STR_RM_DISABLE_ASYNC_MEM_SCRUB "RMDisableAsyncMemScrub" +#define NV_REG_STR_RM_DISABLE_FAST_SCRUBBER "RMDisableFastScrubber" // Type DWORD -// Encoding 0 (default) - Async memory scrubbing is enabled -// 1 - Async memory scrubbing is disabled - -#define NV_REG_STR_RM_INCREASE_ECC_SCRUB_TIMEOUT "RM1441072" -// Type DWORD -// Encoding 0 (default) - Use default ECC Scrub Timeout -// 1 - Increase ECC Scrub Timeout +// Encoding 0 (default) - Enable Fast Scrubber +// 1 - Disable Fast Scrubber // // Type DWORD @@ -888,6 +859,13 @@ // If set, this will cause RM mark GPU as lost when it detects 0xFF from register // access. +#define NV_REG_STR_RM_BLACKLIST_ADDRESSES "RmBlackListAddresses" +// Type BINARY: +// struct +// { +// NvU64 addresses[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +// }; + #define NV_REG_STR_RM_NUM_FIFOS "RmNumFifos" // Type Dword // Override number of fifos (channels) on NV4X @@ -931,7 +909,7 @@ // will fail in such a case. // // TYPE_DEFAULT let RM to choose a P2P type. The priority is: -// C2C > NVLINK > BAR1P2P > mailbox P2P +// C2C > NVLINK > mailbox P2P > BAR1P2P // // TYPE_C2C to use C2C P2P if it supports // TYPE_NVLINK to use NVLINK P2P, including INDIRECT_NVLINK_P2P if it supports @@ -1307,7 +1285,10 @@ #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO (0x00000000) #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_YES (0x00000001) #define NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_DEFAULT (NV_REG_STR_RM_NVLINK_CONTROL_SKIP_TRAIN_NO) -#define NV_REG_STR_RM_NVLINK_CONTROL_RESERVED_0 7:3 +#define NV_REG_STR_RM_NVLINK_CONTROL_RESERVED_0 6:3 +#define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW 7:7 +#define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_OFF (0x00000000) +#define NV_REG_STR_RM_NVLINK_CONTROL_LINK_TRAINING_DEBUG_SPEW_ON (0x00000001) #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG 8:8 #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_NO (0x00000000) #define NV_REG_STR_RM_NVLINK_CONTROL_FORCE_AUTOCONFIG_YES (0x00000001) @@ -1342,7 +1323,23 @@ #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DEFAULT (0x00000000) #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_ENABLE (0x00000001) #define NV_REG_STR_RM_NVLINK_MINION_CONTROL_INITOPTIMIZE_DISABLE (0x00000002) -#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_RESERVED_0 31:20 +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS 23:20 +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_ENABLE (0x00000001) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DISABLE (0x00000002) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE 27:24 +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV (0x00000001) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_FALCON (0x00000002) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_RISCV_MANIFEST (0x00000003) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_BOOT_CORE_NO_MANIFEST (0x00000004) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING 30:28 +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_ENABLE (0x00000001) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DISABLE (0x00000002) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE 31:31 +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DISABLE (0x00000001) // // Type DWORD @@ -1374,8 +1371,10 @@ #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_40G (0x0000000F) #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_50_00000G (0x00000010) #define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_53_12500G (0x00000011) -#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_FAULT (0x00000013) -#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED__LAST (0x00000013) +#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_100_00000G (0x00000012) +#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_106_25000G (0x00000013) +#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_FAULT (0x00000014) +#define NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED__LAST (0x00000014) // // Type DWORD @@ -1401,7 +1400,10 @@ #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DEFAULT (0x00000000) #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_ENABLE (0x00000001) #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_PROD_WRITES_DISABLE (0x00000002) -#define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_RESERVED_0 5:4 +#define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE 5:4 +#define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_ENABLE (0x00000001) +#define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L1_MODE_DISABLE (0x00000002) #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE 7:6 #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_DEFAULT (0x00000000) #define NV_REG_STR_RM_NVLINK_LINK_PM_CONTROL_L2_MODE_ENABLE (0x00000001) @@ -1578,4 +1580,26 @@ // 1 - Force Enable Gen2 (to invalidate PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED) // +#define NV_REG_STR_RM_DISABLE_FSP "RmDisableFsp" +#define NV_REG_STR_RM_DISABLE_FSP_NO (0x00000000) +#define NV_REG_STR_RM_DISABLE_FSP_YES (0x00000001) +// Type DWORD (Boolean) +// Override any other settings and disable FSP + +#define NV_REG_STR_RM_DISABLE_COT_CMD "RmDisableCotCmd" +#define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_SYSMEM 1:0 +#define NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_VIDMEM 3:2 +#define NV_REG_STR_RM_DISABLE_COT_CMD_GSPFMC 5:4 +#define NV_REG_STR_RM_DISABLE_COT_CMD_DEFAULT (0x00000000) +#define NV_REG_STR_RM_DISABLE_COT_CMD_YES (0x00000001) +// Type DWORD (Boolean) +// Disable the specified commands as part of Chain-Of-Trust feature + +#define NV_REG_STR_PCI_LATENCY_TIMER_CONTROL "PciLatencyTimerControl" +// Type Dword +// Encoding Numeric Value +// Override to control setting/not setting of pci timer latency value. +// Not present suggests default value. A value 0xFFFFFFFF will leave the value unmodified (ie bios value). +// All other values must be multiples of 8 + #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/interface/rmapi/src/finn_rm_api.c b/src/nvidia/interface/rmapi/src/finn_rm_api.c index 434b6e6b0..c6b1e97fd 100644 --- a/src/nvidia/interface/rmapi/src/finn_rm_api.c +++ b/src/nvidia/interface/rmapi/src/finn_rm_api.c @@ -17,6 +17,7 @@ #include "ctrl/ctrl83de/ctrl83dedebug.h" #include "ctrl/ctrlb06f.h" +#include #include #if defined(NVRM) /* Kernel Mode */ #include "nvport/nvport.h" @@ -80,232 +81,426 @@ #define FINN_ERROR(err) /* No-op */ #endif -// Copy val into buf as type and increment buf by size. -#define FINN_COPY_TO_BUFFER(buf, val, type, size) \ - do { \ - *((type *)(buf)) = (val); \ - (buf) += (size); \ - } while(0) - -// Copy buf into var as type and increment buf by size. -#define FINN_COPY_FROM_BUFFER(var, buf, type, size) \ - do { \ - (var) = *((type *)(buf)); \ - (buf) += (size); \ - } while(0) - -// Copy size bytes from src to dst and increment dst by size. -#define FINN_MEMCPY_TO_BUFFER(dst, src, size) \ - do { \ - FINN_MEMCPY((dst), (src), (size)); \ - (dst) += (size); \ - } while(0) - -// Copy size bytes from src to dst and increment src by size. -#define FINN_MEMCPY_FROM_BUFFER(dst, src, size) \ - do { \ - FINN_MEMCPY((dst), (src), (size)); \ - (src) += (size); \ - } while(0) - -// Set ptr to buf as type and increment buf by size. -#define FINN_SET_PTR_TO_BUFFER(ptr, buf, type, size) \ - do { \ - (ptr) = (type)(NvUPtr)(buf); \ - (buf) += (size); \ - } while(0) - -// Align a byte pointer up to the 8-byte boundary. -#define FINN_ALIGN_UP_BYTE_PTR(ptr) \ - do { \ - (ptr) = (NvU8 *)(((NvUPtr)(ptr) + 7) &~ 7); \ - } while(0) \ - -NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, NvLength dst_size, NvBool seri_up); -NV_STATUS FinnRmApiDeserializeInternal(char * const *src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); - -static NV_STATUS FinnNv01RootNvdSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01RootNvdDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01RootNvdGetSerializedSize(NvU64 message, const NvP64 src); + + +// +// The purpose of the bit pump is to ensure 64-bit aligned access to the +// buffer while enabling arbitrary bits to be read/written. +// +typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; + +struct finn_bit_pump_for_read +{ + uint64_t accumulator; // Bits not yet read from the data buffer + uint64_t checksum; // Checksum of data + const uint64_t *buffer_position; // Next word within data buffer to be read + const uint64_t *end_of_data; // End of data within buffer + uint8_t remaining_bit_count; // Number of bits remaining in the accumulator +}; + + +// +// Initialize bit pump for reading from the buffer. +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eod` (end of data) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eod` points to the 64-bit word after the data (like most C++ `std` iterators). +// +static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) +{ + bp->accumulator = 0U; + bp->checksum = 0U; + bp->buffer_position = sod; + bp->end_of_data = eod; + bp->remaining_bit_count = 0U; +} + + +// +// Read the next several bits. +// +// `bit_size` must be in range of 0 to 64 inclusive; no check is made. +// When `bit_size` is zero, an unsupported use-case, it works as expected by +// returning zero without advancing the pointer. +// +static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) +{ + // Value to be deserialized and returned + uint64_t value; + + // Boundary crossing + // Accumulator does not have enough to satisfy the request, + if (bit_size > bp->remaining_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->remaining_bit_count; + + // Shift the bits we have into place. + value = bp->accumulator; + + // Return zeroes for unsatisfied bits (if any) at end of data. + if (bp->buffer_position >= bp->end_of_data) + bp->accumulator = 0U; + + // Read the next word from the buffer. + else + bp->accumulator = *(bp->buffer_position++); + + // Update the checksum. + bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; + + // + // This is the special case where we are reading an entire 64-bit word + // without crossing a boundary (when the accumulator is empty). The + // accumulator remains empty on exit. + // + // The bitwise operations in the normal flow do not work in this case. + // Shifts are not well-defined in C when the right operand exceeds the + // size of the left operand. Also, the right operand of the bitwise-and + // would exceed the 64-bit capacity. However, the needed logic is simple. + // + // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. + // + if (bit_size >= 64) + { + // The value is the entire word. + value = bp->accumulator; + + // Discard the consumed data from the accumulator. + bp->accumulator = 0U; + + // Under the assumption that `bit_size` is never larger than 64, + // `bit_size == 64` implies `bp->remaining_bit_count == 0` because + // of the above `bit_size -= bp->remaining_bit_count`. As such, there + // is no need to do `bp->remaining_bit_count = 64U - bit_size`. + + // Done + return value; + } + + // OR in the bits since this was a boundary crossing. + // Shift it over by the number of bits we get from the prior word. + value |= (bp->accumulator + & (((uint64_t) 1U << bit_size) - 1U)) + << bp->remaining_bit_count; + + // Logic below subtracts off the bits consumed in the accumulator. + bp->remaining_bit_count = 64U; + } + + else + { + // The accumulator has enough to satisfy the request. + value = bp->accumulator & (((uint64_t) 1U << bit_size) - 1U); + } + + // Discard the consumed bits from the accumulator. + bp->accumulator >>= bit_size; + + // Keep track of the remaining available bits in the accumulator. + bp->remaining_bit_count -= bit_size; + + // Done + return value; +} + + +// Close the read buffer. +// Postcondition: `bp->checksum` is updated to end-of-data. +static inline void finn_close_buffer_for_read(finn_bit_pump_for_read *bp) +{ + // No need to update the bit pump buffer position, + // so use a local for optimal performance. + const uint64_t *p = bp->buffer_position; + + // Apply any unread words to the checksum. + while (p < bp->end_of_data) + bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ (*(p++)); +} + + +typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; + +struct finn_bit_pump_for_write +{ + uint64_t accumulator; // Bits not yet written to the data buffer + uint64_t checksum; // Checksum of data + uint64_t *buffer_position; // Next word within the data buffer to be written + const uint64_t *end_of_buffer; // End of buffer (which may be after end of data) + uint8_t empty_bit_count; // Number of available bits in the accumulator +}; + + +// +// Initialize bit pump for writing to the buffer. +// +// In the general case for writing to the bit pump: +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eob` (end of buffer) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eob` points to the 64-bit word after the buffer, an illegal access. +// +// +// Special case to get the serialized size without writing to the buffer: +// Both `sod` and `eob` are null. +// When closed, `bp->buffer_position` contains the byte count. +// +static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, uint64_t *eob) +{ + bp->accumulator = 0U; + bp->buffer_position = sod; + bp->end_of_buffer = eob; + bp->checksum = 0U; + bp->empty_bit_count = 64U; +} + +// +// Write several bits to the buffer. +// +// `bit_size` must be in range of 1 to 64 inclusive; no check is made. +// `value` must not have more 1 bits than specified by `bit_size`. +// In other words, bits that are left of `bit_size` must be 0s; no check is made. +// +// Return value is nonzero if the end of buffer is reached, an error. +// +// `bp->end_of_buffer` is null to disable writing to the buffer. +// +static int finn_write_buffer(finn_bit_pump_for_write *bp, uint64_t value, uint8_t bit_size) +{ + // Boundary crossing: Accumulator does not have enough to satisfy the request, + if (bit_size >= bp->empty_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->empty_bit_count; + + // OR as many bits as will fit into the accumulator. + bp->accumulator |= value << (64U - bp->empty_bit_count); + + // Discard these bits by setting them to 0s. + // CAUTION: `value` may be unchanged when `bp->empty_bit_count` is 64 + // depending on the processor/ISA. + value >>= bp->empty_bit_count; + + // Write the word to the buffer unless writes are disabled. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word in the buffer. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; + + // Re-initialize the accumulator and the bits filled. + bp->accumulator = 0U; + bp->empty_bit_count = 64U; + } + + // OR the data into the accumulator. + // When `bit_size` and `bp->empty_bit_count` are both 64 above, `bit_size` + // is assigned zero, but `value` may be unchanged. Check `bit_size` here so + // that stale `value` is not ORed into the accumulator again. + if (bit_size) + { + bp->accumulator |= (value << (64U - bp->empty_bit_count)); + } + + // Advance the bit count + bp->empty_bit_count -= bit_size; + + // Return nonzero on buffer overrun. + return bp->end_of_buffer && bp->buffer_position >= bp->end_of_buffer && bit_size; +} + + +// +// Close the write buffer and compute the checksum. +// +// Do NOT call this function if `finn_write_buffer` returned nonzero; no check is made. +// +// In the general case for writing to the bit pump: +// +// Postcondition: `bp->buffer_position` points to the word after the end of the data, +// which can be used to calculate the data size in 64-bit words by subtracting from +// `bp->end_of_buffer`. Buffer data at and after this point is set to zeroes. +// +// Special case to get the serialized size without writing to the buffer: +// Postcondition: ``bp->buffer_position` contains the byte count. +// +// All cases: +// Postcondition: `bp->checksum` contains the checksum of words written to the buffer. +// +static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) +{ + uint64_t *p; + + // The accumulator is not empty. + if (bp->empty_bit_count < 64U) + { + // Update the buffer with the last word. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word to get an accurate word count. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ bp->accumulator; + } + + // Zero out the rest of the buffer. + for (p = bp->buffer_position; p < bp->end_of_buffer; ++p) + { + *p = 0u; + } +} + + +static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up); +static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0DmaSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0DmaDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0DmaGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FbSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0FbDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FbGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FifoSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0FifoDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FifoGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GpuSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0GpuDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GpuGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GrSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0GrDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GrGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0HostSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0HostDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0HostGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0MsencSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv01Device0MsencDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0MsencGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0CeSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0CeDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0CeGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0GpuSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0GpuDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0GpuGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0I2cSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0I2cDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0I2cGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0NvdSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0NvdDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0NvdGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0PerfSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0PerfDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0PerfGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0RcSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0RcDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0RcGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv40I2cI2cSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnNv40I2cI2cDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv40I2cI2cGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnGt200DebuggerDebugSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnGt200DebuggerDebugDeserialize(NvU8 **src, const NvU8 *src_max, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnGt200DebuggerDebugGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserialize(NvU8 **src, const NvU8 *src_max, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetSerializedSize(NvU64 message, const NvP64 src); +static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message); -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0000CtrlNvdGetDumpParamsGetSerializedSize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlDmaUpdatePde2PageTableParamsGetSerializedSize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlDmaUpdatePde2ParamsGetSerializedSize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src); -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlFbGetCapsParamsGetSerializedSize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlFifoGetCapsParamsGetSerializedSize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src); -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlFifoChannelGetSerializedSize(const NV0080_CTRL_FIFO_CHANNEL *src); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlFifoStartSelectedChannelsParamsGetSerializedSize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlFifoGetChannellistParamsGetSerializedSize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlGpuGetClasslistParamsGetSerializedSize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src); -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlGrGetCapsParamsGetSerializedSize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src); -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlHostGetCapsParamsGetSerializedSize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv0080CtrlMsencGetCapsParamsGetSerializedSize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src); -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlCeGetCapsParamsGetSerializedSize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlGpuGetEnginesParamsGetSerializedSize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlGpuGetEngineClasslistParamsGetSerializedSize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src); -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up, NvU64 interface, NvU64 message); -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlGpumonSamplesGetSerializedSize(const NV2080_CTRL_GPUMON_SAMPLES *src); -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlI2cAccessParamsGetSerializedSize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlNvdGetDumpParamsGetSerializedSize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv2080CtrlRcReadVirtualMemParamsGetSerializedSize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src); -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cIndexedParamsGetSerializedSize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src); -static NV_STATUS Nv402cCtrlI2cTransactionTypeValueToId(NvU8 **buf, const NvU8 *buf_max, NvU64 convert_size); -static NV_STATUS Nv402cCtrlI2cTransactionTypeIdtoValue(NvU8 **buf, const NvU8 *buf_max, NvU64 convert_size); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusQuickRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataI2cByteRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataI2cBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusByteRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusWordRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataI2cBufferRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusProcessCallGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionDataReadEdidDdcGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src); -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NvU64 Nv402cCtrlI2cTransactionDataGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv402cCtrlI2cTransactionParamsGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv83deCtrlDebugReadMemoryParamsGetSerializedSize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nv83deCtrlDebugWriteMemoryParamsGetSerializedSize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(NvU8 **src, const NvU8 *src_max, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nvb06fCtrlGetEngineCtxDataParamsGetSerializedSize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(NvU8 **src, const NvU8 *src_max, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NvU64 Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsGetSerializedSize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src); +static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); +static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); +static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size) { @@ -328,54 +523,108 @@ NV_STATUS FinnRmApiDeserializeUp(NvU8 * const *src, NvLength src_size, void *dst } -NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, NvLength dst_size, NvBool seri_up) +static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up) { - const char *dst_max = *dst + dst_size; + // Header + FINN_RM_API *header; + + // Buffer end + // `char` is the C-standrd unit of measure for `sizeof` and `size_t`. + const char *dst_end; + + // Bit pump is used to fill the buffer with serialized data. + finn_bit_pump_for_write bp; + + // Error code returned from serialization + NV_STATUS error_code; // Input validation - if (!src || !dst || !(*dst) || !dst_size) + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!src || !dst || !(*dst) || !dst_size || (uintptr_t) dst & 0x7u) { FINN_ERROR(NV_ERR_INVALID_ARGUMENT); return NV_ERR_INVALID_ARGUMENT; } - // Forward to interface-specific routine + // Header is at the start of the buffer. + header = (FINN_RM_API *) *dst; + + // Buffer must end on an 8-byte boundary, so round down. + dst_end = (const char *) ((uintptr_t) (*dst + dst_size) & ~ (uintptr_t) 0x7); + + // Set header data. + header->version = FINN_SERIALIZATION_VERSION; + header->payloadSize = 0; // Zero until completed successfully + header->interface = interface; + header->message = message; + + // Advance past header. + (*dst) += sizeof(FINN_RM_API); + + // Open the bit pump. + finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (uint64_t *) dst_end); + + // Call the serializer. + error_code = FinnRmApiSerializeInterface(interface, message, src, &bp, seri_up); + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Payload size in bytes + if (error_code == NV_OK) + header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); + + // Indicate the ending location. + *dst = (char *) bp.buffer_position; + + // Done + return error_code; +} + + +static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + + + // Forward to interface-specific serialize routine switch (interface) { case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01RootNvdSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0DmaSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0FbSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0FifoSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0GpuSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0GrSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0HostSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv01Device0MsencSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0CeSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0GpuSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0I2cSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0NvdSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0PerfSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv20Subdevice0RcSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnNv40I2cI2cSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnGt200DebuggerDebugSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoSerialize(message, src, (NvU8 **) dst, (const NvU8 *) dst_max, seri_up); + return FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(message, src, bp, seri_up); + default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -385,66 +634,124 @@ NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char } -NV_STATUS FinnRmApiDeserializeInternal(char * const *src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) { - const char *src_max = *src + src_size; + // Header + FINN_RM_API *header; + + // End of data + const char *src_max; + + // Bit pump is used to read the serialized data. + finn_bit_pump_for_read bp; + + // Error code + NV_STATUS status; // Input validation - if (!src || !(*src) || !src_size || !dst || !dst_size) + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!src || !(*src) || !src_size || !dst || !dst_size || (uintptr_t) *src & 0x7u) { FINN_ERROR(NV_ERR_INVALID_ARGUMENT); return NV_ERR_INVALID_ARGUMENT; } - if (((NvU64*)(*src))[0] != FINN_SERIALIZATION_VERSION) + // Header data comes first. + header = (FINN_RM_API *) *src; + + // Check the version. + if (header->version != FINN_SERIALIZATION_VERSION) { FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); return NV_ERR_LIB_RM_VERSION_MISMATCH; } - if (((NvU64*)(*src))[1] > src_size || ((NvU64 *)(*src))[1] < (4 * sizeof(NvU64))) + // Set src_max for buffer bounds checking. + src_max = *src + src_size; + + // Check that source buffer is large enough. + if (sizeof(FINN_RM_API) > src_size || + header->payloadSize > src_size || + header->payloadSize < sizeof(FINN_RM_API) || + *src + header->payloadSize > src_max || + *src + header->payloadSize < *src) { + *src = (char *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); return NV_ERR_BUFFER_TOO_SMALL; } + // Open the bit punp, skipping past the header. + finn_open_buffer_for_read(&bp, (const uint64_t *) (*src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); + + // Dispatch to interface-specific routine + status = FinnRmApiDeserializeInterface(header->interface, header->message, &bp, dst, dst_size, deser_up); + + // Update the buffer position, error or not. + *(src) = (char *) bp.buffer_position; + + // Nothing more to do if there was an error. + if (status != NV_OK) + return status; + + // Update the checksum. + finn_close_buffer_for_read(&bp); + + // TODO: Check the checksum + + // Check that the declared size matches the serialization outcome. + if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // All good + return NV_OK; +} + + +static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up) +{ // Forward to interface-specific routine - switch (((NvU64 *)(*src))[2]) + switch (interface) { case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_ROOT_NVD *) dst, dst_size, deser_up); + return FinnNv01RootNvdDeserializeMessage(message, bp, (FINN_NV01_ROOT_NVD *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_DMA *) dst, dst_size, deser_up); + return FinnNv01Device0DmaDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_DMA *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_FB *) dst, dst_size, deser_up); + return FinnNv01Device0FbDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FB *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_FIFO *) dst, dst_size, deser_up); + return FinnNv01Device0FifoDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FIFO *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_GPU *) dst, dst_size, deser_up); + return FinnNv01Device0GpuDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GPU *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_GR *) dst, dst_size, deser_up); + return FinnNv01Device0GrDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GR *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_HOST *) dst, dst_size, deser_up); + return FinnNv01Device0HostDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_HOST *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV01_DEVICE_0_MSENC *) dst, dst_size, deser_up); + return FinnNv01Device0MsencDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_MSENC *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_CE *) dst, dst_size, deser_up); + return FinnNv20Subdevice0CeDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_CE *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_GPU *) dst, dst_size, deser_up); + return FinnNv20Subdevice0GpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_GPU *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_I2C *) dst, dst_size, deser_up); + return FinnNv20Subdevice0I2cDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_I2C *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_NVD *) dst, dst_size, deser_up); + return FinnNv20Subdevice0NvdDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_NVD *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_PERF *) dst, dst_size, deser_up); + return FinnNv20Subdevice0PerfDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV20_SUBDEVICE_0_RC *) dst, dst_size, deser_up); + return FinnNv20Subdevice0RcDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_NV40_I2C_I2C *) dst, dst_size, deser_up); + return FinnNv40I2cI2cDeserializeMessage(message, bp, (FINN_NV40_I2C_I2C *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_GT200_DEBUGGER_DEBUG *) dst, dst_size, deser_up); + return FinnGt200DebuggerDebugDeserializeMessage(message, bp, (FINN_GT200_DEBUGGER_DEBUG *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoDeserialize((NvU8 **) src, (const NvU8 *) src_max, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) dst, dst_size, deser_up); + return FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(message, bp, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) dst, dst_size, deser_up); + default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -453,54 +760,28 @@ NV_STATUS FinnRmApiDeserializeInternal(char * const *src, NvLength src_size, cha } } + NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src) { - // Input validation - if (!src) - return 0; + // Bit pump with writing disabled. + finn_bit_pump_for_write bp; + finn_open_buffer_for_write(&bp, (uint64_t *) 0, (uint64_t *) 0); - // Forward to interface-specific routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugGetSerializedSize(message, src); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoGetSerializedSize(message, src); - default: - return 0; - } + // Call the serializer with write-suppressed bit pump. + // The size is the same in bith directions (up/down). + // Eeturn zero on error to indicate that this API is not serialized by FINN. + if (FinnRmApiSerializeInterface(interface, message, (const char *) src, &bp, 0) != NV_OK) + return 0; + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Add the header size in bytes to the amount of data serialzied. + // `buffer_position` is the payload size (not really the buffer position). + return (NvU64) bp.buffer_position + sizeof(FINN_RM_API); } + NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) { // Forward to interface-specific routine @@ -545,13 +826,15 @@ NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) } } -static NV_STATUS FinnNv01RootNvdSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsSerialize((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) src, dst, dst_max, seri_up); + return Nv0000CtrlNvdGetDumpParamsSerialize((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -560,13 +843,15 @@ static NV_STATUS FinnNv01RootNvdSerialize(NvU64 message, const char *src, NvU8 * } } -static NV_STATUS FinnNv01RootNvdDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsDeserialize(src, src_max, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); + return Nv0000CtrlNvdGetDumpParamsDeserialize(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -575,21 +860,9 @@ static NV_STATUS FinnNv01RootNvdDeserialize(NvU8 **src, const NvU8 *src_max, FIN } } -static NvU64 FinnNv01RootNvdGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): @@ -599,13 +872,15 @@ static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0DmaSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsSerialize((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlDmaUpdatePde2ParamsSerialize((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -614,13 +889,15 @@ static NV_STATUS FinnNv01Device0DmaSerialize(NvU64 message, const char *src, NvU } } -static NV_STATUS FinnNv01Device0DmaDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsDeserialize(src, src_max, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlDmaUpdatePde2ParamsDeserialize(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -629,21 +906,9 @@ static NV_STATUS FinnNv01Device0DmaDeserialize(NvU8 **src, const NvU8 *src_max, } } -static NvU64 FinnNv01Device0DmaGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): @@ -653,13 +918,15 @@ static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0FbSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsSerialize((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlFbGetCapsParamsSerialize((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -668,13 +935,15 @@ static NV_STATUS FinnNv01Device0FbSerialize(NvU64 message, const char *src, NvU8 } } -static NV_STATUS FinnNv01Device0FbDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsDeserialize(src, src_max, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlFbGetCapsParamsDeserialize(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -683,21 +952,9 @@ static NV_STATUS FinnNv01Device0FbDeserialize(NvU8 **src, const NvU8 *src_max, F } } -static NvU64 FinnNv01Device0FbGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): @@ -707,17 +964,19 @@ static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0FifoSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsSerialize((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlFifoGetCapsParamsSerialize((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsSerialize((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlFifoStartSelectedChannelsParamsSerialize((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsSerialize((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlFifoGetChannellistParamsSerialize((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -726,17 +985,19 @@ static NV_STATUS FinnNv01Device0FifoSerialize(NvU64 message, const char *src, Nv } } -static NV_STATUS FinnNv01Device0FifoDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsDeserialize(src, src_max, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlFifoGetCapsParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(src, src_max, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsDeserialize(src, src_max, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlFifoGetChannellistParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -745,25 +1006,9 @@ static NV_STATUS FinnNv01Device0FifoDeserialize(NvU8 **src, const NvU8 *src_max, } } -static NvU64 FinnNv01Device0FifoGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): @@ -777,13 +1022,15 @@ static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0GpuSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsSerialize((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlGpuGetClasslistParamsSerialize((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -792,13 +1039,15 @@ static NV_STATUS FinnNv01Device0GpuSerialize(NvU64 message, const char *src, NvU } } -static NV_STATUS FinnNv01Device0GpuDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsDeserialize(src, src_max, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlGpuGetClasslistParamsDeserialize(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -807,21 +1056,9 @@ static NV_STATUS FinnNv01Device0GpuDeserialize(NvU8 **src, const NvU8 *src_max, } } -static NvU64 FinnNv01Device0GpuGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): @@ -831,13 +1068,15 @@ static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0GrSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsSerialize((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlGrGetCapsParamsSerialize((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -846,13 +1085,15 @@ static NV_STATUS FinnNv01Device0GrSerialize(NvU64 message, const char *src, NvU8 } } -static NV_STATUS FinnNv01Device0GrDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsDeserialize(src, src_max, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlGrGetCapsParamsDeserialize(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -861,21 +1102,9 @@ static NV_STATUS FinnNv01Device0GrDeserialize(NvU8 **src, const NvU8 *src_max, F } } -static NvU64 FinnNv01Device0GrGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): @@ -885,13 +1114,15 @@ static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0HostSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsSerialize((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlHostGetCapsParamsSerialize((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -900,13 +1131,15 @@ static NV_STATUS FinnNv01Device0HostSerialize(NvU64 message, const char *src, Nv } } -static NV_STATUS FinnNv01Device0HostDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsDeserialize(src, src_max, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlHostGetCapsParamsDeserialize(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -915,21 +1148,9 @@ static NV_STATUS FinnNv01Device0HostDeserialize(NvU8 **src, const NvU8 *src_max, } } -static NvU64 FinnNv01Device0HostGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): @@ -939,13 +1160,15 @@ static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv01Device0MsencSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsSerialize((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv0080CtrlMsencGetCapsParamsSerialize((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -954,13 +1177,15 @@ static NV_STATUS FinnNv01Device0MsencSerialize(NvU64 message, const char *src, N } } -static NV_STATUS FinnNv01Device0MsencDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsDeserialize(src, src_max, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv0080CtrlMsencGetCapsParamsDeserialize(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -969,21 +1194,9 @@ static NV_STATUS FinnNv01Device0MsencDeserialize(NvU8 **src, const NvU8 *src_max } } -static NvU64 FinnNv01Device0MsencGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): @@ -993,13 +1206,15 @@ static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0CeSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsSerialize((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlCeGetCapsParamsSerialize((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1008,13 +1223,15 @@ static NV_STATUS FinnNv20Subdevice0CeSerialize(NvU64 message, const char *src, N } } -static NV_STATUS FinnNv20Subdevice0CeDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsDeserialize(src, src_max, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlCeGetCapsParamsDeserialize(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1023,21 +1240,9 @@ static NV_STATUS FinnNv20Subdevice0CeDeserialize(NvU8 **src, const NvU8 *src_max } } -static NvU64 FinnNv20Subdevice0CeGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): @@ -1047,15 +1252,17 @@ static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0GpuSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlGpuGetEnginesParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlGpuGetEngineClasslistParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1064,15 +1271,17 @@ static NV_STATUS FinnNv20Subdevice0GpuSerialize(NvU64 message, const char *src, } } -static NV_STATUS FinnNv20Subdevice0GpuDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsDeserialize(src, src_max, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlGpuGetEnginesParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(src, src_max, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1081,23 +1290,9 @@ static NV_STATUS FinnNv20Subdevice0GpuDeserialize(NvU8 **src, const NvU8 *src_ma } } -static NvU64 FinnNv20Subdevice0GpuGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): @@ -1109,13 +1304,15 @@ static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0I2cSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsSerialize((const NV2080_CTRL_I2C_ACCESS_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlI2cAccessParamsSerialize((const NV2080_CTRL_I2C_ACCESS_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1124,13 +1321,15 @@ static NV_STATUS FinnNv20Subdevice0I2cSerialize(NvU64 message, const char *src, } } -static NV_STATUS FinnNv20Subdevice0I2cDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsDeserialize(src, src_max, (NV2080_CTRL_I2C_ACCESS_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlI2cAccessParamsDeserialize(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1139,21 +1338,9 @@ static NV_STATUS FinnNv20Subdevice0I2cDeserialize(NvU8 **src, const NvU8 *src_ma } } -static NvU64 FinnNv20Subdevice0I2cGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): @@ -1163,13 +1350,15 @@ static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0NvdSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsSerialize((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlNvdGetDumpParamsSerialize((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1178,13 +1367,15 @@ static NV_STATUS FinnNv20Subdevice0NvdSerialize(NvU64 message, const char *src, } } -static NV_STATUS FinnNv20Subdevice0NvdDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsDeserialize(src, src_max, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlNvdGetDumpParamsDeserialize(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1193,21 +1384,9 @@ static NV_STATUS FinnNv20Subdevice0NvdDeserialize(NvU8 **src, const NvU8 *src_ma } } -static NvU64 FinnNv20Subdevice0NvdGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): @@ -1217,13 +1396,15 @@ static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0PerfSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesSerialize((const NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) src, dst, dst_max, seri_up, FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF), FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM)); + return Nv2080CtrlGpumonSamplesSerialize((const NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1232,13 +1413,15 @@ static NV_STATUS FinnNv20Subdevice0PerfSerialize(NvU64 message, const char *src, } } -static NV_STATUS FinnNv20Subdevice0PerfDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesDeserialize(src, src_max, (NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) dst, dst_size, deser_up); + return Nv2080CtrlGpumonSamplesDeserialize(bp, (NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1247,21 +1430,9 @@ static NV_STATUS FinnNv20Subdevice0PerfDeserialize(NvU8 **src, const NvU8 *src_m } } -static NvU64 FinnNv20Subdevice0PerfGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): @@ -1271,13 +1442,15 @@ static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv20Subdevice0RcSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsSerialize((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) src, dst, dst_max, seri_up); + return Nv2080CtrlRcReadVirtualMemParamsSerialize((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1286,13 +1459,15 @@ static NV_STATUS FinnNv20Subdevice0RcSerialize(NvU64 message, const char *src, N } } -static NV_STATUS FinnNv20Subdevice0RcDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsDeserialize(src, src_max, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) dst, dst_size, deser_up); + return Nv2080CtrlRcReadVirtualMemParamsDeserialize(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1301,21 +1476,9 @@ static NV_STATUS FinnNv20Subdevice0RcDeserialize(NvU8 **src, const NvU8 *src_max } } -static NvU64 FinnNv20Subdevice0RcGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): @@ -1325,15 +1488,17 @@ static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnNv40I2cI2cSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsSerialize((const NV402C_CTRL_I2C_INDEXED_PARAMS *) src, dst, dst_max, seri_up); + return Nv402cCtrlI2cIndexedParamsSerialize((const NV402C_CTRL_I2C_INDEXED_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsSerialize((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) src, dst, dst_max, seri_up); + return Nv402cCtrlI2cTransactionParamsSerialize((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1342,15 +1507,17 @@ static NV_STATUS FinnNv40I2cI2cSerialize(NvU64 message, const char *src, NvU8 ** } } -static NV_STATUS FinnNv40I2cI2cDeserialize(NvU8 **src, const NvU8 *src_max, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsDeserialize(src, src_max, (NV402C_CTRL_I2C_INDEXED_PARAMS *) dst, dst_size, deser_up); + return Nv402cCtrlI2cIndexedParamsDeserialize(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsDeserialize(src, src_max, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) dst, dst_size, deser_up); + return Nv402cCtrlI2cTransactionParamsDeserialize(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1359,23 +1526,9 @@ static NV_STATUS FinnNv40I2cI2cDeserialize(NvU8 **src, const NvU8 *src_max, FINN } } -static NvU64 FinnNv40I2cI2cGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): @@ -1387,15 +1540,17 @@ static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnGt200DebuggerDebugSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) src, dst, dst_max, seri_up); + return Nv83deCtrlDebugReadMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) src, dst, dst_max, seri_up); + return Nv83deCtrlDebugWriteMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1404,15 +1559,17 @@ static NV_STATUS FinnGt200DebuggerDebugSerialize(NvU64 message, const char *src, } } -static NV_STATUS FinnGt200DebuggerDebugDeserialize(NvU8 **src, const NvU8 *src_max, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsDeserialize(src, src_max, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) dst, dst_size, deser_up); + return Nv83deCtrlDebugReadMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsDeserialize(src, src_max, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) dst, dst_size, deser_up); + return Nv83deCtrlDebugWriteMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1421,23 +1578,9 @@ static NV_STATUS FinnGt200DebuggerDebugDeserialize(NvU8 **src, const NvU8 *src_m } } -static NvU64 FinnGt200DebuggerDebugGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): @@ -1449,15 +1592,21 @@ static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message) } } -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerialize(NvU64 message, const char *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsSerialize((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) src, dst, dst_max, seri_up); + return Nvb06fCtrlGetEngineCtxDataParamsSerialize((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) src, dst, dst_max, seri_up); + return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return Nvb06fCtrlSaveEngineCtxDataParamsSerialize((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1466,15 +1615,21 @@ static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerialize(NvU64 message, const c } } -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserialize(NvU8 **src, const NvU8 *src_max, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up) { - // Forward to message-specific routine - switch (((NvU64 *)(*src))[3]) + // Forward to message-specific routine. + switch (message) { case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsDeserialize(src, src_max, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); + return Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(src, src_max, (NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); + return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); + + // Everything else is unsupported. default: { FINN_ERROR(NV_ERR_NOT_SUPPORTED); @@ -1483,72 +1638,44 @@ static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserialize(NvU8 **src, const Nv } } -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetSerializedSize(NvU64 message, const NvP64 src) -{ - // Forward to message-specific routine - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsGetSerializedSize(NvP64_VALUE(src)); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsGetSerializedSize(NvP64_VALUE(src)); - default: - return 0; - } -} - static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message) { - // Forward to message-specific routine + // Forward to message-specific routine. switch (message) { case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): return sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); default: return 0; } } -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0000CtrlNvdGetDumpParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->component + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->component, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x6; // Interface ID - header->message = 0x2; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->component, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->size, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; if (src->size < 0 || src->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) { @@ -1557,68 +1684,69 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->size, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pBuffer); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pBuffer), 1); + // Skip if pointer is null. if (src->pBuffer) { - FINN_MEMCPY_TO_BUFFER(pos, src->pBuffer, (src->size)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->size); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pBuffer) + FINN_FREE(src->pBuffer); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->component - // Static size fields - FINN_COPY_FROM_BUFFER(dst->component, pos, NvU32, 4); - - FINN_COPY_FROM_BUFFER(dst->size, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->size < 0 || dst->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -1626,30 +1754,40 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *s goto exit; } - pos += 4; - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pBuffer, pos, (dst->size)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->size)) > src_max || - pos + ((dst->size)) < pos) + dst->pBuffer = FINN_MALLOC((dst->size)); + if (!dst->pBuffer) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pBuffer, pos, NvP64, (dst->size)); + FINN_MEMZERO(dst->pBuffer, (dst->size)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pBuffer) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->size); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -1658,368 +1796,290 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *s dst->pBuffer = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0000CtrlNvdGetDumpParamsGetSerializedSize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src) + +static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pBuffer) + // Statically sized fields + // No range check for src->physAddr + // Deserialize 8-byte NvU64 object. + if (finn_write_buffer(bp, src->physAddr, 8 * 8)) { - size += (src->size); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlDmaUpdatePde2PageTableParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->numEntries + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->numEntries, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->physAddr, NvU64, 8); - FINN_COPY_TO_BUFFER(pos, src->numEntries, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->aperture, NvU32, 4); + // No range check for src->aperture + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->aperture, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 8-byte NvU64 object. + dst->physAddr = (NvU64) finn_read_buffer(bp, 8 * 8); + // No range check for dst->physAddr - // Static size fields - FINN_COPY_FROM_BUFFER(dst->physAddr, pos, NvU64, 8); - FINN_COPY_FROM_BUFFER(dst->numEntries, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->numEntries = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->numEntries - FINN_COPY_FROM_BUFFER(dst->aperture, pos, NvU32, 4); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 4-byte NvU32 object. + dst->aperture = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->aperture - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlDmaUpdatePde2PageTableParamsGetSerializedSize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 56; -} -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlDmaUpdatePde2ParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x3f; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->pdeIndex + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->pdeIndex, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8018; // Interface ID - header->message = 0xf; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x3f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // No range check for src->flags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->flags, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->pdeIndex, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->flags, NvU32, 4); + // No range check for src->hVASpace + // Deserialize 4-byte NvHandle object. + if (finn_write_buffer(bp, src->hVASpace, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->hVASpace, NvHandle, 4); - FINN_COPY_TO_BUFFER(pos, src->subDeviceId, NvU32, 4); + // No range check for src->subDeviceId + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->subDeviceId, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Bounded nested fields for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(&src->ptParams[i], &pos, dst_max, seri_up); + status = Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(&src->ptParams[i], bp, seri_up); if (status != NV_OK) goto exit; } // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pPdeBuffer); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pPdeBuffer), 1); + // Skip if pointer is null. if (src->pPdeBuffer) { - FINN_MEMCPY_TO_BUFFER(pos, src->pPdeBuffer, 8); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 8-byte NvU64 element. + for (NvU64 j = 0; j < 1; ++j) + { + finn_write_buffer(bp, ((NvU64 *) NvP64_VALUE(src->pPdeBuffer))[j], 8 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pPdeBuffer) + FINN_FREE(src->pPdeBuffer); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->pdeIndex = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->pdeIndex + - // Static size fields - FINN_COPY_FROM_BUFFER(dst->pdeIndex, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->flags - FINN_COPY_FROM_BUFFER(dst->flags, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->hVASpace, pos, NvHandle, 4); + // Deserialize 4-byte NvHandle object. + dst->hVASpace = (NvHandle) finn_read_buffer(bp, 4 * 8); + // No range check for dst->hVASpace - FINN_COPY_FROM_BUFFER(dst->subDeviceId, pos, NvU32, 4); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 4-byte NvU32 object. + dst->subDeviceId = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->subDeviceId + // Bounded nested fields for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(&pos, src_max, &dst->ptParams[i], dst_size, deser_up); + status = Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(bp, &dst->ptParams[i], dst_size, deser_up); if (status != NV_OK) goto exit; } // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pPdeBuffer, pos, 8); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - FINN_SET_PTR_TO_BUFFER(dst->pPdeBuffer, pos, NvP64, 8); + dst->pPdeBuffer = FINN_MALLOC(8); + if (!dst->pPdeBuffer) + { + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); + goto exit; + } + + FINN_MEMZERO(dst->pPdeBuffer, 8); } - } - else - { - if (!deser_up) - dst->pPdeBuffer = NULL; - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Otherwise the pointer must be provided. + else if (!dst->pPdeBuffer) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) + // Deserialize each 8-byte NvU64 element. + for (NvU64 j = 0; j < 1; ++j) + { + ((NvU64 *) NvP64_VALUE(dst->pPdeBuffer))[j] = (NvU64) finn_read_buffer(bp, 8 * 8); + } + } + else { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; + if (!deser_up) + dst->pPdeBuffer = NULL; } exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlDmaUpdatePde2ParamsGetSerializedSize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 168; - - // Add sizes that require runtime calculation - size += 112; - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->pPdeBuffer) - { - size += 8; - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlFbGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) - { - status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8013; // Interface ID - header->message = 0x1; // Message ID + uint64_t field_presence_mask; // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + // Statically sized fields if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -2027,66 +2087,64 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAP goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -2094,30 +2152,40 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(NvU8 **src, const NvU8 *sr goto exit; } - pos += 4; - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -2126,81 +2194,22 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(NvU8 **src, const NvU8 *sr dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlFbGetCapsParamsGetSerializedSize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlFifoGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) - { - status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8017; // Interface ID - header->message = 0x1; // Message ID + uint64_t field_presence_mask; // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + // Statically sized fields if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -2208,66 +2217,64 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -2275,30 +2282,40 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(NvU8 **src, const NvU8 * goto exit; } - pos += 4; - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -2307,199 +2324,114 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(NvU8 **src, const NvU8 * dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlFifoGetCapsParamsGetSerializedSize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlFifoChannelGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x1; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->hChannel + // Deserialize 4-byte NvHandle object. + if (finn_write_buffer(bp, src->hChannel, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x1; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->hChannel, NvHandle, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->hChannel, pos, NvHandle, 4); + // Statically sized fields + // Deserialize 4-byte NvHandle object. + dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); + // No range check for dst->hChannel - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlFifoChannelGetSerializedSize(const NV0080_CTRL_FIFO_CHANNEL *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 48; -} -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlFifoStartSelectedChannelsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->fifoStartChannelListSize + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->fifoStartChannelListSize, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8017; // Interface ID - header->message = 0x5; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->fifoStartChannelListSize, NvU32, 4); - - FINN_MEMCPY_TO_BUFFER(pos, src->channelHandle, 32); + for (NvU64 i = 0; i < (8); ++i) + { + // No range check for src->channelHandle[i] + // Deserialize 4-byte NvHandle object. + if (finn_write_buffer(bp, src->channelHandle[i], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->fifoStartChannelList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->fifoStartChannelList), 1); + // Skip if pointer is null. if (src->fifoStartChannelList) { - // Align - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - for (NvU64 i = 0; i < (src->fifoStartChannelListSize); ++i) { - status = Nv0080CtrlFifoChannelSerialize(&(((const NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(src->fifoStartChannelList)))[i]), &pos, dst_max, seri_up); + status = Nv0080CtrlFifoChannelSerialize(&(((const NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(src->fifoStartChannelList)))[i]), bp, seri_up); if (status != NV_OK) goto exit; @@ -2511,77 +2443,66 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080 } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->fifoStartChannelListSize = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->fifoStartChannelListSize - // Static size fields - FINN_COPY_FROM_BUFFER(dst->fifoStartChannelListSize, pos, NvU32, 4); - FINN_MEMCPY_FROM_BUFFER(dst->channelHandle, pos, 32); + for (NvU64 i = 0; i < (8); ++i) + { + // Deserialize 4-byte NvHandle object. + dst->channelHandle[i] = (NvHandle) finn_read_buffer(bp, 4 * 8); + // No range check for dst->channelHandle[i] + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - // Align - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Caller must set up the pointers when deserializing down. if (!deser_up) { - // Variable element size - NvU64 element_size = Nv0080CtrlFifoChannelGetSerializedSize(NvP64_VALUE(dst->fifoStartChannelList)); - - // Validate variable length buffer length - if (element_size * (dst->fifoStartChannelListSize) < element_size || - pos + (element_size * (dst->fifoStartChannelListSize)) > src_max || - pos + (element_size * (dst->fifoStartChannelListSize)) < pos) + // Data-presence indicator should be false if empty. + // Check for integer overflow in the element size variable. + if ((dst->fifoStartChannelListSize) < 1 || + (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize)) < sizeof(NV0080_CTRL_FIFO_CHANNEL)) { status = NV_ERR_BUFFER_TOO_SMALL; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // FINN-generated code allocates memory and sets pointer when deserializing down. + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) dst->fifoStartChannelList = FINN_MALLOC((sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize))); if (!dst->fifoStartChannelList) { @@ -2591,7 +2512,6 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(NvU8 **src } FINN_MEMZERO(dst->fifoStartChannelList, (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize))); - } // Otherwise the pointer must be provided. @@ -2605,13 +2525,13 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(NvU8 **src for (NvU64 i = 0; i < (dst->fifoStartChannelListSize); ++i) { // Deserialize each element. - status = Nv0080CtrlFifoChannelDeserialize(&pos, src_max, &(((NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(dst->fifoStartChannelList)))[i]), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); + status = Nv0080CtrlFifoChannelDeserialize(bp, &(((NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(dst->fifoStartChannelList)))[i]), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); if (status != NV_OK) goto exit; } } - // Data is not present, set to NULL. + // Data is not present; set to NULL. else { if (!deser_up) @@ -2619,167 +2539,134 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(NvU8 **src } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlFifoStartSelectedChannelsParamsGetSerializedSize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 80; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - // For non-NULL pointers, proceed to size calculation. - if (src->fifoStartChannelList) - { - // Alignment - size = (size + 7) & ~7; - size += Nv0080CtrlFifoChannelGetSerializedSize((const NV0080_CTRL_FIFO_CHANNEL *) src->fifoStartChannelList) * ((src->fifoStartChannelListSize)); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlFifoGetChannellistParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->numChannels + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->numChannels, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8017; // Interface ID - header->message = 0xd; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->numChannels, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pChannelHandleList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pChannelHandleList), 1); + // Skip if pointer is null. if (src->pChannelHandleList) { - FINN_MEMCPY_TO_BUFFER(pos, src->pChannelHandleList, (src->numChannels) * 4); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (src->numChannels); ++j) + { + finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelHandleList))[j], 4 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pChannelHandleList) + FINN_FREE(src->pChannelHandleList); + } - // Set data presence byte - *(pos++) = !!(src->pChannelList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pChannelList), 1); + // Skip if pointer is null. if (src->pChannelList) { - FINN_MEMCPY_TO_BUFFER(pos, src->pChannelList, (src->numChannels) * 4); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (src->numChannels); ++j) + { + finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelList))[j], 4 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pChannelList) + FINN_FREE(src->pChannelList); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->numChannels = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->numChannels - // Static size fields - FINN_COPY_FROM_BUFFER(dst->numChannels, pos, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pChannelHandleList, pos, (dst->numChannels) * 4); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if ((dst->numChannels) * 4 < 4 || - pos + ((dst->numChannels) * 4) > src_max || - pos + ((dst->numChannels) * 4) < pos) + dst->pChannelHandleList = FINN_MALLOC((dst->numChannels) * 4); + if (!dst->pChannelHandleList) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pChannelHandleList, pos, NvP64, (dst->numChannels) * 4); + FINN_MEMZERO(dst->pChannelHandleList, (dst->numChannels) * 4); + } + + // Otherwise the pointer must be provided. + else if (!dst->pChannelHandleList) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (dst->numChannels); ++j) + { + ((NvU32 *) NvP64_VALUE(dst->pChannelHandleList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); } } else @@ -2788,27 +2675,37 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(NvU8 **src, const dst->pChannelHandleList = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pChannelList, pos, (dst->numChannels) * 4); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if ((dst->numChannels) * 4 < 4 || - pos + ((dst->numChannels) * 4) > src_max || - pos + ((dst->numChannels) * 4) < pos) + dst->pChannelList = FINN_MALLOC((dst->numChannels) * 4); + if (!dst->pChannelList) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pChannelList, pos, NvP64, (dst->numChannels) * 4); + FINN_MEMZERO(dst->pChannelList, (dst->numChannels) * 4); + } + + // Otherwise the pointer must be provided. + else if (!dst->pChannelList) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (dst->numChannels); ++j) + { + ((NvU32 *) NvP64_VALUE(dst->pChannelList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); } } else @@ -2817,166 +2714,116 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(NvU8 **src, const dst->pChannelList = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlFifoGetChannellistParamsGetSerializedSize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->pChannelHandleList) - { - size += (src->numChannels) * 4; - } - - // Add padding - size = (size + 7) &~ 7; - - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->pChannelList) - { - size += (src->numChannels) * 4; - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlGpuGetClasslistParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->numClasses + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->numClasses, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8002; // Interface ID - header->message = 0x1; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->numClasses, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->classList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->classList), 1); + // Skip if pointer is null. if (src->classList) { - FINN_MEMCPY_TO_BUFFER(pos, src->classList, (src->numClasses) * 4); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (src->numClasses); ++j) + { + finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->classList) + FINN_FREE(src->classList); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->numClasses - // Static size fields - FINN_COPY_FROM_BUFFER(dst->numClasses, pos, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->classList, pos, (dst->numClasses) * 4); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if ((dst->numClasses) * 4 < 4 || - pos + ((dst->numClasses) * 4) > src_max || - pos + ((dst->numClasses) * 4) < pos) + dst->classList = FINN_MALLOC((dst->numClasses) * 4); + if (!dst->classList) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->classList, pos, NvP64, (dst->numClasses) * 4); + FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); + } + + // Otherwise the pointer must be provided. + else if (!dst->classList) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (dst->numClasses); ++j) + { + ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); } } else @@ -2985,153 +2832,116 @@ static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(NvU8 **src, const Nv dst->classList = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlGpuGetClasslistParamsGetSerializedSize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->classList) - { - size += (src->numClasses) * 4; - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlGrGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->capsTblSize + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8011; // Interface ID - header->message = 0x2; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->capsTblSize - // Static size fields - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -3140,81 +2950,22 @@ static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(NvU8 **src, const NvU8 *sr dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlGrGetCapsParamsGetSerializedSize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlHostGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) - { - status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x8014; // Interface ID - header->message = 0x1; // Message ID + uint64_t field_presence_mask; // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + // Statically sized fields if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -3222,66 +2973,64 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -3289,30 +3038,40 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(NvU8 **src, const NvU8 * goto exit; } - pos += 4; - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -3321,81 +3080,22 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(NvU8 **src, const NvU8 * dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlHostGetCapsParamsGetSerializedSize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv0080CtrlMsencGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) - { - status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x801b; // Interface ID - header->message = 0x1; // Message ID + uint64_t field_presence_mask; // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + // Statically sized fields if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -3403,66 +3103,64 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_G goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -3470,30 +3168,40 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(NvU8 **src, const NvU8 goto exit; } - pos += 4; - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -3502,82 +3210,31 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(NvU8 **src, const NvU8 dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv0080CtrlMsencGetCapsParamsGetSerializedSize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlCeGetCapsParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->ceEngineType + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->ceEngineType, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x20802a; // Interface ID - header->message = 0x1; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->ceEngineType, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->capsTblSize, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; if (src->capsTblSize < 0 || src->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) { @@ -3586,68 +3243,69 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP goto exit; } - pos += 4; - + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->capsTbl); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->capsTbl), 1); + // Skip if pointer is null. if (src->capsTbl) { - FINN_MEMCPY_TO_BUFFER(pos, src->capsTbl, (src->capsTblSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->capsTblSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + } -exit: - *dst = pos; + // Free memory that was allocated during downward deserialization. + if (seri_up && src->capsTbl) + FINN_FREE(src->capsTbl); + } + + goto exit; // Suppress potential not-used warning +exit: return status; } -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->ceEngineType, pos, NvU32, 4); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->ceEngineType = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->ceEngineType - FINN_COPY_FROM_BUFFER(dst->capsTblSize, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->capsTblSize < 0 || dst->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; @@ -3655,30 +3313,40 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(NvU8 **src, const NvU8 *sr goto exit; } - pos += 4; - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->capsTbl, pos, (dst->capsTblSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->capsTblSize)) > src_max || - pos + ((dst->capsTblSize)) < pos) + dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); + if (!dst->capsTbl) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->capsTbl, pos, NvP64, (dst->capsTblSize)); + FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->capsTbl) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->capsTblSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -3687,154 +3355,116 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(NvU8 **src, const NvU8 *sr dst->capsTbl = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlCeGetCapsParamsGetSerializedSize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->capsTbl) - { - size += (src->capsTblSize); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlGpuGetEnginesParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->engineCount + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->engineCount, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x208001; // Interface ID - header->message = 0x23; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->engineCount, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->engineList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->engineList), 1); + // Skip if pointer is null. if (src->engineList) { - FINN_MEMCPY_TO_BUFFER(pos, src->engineList, (src->engineCount) * 4); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (src->engineCount); ++j) + { + finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->engineList))[j], 4 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->engineList) + FINN_FREE(src->engineList); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->engineCount, pos, NvU32, 4); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->engineCount = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->engineCount - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->engineList, pos, (dst->engineCount) * 4); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if ((dst->engineCount) * 4 < 4 || - pos + ((dst->engineCount) * 4) > src_max || - pos + ((dst->engineCount) * 4) < pos) + dst->engineList = FINN_MALLOC((dst->engineCount) * 4); + if (!dst->engineList) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->engineList, pos, NvP64, (dst->engineCount) * 4); + FINN_MEMZERO(dst->engineList, (dst->engineCount) * 4); + } + + // Otherwise the pointer must be provided. + else if (!dst->engineList) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (dst->engineCount); ++j) + { + ((NvU32 *) NvP64_VALUE(dst->engineList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); } } else @@ -3843,158 +3473,131 @@ static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(NvU8 **src, const NvU8 dst->engineList = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlGpuGetEnginesParamsGetSerializedSize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src) + +static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->engineList) + // Statically sized fields + // No range check for src->engineType + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->engineType, 4 * 8)) { - size += (src->engineCount) * 4; + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlGpuGetEngineClasslistParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->numClasses + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->numClasses, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x208001; // Interface ID - header->message = 0x24; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->engineType, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->numClasses, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->classList); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->classList), 1); + // Skip if pointer is null. if (src->classList) { - FINN_MEMCPY_TO_BUFFER(pos, src->classList, (src->numClasses) * 4); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (src->numClasses); ++j) + { + finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->classList) + FINN_FREE(src->classList); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->engineType = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->engineType - // Static size fields - FINN_COPY_FROM_BUFFER(dst->engineType, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->numClasses, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->numClasses - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->classList, pos, (dst->numClasses) * 4); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if ((dst->numClasses) * 4 < 4 || - pos + ((dst->numClasses) * 4) > src_max || - pos + ((dst->numClasses) * 4) < pos) + dst->classList = FINN_MALLOC((dst->numClasses) * 4); + if (!dst->classList) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->classList, pos, NvP64, (dst->numClasses) * 4); + FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); + } + + // Otherwise the pointer must be provided. + else if (!dst->classList) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 4-byte NvU32 element. + for (NvU64 j = 0; j < (dst->numClasses); ++j) + { + ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); } } else @@ -4003,165 +3606,161 @@ static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(NvU8 **src, co dst->classList = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlGpuGetEngineClasslistParamsGetSerializedSize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src) + +static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x1f; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->classList) + // Statically sized fields + // No range check for src->bufSize + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->bufSize, 4 * 8)) { - size += (src->numClasses) * 4; + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up, NvU64 interface, NvU64 message) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlGpumonSamplesGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->count + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->count, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = interface; // Interface ID - header->message = message; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x1f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->bufSize, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->count, NvU32, 4); + // No range check for src->tracker + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->tracker, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->tracker, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->type, NvU8, 1); + // No range check for src->type + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->type, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pSamples); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pSamples), 1); + // Skip if pointer is null. if (src->pSamples) { - FINN_MEMCPY_TO_BUFFER(pos, src->pSamples, (src->bufSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->bufSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pSamples))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pSamples) + FINN_FREE(src->pSamples); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->bufSize = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->bufSize + + + // Deserialize 4-byte NvU32 object. + dst->count = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->count - // Static size fields - FINN_COPY_FROM_BUFFER(dst->bufSize, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->count, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->tracker = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->tracker - FINN_COPY_FROM_BUFFER(dst->tracker, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->type, pos, NvU8, 1); + // Deserialize 1-byte NvU8 object. + dst->type = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->type - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pSamples, pos, (dst->bufSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->bufSize)) > src_max || - pos + ((dst->bufSize)) < pos) + dst->pSamples = FINN_MALLOC((dst->bufSize)); + if (!dst->pSamples) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pSamples, pos, NvP64, (dst->bufSize)); + FINN_MEMZERO(dst->pSamples, (dst->bufSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pSamples) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->bufSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pSamples))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -4170,90 +3769,71 @@ static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(NvU8 **src, const NvU8 *src_ dst->pSamples = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlGpumonSamplesGetSerializedSize(const NV2080_CTRL_GPUMON_SAMPLES *src) + +static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 56; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x1ff; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pSamples) + // Statically sized fields + // No range check for src->token + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->token, 4 * 8)) { - size += (src->bufSize); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlI2cAccessParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->cmd + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->cmd, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x208006; // Interface ID - header->message = 0x10; // Message ID - // Field bitmasks - header->fieldMask[0] = 0x1ff; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->token, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->cmd, NvU32, 4); + // No range check for src->port + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->port, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->port, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->flags, NvU32, 4); + // No range check for src->flags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->flags, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->status, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->dataBuffSize, NvU32, 4); + // No range check for src->status + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->status, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Range validation, rewind buffer - pos -= 4; if (src->dataBuffSize < 0 || src->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) { @@ -4262,80 +3842,109 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS goto exit; } - pos += 4; + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->dataBuffSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + + // No range check for src->speed + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->speed, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->speed, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->encrClientID, NvU32, 4); + // No range check for src->encrClientID + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->encrClientID, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->data); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->data), 1); + // Skip if pointer is null. if (src->data) { - FINN_MEMCPY_TO_BUFFER(pos, src->data, (src->dataBuffSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->dataBuffSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->data))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->data) + FINN_FREE(src->data); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1ff) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1ff) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->token = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->token + + + // Deserialize 4-byte NvU32 object. + dst->cmd = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->cmd - // Static size fields - FINN_COPY_FROM_BUFFER(dst->token, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->cmd, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->port = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->port - FINN_COPY_FROM_BUFFER(dst->port, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->flags, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->flags - FINN_COPY_FROM_BUFFER(dst->status, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->dataBuffSize, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->status = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->status - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->dataBuffSize = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->dataBuffSize < 0 || dst->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) { status = NV_ERR_OUT_OF_RANGE; @@ -4343,193 +3952,183 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(NvU8 **src, const NvU8 *sr goto exit; } - pos += 4; - FINN_COPY_FROM_BUFFER(dst->speed, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->speed = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->speed - FINN_COPY_FROM_BUFFER(dst->encrClientID, pos, NvU32, 4); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 4-byte NvU32 object. + dst->encrClientID = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->encrClientID + // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->data, pos, (dst->dataBuffSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->dataBuffSize)) > src_max || - pos + ((dst->dataBuffSize)) < pos) + dst->data = FINN_MALLOC((dst->dataBuffSize)); + if (!dst->data) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->data, pos, NvP64, (dst->dataBuffSize)); + FINN_MEMZERO(dst->data, (dst->dataBuffSize)); } - } - else - { - if (!deser_up) - dst->data = NULL; - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Otherwise the pointer must be provided. + else if (!dst->data) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->dataBuffSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->data))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); + } + } + else { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; + if (!deser_up) + dst->data = NULL; } exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlI2cAccessParamsGetSerializedSize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src) + +static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 72; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->data) + // Statically sized fields + // No range check for src->component + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->component, 4 * 8)) { - size += (src->dataBuffSize); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlNvdGetDumpParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->size + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->size, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x208024; // Interface ID - header->message = 0x2; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->component, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->size, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pBuffer); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pBuffer), 1); + // Skip if pointer is null. if (src->pBuffer) { - FINN_MEMCPY_TO_BUFFER(pos, src->pBuffer, (src->size)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->size); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pBuffer) + FINN_FREE(src->pBuffer); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->component - // Static size fields - FINN_COPY_FROM_BUFFER(dst->component, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->size, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->size - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pBuffer, pos, (dst->size)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->size)) > src_max || - pos + ((dst->size)) < pos) + dst->pBuffer = FINN_MALLOC((dst->size)); + if (!dst->pBuffer) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pBuffer, pos, NvP64, (dst->size)); + FINN_MEMZERO(dst->pBuffer, (dst->size)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pBuffer) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->size); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -4538,161 +4137,146 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(NvU8 **src, const NvU8 *s dst->pBuffer = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlNvdGetDumpParamsGetSerializedSize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src) + +static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0xf; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pBuffer) + // Statically sized fields + // No range check for src->virtAddress + // Deserialize 8-byte NvU64 object. + if (finn_write_buffer(bp, src->virtAddress, 8 * 8)) { - size += (src->size); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv2080CtrlRcReadVirtualMemParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->hChannel + // Deserialize 4-byte NvHandle object. + if (finn_write_buffer(bp, src->hChannel, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x208022; // Interface ID - header->message = 0x4; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0xf; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->virtAddress, NvU64, 8); - - FINN_COPY_TO_BUFFER(pos, src->hChannel, NvHandle, 4); - - FINN_COPY_TO_BUFFER(pos, src->bufferSize, NvU32, 4); + // No range check for src->bufferSize + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->bufferSize, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->bufferPtr); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->bufferPtr), 1); + // Skip if pointer is null. if (src->bufferPtr) { - FINN_MEMCPY_TO_BUFFER(pos, src->bufferPtr, (src->bufferSize)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->bufferSize); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->bufferPtr))[j], 1 * 8); + } + // Free memory that was allocated during downward deserialization. + if (seri_up && src->bufferPtr) + FINN_FREE(src->bufferPtr); + } + + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xf) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xf) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 8-byte NvU64 object. + dst->virtAddress = (NvU64) finn_read_buffer(bp, 8 * 8); + // No range check for dst->virtAddress - // Static size fields - FINN_COPY_FROM_BUFFER(dst->virtAddress, pos, NvU64, 8); - FINN_COPY_FROM_BUFFER(dst->hChannel, pos, NvHandle, 4); + // Deserialize 4-byte NvHandle object. + dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); + // No range check for dst->hChannel - FINN_COPY_FROM_BUFFER(dst->bufferSize, pos, NvU32, 4); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 4-byte NvU32 object. + dst->bufferSize = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->bufferSize + // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->bufferPtr, pos, (dst->bufferSize)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->bufferSize)) > src_max || - pos + ((dst->bufferSize)) < pos) + dst->bufferPtr = FINN_MALLOC((dst->bufferSize)); + if (!dst->bufferPtr) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->bufferPtr, pos, NvP64, (dst->bufferSize)); + FINN_MEMZERO(dst->bufferPtr, (dst->bufferSize)); + } + + // Otherwise the pointer must be provided. + else if (!dst->bufferPtr) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->bufferSize); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->bufferPtr))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -4701,162 +4285,155 @@ static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(NvU8 **src, const N dst->bufferPtr = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv2080CtrlRcReadVirtualMemParamsGetSerializedSize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src) + +static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 56; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0xff; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->bufferPtr) + // Statically sized fields + // No range check for src->flags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->flags, 4 * 8)) { - size += (src->bufferSize); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - return size; -} - -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cIndexedParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; + if (src->indexLength < 0 || src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + status = NV_ERR_OUT_OF_RANGE; + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + goto exit; + } - // Validate buffer size - if (pos + serializedSize > dst_max) + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->indexLength, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x402c01; // Interface ID - header->message = 0x2; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0xff; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->flags, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->indexLength, NvU32, 4); + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Range validation, rewind buffer - pos -= 4; - if (src->indexLength < 0 || src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + // No range check for src->address + // Deserialize 2-byte NvU16 object. + if (finn_write_buffer(bp, src->address, 2 * 8)) { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - pos += 4; - - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); + // No range check for src->portId + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->portId, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->address, NvU16, 2); - FINN_COPY_TO_BUFFER(pos, src->portId, NvU8, 1); + // No range check for src->bIsWrite + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->bIsWrite, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->bIsWrite, NvU8, 1); - FINN_MEMCPY_TO_BUFFER(pos, src->index, 4); + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) + { + // No range check for src->index[i] + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->index[i], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xff) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xff) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->flags, pos, NvU32, 4); - - FINN_COPY_FROM_BUFFER(dst->indexLength, pos, NvU32, 4); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->flags - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->indexLength < 0 || dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; @@ -4864,40 +4441,68 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(NvU8 **src, const NvU8 *s goto exit; } - pos += 4; - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - FINN_COPY_FROM_BUFFER(dst->address, pos, NvU16, 2); - FINN_COPY_FROM_BUFFER(dst->portId, pos, NvU8, 1); + // Deserialize 2-byte NvU16 object. + dst->address = (NvU16) finn_read_buffer(bp, 2 * 8); + // No range check for dst->address - FINN_COPY_FROM_BUFFER(dst->bIsWrite, pos, NvU8, 1); - FINN_MEMCPY_FROM_BUFFER(dst->index, pos, 4); + // Deserialize 1-byte NvU8 object. + dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->portId + + + // Deserialize 1-byte NvU8 object. + dst->bIsWrite = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bIsWrite + + + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) + { + // Deserialize 1-byte NvU8 object. + dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->index[i] + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -4906,505 +4511,300 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(NvU8 **src, const NvU8 *s dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cIndexedParamsGetSerializedSize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 64; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) - { - size += (src->messageLength); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv402cCtrlI2cTransactionTypeValueToId(NvU8 **buf, const NvU8 *buf_max, NvU64 convert_size) +static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id) { - NV402C_CTRL_I2C_TRANSACTION_TYPE *pEnum = NULL; - NvU8 *buf_end = *buf + convert_size; - - // Bounds checking before overwriting data - if (buf_end > buf_max) + switch (id) { - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - return NV_ERR_BUFFER_TOO_SMALL; - } - - // Convert each enum value to its corresponding ID. - while (*buf < buf_end) - { - pEnum = (NV402C_CTRL_I2C_TRANSACTION_TYPE *)*buf; - - switch (*pEnum) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - *pEnum = 0; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - *pEnum = 1; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - *pEnum = 2; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - *pEnum = 3; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - *pEnum = 4; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - *pEnum = 5; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - *pEnum = 6; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - *pEnum = 7; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - *pEnum = 8; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - *pEnum = 9; - break; - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - *pEnum = 10; - break; - default: - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - } - - *buf += sizeof(NV402C_CTRL_I2C_TRANSACTION_TYPE); + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + return NV_OK; // okay } - return NV_OK; + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; } - -static NV_STATUS Nv402cCtrlI2cTransactionTypeIdtoValue(NvU8 **buf, const NvU8 *buf_max, NvU64 convert_size) +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU32 *pID = NULL; - NvU8 *buf_end = *buf + convert_size; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Bounds checking before overwriting data - if (buf_end > buf_max) + // Field bitmasks + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->warFlags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->warFlags, 4 * 8)) { + status = NV_ERR_BUFFER_TOO_SMALL; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - return NV_ERR_BUFFER_TOO_SMALL; - } - - // Convert each ID to its corresponding enum value. - while (*buf < buf_end) - { - pID = (NvU32 *)*buf; - - switch (*pID) - { - case 0: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW; - break; - case 1: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW; - break; - case 2: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW; - break; - case 3: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW; - break; - case 4: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; - break; - case 5: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW; - break; - case 6: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW; - break; - case 7: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL; - break; - case 8: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL; - break; - case 9: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW; - break; - case 10: - *pID = NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC; - break; - default: - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - } - - *buf += sizeof(NvU32); + goto exit; } - return NV_OK; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusQuickRwGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x3; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->warFlags, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->warFlags - // Static size fields - FINN_COPY_FROM_BUFFER(dst->warFlags, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusQuickRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src) -{ - // Suppress used-variable warnings. - (void) src; - // This struct is static and its size is known at compile time. - return 48; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataI2cByteRwGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x3; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x3; - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - - FINN_COPY_TO_BUFFER(pos, src->message, NvU8, 1); + // No range check for src->message + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->message, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); + // Statically sized fields + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - FINN_COPY_FROM_BUFFER(dst->message, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->message - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataI2cByteRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 48; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataI2cBlockRwGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - // Static size fields - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -5413,391 +4813,339 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(NvU8 **src, c dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataI2cBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) + // Statically sized fields + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) { - size += (src->messageLength); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusByteRwGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); - - FINN_COPY_TO_BUFFER(pos, src->message, NvU8, 1); + // No range check for src->message + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->message, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - // Static size fields - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress - FINN_COPY_FROM_BUFFER(dst->message, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->message - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusByteRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 48; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusWordRwGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->message + // Deserialize 2-byte NvU16 object. + if (finn_write_buffer(bp, src->message, 2 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->message, NvU16, 2); + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 2-byte NvU16 object. + dst->message = (NvU16) finn_read_buffer(bp, 2 * 8); + // No range check for dst->message - // Static size fields - FINN_COPY_FROM_BUFFER(dst->message, pos, NvU16, 2); - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusWordRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 48; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataI2cBufferRwGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x1f; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->warFlags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->warFlags, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - // Field bitmasks - header->fieldMask[0] = 0x1f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->warFlags, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->warFlags - // Static size fields - FINN_COPY_FROM_BUFFER(dst->warFlags, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite + + + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -5806,163 +5154,146 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(NvU8 **src, dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataI2cBufferRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 56; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0xf; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) + // Statically sized fields + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) { - size += (src->messageLength); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusBlockRwGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0xf; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xf) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xf) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - // Static size fields - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress + // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -5971,271 +5302,209 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(NvU8 **src, dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) + // Statically sized fields + // No range check for src->writeMessage + // Deserialize 2-byte NvU16 object. + if (finn_write_buffer(bp, src->writeMessage, 2 * 8)) { - size += (src->messageLength); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusProcessCallGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->readMessage + // Deserialize 2-byte NvU16 object. + if (finn_write_buffer(bp, src->readMessage, 2 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->writeMessage, NvU16, 2); - - FINN_COPY_TO_BUFFER(pos, src->readMessage, NvU16, 2); - - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 2-byte NvU16 object. + dst->writeMessage = (NvU16) finn_read_buffer(bp, 2 * 8); + // No range check for dst->writeMessage - // Static size fields - FINN_COPY_FROM_BUFFER(dst->writeMessage, pos, NvU16, 2); - FINN_COPY_FROM_BUFFER(dst->readMessage, pos, NvU16, 2); + // Deserialize 2-byte NvU16 object. + dst->readMessage = (NvU16) finn_read_buffer(bp, 2 * 8); + // No range check for dst->readMessage - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusProcessCallGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 48; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x1f; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + if (src->writeMessageLength < 0 || src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + status = NV_ERR_OUT_OF_RANGE; + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + goto exit; + } - // Validate buffer size - if (pos + serializedSize > dst_max) + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->writeMessageLength, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x1f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->writeMessageLength, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - if (src->writeMessageLength < 0 || src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + if (src->readMessageLength < 0 || src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); goto exit; } - pos += 4; - - - FINN_COPY_TO_BUFFER(pos, src->readMessageLength, NvU32, 4); + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->readMessageLength, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Range validation, rewind buffer - pos -= 4; - if (src->readMessageLength < 0 || src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - pos += 4; + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) + { + // No range check for src->writeMessage[i] + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->writeMessage[i], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); - - FINN_MEMCPY_TO_BUFFER(pos, src->writeMessage, 32); - FINN_MEMCPY_TO_BUFFER(pos, src->readMessage, 32); + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) + { + // No range check for src->readMessage[i] + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->readMessage[i], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->writeMessageLength, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; - + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->writeMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->writeMessageLength < 0 || dst->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; @@ -6243,14 +5512,10 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(Nv goto exit; } - pos += 4; - - FINN_COPY_FROM_BUFFER(dst->readMessageLength, pos, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->readMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->readMessageLength < 0 || dst->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; @@ -6258,81 +5523,54 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(Nv goto exit; } - pos += 4; - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress - FINN_MEMCPY_FROM_BUFFER(dst->writeMessage, pos, 32); - FINN_MEMCPY_FROM_BUFFER(dst->readMessage, pos, 32); + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) + { + // Deserialize 1-byte NvU8 object. + dst->writeMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->writeMessage[i] + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; + // Deserialize 1-byte NvU8 object. + dst->readMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->readMessage[i] } + exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src) -{ - // Suppress used-variable warnings. - (void) src; - - // This struct is static and its size is known at compile time. - return 120; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x3f; + finn_write_buffer(bp, field_presence_mask, 64); - // Validate buffer size - if (pos + serializedSize > dst_max) + // Statically sized fields + // No range check for src->warFlags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->warFlags, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0x3f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->warFlags, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->indexLength, NvU32, 4); - - // Range validation, rewind buffer - pos -= 4; if (src->indexLength < 0 || src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { @@ -6341,74 +5579,102 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial goto exit; } - pos += 4; + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->indexLength, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + + + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); + // No range check for src->bWrite + // Deserialize 1-byte NvBool object. + if (finn_write_buffer(bp, src->bWrite, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->bWrite, NvBool, 1); - FINN_MEMCPY_TO_BUFFER(pos, src->index, 4); + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) + { + // No range check for src->index[i] + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->index[i], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x3f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x3f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_FROM_BUFFER(dst->warFlags, pos, NvU32, 4); - - FINN_COPY_FROM_BUFFER(dst->indexLength, pos, NvU32, 4); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->warFlags - // Range validation, rewind buffer - pos -= 4; + // Deserialize 4-byte NvU32 object. + dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); if (dst->indexLength < 0 || dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; @@ -6416,36 +5682,58 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeseri goto exit; } - pos += 4; - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - FINN_COPY_FROM_BUFFER(dst->bWrite, pos, NvBool, 1); - FINN_MEMCPY_FROM_BUFFER(dst->index, pos, 4); + // Deserialize 1-byte NvBool object. + dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); + // No range check for dst->bWrite + + + for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) + { + // Deserialize 1-byte NvU8 object. + dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->index[i] + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -6454,163 +5742,146 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeseri dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src) + +static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 64; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0xf; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) + // Statically sized fields + // No range check for src->messageLength + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->messageLength, 4 * 8)) { - size += (src->messageLength); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataReadEdidDdcGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->segmentNumber + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->segmentNumber, 1 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // - - // Field bitmasks - header->fieldMask[0] = 0xf; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->messageLength, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->segmentNumber, NvU8, 1); - - FINN_COPY_TO_BUFFER(pos, src->registerAddress, NvU8, 1); + // No range check for src->registerAddress + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pMessage); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pMessage), 1); + // Skip if pointer is null. if (src->pMessage) { - FINN_MEMCPY_TO_BUFFER(pos, src->pMessage, (src->messageLength)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->messageLength); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pMessage) + FINN_FREE(src->pMessage); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xf) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xf) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->messageLength - // Static size fields - FINN_COPY_FROM_BUFFER(dst->messageLength, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->segmentNumber, pos, NvU8, 1); + // Deserialize 1-byte NvU8 object. + dst->segmentNumber = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->segmentNumber - FINN_COPY_FROM_BUFFER(dst->registerAddress, pos, NvU8, 1); - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 1-byte NvU8 object. + dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->registerAddress + // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pMessage, pos, (dst->messageLength)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->messageLength)) > src_max || - pos + ((dst->messageLength)) < pos) + dst->pMessage = FINN_MALLOC((dst->messageLength)); + if (!dst->pMessage) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pMessage, pos, NvP64, (dst->messageLength)); + FINN_MEMZERO(dst->pMessage, (dst->messageLength)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pMessage) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->messageLength); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -6619,83 +5890,27 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(NvU8 **src, dst->pMessage = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataReadEdidDdcGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 48; - - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; - // For non-NULL pointers, proceed to size calculation. - if (src->pMessage) - { - size += (src->messageLength); - } - - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) +static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionDataGetSerializedSize(src, transType); + // Local variables NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) - { - status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - - // - // Non-message type has no interface/message ID - // + uint64_t field_presence_mask; // Field bitmasks - header->fieldMask[0] = 0x7ff; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + field_presence_mask = 0x7ff; + finn_write_buffer(bp, field_presence_mask, 64); // Field copying based on union selector switch (transType) { case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(&src->smbusQuickData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(&src->smbusQuickData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6703,7 +5918,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: { - status = Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(&src->i2cByteData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(&src->i2cByteData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6711,7 +5926,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(&src->smbusByteData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(&src->smbusByteData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6719,7 +5934,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(&src->smbusWordData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(&src->smbusWordData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6727,7 +5942,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(&src->smbusProcessData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(&src->smbusProcessData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6735,7 +5950,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(&src->smbusBlockProcessData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(&src->smbusBlockProcessData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6743,7 +5958,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(&src->i2cBlockData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(&src->i2cBlockData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6751,7 +5966,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(&src->i2cBufferData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(&src->i2cBufferData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6759,7 +5974,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(&src->smbusBlockData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(&src->smbusBlockData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6767,7 +5982,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(&src->smbusMultibyteRegisterData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(&src->smbusMultibyteRegisterData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6775,7 +5990,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(&src->edidData, &pos, dst_max, seri_up); + status = Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(&src->edidData, bp, seri_up); if (status != NV_OK) goto exit; @@ -6789,51 +6004,39 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA } } - // Align - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) + +static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7ff) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7ff) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Field copying based on union selector switch (transType) { case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(&pos, src_max, &dst->smbusQuickData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(bp, &dst->smbusQuickData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6841,7 +6044,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: { - status = Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(&pos, src_max, &dst->i2cByteData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(bp, &dst->i2cByteData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6849,7 +6052,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(&pos, src_max, &dst->smbusByteData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(bp, &dst->smbusByteData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6857,7 +6060,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(&pos, src_max, &dst->smbusWordData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(bp, &dst->smbusWordData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6865,7 +6068,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(&pos, src_max, &dst->smbusProcessData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(bp, &dst->smbusProcessData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6873,7 +6076,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(&pos, src_max, &dst->smbusBlockProcessData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(bp, &dst->smbusBlockProcessData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6881,7 +6084,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(&pos, src_max, &dst->i2cBlockData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(bp, &dst->i2cBlockData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6889,7 +6092,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(&pos, src_max, &dst->i2cBufferData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(bp, &dst->i2cBufferData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6897,7 +6100,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(&pos, src_max, &dst->smbusBlockData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(bp, &dst->smbusBlockData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6905,7 +6108,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(&pos, src_max, &dst->smbusMultibyteRegisterData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(bp, &dst->smbusMultibyteRegisterData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6913,7 +6116,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(&pos, src_max, &dst->edidData, dst_size, deser_up); + status = Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(bp, &dst->edidData, dst_size, deser_up); if (status != NV_OK) goto exit; @@ -6927,370 +6130,268 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(NvU8 **src, const NvU8 } } - // Align - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionDataGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) -{ - // Start with the header size - NvU64 size = 40; - - // Calculate size based on union selector - switch (transType) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - { - size += 48; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - { - size += 48; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - { - size += 48; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - { - size += 48; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - { - size += 48; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - { - size += 120; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - { - size += Nv402cCtrlI2cTransactionDataI2cBlockRwGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *) &(src->i2cBlockData)); - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - { - size += Nv402cCtrlI2cTransactionDataI2cBufferRwGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *) &(src->i2cBufferData)); - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - { - size += Nv402cCtrlI2cTransactionDataSmbusBlockRwGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *) &(src->smbusBlockData)); - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - { - size += Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *) &(src->smbusMultibyteRegisterData)); - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - { - size += Nv402cCtrlI2cTransactionDataReadEdidDdcGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *) &(src->edidData)); - break; - } - default: - { - break; - } - } - - // Add padding for alignment - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv402cCtrlI2cTransactionParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x1f; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->flags + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->flags, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x402c01; // Interface ID - header->message = 0x5; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x1f; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->flags, NvU32, 4); + // No range check for src->transType + status = Nv402cCtrlI2cTransactionTypeCheckEnum(src->transType); + if (status != NV_OK) + goto exit; - FINN_COPY_TO_BUFFER(pos, src->transType, NV402C_CTRL_I2C_TRANSACTION_TYPE, 4); + // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. + if (finn_write_buffer(bp, src->transType, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Rewind buffer for conversion - pos -= 4; - status = Nv402cCtrlI2cTransactionTypeValueToId(&pos, dst_max, 4); - if (status != NV_OK) + // No range check for src->deviceAddress + // Deserialize 2-byte NvU16 object. + if (finn_write_buffer(bp, src->deviceAddress, 2 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->deviceAddress, NvU16, 2); - FINN_COPY_TO_BUFFER(pos, src->portId, NvU8, 1); + // No range check for src->portId + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->portId, 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - status = Nv402cCtrlI2cTransactionDataSerialize(&src->transData, &pos, dst_max, seri_up, src->transType); + status = Nv402cCtrlI2cTransactionDataSerialize(&src->transData, bp, seri_up, src->transType); if (status != NV_OK) goto exit; - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1f) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1f) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->flags - // Static size fields - FINN_COPY_FROM_BUFFER(dst->flags, pos, NvU32, 4); - status = Nv402cCtrlI2cTransactionTypeIdtoValue(&pos, src_max, 4); + // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. + dst->transType = (NV402C_CTRL_I2C_TRANSACTION_TYPE) finn_read_buffer(bp, 4 * 8); + // No range check for dst->transType + status = Nv402cCtrlI2cTransactionTypeCheckEnum(dst->transType); if (status != NV_OK) goto exit; - // Rewind buffer after conversion - pos -= 4; - FINN_COPY_FROM_BUFFER(dst->transType, pos, NV402C_CTRL_I2C_TRANSACTION_TYPE, 4); - FINN_COPY_FROM_BUFFER(dst->deviceAddress, pos, NvU16, 2); + // Deserialize 2-byte NvU16 object. + dst->deviceAddress = (NvU16) finn_read_buffer(bp, 2 * 8); + // No range check for dst->deviceAddress + - FINN_COPY_FROM_BUFFER(dst->portId, pos, NvU8, 1); + // Deserialize 1-byte NvU8 object. + dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->portId - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - status = Nv402cCtrlI2cTransactionDataDeserialize(&pos, src_max, &dst->transData, dst_size, deser_up, dst->transType); + status = Nv402cCtrlI2cTransactionDataDeserialize(bp, &dst->transData, dst_size, deser_up, dst->transType); if (status != NV_OK) goto exit; - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv402cCtrlI2cTransactionParamsGetSerializedSize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src) -{ - // Start with the portion of the size known at compile time. - NvU64 size = 56; - - // Add sizes that require runtime calculation - size += Nv402cCtrlI2cTransactionDataGetSerializedSize((const NV402C_CTRL_I2C_TRANSACTION_DATA *) &(src->transData), - src->transType); - // Add padding - size = (size + 7) &~ 7; - - return size; -} -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) +static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv83deCtrlDebugReadMemoryParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0xf; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->offset + // Deserialize 8-byte NvU64 object. + if (finn_write_buffer(bp, src->offset, 8 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x83de03; // Interface ID - header->message = 0x15; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0xf; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->offset, NvU64, 8); + // No range check for src->hMemory + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->hMemory, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - FINN_COPY_TO_BUFFER(pos, src->hMemory, NvU32, 4); - FINN_COPY_TO_BUFFER(pos, src->length, NvU32, 4); + // No range check for src->length + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->length, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->buffer); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->buffer), 1); + // Skip if pointer is null. if (src->buffer) { - FINN_MEMCPY_TO_BUFFER(pos, src->buffer, (src->length)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->length); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->buffer) + FINN_FREE(src->buffer); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xf) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xf) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 8-byte NvU64 object. + dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); + // No range check for dst->offset + - // Static size fields - FINN_COPY_FROM_BUFFER(dst->offset, pos, NvU64, 8); + // Deserialize 4-byte NvU32 object. + dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->hMemory - FINN_COPY_FROM_BUFFER(dst->hMemory, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->length, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->length - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->buffer, pos, (dst->length)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->length)) > src_max || - pos + ((dst->length)) < pos) + dst->buffer = FINN_MALLOC((dst->length)); + if (!dst->buffer) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->buffer, pos, NvP64, (dst->length)); + FINN_MEMZERO(dst->buffer, (dst->length)); + } + + // Otherwise the pointer must be provided. + else if (!dst->buffer) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->length); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -7299,161 +6400,146 @@ static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(NvU8 **src, const Nv dst->buffer = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv83deCtrlDebugReadMemoryParamsGetSerializedSize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src) + +static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 56; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0xf; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->buffer) + // Statically sized fields + // No range check for src->offset + // Deserialize 8-byte NvU64 object. + if (finn_write_buffer(bp, src->offset, 8 * 8)) { - size += (src->length); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - - return size; -} - -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nv83deCtrlDebugWriteMemoryParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->hMemory + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->hMemory, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0x83de03; // Interface ID - header->message = 0x16; // Message ID - // Field bitmasks - header->fieldMask[0] = 0xf; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->offset, NvU64, 8); - - FINN_COPY_TO_BUFFER(pos, src->hMemory, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->length, NvU32, 4); + // No range check for src->length + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->length, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->buffer); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->buffer), 1); + // Skip if pointer is null. if (src->buffer) { - FINN_MEMCPY_TO_BUFFER(pos, src->buffer, (src->length)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->length); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->buffer) + FINN_FREE(src->buffer); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(NvU8 **src, const NvU8 *src_max, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0xf) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0xf) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 8-byte NvU64 object. + dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); + // No range check for dst->offset + - // Static size fields - FINN_COPY_FROM_BUFFER(dst->offset, pos, NvU64, 8); + // Deserialize 4-byte NvU32 object. + dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->hMemory - FINN_COPY_FROM_BUFFER(dst->hMemory, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->length, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->length - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->buffer, pos, (dst->length)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->length)) > src_max || - pos + ((dst->length)) < pos) + dst->buffer = FINN_MALLOC((dst->length)); + if (!dst->buffer) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->buffer, pos, NvP64, (dst->length)); + FINN_MEMZERO(dst->buffer, (dst->length)); + } + + // Otherwise the pointer must be provided. + else if (!dst->buffer) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->length); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -7462,157 +6548,131 @@ static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(NvU8 **src, const N dst->buffer = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); - - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - exit: - *src = pos; return status; } -static NvU64 Nv83deCtrlDebugWriteMemoryParamsGetSerializedSize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src) + +static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 56; + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); - // For non-NULL pointers, proceed to size calculation. - if (src->buffer) + // Statically sized fields + // No range check for src->engineID + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->engineID, 4 * 8)) { - size += (src->length); + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; } - // Add padding - size = (size + 7) &~ 7; - return size; -} - -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) -{ - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nvb06fCtrlGetEngineCtxDataParamsGetSerializedSize(src); - NV_STATUS status = NV_OK; - - // Validate buffer size - if (pos + serializedSize > dst_max) + // No range check for src->size + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->size, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0xb06f01; // Interface ID - header->message = 0xc; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x7; - - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - - // Static size fields - FINN_COPY_TO_BUFFER(pos, src->engineID, NvU32, 4); - - FINN_COPY_TO_BUFFER(pos, src->size, NvU32, 4); - - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Set data presence byte - *(pos++) = !!(src->pEngineCtxBuff); + // Set data-presence indicator. + finn_write_buffer(bp, !!(src->pEngineCtxBuff), 1); + // Skip if pointer is null. if (src->pEngineCtxBuff) { - FINN_MEMCPY_TO_BUFFER(pos, src->pEngineCtxBuff, (src->size)); - } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Serialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (src->size); ++j) + { + finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pEngineCtxBuff))[j], 1 * 8); + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && src->pEngineCtxBuff) + FINN_FREE(src->pEngineCtxBuff); + } + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(NvU8 **src, const NvU8 *src_max, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x7) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->engineID - // Static size fields - FINN_COPY_FROM_BUFFER(dst->engineID, pos, NvU32, 4); - FINN_COPY_FROM_BUFFER(dst->size, pos, NvU32, 4); + // Deserialize 4-byte NvU32 object. + dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->size - // Align after static size fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); // Unbounded fields - // Check data presence byte - if (*(pos++)) + // Skip if data is not present (null pointer). + if (finn_read_buffer(bp, 1)) { - if (deser_up) - FINN_MEMCPY_FROM_BUFFER(dst->pEngineCtxBuff, pos, (dst->size)); - else + + // Allocate memory and set pointer when deserializing down. + // (Calling cods is expected to do so when deserializing up.) + if (!deser_up) { - // Validate variable length buffer length - if (pos + ((dst->size)) > src_max || - pos + ((dst->size)) < pos) + dst->pEngineCtxBuff = FINN_MALLOC((dst->size)); + if (!dst->pEngineCtxBuff) { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + status = NV_ERR_NO_MEMORY; + FINN_ERROR(NV_ERR_NO_MEMORY); goto exit; } - FINN_SET_PTR_TO_BUFFER(dst->pEngineCtxBuff, pos, NvP64, (dst->size)); + FINN_MEMZERO(dst->pEngineCtxBuff, (dst->size)); + } + + // Otherwise the pointer must be provided. + else if (!dst->pEngineCtxBuff) + { + status = NV_ERR_INVALID_POINTER; + FINN_ERROR(NV_ERR_INVALID_POINTER); + goto exit; + } + + // Deserialize each 1-byte NvU8 element. + for (NvU64 j = 0; j < (dst->size); ++j) + { + ((NvU8 *) NvP64_VALUE(dst->pEngineCtxBuff))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); } } else @@ -7621,151 +6681,207 @@ static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(NvU8 **src, const N dst->pEngineCtxBuff = NULL; } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); +exit: + return status; +} - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) - { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + +static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x1; + finn_write_buffer(bp, field_presence_mask, 64); + + // Unbounded fields + status = Nvb06fCtrlGetEngineCtxDataParamsSerialize(&src->params, bp, seri_up); + if (status != NV_OK) goto exit; - } + goto exit; // Suppress potential not-used warning exit: - *src = pos; return status; } -static NvU64 Nvb06fCtrlGetEngineCtxDataParamsGetSerializedSize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src) + +static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 48; + // Local variables + NV_STATUS status = NV_OK; - // Add sizes that require runtime calculation - // Increment size to account for the data presence byte. - ++size; + // Check that the destination struct fits within the destination buffer + if (sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // For non-NULL pointers, proceed to size calculation. - if (src->pEngineCtxBuff) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1) { - size += (src->size); + status = NV_ERR_LIB_RM_VERSION_MISMATCH; + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + goto exit; } - // Add padding - size = (size + 7) &~ 7; + // Unbounded fields + status = Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); + if (status != NV_OK) + goto exit; - return size; +exit: + return status; } -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, NvU8 **dst, const NvU8 *dst_max, NvBool seri_up) + +static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) { - NvU8 *pos = *dst; - FINN_RM_API *header = (FINN_RM_API *)pos; - NvU64 serializedSize = Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsGetSerializedSize(src); + // Local variables NV_STATUS status = NV_OK; + uint64_t field_presence_mask; - // Validate buffer size - if (pos + serializedSize > dst_max) + // Field bitmasks + field_presence_mask = 0x7; + finn_write_buffer(bp, field_presence_mask, 64); + + // Statically sized fields + // No range check for src->engineID + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->engineID, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Clear destination buffer - FINN_MEMZERO(pos, serializedSize); - // Serialization header - header->version = FINN_SERIALIZATION_VERSION; // Serialization version - header->payloadSize = serializedSize; // Serialized size - header->interface = 0xb06f01; // Interface ID - header->message = 0xd; // Message ID - - // Field bitmasks - header->fieldMask[0] = 0x1; + // No range check for src->size + // Deserialize 4-byte NvU32 object. + if (finn_write_buffer(bp, src->size, 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsSerialize(&src->params, &pos, dst_max, seri_up); - if (status != NV_OK) - goto exit; + for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) + { + // No range check for src->engineCtxBuff[i] + // Deserialize 1-byte NvU8 object. + if (finn_write_buffer(bp, src->engineCtxBuff[i], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + } - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + goto exit; // Suppress potential not-used warning exit: - *dst = pos; return status; } -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(NvU8 **src, const NvU8 *src_max, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) + +static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - NvU8 *pos = *src; - FINN_RM_API *header = (FINN_RM_API *)pos; + // Local variables NV_STATUS status = NV_OK; // Check that the destination struct fits within the destination buffer - // and that the declared size fits within the source buffer - if (sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size || - header->payloadSize < (sizeof(FINN_RM_API) + sizeof(NvU64)) || - pos + header->payloadSize > src_max || - pos + header->payloadSize < pos) + if (sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS) > dst_size) { status = NV_ERR_BUFFER_TOO_SMALL; - pos = (NvU8 *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); goto exit; } - // Validate the field bitmasks. They must match the expected values for now - if (header->fieldMask[0] != 0x1) + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x7) { status = NV_ERR_LIB_RM_VERSION_MISMATCH; - pos = (NvU8 *) &header->fieldMask; FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); goto exit; } - // Jump past header - pos += sizeof(FINN_RM_API) + (1 * sizeof(NvU64)); + // Statically sized fields + // Deserialize 4-byte NvU32 object. + dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->engineID - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsDeserialize(&pos, src_max, &dst->params, dst_size, deser_up); - if (status != NV_OK) - goto exit; - // Align after unbounded fields - pos = (NvU8*)(((NvU64)pos + 7) &~ 7); + // Deserialize 4-byte NvU32 object. + dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->size + - // Check that the declared size matches the serialization outcome - if (header->payloadSize != (NvU64) (pos - *src)) + for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) { - status = NV_ERR_INVALID_ARGUMENT; - pos = (NvU8 *) &header->payloadSize; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; + // Deserialize 1-byte NvU8 object. + dst->engineCtxBuff[i] = (NvU8) finn_read_buffer(bp, 1 * 8); + // No range check for dst->engineCtxBuff[i] } + +exit: + return status; +} + + +static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Local variables + NV_STATUS status = NV_OK; + uint64_t field_presence_mask; + + // Field bitmasks + field_presence_mask = 0x1; + finn_write_buffer(bp, field_presence_mask, 64); + + // Bounded nested fields + status = Nvb06fCtrlSaveEngineCtxDataParamsSerialize(&src->params, bp, seri_up); + if (status != NV_OK) + goto exit; + + goto exit; // Suppress potential not-used warning exit: - *src = pos; return status; } -static NvU64 Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsGetSerializedSize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src) + +static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) { - // Start with the portion of the size known at compile time. - NvU64 size = 40; + // Local variables + NV_STATUS status = NV_OK; + + // Check that the destination struct fits within the destination buffer + if (sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } + + // Validate the field bitmasks, which must match the expected values for now. + if (finn_read_buffer(bp, 64) != 0x1) + { + status = NV_ERR_LIB_RM_VERSION_MISMATCH; + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + goto exit; + } - // Add sizes that require runtime calculation - size += Nvb06fCtrlGetEngineCtxDataParamsGetSerializedSize((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) &(src->params)); - // Add padding - size = (size + 7) &~ 7; + // Bounded nested fields + status = Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); + if (status != NV_OK) + goto exit; - return size; +exit: + return status; } + diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index 52bf33c44..b5e0ec872 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -195,6 +195,8 @@ enum { X(RM, CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN) //186 X(RM, CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX) //187 X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION) //188 + X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK) //189 + X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER) //190 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; diff --git a/src/nvidia/kernel/inc/vgpu/rpc_headers.h b/src/nvidia/kernel/inc/vgpu/rpc_headers.h index edc37a744..3a1826b74 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_headers.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_headers.h @@ -206,19 +206,6 @@ typedef enum UVM_PAGING_CHANNEL_VASPACE_FREE, } UVM_PAGING_CHANNEL_VASPACE_OPERATION; -typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS -{ - NvU32 headIndex; - NvU32 maxHResolution; - NvU32 maxVResolution; -} VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; - -typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS -{ - NvU32 numHeads; - NvU32 maxNumHeads; -} VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; - /* * Maximum guest pages that can be mapped for UVM method stream diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index d69982b8f..bf64f0b0a 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -26,6 +26,7 @@ #define _RPC_SDK_STRUCTURES_H_ #include +#include #include #include #include @@ -63,6 +64,8 @@ #include "rpc_headers.h" #include "nvctassert.h" + + typedef struct vmiopd_SM_info { NvU32 version; NvU32 regBankCount; @@ -123,6 +126,8 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12 #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 100 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the @@ -225,6 +230,7 @@ typedef struct HYPERV_SHARED_MEMORY_DESCRIPTOR #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v15_01 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v20_03 (0x00000018) #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_events.h b/src/nvidia/kernel/inc/vgpu/vgpu_events.h index 2205e1651..a0975213b 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_events.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_events.h @@ -35,6 +35,7 @@ #include "rmconfig.h" +#include "ctrl/ctrla083.h" #include "ctrl/ctrlc637.h" #include "ctrl/ctrl2080/ctrl2080bios.h" #include "ctrl/ctrl2080/ctrl2080fb.h" diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index 5add972b5..3e25eaea4 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -30,8 +30,8 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x1F -#define VGX_MINOR_VERSION_NUMBER 0x0F +#define VGX_MAJOR_VERSION_NUMBER 0x20 +#define VGX_MINOR_VERSION_NUMBER 0x04 // The NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL macros are auto-generated using the value from rpc-structures.def file. #define AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index c5766045a..e53e4e646 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -50,10 +50,13 @@ #include "vgpu/vgpu_events.h" #include "virtualization/hypervisor/hypervisor.h" #include "finn_rm_api.h" +#include "os/os.h" #define SDK_ALL_CLASSES_INCLUDE_FULL_HEADER #include "g_allclasses.h" #undef SDK_ALL_CLASSES_INCLUDE_FULL_HEADER +#include "nverror.h" + #define RPC_STRUCTURES #define RPC_GENERIC_UNION @@ -996,6 +999,18 @@ NV_STATUS rpcGetStaticInfo_v1A_05(OBJGPU *pGpu, OBJRPC *pRpc) return status; } +NV_STATUS rpcGetStaticInfo_v20_01(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status = NV_OK; + return status; +} + +NV_STATUS rpcGetStaticInfo_v20_04(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status = NV_OK; + return status; +} + NV_STATUS rpcGetGspStaticInfo_v14_00(OBJGPU *pGpu, OBJRPC *pRpc) { NV_STATUS status = NV_ERR_NOT_SUPPORTED; @@ -1258,7 +1273,10 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 { rpcInfo->simAccessBufPhysAddr = 0; } + rpcInfo->pcieAtomicsOpMask = GPU_GET_KERNEL_BIF(pGpu) ? + GPU_GET_KERNEL_BIF(pGpu)->osPcieAtomicsOpMask : 0U; rpcInfo->consoleMemSize = GPU_GET_MEMORY_MANAGER(pGpu)->Ram.ReservedConsoleDispMemSize; + rpcInfo->maxUserVa = osGetMaxUserVa(); OBJCL *pCl = SYS_GET_CL(SYS_GET_INSTANCE()); if (pCl != NULL) diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index a7b08cc93..bb86402c7 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -639,17 +639,6 @@ sysInitRegistryOverrides_IMPL _sysRegistryOverrideExternalFabricMgmt(pSys, pGpu); _sysRegistryOverrideResourceServer(pSys, pGpu); - if ((data32 = osGetReleaseAssertBehavior()) != 0) - { - NvBool bRmAssertBehaviorBugcheck = NV_FALSE; -#if defined(DEVELOP) - bRmAssertBehaviorBugcheck = ((data32 & RM_ASSERT_BEHAVIOR_BUGCHECK_DEVELOP) == RM_ASSERT_BEHAVIOR_BUGCHECK_DEVELOP); -#elif !defined(DEBUG) // !DEVELOP and !DEBUG = RELEASE - bRmAssertBehaviorBugcheck = ((data32 & RM_ASSERT_BEHAVIOR_BUGCHECK_RELEASE) == RM_ASSERT_BEHAVIOR_BUGCHECK_RELEASE); -#endif - pSys->setProperty(pSys, PDB_PROP_SYS_BSOD_ON_ASSERT, bRmAssertBehaviorBugcheck); - } - if (osBugCheckOnTimeoutEnabled()) { pSys->setProperty(pSys, PDB_PROP_SYS_BUGCHECK_ON_TIMEOUT, NV_TRUE); diff --git a/src/nvidia/src/kernel/diagnostics/journal.c b/src/nvidia/src/kernel/diagnostics/journal.c index 1f28af5e8..118c22c85 100644 --- a/src/nvidia/src/kernel/diagnostics/journal.c +++ b/src/nvidia/src/kernel/diagnostics/journal.c @@ -3065,7 +3065,7 @@ _rcdbNocatCollectContext(OBJGPU *pGpu, Journal* pRcdb, NV2080_NOCAT_JOURNAL_GPU_ if (!osIsRaisedIRQL()) { - + pContextCache->bValid = NV_TRUE; } } @@ -3477,7 +3477,7 @@ rcdbReportNextNocatJournalEntry } /* -** rcdbGetNocatOutstandingCount returns the number of NOCAT events that have +** rcdbGetNocatOutstandingCount returns the number of NOCAT events that have ** been recorded since the last reported record. ** ** parameters: @@ -3571,7 +3571,7 @@ void rcdbInitNocatGpuCache_IMPL(OBJGPU *pGpu) Journal *pRcdb = SYS_GET_RCDB(pSys); #if NOCAT_PROBE_FB_MEMORY NvU8 *pCpuPtr; -#endif +#endif if (pGpu == NULL) { return; diff --git a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c index 9a2b0d305..c7cd7a797 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c @@ -1033,253 +1033,6 @@ static int strtofmtstr(const char *src, char *dest, char *destLimit, int fieldwi return((int)(d - dest)); // Return the character count, not including the null } -//******************************************************************************** -// -// NVRM_TRACE support -// low-overhead runtime state capture -// to enable, define USE_NVRM_TRACE (retail or debug builds) -// -//******************************************************************************** - -#ifdef USE_NVRM_TRACE - -// TODO: It would be really cool if we could -// find a way to tie this to a board instance. -// Or at least provide some way to tag entries -// relative to the board. It would be even -// more cool if each entry was of the form: -// -// TIMESTAMP : CPU# : BOARD# : LINE# : FILENAME : -// -// where could be either a string or a value. -// - -// the number of trace words in the ring buffer. -// a trace event can be 1 or more words -#define NVRM_TRACE_ENTRIES (2048) -// a typedef for the trace table. Add a pad to simplify -// bounds checking -typedef NvU32 NVRM_TRACE_t[NVRM_TRACE_ENTRIES + 16]; - -NvU32 NVRM_tracing = 0; // enabled or not? -// a type'd ptr to the table. This may make it easier for your debugger -// to dump out the table (definitely helps on the mac) -NVRM_TRACE_t *NVRM_TRACE_GTRACE; -// actual table pointer -NvU32 *NVRM_TRACE_table; -// current index into the table -NvU32 NVRM_TRACE_idx; - -#define NVRM_TRACE_BUMP(inc) { NVRM_TRACE_idx += (inc); \ - if (NVRM_TRACE_idx >= NVRM_TRACE_ENTRIES) NVRM_TRACE_idx = 0; \ - NVRM_TRACE_table[NVRM_TRACE_idx] = '****'; \ - } - -NvU32 NVRM_TRACE_INIT() -{ - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); - - // skip out if already initialized - if (NVRM_TRACE_table) - goto done; - - // - // allocate the table - // depending on when you call NVRM_TRACE_INIT, might not be able to - // use portMemAllocNonPaged() - // - NVRM_TRACE_table = portMemAllocNonPaged(sizeof(NVRM_TRACE_t)); - - // clear the table - if (NVRM_TRACE_table) - portMemSet(NVRM_TRACE_table, 0, sizeof(NVRM_TRACE_t)); - - NVRM_TRACE_GTRACE = (void *) NVRM_TRACE_table; - - NV_PRINTF(LEVEL_ERROR, - "trace table at 0x%x through 0x%x, idx at 0x%x\n", - NVRM_TRACE_table, &NVRM_TRACE_table[NVRM_TRACE_ENTRIES], - &NVRM_TRACE_idx); - - if (NVRM_TRACE_table != NULL) - { - NVRM_tracing = 1; - } - - done: - return NVRM_tracing; -} - -NvU32 NVRM_TRACE_DISABLE(void) -{ - NvU32 previous = NVRM_tracing; - NVRM_tracing = 0; - return previous; -} - -void NVRM_TRACE_ENABLE(void) -{ - NVRM_tracing = 1; -} - -void NVRM_TRACE(NvU32 value) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value; - NVRM_TRACE_BUMP(1); -} - -void NVRM_TRACE1(NvU32 value) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value; - NVRM_TRACE_BUMP(1); -} - -void NVRM_TRACE2(NvU32 value1, NvU32 value2) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value1; - NVRM_TRACE_table[NVRM_TRACE_idx+1] = value2; - NVRM_TRACE_BUMP(2); -} - -void NVRM_TRACE3(NvU32 value1, NvU32 value2, NvU32 value3) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value1; - NVRM_TRACE_table[NVRM_TRACE_idx+1] = value2; - NVRM_TRACE_table[NVRM_TRACE_idx+2] = value3; - NVRM_TRACE_BUMP(3); -} - -void NVRM_TRACE4(NvU32 value1, NvU32 value2, NvU32 value3, NvU32 value4) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value1; - NVRM_TRACE_table[NVRM_TRACE_idx+1] = value2; - NVRM_TRACE_table[NVRM_TRACE_idx+2] = value3; - NVRM_TRACE_table[NVRM_TRACE_idx+3] = value4; - NVRM_TRACE_BUMP(4); -} - -void NVRM_TRACE5(NvU32 value1, NvU32 value2, NvU32 value3, NvU32 value4, NvU32 value5) -{ - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - NVRM_TRACE_table[NVRM_TRACE_idx] = value1; - NVRM_TRACE_table[NVRM_TRACE_idx+1] = value2; - NVRM_TRACE_table[NVRM_TRACE_idx+2] = value3; - NVRM_TRACE_table[NVRM_TRACE_idx+3] = value4; - NVRM_TRACE_table[NVRM_TRACE_idx+4] = value5; - NVRM_TRACE_BUMP(5); -} - -#ifndef ACTUAL_REG_RD32 -#define ACTUAL_REG_RD32 GPU_REG_RD32 -#endif -#ifndef ACTUAL_REG_WR32 -#define ACTUAL_REG_WR32 GPU_REG_WR32 -#endif -#ifndef ACTUAL_REG_RD08 -#define ACTUAL_REG_RD08 GPU_REG_RD08 -#endif -#ifndef ACTUAL_REG_WR08 -#define ACTUAL_REG_WR08 GPU_REG_WR08 -#endif - -NvU32 NVRM_TRACE_REG_RD32(OBJGPU *pGpu, NvU32 offset) -{ - NvU32 value = ACTUAL_REG_RD32(pGpu, offset); - NVRM_TRACE3('RD32', offset, value); - return value; -} - -void NVRM_TRACE_REG_WR32(OBJGPU *pGpu, NvU32 offset, NvU32 value) -{ - ACTUAL_REG_WR32(pGpu, offset, value); - NVRM_TRACE3('WR32', offset, value); -} - -NvU8 NVRM_TRACE_REG_RD08(OBJGPU *pGpu, NvU32 offset) -{ - NvU32 value = ACTUAL_REG_RD08(pGpu, offset); - NVRM_TRACE3('RD08', offset, value); - return (NvU8) value; -} - -void NVRM_TRACE_REG_WR08(OBJGPU *pGpu, NvU32 offset, NvU8 value) -{ - ACTUAL_REG_WR08(pGpu, offset, value); - NVRM_TRACE3('WR08', offset, value); -} - -void NVRM_TRACEV(NvU32 *values, NvU32 numValues) -{ - NvU32 n; - - if ( ! NVRM_tracing) return; - if (NVRM_TRACE_table == (NvU32 *) 0) - if ( ! NVRM_TRACE_INIT()) - return; - - for ( n = 0; n < numValues; n++ ) - NVRM_TRACE_table[NVRM_TRACE_idx+n] = values[n]; - - NVRM_TRACE_BUMP(n); -} - -void NVRM_TRACE_DUMP(void) -{ - int i; - static int dumping = 0; - - // No table? - if ( ! NVRM_TRACE_table) return; - - // don't nest while dumping this - if (dumping) return; - dumping = 1; - - NVRM_TRACE_DISABLE(); - - for (i=0; i <= NVRM_TRACE_ENTRIES; i += 8) - { - NV_PRINTF(LEVEL_ERROR, "%x %x %x %x %x %x %x %x\n", - NVRM_TRACE_table[i + 0], NVRM_TRACE_table[i + 1], - NVRM_TRACE_table[i + 2], NVRM_TRACE_table[i + 3], - NVRM_TRACE_table[i + 4], NVRM_TRACE_table[i + 5], - NVRM_TRACE_table[i + 6], NVRM_TRACE_table[i + 7]); - } - dumping = 0; -} - -#endif // USE_NVRM_TRACE - #if NV_PRINTF_STRINGS_ALLOWED // // String matching helper for nvDbgRmMsgCheck. diff --git a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c new file mode 100644 index 000000000..8cb1390e2 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************** HW State Routines ***************************\ +* * +* ADA specific Descriptor List management functions * +* * +\***************************************************************************/ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/eng_desc.h" + +// +// List of GPU children that present for the chip. List entries contain$ +// {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$ +// list controls only engine presence. Order is defined by$ +// gpuGetChildrenOrder_HAL.$ +// +// IMPORTANT: This function is to be deleted. Engine removal should instead be$ +// handled by ConstructEngine returning NV_ERR_NOT_SUPPORTED. PLEASE DO NOT$ +// FORK THIS LIST!$ +// +// List entries contain {CLASS-ID, # of instances} pairs. +// + +static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = +{ + {classId(OBJSWENG), 1}, + {classId(OBJUVM), 1}, + {classId(OBJACR), 1}, + {classId(OBJBIF), 1}, + {classId(KernelBif), 1}, + {classId(OBJNNE), 1}, + {classId(OBJBSP), 4}, + {classId(OBJBUS), 1}, + {classId(KernelBus), 1}, + {classId(OBJCE), 5}, + {classId(KernelCE), 5}, + {classId(OBJCIPHER), 1}, + {classId(ClockManager), 1}, + {classId(OBJDISP), 1}, + {classId(KernelDisplay), 1}, + {classId(VirtMemAllocator), 1}, + {classId(OBJDPAUX), 1}, + {classId(OBJFAN), 1}, + {classId(OBJHSHUBMANAGER), 1}, + {classId(OBJHSHUB), 2 }, + {classId(MemorySystem), 1}, + {classId(KernelMemorySystem), 1}, + {classId(MemoryManager), 1}, + {classId(OBJFBFLCN), 1}, + {classId(KernelFifo), 1 }, + {classId(OBJFIFO), 1}, + {classId(OBJGMMU), 1}, + {classId(KernelGmmu), 1}, + {classId(OBJGPULOG), 1}, + {classId(OBJGPUMON), 1}, + {classId(GraphicsManager), 1}, + {classId(MIGManager), 1}, + {classId(KernelMIGManager), 1}, + {classId(KernelGraphicsManager), 1}, + {classId(Graphics), 1}, + {classId(KernelGraphics), 1}, + {classId(OBJHDACODEC), 1}, + {classId(OBJHWPM), 1}, + {classId(OBJINFOROM), 1}, + {classId(Intr), 1}, + {classId(Lpwr ), 1}, + {classId(OBJLSFM), 1}, + {classId(OBJMC), 1}, + {classId(KernelMc), 1}, + {classId(PrivRing), 1}, + {classId(SwIntr), 1}, + {classId(OBJNVJPG), 4}, + {classId(OBJMSENC), 3}, + {classId(NvDebugDump), 1}, + {classId(KernelNvlink), 1}, + {classId(Nvlink), 1}, + {classId(Perf), 1}, + {classId(KernelPerf), 1}, + {classId(Pmgr), 1}, + {classId(Pmu), 1}, + {classId(KernelPmu), 1}, + {classId(OBJSEC2), 1}, + {classId(Gsp), 1}, + {classId(Therm), 1}, + {classId(OBJTMR), 1}, + {classId(OBJVOLT), 1}, + {classId(OBJGRIDDISPLAYLESS), 1}, + {classId(OBJFAS), 1}, + {classId(OBJVMMU), 1}, + {classId(OBJOFA), 1 }, + {classId(KernelSec2), 1}, + {classId(KernelGsp), 1}, +}; + +const GPUCHILDPRESENT * +gpuGetChildrenPresent_AD102(OBJGPU *pGpu, NvU32 *pNumEntries) +{ + *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_AD102); + return gpuChildrenPresent_AD102; +} + diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 7888a6c6a..e4fe11c9c 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -147,6 +147,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(VirtMemAllocator), 1 }, { classId(OBJDPAUX), 1 }, { classId(OBJFAN), 1 }, + { classId(OBJHSHUBMANAGER), 1 }, { classId(OBJHSHUB), 2 }, { classId(MemorySystem), 1 }, { classId(KernelMemorySystem), 1 }, @@ -192,7 +193,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(OBJFAS), 1 }, { classId(OBJVMMU), 1 }, { classId(OBJOFA), 1 }, - { classId(KernelNvdec), 1 }, { classId(KernelSec2), 1 }, { classId(KernelGsp), 1 }, }; @@ -236,6 +236,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, {classId(OBJFAN), 1}, + {classId(OBJHSHUBMANAGER), 1 }, {classId(OBJHSHUB), 2 }, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, @@ -281,7 +282,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(OBJOFA), 1 }, - {classId(KernelNvdec), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, }; diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c new file mode 100644 index 000000000..ff1a0d72f --- /dev/null +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -0,0 +1,391 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "os/os.h" +#include "nverror.h" + +#include "published/hopper/gh100/hwproject.h" +#include "published/hopper/gh100/dev_gc6_island.h" +#include "published/hopper/gh100/dev_pmc.h" +#include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" +#include "published/hopper/gh100/pri_nv_xal_ep.h" + +#include "gpu/gsp/gsp_static_config.h" + +/*! + * @brief Write to non-private registers in XTL using config cycles + * + * @param[in] pGpu GPU object pointer + * @param[in] index Register offset in PCIe config space + * @param[in] value Write this value to the register + * + * @returns NV_OK on success + */ +NV_STATUS +gpuWriteBusConfigReg_GH100 +( + OBJGPU *pGpu, + NvU32 index, + NvU32 value +) +{ + return gpuWriteBusConfigCycle(pGpu, index, value); +} + +/*! + * @brief Read the non-private registers in XTL using config cycles + * + * @param[in] pGpu GPU object pointer + * @param[in] index Register offset in PCIe config space + * @param[out] pData Value of the register + * + * @returns NV_OK on success + */ +NV_STATUS +gpuReadBusConfigReg_GH100 +( + OBJGPU *pGpu, + NvU32 index, + NvU32 *pData +) +{ + return gpuReadBusConfigCycle(pGpu, index, pData); +} + +/*! + * @brief Get GPU ID based on PCIE config reads. + * Also determine other properties of the PCIE capabilities. + * + * @param[in] pGpu OBJGPU pointer + * @returns void. + */ +void +gpuGetIdInfo_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 data; + NvU32 deviceId; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE, + &data) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "unable to read NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE\n"); + return; + } + + // we only need the FIB and MASK values + pGpu->idInfo.PCIRevisionID = (data & ~GPU_DRF_SHIFTMASK(NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE) + & ~GPU_DRF_SHIFTMASK(NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE) + & ~GPU_DRF_SHIFTMASK(NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE)); + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_SUBSYSTEM_ID, + &data) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "unable to read NV_EP_PCFG_GPU_SUBSYSTEM_ID\n"); + return; + } + pGpu->idInfo.PCISubDeviceID = data; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_ID, &deviceId) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "unable to read NV_EP_PCFG_GPU_ID\n"); + return; + } + // For universal GPU use unlatched value + pGpu->idInfo.PCIDeviceID = deviceId; + +} + +/*! + * @brief Returns the physical address width for the given @ref NV_ADDRESS_SPACE + */ +NvU32 gpuGetPhysAddrWidth_GH100 +( + OBJGPU *pGpu, + NV_ADDRESS_SPACE addrSp +) +{ + // Currently this function supports only sysmem addresses + NV_ASSERT_OR_RETURN(ADDR_SYSMEM == addrSp, 0); + + return NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS; +} + +/** + * @brief Check if the GPU supports ATS with SMC memory partitioning enabled. + * + * @param pGpu + * + * @return NV_TRUE if ATS is supported with SMC memory partitioning + * NV_FALSE otherwise + */ +NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(OBJGPU *pGpu) +{ + + if (IS_SIMULATION(pGpu)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +/*! + * @brief Handle SEC_FAULT + * + * @param[in] pGpu GPU object pointer + */ +static void +_gpuHandleSecFault_GH100(OBJGPU *pGpu) +{ + NvU32 secDebug = 0; + + // + // Read SEC_FAULT config space to determine what went wrong. + // Do not return early on error, we must take the GPU down. + // + NV_ASSERT_OK(GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_VSEC_DEBUG_SEC, &secDebug)); + + MODS_ARCH_ERROR_PRINTF("NV_EP_PCFG_GPU_VSEC_DEBUG_SEC:0x%x\n", secDebug); + NV_PRINTF(LEVEL_FATAL, "SEC_FAULT lockdown detected. This is fatal. " + "RM will now shut down. NV_EP_PCFG_GPU_VSEC_DEBUG_SEC: 0x%x\n", secDebug); + +// (void)REF_NUM grants us mcheck protection +#define LOG_SEC_FAULT(field) \ + (void)REF_NUM(NV_EP_PCFG_GPU_VSEC_DEBUG_SEC##field, 0); \ + if (DRF_VAL(_EP_PCFG_GPU, _VSEC_DEBUG_SEC, field, secDebug) != 0) \ + { \ + MODS_ARCH_ERROR_PRINTF("NV_EP_PCFG_GPU_VSEC_DEBUG_SEC" #field "\n"); \ + NV_PRINTF(LEVEL_FATAL, "SEC_FAULT type: " #field "\n"); \ + nvErrorLog_va((void *)(pGpu), SEC_FAULT_ERROR, \ + "SEC_FAULT: " #field ); \ + } + + LOG_SEC_FAULT(_FAULT_FUSE_POD); + LOG_SEC_FAULT(_FAULT_FUSE_SCPM); + LOG_SEC_FAULT(_FAULT_FSP_SCPM); + LOG_SEC_FAULT(_FAULT_SEC2_SCPM); + LOG_SEC_FAULT(_FAULT_FSP_DCLS); + LOG_SEC_FAULT(_FAULT_SEC2_DCLS); + LOG_SEC_FAULT(_FAULT_GSP_DCLS); + LOG_SEC_FAULT(_FAULT_PMU_DCLS); + LOG_SEC_FAULT(_FAULT_SEQ_TOO_BIG); + LOG_SEC_FAULT(_FAULT_PRE_IFF_CRC); + LOG_SEC_FAULT(_FAULT_POST_IFF_CRC); + LOG_SEC_FAULT(_FAULT_ECC); + LOG_SEC_FAULT(_FAULT_CMD); + LOG_SEC_FAULT(_FAULT_PRI); + LOG_SEC_FAULT(_FAULT_WDG); + LOG_SEC_FAULT(_FAULT_BOOTFSM); + LOG_SEC_FAULT(_IFF_POS); + +#undef LOG_SEC_FAULT + + // + // After SEC_FAULT occurs, the GPU will only return SCPM dummy values until properly reset. + // Only cold reset will clear SEC_FAULT, not hot reset. This GPU is as good as lost. + // handleGpuLost first to setGpuDisconnectedProperties so that another reg read does not + // happen when the notifier is sent below. + // + osHandleGpuLost(pGpu); + + // + // Send SEC_FAULT notification. This should tells any MODS test testing for this + // error to pass and exit + // + gpuNotifySubDeviceEvent(pGpu, + NV2080_NOTIFIERS_SEC_FAULT_ERROR, + NULL, + 0, + 0, + SEC_FAULT_ERROR); +} + +/*! + * @brief Perform gpu-dependent error handling for error during register read sanity check + * + * @param[in] pGpu GPU object pointer + * @param[in] addr Value address + * @param[in] value Value read during check + */ +void +gpuHandleSanityCheckRegReadError_GH100 +( + OBJGPU *pGpu, + NvU32 addr, + NvU32 value +) +{ + // SEC_FAULT possibly detected, confirm by reading NV_PMC_BOOT_0 + if ((value == NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT) && + (osGpuReadReg032(pGpu, NV_PMC_BOOT_0) == NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT)) + { + _gpuHandleSecFault_GH100(pGpu); + } + else + { + NvU32 intr = ~0U; + { + // + // Read the interrupt status using the direct OS reg read call so we don't recurs + // if we happen to see GPU_READ_PRI_ERROR_CODE there as well (bug 799876) + // + intr = osGpuReadReg032(pGpu, NV_XAL_EP_INTR_0); + } + + + // To be sure, filter this down further by checking the related pri interrupts: + if (FLD_TEST_DRF(_XAL_EP, _INTR_0, _PRI_FECSERR, _PENDING, intr) || + FLD_TEST_DRF(_XAL_EP, _INTR_0, _PRI_REQ_TIMEOUT, _PENDING, intr) || + FLD_TEST_DRF(_XAL_EP, _INTR_0, _PRI_RSP_TIMEOUT, _PENDING, intr)) + { +#if NV_PRINTF_STRINGS_ALLOWED + const char *errorString = "Unknown SYS_PRI_ERROR_CODE"; + gpuGetSanityCheckRegReadError_HAL(pGpu, value, + &errorString); + NV_PRINTF(LEVEL_ERROR, + "Possible bad register read: addr: 0x%x, regvalue: 0x%x, error code: %s\n", + addr, value, errorString); +#else // NV_PRINTF_STRINGS_ALLOWED + NV_PRINTF(LEVEL_ERROR, + "Possible bad register read: addr: 0x%x, regvalue: 0x%x\n", + addr, value); +#endif // NV_PRINTF_STRINGS_ALLOWED + } + } +} + +/*! + * @brief Returns FLA VASpace Size for Hopper+ + * + * @param[in] pGpu OBJGPU pointer + * @param[in] bNvSwitchVirtualization boolean + * + * @returns NvU64 -> size of FLA VASpace + */ +NvU64 +gpuGetFlaVasSize_GH100 +( + OBJGPU *pGpu, + NvBool bNvswitchVirtualization +) +{ + return 0x8000000000; // 512GB +} + +// +// List of GPU children that present for the chip. List entries contain$ +// {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$ +// list controls only engine presence. Order is defined by$ +// gpuGetChildrenOrder_HAL.$ +// +// IMPORTANT: This function is to be deleted. Engine removal should instead be$ +// handled by ConstructEngine returning NV_ERR_NOT_SUPPORTED. PLEASE DO NOT$ +// FORK THIS LIST!$ +// +// List entries contain {CLASS-ID, # of instances} pairs. +// + +static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = +{ + { classId(OBJSWENG), 1 }, + { classId(OBJUVM), 1 }, + { classId(OBJACR), 1 }, + { classId(OBJBIF), 1 }, + { classId(KernelBif), 1 }, + { classId(OBJBSP), 8 }, + { classId(OBJBUS), 1 }, + { classId(KernelBus), 1 }, + { classId(OBJCE), 10 }, + { classId(KernelCE), 10 }, + { classId(OBJCIPHER), 1 }, + { classId(ClockManager), 1 }, + { classId(OBJDISP), 1 }, + { classId(KernelDisplay), 1 }, + { classId(VirtMemAllocator), 1 }, + { classId(OBJDPAUX), 1 }, + { classId(OBJFAN), 1 }, + { classId(OBJHSHUBMANAGER), 1 }, + { classId(OBJHSHUB), 5 }, + { classId(MemorySystem), 1 }, + { classId(KernelMemorySystem), 1 }, + { classId(MemoryManager), 1 }, + { classId(OBJFBFLCN), 1 }, + {classId(KernelFifo), 1}, + { classId(OBJFIFO), 1 }, + { classId(OBJGMMU), 1 }, + { classId(KernelGmmu), 1}, + { classId(OBJGPULOG), 1 }, + { classId(OBJGPUMON), 1 }, + { classId(GraphicsManager), 1 }, + { classId(MIGManager), 1 }, + { classId(KernelMIGManager), 1 }, + { classId(KernelGraphicsManager), 1 }, + { classId(Graphics), 8 }, + { classId(KernelGraphics), 8 }, + { classId(OBJHDACODEC), 1 }, + { classId(OBJHWPM), 1 }, + { classId(OBJINFOROM), 1 }, + { classId(Intr), 1 }, + { classId(Lpwr ), 1 }, + { classId(OBJLSFM), 1 }, + { classId(OBJMC), 1 }, + { classId(KernelMc), 1 }, + { classId(PrivRing), 1 }, + { classId(SwIntr), 1 }, + { classId(OBJNVJPG), 8 }, + { classId(NvDebugDump), 1 }, + { classId(KernelNvlink), 1 }, + { classId(Nvlink), 1 }, + { classId(Perf), 1 }, + { classId(KernelPerf), 1 }, + { classId(Pmgr), 1 }, + { classId(Pmu), 1 }, + { classId(KernelPmu), 1 }, + { classId(OBJSEC2), 1 }, + { classId(Gsp), 1 }, + { classId(OBJFSP), 1 }, + { classId(KernelFsp), 1 }, + { classId(Therm), 1 }, + { classId(OBJTMR), 1 }, + { classId(OBJVOLT), 1 }, + { classId(OBJGRIDDISPLAYLESS), 1 }, + { classId(OBJFAS), 1 }, + { classId(OBJVMMU), 1 }, + { classId(OBJOFA), 1 }, + { classId(KernelGsp), 1}, + { classId(KernelCcu), 1 }, +}; + +const GPUCHILDPRESENT * +gpuGetChildrenPresent_GH100(OBJGPU *pGpu, NvU32 *pNumEntries) +{ + *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GH100); + return gpuChildrenPresent_GH100; +} + diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index af1147c15..75b5318e7 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -356,6 +356,7 @@ gpuChildOrderList_GM200[] = {classId(Intr), GCO_ALL}, {classId(OBJTMR), GCO_ALL}, {classId(Therm), GCO_ALL}, + {classId(OBJHSHUBMANAGER), GCO_ALL}, {classId(OBJHSHUB), GCO_ALL}, {classId(MemorySystem), GCO_ALL}, {classId(KernelMemorySystem), GCO_ALL}, @@ -366,7 +367,6 @@ gpuChildOrderList_GM200[] = {classId(OBJGMMU), GCO_ALL}, {classId(KernelGmmu), GCO_ALL}, {classId(OBJVMMU), GCO_ALL}, - {classId(KernelNvdec), GCO_ALL}, {classId(KernelSec2), GCO_ALL}, {classId(KernelGsp), GCO_ALL}, {classId(OBJBUS), GCO_ALL}, @@ -430,6 +430,7 @@ gpuChildOrderList_GM200[] = {classId(OBJHWPM), GCO_ALL}, {classId(OBJSWENG), GCO_ALL}, {classId(OBJGRIDDISPLAYLESS), GCO_ALL}, + {classId(KernelCcu), GCO_ALL}, }; const GPUCHILDORDER * @@ -469,6 +470,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, {classId(OBJFAN), 1}, + {classId(OBJHSHUBMANAGER), 1}, {classId(OBJHSHUB), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index 1352e072d..2af85cc01 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -88,6 +88,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, {classId(OBJFAN), 1}, + {classId(OBJHSHUBMANAGER), 1}, {classId(OBJHSHUB), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, @@ -132,7 +133,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(OBJGRIDDISPLAYLESS), 1}, {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, - {classId(KernelNvdec), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, }; @@ -156,6 +156,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, {classId(OBJFAN), 1}, + {classId(OBJHSHUBMANAGER), 1}, {classId(OBJHSHUB), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, @@ -200,7 +201,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(OBJGRIDDISPLAYLESS), 1}, {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, - {classId(KernelNvdec), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, }; @@ -267,7 +267,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = {classId(OBJGRIDDISPLAYLESS), 1}, {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, - {classId(KernelNvdec), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, }; diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c new file mode 100644 index 000000000..4512200ee --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -0,0 +1,738 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" + +#include "nverror.h" +#include "gpu/bif/kernel_bif.h" +#include "platform/chipset/chipset.h" +#include "ctrl/ctrl2080/ctrl2080bus.h" + +#include "published/hopper/gh100/dev_fb.h" +#include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" +#include "published/hopper/gh100/hwproject.h" + +#include "os/os.h" + +static void _kbifEnablePcieAtomics_GH100(OBJGPU *); + +/*! + * @brief Check if MSI is enabled in HW + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return True if MSI enabled else False + */ +NvBool +kbifIsMSIEnabledInHW_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 data32; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_MSI_64_HEADER, + &data32) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "unable to read NV_EP_PCFG_GPU_MSI_64_HEADER\n"); + } + + return FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _MSI_64_HEADER, + _MSI_ENABLE, 0x1, data32); +} + +/*! + * @brief Check if MSIX is enabled in HW + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return True if MSIX enabled else False + */ +NvBool +kbifIsMSIXEnabledInHW_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 data32; + + if (IS_VIRTUAL(pGpu)) + { + // SR-IOV guests only support MSI-X + return IS_VIRTUAL_WITH_SRIOV(pGpu); + } + else + { + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_MSIX_CAP_HEADER, &data32) != NV_OK) + { + NV_ASSERT_FAILED("Unable to read NV_EP_PCFG_GPU_MSIX_CAP_HEADER\n"); + return NV_FALSE; + } + return FLD_TEST_DRF(_EP_PCFG_GPU, _MSIX_CAP_HEADER, _ENABLE, + _ENABLED, data32); + } +} + +/*! + * @brief Check if access to PCI config space is enabled or not + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return NV_TRUE Pci IO access is enabled + */ +NvBool +kbifIsPciIoAccessEnabled_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 data = 0; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS, &data) == NV_OK) + { + if (FLD_TEST_DRF(_EP_PCFG_GPU, _CTRL_CMD_AND_STATUS, _CMD_IO_SPACE, _ENABLE, data)) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +/*! + * @brief Check if device is a 3D controller + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return NV_TRUE If device is a 3D controller + */ +NvBool +kbifIs3dController_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 data = 0; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE, &data) == NV_OK) + { + if (FLD_TEST_DRF(_EP_PCFG_GPU, _REVISION_ID_AND_CLASSCODE, _BASE_CLASSCODE, _3D, data)) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +/*! + * @brief Enables extended tag support for GPU. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + */ +void +kbifEnableExtendedTagSupport_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 reg; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CAPABILITIES, + ®) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CAPABILITIES\n"); + goto _kbifEnableExtendedTagSupport_GH100_exit; + } + + reg = GPU_DRF_VAL(_EP_PCFG_GPU, _DEVICE_CAPABILITIES, + _EXTENDED_TAG_FIELD_SUPPORTED, reg); + if ((reg != 0) && + !pCl->getProperty(pCl, PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE)) + { + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + ®) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS\n"); + goto _kbifEnableExtendedTagSupport_GH100_exit; + } + reg = FLD_SET_DRF(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _EXTENDED_TAG_FIELD_ENABLE, _INIT, reg); + + if (GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + reg) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to write NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS\n"); + goto _kbifEnableExtendedTagSupport_GH100_exit; + } + } + +_kbifEnableExtendedTagSupport_GH100_exit: + return; +} + +/*! + * @brief Enable/disable no snoop for GPU + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * @param[in] bEnable True if No snoop needs to be enabled + * + * @return NV_OK If no snoop modified as requested + */ +NV_STATUS +kbifEnableNoSnoop_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool bEnable +) +{ + NvU8 fieldVal; + NvU32 regVal; + NvU32 status = NV_OK; + + status = GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, ®Val); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS.\n"); + goto _kbifEnableNoSnoop_GH100_exit; + } + + fieldVal = bEnable ? 1 : 0; + regVal = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _ENABLE_NO_SNOOP, fieldVal, regVal); + status = GPU_BUS_CFG_CYCLE_WR32(pGpu, + NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, regVal); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS.\n"); + goto _kbifEnableNoSnoop_GH100_exit; + } + +_kbifEnableNoSnoop_GH100_exit: + return status; +} + +/*! + * @brief Enables Relaxed Ordering PCI-E Capability in the PCI Config Space + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + */ +void +kbifPcieConfigEnableRelaxedOrdering_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + + NvU32 xveDevCtrlStatus; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + &xveDevCtrlStatus) == NV_ERR_GENERIC) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS!\n"); + } + else + { + GPU_BUS_CFG_CYCLE_FLD_WR_DRF_DEF(pGpu, xveDevCtrlStatus, _EP_PCFG_GPU, + _DEVICE_CONTROL_STATUS, _ENABLE_RELAXED_ORDERING, _INIT); + } +} + +/*! + * @brief Disables Relaxed Ordering PCI-E Capability in the PCI Config Space + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + */ +void +kbifPcieConfigDisableRelaxedOrdering_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 xtlDevCtrlStatus; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + &xtlDevCtrlStatus) == NV_ERR_GENERIC) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS!\n"); + } + else + { + xtlDevCtrlStatus = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _ENABLE_RELAXED_ORDERING, 0, xtlDevCtrlStatus); + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + xtlDevCtrlStatus); + } +} + +/*! + * @brief Get the status of XTL + * (Function name ideally should be bifGetXtlStatusBits) + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[out] pBits PCIE error status values + * @param[out] pStatus Full XTL status + * + * @return NV_OK + */ +NV_STATUS +kbifGetXveStatusBits_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 *pBits, + NvU32 *pStatus +) +{ + + // control/status reg 0x68 + NvU32 xtlDevCtrlStatus; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + &xtlDevCtrlStatus) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS!\n"); + } + if (pBits == NULL) + return NV_ERR_GENERIC; + + *pBits = 0; + + // The register read above returns garbage on fmodel, so just return. + if (IS_FMODEL(pGpu)) + { + if (pStatus) + { + *pStatus = 0; + } + return NV_OK; + } + + // Optionally return full status + if (pStatus) + { + *pStatus = xtlDevCtrlStatus; + } + + if (xtlDevCtrlStatus & DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _CORR_ERROR_DETECTED, 1)) + { + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR; + } + if (xtlDevCtrlStatus & DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _NON_FATAL_ERROR_DETECTED, 1)) + { + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR; + } + if (xtlDevCtrlStatus & DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _FATAL_ERROR_DETECTED, 1)) + { + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR; + } + if (xtlDevCtrlStatus & DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, + _UNSUPP_REQUEST_DETECTED, 1)) + { + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST; + } + + if (pKernelBif->EnteredRecoverySinceErrorsLastChecked) + { + pKernelBif->EnteredRecoverySinceErrorsLastChecked = NV_FALSE; + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY; + } + + return NV_OK; +} + +/*! + * @brief Clear XVE status + * (Function name ideally should be bifClearXtlStatus) + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[out] pStatus Full XTL status + * + * @return NV_OK + */ +NV_STATUS +kbifClearXveStatus_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 *pStatus +) +{ + + NvU32 xtlDevCtrlStatus; + + if (pStatus) + { + xtlDevCtrlStatus = *pStatus; + if (xtlDevCtrlStatus == 0) + { + return NV_OK; + } + } + else + { + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, + NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, &xtlDevCtrlStatus) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS!\n"); + } + } + + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, xtlDevCtrlStatus); + + return NV_OK; +} + +/*! + * @brief Get XTL AER bits + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[out] pBits XTL AER bits value + * + * @return NV_OK + */ +NV_STATUS +kbifGetXveAerBits_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 *pBits +) +{ + + NvU32 xtlAerUncorr; + NvU32 xtlAerCorr; + + if (pBits == NULL) + return NV_ERR_GENERIC; + + // The register read below returns garbage on fmodel, so just return. + if (IS_FMODEL(pGpu)) + { + return NV_OK; + } + + *pBits = 0; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS, + &xtlAerUncorr) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS\n"); + return NV_ERR_GENERIC; + } + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS, + &xtlAerCorr) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS\n"); + return NV_ERR_GENERIC; + } + + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _DL_PROTOCOL_ERROR, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _POISONED_TLP_RCVD, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _COMPLETION_TIMEOUT, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _UNEXPECTED_COMPLETION, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _MALFORMED_TLP, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _UNSUPPORTED_REQUEST_ERROR, 0x1, xtlAerUncorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ; + + // FERMI-TODO + + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _RECEIVER_ERROR, 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _BAD_TLP, 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _BAD_DLLP , 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _REPLAY_NUM_ROLLOVER, 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _REPLAY_TIMER_TIMEOUT, 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT; + if (FLD_TEST_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _ADVISORY_NON_FATAL_ERROR, 0x1, xtlAerCorr)) + *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL; + + return NV_OK; +} + +/*! + * @brief Clear XTL AER bits + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[in] bits XTL AER bits to be cleared + * + * @return NV_OK + */ +NV_STATUS +kbifClearXveAer_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 bits +) +{ + + NvU32 xtlAerUncorr = 0; + NvU32 xtlAerCorr = 0; + + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _DL_PROTOCOL_ERROR, 0x1, + xtlAerUncorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _POISONED_TLP_RCVD, 0x1, + xtlAerUncorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _COMPLETION_TIMEOUT, 0x1, + xtlAerUncorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _UNEXPECTED_COMPLETION, 0x1, + xtlAerUncorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _MALFORMED_TLP, 0x1, + xtlAerUncorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ) + xtlAerUncorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _UNCORRECTABLE_ERROR_STATUS, _UNSUPPORTED_REQUEST_ERROR, 0x1, + xtlAerUncorr); + + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _RECEIVER_ERROR, 0x1, + xtlAerCorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _BAD_TLP, 0x1, + xtlAerCorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _BAD_DLLP, 0x1, + xtlAerCorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _REPLAY_NUM_ROLLOVER, 0x1, + xtlAerCorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _REPLAY_TIMER_TIMEOUT, 0x1, + xtlAerCorr); + if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL) + xtlAerCorr = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _CORRECTABLE_ERROR_STATUS, _ADVISORY_NON_FATAL_ERROR, 0x1, + xtlAerCorr); + + if (xtlAerUncorr != 0) + { + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS, xtlAerUncorr); + } + if (xtlAerCorr != 0) + { + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS, xtlAerCorr); + } + + return NV_OK; +} + +/*! + * @brief Return the BAR0 offset and size of the PCI config space mirror. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * @param[out] pBase BAR0 offset of the PCI config space mirror + * @param[out] pSize Size in bytes of the PCI config space mirror + * + * @returns NV_OK + */ +NV_STATUS +kbifGetPciConfigSpacePriMirror_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 *pBase, + NvU32 *pSize +) +{ + + *pBase = DEVICE_BASE(NV_EP_PCFGM); + *pSize = DEVICE_EXTENT(NV_EP_PCFGM) - DEVICE_BASE(NV_EP_PCFGM) + 1; + return NV_OK; +} + +/*! + * Kernel-RM only function to enable PCIe requester atomics by + * using OS HAL interface and to cache the completer side capabilities returned + * by the OS HAL interface. RM regkeys "RMSysmemSelectAtomicsConfig" and + * "RMSysmemOverridePcieReqAtomicOps" can be used to force override the + * settings. + * + * + * @param[in] pGpu OBJGPU pointer + * @param[in/out] pKernelBif Kernel BIF object pointer, PCIe requester atomics details + * are cached in here. + * @returns None + */ +void +kbifProbePcieReqAtomicCaps_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 osAtomicsMask = 0; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + if (!pCl->getProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS)) + { + NV_PRINTF(LEVEL_INFO, "PCIe atomics not supported in this platform!\n"); + return; + } + + if (osConfigurePcieReqAtomics(pGpu->pOsGpuInfo, &osAtomicsMask) != NV_OK || + osAtomicsMask == 0) + { + NV_PRINTF(LEVEL_INFO, "PCIe requester atomics not enabled since " + "completer is not capable!\n"); + return; + } + + pKernelBif->osPcieAtomicsOpMask = osAtomicsMask; + + // Program PCIe atomics register settings + _kbifEnablePcieAtomics_GH100(pGpu); + + return; +} + +/*! + * @brief Enable PCIe atomics if PCIe hierarchy supports it + * + * @param[in] Gpu GPU object pointer + */ +static void +_kbifEnablePcieAtomics_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 regVal; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2, ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Read of NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 failed.\n"); + return; + } + + regVal = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS_2, _ATOMIC_OP_REQUESTER_ENABLE, 0x1, regVal); + + if (GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2, regVal) != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Write of NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 failed.\n"); + return; + } + + NV_PRINTF(LEVEL_INFO, "PCIe Requester atomics enabled.\n"); +} + +/*! + * @brief Get bus options: link specific capabilities or + * pcie device specific parameters or pcie link specific parameters + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[in] options XTL bus options + * @param[out] pAddrReg Address of the register for the given bus option + * + * @return NV_OK on success + * NV_ERR_GENERIC + */ +NV_STATUS +kbifGetBusOptionsAddr_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + BUS_OPTIONS options, + NvU32 *pAddrReg +) +{ + NV_STATUS status = NV_OK; + + switch (options) + { + case BUS_OPTIONS_DEV_CONTROL_STATUS: + *pAddrReg = NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS; + break; + case BUS_OPTIONS_LINK_CONTROL_STATUS: + *pAddrReg = NV_EP_PCFG_GPU_LINK_CONTROL_STATUS; + break; + case BUS_OPTIONS_LINK_CAPABILITIES: + *pAddrReg = NV_EP_PCFG_GPU_LINK_CAPABILITIES; + break; + default: + NV_PRINTF(LEVEL_ERROR, "Invalid register type passed 0x%x\n", + options); + status = NV_ERR_GENERIC; + break; + } + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index b7818369c..9c1f48503 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -92,9 +92,10 @@ kbifStateInitLocked_IMPL KernelBif *pKernelBif ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); - OBJCL *pCl = SYS_GET_CL(pSys); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + OBJCL *pCl = SYS_GET_CL(pSys); + NV_STATUS status = NV_OK; // Return early if GPU is connected to an unsupported chipset if (pCl->getProperty(pCl, PDB_PROP_CL_UNSUPPORTED_CHIPSET)) @@ -102,6 +103,13 @@ kbifStateInitLocked_IMPL return NV_ERR_NOT_COMPATIBLE; } + // Initialize OS mapping and core logic + status = osInitMapping(pGpu); + if (status != NV_OK) + { + return status; + } + // Initialize BIF static info kbifStaticInfoInit(pGpu, pKernelBif); @@ -119,7 +127,7 @@ kbifStateInitLocked_IMPL pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SUPPORT_NONCOHERENT, NV_FALSE); } - return NV_OK; + return status; } /*! @@ -145,8 +153,6 @@ kbifStateLoad_IMPL // Check for stale PCI-E dev ctrl/status errors and AER errors kbifClearConfigErrors(pGpu, pKernelBif, NV_TRUE, KBIF_CLEAR_XVE_AER_ALL_MASK); - kbifInitPcieDeviceControlStatus(pGpu, pKernelBif); - // // A vGPU cannot disappear and these accesses are // particularly expensive on vGPUs @@ -366,6 +372,15 @@ kbifInitPcieDeviceControlStatus kbifPcieConfigDisableRelaxedOrdering_HAL(pGpu, pKernelBif); } + // + // WAR for bug 3661529. All GH100 SKUs will need the NoSnoop WAR. + // But currently GSP-RM does not detect this correctly, + // + if (IsGH100(pGpu)) + { + pCl->setProperty(pCl, PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR, NV_TRUE); + } + if (!pCl->getProperty(pCl, PDB_PROP_CL_NOSNOOP_NOT_CAPABLE) && !pCl->getProperty(pCl, PDB_PROP_CL_ROOTPORT_NEEDS_NOSNOOP_WAR)) { @@ -910,7 +925,7 @@ kbifControlGetPCIEInfo_IMPL { NV2080_CTRL_BUS_INFO busInfo = {0}; NV_STATUS rmStatus = NV_OK; - + busInfo.index = NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO; if ((rmStatus = kbusSendBusInfo(pGpu, GPU_GET_KERNEL_BUS(pGpu), &busInfo)) != NV_OK) @@ -918,7 +933,7 @@ kbifControlGetPCIEInfo_IMPL NV_PRINTF(LEVEL_INFO, "Squashing rmStatus: %x \n", rmStatus); rmStatus = NV_OK; busInfo.data = 0; - } + } data = busInfo.data; } } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c index 0dcbc27c4..7307650bd 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c @@ -532,7 +532,8 @@ kbusInitFla_GA100 // Bug: 2985556, re-enable once we fix this bug. // if (((NULL != pKernelMIGManager) && !kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)) || - (IsSLIEnabled(pGpu))) + (IsSLIEnabled(pGpu)) || pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) { NV_PRINTF(LEVEL_INFO, "FLA is disabled, gpu %x is in MIG/SLI mode \n", pGpu->gpuInstance); pKernelBus->bFlaSupported = NV_FALSE; @@ -577,6 +578,7 @@ kbusInitFla_GA100 NV_PRINTF(LEVEL_INFO, "Failed to enable FLA for GPU: %x\n", pGpu->gpuInstance); return status; } + base = params.addr; } else @@ -713,36 +715,34 @@ kbusDestroyHostManagedFlaVaspace_GA100 NV_PRINTF(LEVEL_INFO, "Freeing the FLA client: 0x%x FLAVASpace:%x, gpu:%x \n", pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hFlaVASpace, pGpu->gpuInstance); - if (pKernelBus->flaInfo.pFlaVAS) + if (pKernelBus->flaInfo.bFlaAllocated) { - NV_ASSERT(pKernelBus->flaInfo.bFlaBind == NV_FALSE); - if (pKernelBus->flaInfo.bFlaAllocated) - { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + if (pKernelBus->flaInfo.pFlaVAS != NULL) + { vaspaceUnpinRootPageDir(pKernelBus->flaInfo.pFlaVAS, pGpu); - - if (pGpu->pFabricVAS != NULL) - { - vaspaceUnpinRootPageDir(pGpu->pFabricVAS, pGpu); - vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); - pGpu->pFabricVAS = NULL; - } - - kbusDestructFlaInstBlk_HAL(pGpu, pKernelBus); - pKernelBus->flaInfo.hClient = NV01_NULL_OBJECT; - pKernelBus->flaInfo.hDevice = NV01_NULL_OBJECT; - pKernelBus->flaInfo.hSubDevice = NV01_NULL_OBJECT; pKernelBus->flaInfo.hFlaVASpace = NV01_NULL_OBJECT; pKernelBus->flaInfo.pFlaVAS = NULL; - pKernelBus->flaInfo.bFlaAllocated = NV_FALSE; + } - if (pKernelNvlink == NULL || !knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) - { - pKernelBus->flaInfo.bFlaRangeRegistered = NV_FALSE; - pKernelBus->flaInfo.base = 0; - pKernelBus->flaInfo.size = 0; - } + if (pGpu->pFabricVAS != NULL) + { + vaspaceUnpinRootPageDir(pGpu->pFabricVAS, pGpu); + vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); + pGpu->pFabricVAS = NULL; + } + + kbusDestructFlaInstBlk_HAL(pGpu, pKernelBus); + pKernelBus->flaInfo.hClient = NV01_NULL_OBJECT; + pKernelBus->flaInfo.hDevice = NV01_NULL_OBJECT; + pKernelBus->flaInfo.hSubDevice = NV01_NULL_OBJECT; + pKernelBus->flaInfo.bFlaAllocated = NV_FALSE; + if (pKernelNvlink == NULL || !knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + pKernelBus->flaInfo.bFlaRangeRegistered = NV_FALSE; + pKernelBus->flaInfo.base = 0; + pKernelBus->flaInfo.size = 0; } } } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c new file mode 100644 index 000000000..634f95e02 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -0,0 +1,1143 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bus/p2p_api.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "os/os.h" + +#include "published/hopper/gh100/dev_ram.h" +#include "published/hopper/gh100/pri_nv_xal_ep.h" +#include "published/hopper/gh100/pri_nv_xal_ep_p2p.h" +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_mmu.h" + +#include "nvRmReg.h" + + // Defines for P2P +#define HOPPER_WRITE_MAILBOX_SIZE ((NvU64)64 * 1024) +#define HOPPER_MAX_WRITE_MAILBOX_ADDR \ + ((HOPPER_WRITE_MAILBOX_SIZE << DRF_SIZE(NV_XAL_EP_P2P_WMBOX_ADDR_ADDR)) - \ + HOPPER_WRITE_MAILBOX_SIZE) + +NV_STATUS +kbusSetBAR0WindowVidOffset_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 vidOffset +) +{ + + NV_ASSERT((vidOffset & 0xffff)==0); + NV_ASSERT((vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT) <= DRF_MASK(NV_XAL_EP_BAR0_WINDOW_BASE)); + + // + // RM initialises cachedBar0WindowVidOffset with 0. Refresh its value with + // current NV_XAL_EP_BAR0_WINDOW_BASE. + // + if (pKernelBus->cachedBar0WindowVidOffset == 0) + { + pKernelBus->cachedBar0WindowVidOffset = ((NvU64) GPU_REG_RD_DRF(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE)) + << NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT; + } + + // Update only if the new offset is different from the cached value + if (pKernelBus->cachedBar0WindowVidOffset != vidOffset) + { + NV_PRINTF(LEVEL_INFO, + "mapping BAR0_WINDOW to VID:%x'%08x\n", + NvU64_HI32(vidOffset), NvU64_LO32(vidOffset)); + + // _BAR0_WINDOW_TARGET field is removed. It's always VIDMEM + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(vidOffset >> 16)); + + pKernelBus->cachedBar0WindowVidOffset = vidOffset; + } + + return (NV_OK); +} + +NvU64 +kbusGetBAR0WindowVidOffset_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 vidOffset; + + // + // RM initialises cachedBar0WindowVidOffset with 0. Refresh its value with + // current NV_XAL_EP_BAR0_WINDOW_BASE. + // + if (pKernelBus->cachedBar0WindowVidOffset == 0) + { + pKernelBus->cachedBar0WindowVidOffset = ((NvU64) GPU_REG_RD_DRF(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE)) + << NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT; + } + + vidOffset = pKernelBus->cachedBar0WindowVidOffset; + + return (vidOffset); +} + +/*! + * @brief Tests BAR2 against BAR0. + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] pMemDescIn If memDescIn is NULL, a test mem desc is created and map/unmapped. + * If memDescIn is not NULL and provided, this method assumes that it has + * already been alloc'ed and mapping/unmapping is handled outside + * this method. + * @param[in] offset offset of the test memory + * @param[in] size size of the test memory + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusVerifyBar2_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + PMEMORY_DESCRIPTOR pMemDescIn, + NvU8 *pCpuPtrIn, + NvU64 offset, + NvU64 size +) +{ + MEMORY_DESCRIPTOR memDesc, *pMemDesc = NULL; + NvU8 *pOffset = NULL; + NvU32 index = 0; + NvU64 bar0Window = 0; + NvU64 testMemoryOffset = 0; + NvU32 testMemorySize = 0; + NV_STATUS status = NV_OK; + NvU32 testData = 0; + NvU32 temp = 0; + NV_ADDRESS_SPACE testAddrSpace = ADDR_FBMEM; + NvBool bIsStandaloneTest; + const NvU32 SAMPLEDATA = 0xabcdabcd; + const NvU32 FBSIZETESTED = 0x10; + NvU64 bar0TestAddr = 0; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU32 flagsClean = 0; + NvU64 bar2VirtualAddr = 0; + + // + // kbusVerifyBar2 will test BAR0 against sysmem on Tegra; otherwise skip + // the test if inst_in_sys is used + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) && + !IsTEGRA(pGpu)) + { + return NV_OK; + } + + // In L2 Cache only mode or FB broken, don't verify Bar2 + if (gpuIsCacheOnlyModeEnabled(pGpu) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + kbusIsBar2TestSkipped(pKernelBus)) + { + return NV_OK; + } + + NV_PRINTF(LEVEL_INFO, "\n"); + + flagsClean = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | + NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; + if (kmemsysIsL2CleanFbPull(pKernelMemorySystem)) + { + flagsClean |= NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL; + } + + if (pMemDescIn && pCpuPtrIn) + { + if ((size + offset) > pMemDescIn->Size) + { + NV_PRINTF(LEVEL_ERROR, + "input offset 0x%llx size 0x%llx exceeds surface size 0x%llx\n", + offset, size, pMemDescIn->Size); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + bIsStandaloneTest = NV_FALSE; + pOffset = pCpuPtrIn; + pMemDesc = pMemDescIn; + } + else + { + offset = 0; + size = FBSIZETESTED; + // Allocate some memory to test virtual BAR2 with + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + memdescCreateExisting(&memDesc, pGpu, size, ADDR_SYSMEM, pGpu->instCacheOverride, MEMDESC_FLAGS_NONE); + } + else + { + memdescCreateExisting(&memDesc, pGpu, size, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); + } + status = memdescAlloc(&memDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Could not allocate vidmem to test bar2 with\n"); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + bIsStandaloneTest = NV_TRUE; + pOffset = kbusMapRmAperture_HAL(pGpu, &memDesc); + if (pOffset == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto kbusVerifyBar2_failed; + } + pMemDesc = &memDesc; + } + testMemoryOffset = memdescGetPhysAddr(pMemDesc, AT_GPU, 0) + offset; + testMemorySize = NvU64_LO32(size); + testAddrSpace = kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pMemDesc); + + if (testAddrSpace != NV_MMU_PTE_APERTURE_VIDEO_MEMORY) + { + NV_PRINTF(LEVEL_ERROR, + "Test is not supported. NV_XAL_EP_BAR0_WINDOW only supports vidmem\n"); + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto kbusVerifyBar2_failed; + } + + // ========================================================== + // Does the BAR0 window work? + + NV_PRINTF((IS_EMULATION(pGpu)) ? LEVEL_ERROR : LEVEL_INFO, + "Testing BAR0 window...\n"); + + bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); + bar0TestAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0TestAddr >> 16)); + + testData = GPU_REG_RD32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff)); + + GPU_REG_WR32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff), SAMPLEDATA); + + if (GPU_REG_RD32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff)) != SAMPLEDATA) + { + // + // Ideally, this should hit the L2 cache and even if memory is bad, + // unless something in the path up to L2 is messed up, we should not + // get here. + // + NV_PRINTF(LEVEL_ERROR, + "Pre-L2 invalidate evict: Address 0x%llx programmed through the bar0 " + "window with value 0x%x did not read back the last write.\n", + bar0TestAddr, SAMPLEDATA); + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_MEMORY_ERROR; + goto kbusVerifyBar2_failed; + } + + // + // Evict L2 to ensure that the next read doesn't hit L2 and mistakenly + // assume that the BAR0 window to vidmem works + // + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); + goto kbusVerifyBar2_failed; + } + + if (GPU_REG_RD32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff)) != SAMPLEDATA) + { + NV_PRINTF(LEVEL_ERROR, + "Post-L2 invalidate evict: Address 0x%llx programmed through the bar0 " + "window with value 0x%x did not read back the last write\n", + bar0TestAddr, SAMPLEDATA); + if (IS_EMULATION(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Setup a trigger on write with a 3 quarters post " + "trigger capture\n"); + NV_PRINTF(LEVEL_ERROR, + "and search for the last bar0 window write not returning the same value" + " in a subsequent read\n"); + } + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_MEMORY_ERROR; + goto kbusVerifyBar2_failed; + } + + NV_PRINTF((IS_EMULATION(pGpu)) ? LEVEL_ERROR : LEVEL_INFO, + "Bar0 window tests successfully\n"); + GPU_REG_WR32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff), testData); + + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0Window >> 16)); + + // ========================================================== + // Does MMU's translation logic work? + + bar2VirtualAddr = (NvU64)(pOffset - pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping); + NV_PRINTF(LEVEL_INFO, + "MMUTest Writing test data through virtual BAR2 starting at bar2 offset" + " (%p - %p) = %p and of size 0x%x\n", (NvU8 *)pOffset, + (NvU8 *)pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping, + (NvU8 *)bar2VirtualAddr, testMemorySize); + + NV_PRINTF((IS_EMULATION(pGpu) == NV_TRUE) ? LEVEL_ERROR : LEVEL_INFO, + "MMUTest The physical address being targetted is 0x%llx\n", + testMemoryOffset); + + for(index = 0; index < testMemorySize; index += 4) + { + MEM_WR32(pOffset + index, SAMPLEDATA); + } + + // Flush the bar2 writes + // A uflush should not be required since a bar0 window read follows after this + osFlushCpuWriteCombineBuffer(); + + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); + goto kbusVerifyBar2_failed; + } + + // + // Read back using the same BAR2 VA. This can make sure the writes have + // gotten to memory after MMU translation. + // + // What it will catch: + // - FB dead (also caught by BAR0 test above) + // - MMU translation fails on BAR2 + // - MMU translation works but other parts of memsys having issues + // + // It will not verify whether the mapping points to the right physical + // memory. The BAR0 readback test will do that next. + // + for(index = 0; index < testMemorySize; index += 4) + { + NvU32 bar2ReadbackData = 0; + bar2ReadbackData = MEM_RD32(pOffset + index); + + if (bar2ReadbackData != SAMPLEDATA) + { + NV_PRINTF(LEVEL_ERROR, + "MMUTest BAR2 readback VA = 0x%llx returned garbage 0x%x\n", + (bar2VirtualAddr + index), bar2ReadbackData); + + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_MEMORY_ERROR; + goto kbusVerifyBar2_failed; + } + } + + // Readback through the bar0 window + bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); + + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(testMemoryOffset >> 16)); + + NV_PRINTF(LEVEL_INFO, + "bar0Window = 0x%llx, testMemoryOffset = 0x%llx, testAddrSpace = %d, " + "_XAL_EP_BAR0_WINDOW = 0x%08x\n", bar0Window, testMemoryOffset, + testAddrSpace, GPU_REG_RD32(pGpu, NV_XAL_EP_BAR0_WINDOW)); + + temp = (DRF_BASE(NV_PRAMIN) + (NvU32)(testMemoryOffset & 0xffff)); + for(index = 0; index < testMemorySize; index += 4) + { + NvU32 bar0WindowData = GPU_REG_RD32(pGpu, temp + index); + if (bar0WindowData != SAMPLEDATA) + { + NV_PRINTF(LEVEL_ERROR, + "MMUTest BAR0 window offset 0x%x returned garbage 0x%x\n", + temp + index, bar0WindowData); + if (IS_EMULATION(pGpu) == NV_TRUE) + { + NV_PRINTF(LEVEL_ERROR, + "Setup a trigger for write and in the waves search" + " the last few bar2 virtual writes mixed with bar0 window reads\n"); + } + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_MEMORY_ERROR; + goto kbusVerifyBar2_failed; + } + // Write through the BAR0 window to be readback through BAR2 later + GPU_REG_WR32(pGpu, temp + index, SAMPLEDATA + 0x10); + } + + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0Window >> 16)); + + status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + + // Bail now if we have encountered any error + if (status != NV_OK) + { + goto kbusVerifyBar2_failed; + } + + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + goto kbusVerifyBar2_failed; + } + + // Verify BAR2 virtual reads + for(index = 0; index < testMemorySize; index +=4) + { + temp = MEM_RD32(pOffset + index); + if (temp != (SAMPLEDATA + 0x10)) + { + NV_PRINTF(LEVEL_ERROR, + "MMUTest BAR2 Read of virtual addr 0x%x returned garbage 0x%x\n", + (NvU32)(pOffset - pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) + index, + temp); + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_MEMORY_ERROR; + goto kbusVerifyBar2_failed; + } + } + +kbusVerifyBar2_failed: + if (bIsStandaloneTest) + { + if (pOffset != NULL) + { + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pOffset, NV_TRUE); + } + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + } + + if (status == NV_OK) + { + NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, + "BAR2 virtual test passes\n"); + } + + return status; +} + +/*! + * @brief Tear down BAR2 CPU aperture + * + * 1. Release BAR2 GPU vaspace mappings. + * 2. Release BAR2 CPU mapping. + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] gfid + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusTeardownBar2CpuAperture_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + // Nothing to be done in guest in the paravirtualization case. + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_GFID_VF(gfid)) + { + return NV_OK; + } + + if (KBUS_BAR2_TUNNELLED(pKernelBus)) + { + // KBUS-TODO -- dead code path? + // KBUS_BAR2_TUNNELLED is never true on HOPPER+ + + // Unmap bar2 space + if (pKernelBus->virtualBar2[gfid].pCpuMapping) + { + // Remove the memory access filter + osMemRemoveFilter((NvU64)((NvUPtr)(pKernelBus->virtualBar2[gfid].pCpuMapping))); + portMemFree(pKernelBus->virtualBar2[gfid].pCpuMapping); + pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; + } + } + else + { + if (pKernelBus->virtualBar2[gfid].pPageLevels) + { + memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, + TRANSFER_FLAGS_NONE); + pKernelBus->virtualBar2[gfid].pPageLevels = NULL; + } + + kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus); + + kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); + + if (pKernelBus->virtualBar2[gfid].pCpuMapping) + { + osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); + // Mark the BAR as un-initialized so that a later call + // to initbar2 can succeed. + pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; + } + + // + // make sure that the bar2 mode is physical so that the vesa extended + // linear framebuffer works after driver unload. Clear other bits to force + // vid. + // + // if BROKEN_FB, merely rewriting this to 0 (as it already was) causes + // FBACKTIMEOUT -- don't do it (Bug 594539) + // + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) + { + GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _MODE, _PHYSICAL); + // bug 1738008: temporary fix to unblock -inst_in_sys argument + // we tried to correct bar2 unbind sequence but didn't fix the real issue + // will fix this soon 4/8/16 + GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR); + } + } + + return NV_OK; +} + +// +// Returns the P2P mailbox attributes such as: +// - pMailboxAreaSize: total size +// - pMailboxAlignmentBits: aligment in number of bits +// - pMailboxMaxOffset: max supported offset +// +void +kbusGetP2PMailboxAttributes_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32* pMailboxAreaSize, + NvU32* pMailboxAlignmentSize, + NvU32* pMailboxBar1MaxOffset64KB +) +{ + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + // Initialize null values by default + if (pMailboxAreaSize != NULL) + { + *pMailboxAreaSize = 0; + } + if (pMailboxAlignmentSize != NULL) + { + *pMailboxAlignmentSize = 0; + } + if (pMailboxBar1MaxOffset64KB != NULL) + { + *pMailboxBar1MaxOffset64KB = 0; + } + + if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) + { + // Return null values + return; + } + + // Retrieve attributes + if (pMailboxAreaSize != NULL) + { + *pMailboxAreaSize = HOPPER_WRITE_MAILBOX_SIZE * P2P_MAX_NUM_PEERS; + } + + if (pMailboxAlignmentSize != NULL) + { + // Write mailbox data window needs to be 64KB aligned. + *pMailboxAlignmentSize = 0x10000; + } + + if (pMailboxBar1MaxOffset64KB != NULL) + { + *pMailboxBar1MaxOffset64KB = + NvU64_LO32( + (HOPPER_MAX_WRITE_MAILBOX_ADDR + HOPPER_WRITE_MAILBOX_SIZE) >> 16 + ); + } + + return; +} + +RmPhysAddr +kbusSetupP2PDomainAccess_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + PMEMORY_DESCRIPTOR *ppP2PDomMemDesc +) +{ + return kbusSetupPeerBarAccess(pGpu0, pGpu1, + pGpu0->busInfo.gpuPhysAddr + DRF_BASE(NV_XAL_EP_P2P), + DRF_SIZE(NV_XAL_EP_P2P), ppP2PDomMemDesc); +} + +NV_STATUS +kbusFlushPcieForBar0Doorbell_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + return kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); +} + +/*! + * @brief Create a P2P mapping to a given peer GPU + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[out] peer0 Peer ID (local to remote) + * @param[out] peer1 Peer ID (remote to local) + * @param[in] attributes Sepcial attributes for the mapping + * + * return NV_OK on success + */ +NV_STATUS +kbusCreateP2PMapping_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 *peer0, + NvU32 *peer1, + NvU32 attributes +) +{ + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _C2C, attributes)) + { + return kbusCreateP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, attributes) || + FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK_INDIRECT, attributes)) + { + return kbusCreateP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes)) + { + return kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes)) + { + return kbusCreateP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + NV_PRINTF(LEVEL_ERROR, "P2P type %d is not supported\n", DRF_VAL(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, attributes)); + + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Remove the P2P mapping to a given peer GPU + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[out] peer0 Peer ID (local to remote) + * @param[out] peer1 Peer ID (remote to local) + * @param[in] attributes Sepcial attributes for the mapping + * + * return NV_OK on success + */ +NV_STATUS +kbusRemoveP2PMapping_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 peer0, + NvU32 peer1, + NvU32 attributes +) +{ + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _C2C, attributes)) + { + return kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, attributes) || + FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK_INDIRECT, attributes)) + { + return kbusRemoveP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE_BAR1, attributes)) + { + return kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); + } + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _PCIE, attributes)) + { + return kbusRemoveP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); + } + + NV_PRINTF(LEVEL_ERROR, "P2P type %d is not supported\n", DRF_VAL(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, attributes)); + + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Returns the peer number from pGpu (Local) to pGpuPeer + * + * @param[in] pGpu Local + * @param[in] pKernelBus Local + * @param[in] pGpuPeer Remote + * + * @returns NvU32 bus peer number + */ +NvU32 +kbusGetPeerId_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + OBJGPU *pGpuPeer +) +{ + NvU32 gpuPeerInst = gpuGetInstance(pGpuPeer); + NvU32 peerId = pKernelBus->c2cPeerInfo.busC2CPeerNumberMask[gpuPeerInst]; + + // Fall back to Nvlink + if (peerId == 0) + { + NV_PRINTF(LEVEL_INFO, + "C2C P2P not set up between GPU%u and GPU%u, checking for Nvlink...\n", + gpuGetInstance(pGpu), gpuPeerInst); + return kbusGetPeerId_GP100(pGpu, pKernelBus, pGpuPeer); + } + + LOWESTBITIDX_32(peerId); + return peerId; +} + +/** + * @brief Returns if the given peerId is a valid for a given GPU + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] peerId The peer identifier + * + * @return return NV_OK is valid + */ +NV_STATUS +kbusIsPeerIdValid_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 peerId +) +{ + NV_ASSERT_OR_RETURN(peerId < P2P_MAX_NUM_PEERS, NV_ERR_INVALID_INDEX); + if (pKernelBus->c2cPeerInfo.busC2CPeerNumberMask[gpuGetInstance(pGpu)] & NVBIT(peerId)) + return NV_OK; + return kbusIsPeerIdValid_GP100(pGpu, pKernelBus, peerId); +} + +/*! + * @brief check if there is BAR1 P2P mapping between given GPUs + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * + * return NV_TRUE if the P2P is using BAR1 + */ +NvBool +kbusHasPcieBar1P2PMapping_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + return (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu1)] != 0 && + pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu0)] != 0); +} + +/*! + * @brief Create a Bar1 P2P mapping to given GPUs + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[in] attributes attributes to control the mapping + * + * return NV_OK on success + * NV_ERR_NOT_SUPPORTED if it fails + */ +NV_STATUS +kbusCreateP2PMappingForBar1P2P_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 attributes +) +{ + NvU32 gpuInst0 = gpuGetInstance(pGpu0); + NvU32 gpuInst1 = gpuGetInstance(pGpu1); + + if (!kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1)) + return NV_ERR_NOT_SUPPORTED; + + pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]++; + pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]++; + + NV_PRINTF(LEVEL_INFO, "added PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", + gpuInst0, gpuInst1); + + return NV_OK; +} + +/*! + * @brief remove a Bar1 P2P mapping to given GPUs + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[in] attributes attributes of the P2P + * + * return NV_OK on success + */ +NV_STATUS +kbusRemoveP2PMappingForBar1P2P_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 attributes +) +{ + NvU32 gpuInst0, gpuInst1; + + gpuInst0 = gpuGetInstance(pGpu0); + gpuInst1 = gpuGetInstance(pGpu1); + + if ( (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) || + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0) ) + { + return NV_ERR_INVALID_STATE; + } + + pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]--; + pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]--; + + NV_PRINTF(LEVEL_INFO, + "removed PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", + gpuInst0, gpuInst1); + + return NV_OK; +} + +/*! + * @brief Returns the C2C peer ID from pGpu0 to pGpu1 after + * reserving it if peer mapping doesn't exist already + * for the GPU pair + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[out] c2cPeer NvU32 pointer contains the peer ID to use + * for local GPU to remote GPU when return value + * is NV_OK + * + * return NV_OK on success + */ +static NV_STATUS +_kbusGetC2CP2PPeerId +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 *c2cPeer +) +{ + NV_STATUS status = NV_OK; + return status; +} + +/*! + * @brief Create C2C mapping to a given peer GPU + * + * + * @param[in] pGpu0 (Local) + * @param[in] pKernelBus0 (Local) + * @param[in] pGpu1 (Remote) + * @param[in] peerId Peer ID to use for local GPU to + * remote GPU mapping. + * + * return NV_OK on success + */ +static NV_STATUS +_kbusCreateC2CPeerMapping +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + NvU32 peerId +) +{ + NvU32 gpuInstance = gpuGetInstance(pGpu1); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu0); + NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS params = {0}; + NV_STATUS status = NV_OK; + + // + // Increment the mapping refcount per peerID - since there is a new mapping that + // will use this peerID + // + pKernelBus0->c2cPeerInfo.busC2CMappingRefcountPerPeerId[peerId]++; + + // Set the peer IDs in the corresponding peer number masks + pKernelBus0->c2cPeerInfo.busC2CPeerNumberMask[gpuInstance] |= NVBIT(peerId); + + params.peerId = peerId; + status = pRmApi->Control(pRmApi, + pGpu0->hInternalClient, + pGpu0->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING, + ¶ms, + sizeof(NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS)); + NV_ASSERT(status == NV_OK); + + return status; +} + +/*! + * @brief Create a C2C P2P mapping to a given peer GPU + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[out] peer0 Peer ID (local to remote) + * @param[out] peer1 Peer ID (remote to local) + * + * return NV_OK on success + */ +NV_STATUS +kbusCreateP2PMappingForC2C_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 *peer0, + NvU32 *peer1, + NvU32 attributes +) +{ + NvU32 gpu0Instance = gpuGetInstance(pGpu0); + NvU32 gpu1Instance = gpuGetInstance(pGpu1); + NvU32 c2cPeer0; + NvU32 c2cPeer1; + NV_STATUS status; + + if (peer0 == NULL || peer1 == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((*peer0 != BUS_INVALID_PEER && *peer0 >= P2P_MAX_NUM_PEERS) || + (*peer1 != BUS_INVALID_PEER && *peer1 >= P2P_MAX_NUM_PEERS)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + c2cPeer0 = *peer0; + c2cPeer1 = *peer1; + + // Get the peer ID pGpu0 should use for P2P over C2C to pGpu1 + if ((status = _kbusGetC2CP2PPeerId(pGpu0, pKernelBus0, + pGpu1, pKernelBus1, + &c2cPeer0)) != NV_OK) + { + return status; + } + + // Get the peer ID pGpu1 should use for P2P over C2C to pGpu0 + if ((status = _kbusGetC2CP2PPeerId(pGpu1, pKernelBus1, + pGpu0, pKernelBus0, + &c2cPeer1)) != NV_OK) + { + return status; + } + + if ((c2cPeer0 == BUS_INVALID_PEER) || (c2cPeer1 == BUS_INVALID_PEER)) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create C2C P2P mapping between GPU%u and GPU%u\n", + gpu0Instance, gpu1Instance); + + return NV_ERR_INVALID_REQUEST; + } + + *peer0 = c2cPeer0; + *peer1 = c2cPeer1; + + // + // Does the mapping already exist between the given pair of GPUs using the peerIDs + // *peer0 and *peer1 respectively ? + // + if ((pKernelBus0->c2cPeerInfo.busC2CPeerNumberMask[gpu1Instance] & NVBIT(*peer0)) && + (pKernelBus1->c2cPeerInfo.busC2CPeerNumberMask[gpu0Instance] & NVBIT(*peer1))) + { + // + // Increment the mapping refcount per peerID - since there is another usage + // of a mapping that is using this peerID + // + pKernelBus0->c2cPeerInfo.busC2CMappingRefcountPerPeerId[*peer0]++; + pKernelBus1->c2cPeerInfo.busC2CMappingRefcountPerPeerId[*peer1]++; + + NV_PRINTF(LEVEL_INFO, + "- P2P: Peer mapping is already in use for gpu instances %x and %x " + "with peer id's %d and %d. Increasing the mapping refcounts for the" + " peer IDs to %d and %d respectively.\n", + gpu0Instance, gpu1Instance, *peer0, *peer1, + pKernelBus0->c2cPeerInfo.busC2CMappingRefcountPerPeerId[*peer0], + pKernelBus1->c2cPeerInfo.busC2CMappingRefcountPerPeerId[*peer1]); + + return NV_OK; + } + + // + // Reached here implies the mapping between the given pair of GPUs using the peerIDs + // *peer0 and *peer1 does not exist. Create the mapping + // + + NV_ASSERT_OK_OR_RETURN(_kbusCreateC2CPeerMapping(pGpu0, pKernelBus0, pGpu1, *peer0)); + NV_ASSERT_OK_OR_RETURN(_kbusCreateC2CPeerMapping(pGpu1, pKernelBus1, pGpu0, *peer1)); + + NV_PRINTF(LEVEL_INFO, + "added C2C P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", + gpu0Instance, *peer0, gpu1Instance, *peer1); + + return NV_OK; +} + +/*! + * @brief Remove C2C mapping to a given peer GPU + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] peerId Peer ID for local to remote GPU + * + * return NV_OK on success + */ +static NV_STATUS +_kbusRemoveC2CPeerMapping +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + NvU32 peerId +) +{ + NV_STATUS status = NV_OK; + return status; +} + +/*! + * @brief Remove the C2C P2P mapping to a pair of GPU + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[in] peer0 Peer ID (local to remote) + * @param[in] peer1 Peer ID (remote to local) + * + * return NV_OK on success + */ +NV_STATUS +kbusRemoveP2PMappingForC2C_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 peer0, + NvU32 peer1, + NvU32 attributes +) +{ + NV_STATUS status = NV_OK; + + // Check if there's C2C mapping + if (((pKernelBus0->c2cPeerInfo.busC2CPeerNumberMask[pGpu1->gpuInstance] & NVBIT(peer0)) == 0) || + ((pKernelBus1->c2cPeerInfo.busC2CPeerNumberMask[pGpu0->gpuInstance] & NVBIT(peer1)) == 0)) + { + return NV_ERR_INVALID_STATE; + } + + // C2C mapping exists, remove the C2C mapping + NV_ASSERT_OK_OR_RETURN(_kbusRemoveC2CPeerMapping(pGpu0, pKernelBus0, pGpu1, peer0)); + NV_ASSERT_OK_OR_RETURN(_kbusRemoveC2CPeerMapping(pGpu1, pKernelBus1, pGpu0, peer1)); + + return status; +} + +void +kbusWriteP2PWmbTag_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 remote2Local, + NvU64 p2pWmbTag +) +{ + // See bug 3558208 comment 34 and 50 + GPU_REG_RD32(pGpu, NV_XAL_EP_P2P_WREQMB_L(remote2Local)); + GPU_REG_WR32(pGpu, NV_XAL_EP_P2P_WREQMB_L(remote2Local), NvU64_LO32(p2pWmbTag)); + GPU_REG_WR32(pGpu, NV_XAL_EP_P2P_WREQMB_H(remote2Local), NvU64_HI32(p2pWmbTag)); +} + diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index 2fab6ca47..2b8ddb65b 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -156,6 +156,8 @@ kbusStatePreInitLocked_GM107 kbusDetermineBar1ApertureLength(pKernelBus, GPU_GFID_PF); + kbusSetupBar1P2PCapability(pGpu, pKernelBus); + if (NV_OK != kbusConstructVirtualBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -2120,6 +2122,31 @@ kbusUpdateRmAperture_GM107 // PTEs during mapping. // nvFieldSetBool(&pFmt->pPte->fldValid, NV_TRUE, mapIter.pteTemplate.v8); + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfHw = 0; + NvU32 ptePcfSw = 0; + + if (memdescGetVolatility(pMemDesc)) + { + ptePcfSw = 1 << SW_MMU_PCF_UNCACHED_IDX; + } + else + { + // + // For internal DMA mappings to sysmem, we should always use + // GPU-uncached because RM won't invalidate L2 upon unmap + // + NV_ASSERT(mapIter.aperture == GMMU_APERTURE_VIDEO); + } + + ptePcfSw |= (1 << SW_MMU_PCF_REGULAR_IDX); + + NV_ASSERT_OR_RETURN(kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, + &ptePcfHw) == NV_OK, NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pFmt->pPte->fldPtePcf, ptePcfHw, mapIter.pteTemplate.v8); + } + else { nvFieldSetBool(&pFmt->pPte->fldVolatile, memdescGetVolatility(pMemDesc), mapIter.pteTemplate.v8); } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index d1bbeccae..9e9762ac9 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -305,8 +305,13 @@ kbusRemoveNvlinkPeerMapping_GP100 NvU32 attributes ) { - NV_STATUS status = NV_OK; - NvU32 peerGpuInst = gpuGetInstance(pGpu1); + NV_STATUS status = NV_OK; + NvU32 peerGpuInst = gpuGetInstance(pGpu1); + KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); + NvBool bLoopback = (pGpu0 == pGpu1); + NvBool bBufferReady = NV_FALSE; + + NV_ASSERT_OR_RETURN(pKernelNvlink0 != NULL, NV_ERR_NOT_SUPPORTED); // If no peer mapping exists between the GPUs, return NV_WARN_NOTHING_TO_DO if ((pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] & NVBIT(peerId)) == 0) @@ -322,28 +327,38 @@ kbusRemoveNvlinkPeerMapping_GP100 return NV_ERR_INVALID_STATE; } - // Decrement the mapping refcount associated with the peerID - pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; - - // Decrement the mapping refcount for the given remote GPU1 - pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst]--; - - if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes)) + if (pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT) || + (bLoopback == NV_TRUE) || + (knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0))) { + // + // WAR 3740439 : Since this code fails for loopback, when we reuse peer ID and not destroy P2P + // objects, we will follow legacy code for loopback and nvswitch and unblock DVT while we debug + // + + // Decrement the mapping refcount associated with the peerID pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; - } - // - // If mapping refcount to remote GPU1 is 0, this implies the peerID is no - // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask - // - if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) - { - NV_PRINTF(LEVEL_INFO, - "Removing mapping for GPU%u peer %u (GPU%u)\n", - gpuGetInstance(pGpu0), peerId, peerGpuInst); + // Decrement the mapping refcount for the given remote GPU1 + pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst]--; + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes)) + { + pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; + } - pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] &= ~NVBIT(peerId); + // + // If mapping refcount to remote GPU1 is 0, this implies the peerID is no + // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask + // + if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) + { + NV_PRINTF(LEVEL_INFO, + "Removing mapping for GPU%u peer %u (GPU%u)\n", + gpuGetInstance(pGpu0), peerId, peerGpuInst); + + pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] &= ~NVBIT(peerId); + } } // @@ -352,18 +367,19 @@ kbusRemoveNvlinkPeerMapping_GP100 // if (pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0) { - KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); - - NV_ASSERT_OR_RETURN(pKernelNvlink0 != NULL, NV_ERR_NOT_SUPPORTED); NV_ASSERT(pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0); NV_PRINTF(LEVEL_INFO, "PeerID %u is not being used for P2P from GPU%d to any other " "remote GPU. Can be freed\n", peerId, gpuGetInstance(pGpu0)); - // Before removing the NVLink peer mapping in HSHUB flush both ends - kbusFlush_HAL(pGpu0, pKernelBus0, BUS_FLUSH_VIDEO_MEMORY); - kbusFlush_HAL(pGpu1, GPU_GET_KERNEL_BUS(pGpu1), BUS_FLUSH_VIDEO_MEMORY); + if (pKernelNvlink0->getProperty(pKernelNvlink0, + PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) + { + // Before removing the NVLink peer mapping in HSHUB flush both ends + kbusFlush_HAL(pGpu0, pKernelBus0, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu1, GPU_GET_KERNEL_BUS(pGpu1), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + } NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); @@ -400,8 +416,23 @@ kbusRemoveNvlinkPeerMapping_GP100 } } + // // Call knvlinkUpdateCurrentConfig to flush settings to the registers - status = knvlinkUpdateCurrentConfig(pGpu0, pKernelNvlink0); + // Skip this call if buffer ready is set and CONFIG_REQUIRE_INITIALIZED is true + // + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu0, pKernelNvlink0); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + bBufferReady = ((pKernelNvlink0->initializedLinks & pKernelNvlink0->peerLinkMasks[peerId]) != 0) ? NV_TRUE : NV_FALSE; + if (!pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK) || + !bBufferReady) + { + status = knvlinkUpdateCurrentConfig(pGpu0, pKernelNvlink0); + } } return status; diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index a58b73a66..393e1b1d2 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -28,6 +28,7 @@ #include "mem_mgr/gpu_vaspace.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" +#include "gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "platform/chipset/chipset.h" @@ -951,8 +952,29 @@ kbusCheckEngine_KERNEL return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC3))) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(4): return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC4))) ? NV_TRUE: NV_FALSE); + case ENG_NVDEC(5): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC5))) ? NV_TRUE: NV_FALSE); + case ENG_NVDEC(6): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC6))) ? NV_TRUE: NV_FALSE); + case ENG_NVDEC(7): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC7))) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(0): return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG0))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(1): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG1))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(2): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG2))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(3): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG3))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(4): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG4))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(5): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG5))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(6): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG6))) ? NV_TRUE: NV_FALSE); + case ENG_NVJPEG(7): + return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG7))) ? NV_TRUE: NV_FALSE); + case ENG_GR(1): case ENG_GR(2): case ENG_GR(3): @@ -1249,3 +1271,20 @@ kbusSendBusInfo_IMPL pBusInfo->data = busGetInfoParams.busInfoList[0].data; return status; } + +/** + * @brief Check for any P2P references in to remote GPUs + * which are still have a P2P api object alive. + * + * @param[in] pGpu + * @param[in] pKernelBus + */ +NV_STATUS +kbusIsGpuP2pAlive_IMPL +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + return (pKernelBus->totalP2pObjectsAliveRefCount > 0); +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index e4c06084b..46708b689 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -617,6 +617,14 @@ p2papiConstruct_IMPL } } } + + if (status == NV_OK) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, pLocalKernelBus->totalP2pObjectsAliveRefCount < NV_U32_MAX, NV_ERR_INSUFFICIENT_RESOURCES); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRemoteKernelBus->totalP2pObjectsAliveRefCount < NV_U32_MAX, NV_ERR_INSUFFICIENT_RESOURCES); + pLocalKernelBus->totalP2pObjectsAliveRefCount++; + pRemoteKernelBus->totalP2pObjectsAliveRefCount++; + } return status; fail: @@ -804,6 +812,14 @@ NV_STATUS CliInvalidateP2PInfo pLocalKernelBus = GPU_GET_KERNEL_BUS(pLocalGpu); pRemoteKernelBus = GPU_GET_KERNEL_BUS(pRemoteGpu); + NV_ASSERT(pLocalKernelBus->totalP2pObjectsAliveRefCount > 0); + NV_ASSERT(pRemoteKernelBus->totalP2pObjectsAliveRefCount > 0); + if (pLocalKernelBus->totalP2pObjectsAliveRefCount > 0) + pLocalKernelBus->totalP2pObjectsAliveRefCount--; + + if (pRemoteKernelBus->totalP2pObjectsAliveRefCount > 0) + pRemoteKernelBus->totalP2pObjectsAliveRefCount--; + if (!IS_VIRTUAL(pLocalGpu)) { // remove any mailbox resources associated with this mapping diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c new file mode 100644 index 000000000..e37770f12 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c @@ -0,0 +1,486 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/**************************************************************************** +* +* Kernel Ccu Module +* This file contains functions managing CCU core on CPU RM +* +****************************************************************************/ + +#include "gpu/ccu/kernel_ccu.h" +#include "gpu/mig_mgr/kernel_mig_manager.h" +#include "objtmr.h" +#include "ctrl/ctrl2080/ctrl2080perf_cf.h" +#include "utils/nvassert.h" + +/*! + * Constrcutor for kccu class. + * + * @param[in] pGpu GPU object pointer. + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] engDesc KernelCcu Engine descriptor + * + * @return NV_OK If successfully constructed. + */ +NV_STATUS +kccuConstructEngine_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + ENGDESCRIPTOR engDesc +) +{ + NV_PRINTF(LEVEL_INFO, "KernelCcu: Constructor\n"); + + return NV_OK; +} + +/*! + * Destructor + * + * @param[in] pKernelCcu KernelCcu object pointer + */ +void +kccuDestruct_IMPL +( + KernelCcu *pKernelCcu +) +{ + NV_PRINTF(LEVEL_INFO, "KernelCcu: Destructor\n"); + + return; +} + +/*! + * Allocate memory for class members, create & map shared buffer and initialize counter start + * address and head/tail timestamp address + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] idx MIG inst/for non-mig case idx is "0" + * @param[in] shrBufSize Shared buffer size + * @param[in] counterBlockSize Counter block size + * + * @return NV_OK on success, specific error code on failure. + */ +static NV_STATUS +_kccuAllocMemory +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 idx, + NvU32 shrBufSize, + NvU64 counterBlockSize +) +{ + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + NV_PRINTF(LEVEL_INFO, "KernelCcu: Allocate memory for class members and shared buffer\n"); + + // Allocate memory & init the KernelCcu class members to store shared buffer info + pKernelCcu->shrBuf[idx].pCounterDstInfo = portMemAllocNonPaged(sizeof(CCU_SHRBUF_INFO)); + pKernelCcu->shrBuf[idx].pKernelMapInfo = portMemAllocNonPaged(sizeof(SHARED_BUFFER_MAP_INFO)); + + if (pKernelCcu->shrBuf[idx].pCounterDstInfo == NULL || pKernelCcu->shrBuf[idx].pKernelMapInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_ERROR, "CCU port mem alloc failed for(%u) with status: 0x%x \r\n", idx, status); + goto free_alloc; + } + portMemSet(pKernelCcu->shrBuf[idx].pCounterDstInfo, 0, sizeof(CCU_SHRBUF_INFO)); + portMemSet(pKernelCcu->shrBuf[idx].pKernelMapInfo, 0, sizeof(SHARED_BUFFER_MAP_INFO)); + + // Create a memory descriptor data structure for the shared buffer + status = memdescCreate(&pKernelCcu->pMemDesc[idx], pGpu, shrBufSize, 0, NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, NV_MEMORY_CACHED, + MEMDESC_FLAGS_USER_READ_ONLY); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed for(%u) with status: 0x%x \r\n", idx, status); + goto free_alloc; + } + + pMemDesc = pKernelCcu->pMemDesc[idx]; + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed. memdesc for(%u) is NULL\r\n", idx); + goto free_alloc; + } + + // Allocate physical storage for the memory descriptor + status = memdescAlloc(pMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdescAlloc failed for(%u) with status: 0x%x \r\n", idx, status); + memdescDestroy(pMemDesc); + goto free_alloc; + } + + // Map memory to kernel VA space + status = memdescMap(pMemDesc, 0, shrBufSize, NV_TRUE, NV_PROTECT_READ_WRITE, + &pKernelCcu->shrBuf[idx].pKernelMapInfo->addr, + &pKernelCcu->shrBuf[idx].pKernelMapInfo->priv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdescMap failed for(%u)with status: 0x%x \r\n", idx, status); + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + goto free_alloc; + } + portMemSet(pKernelCcu->shrBuf[idx].pKernelMapInfo->addr, 0, shrBufSize); + + // Init the counter start address, head & tail timestamp address and counter block size + pKernelCcu->shrBuf[idx].pCounterDstInfo->pHeadTimeStamp = + (NvU64 *)pKernelCcu->shrBuf[idx].pKernelMapInfo->addr; + pKernelCcu->shrBuf[idx].pCounterDstInfo->pCounterBlock = + (NvP64)((NvUPtr)pKernelCcu->shrBuf[idx].pKernelMapInfo->addr + CCU_TIMESTAMP_SIZE); + pKernelCcu->shrBuf[idx].pCounterDstInfo->pTailTimeStamp = + (NvU64 *)((NvUPtr)pKernelCcu->shrBuf[idx].pCounterDstInfo->pCounterBlock + counterBlockSize); + pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId = + (NvU8 *)((NvUPtr)pKernelCcu->shrBuf[idx].pCounterDstInfo->pTailTimeStamp + CCU_TIMESTAMP_SIZE); + pKernelCcu->shrBuf[idx].pCounterDstInfo->counterBlockSize = counterBlockSize; + + // Set mig swizz-id to invalid + if (!NV_IS_MODS) + { + *pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId = CCU_MIG_INVALID_SWIZZID; + } + + return NV_OK; + +free_alloc: + if (pKernelCcu->shrBuf[idx].pCounterDstInfo) + { + portMemFree(pKernelCcu->shrBuf[idx].pCounterDstInfo); + } + if (pKernelCcu->shrBuf[idx].pKernelMapInfo) + { + portMemFree(pKernelCcu->shrBuf[idx].pKernelMapInfo); + } + return status; +} + +/*! + * Free memory desc, shared buffer and class member memory + * + * @param[in] pKernelCcu KernelCcu object pointer + * + */ +static void +_kccuUnmapAndFreeMemory +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu +) +{ + NvU32 i = 0; + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "KernelCcu: Unmap and free shared buffer\n"); + + // Internal RM api ctrl call to physical RM to unmap shared buffer memdesc + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP, + NULL, + 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdesc unmap request failed with status: 0x%x \r\n", status); + } + + // Unmap & free mem desc + for (i = 0; i < CCU_SHRBUF_COUNT_MAX; i++) + { + MEMORY_DESCRIPTOR *pMemDesc = pKernelCcu->pMemDesc[i]; + + if (pMemDesc == NULL) + continue; + + memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), + pKernelCcu->shrBuf[i].pKernelMapInfo->addr, + pKernelCcu->shrBuf[i].pKernelMapInfo->priv); + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + + // Free class member memory + portMemFree(pKernelCcu->shrBuf[i].pCounterDstInfo); + portMemFree(pKernelCcu->shrBuf[i].pKernelMapInfo); + pKernelCcu->shrBuf[i].pCounterDstInfo = NULL; + pKernelCcu->shrBuf[i].pKernelMapInfo = NULL; + } + + return; +} + +/*! + * Create shared buffer for counter data + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * + * @return NV_OK on success, specific error code on failure. + */ +static NV_STATUS +_kccuInitSharedBuffer +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu +) +{ + NV_STATUS status = NV_OK; + NvU32 idx; + + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Allocate shared buffer for device counters + + status = _kccuAllocMemory(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, CCU_GPU_SHARED_BUFFER_SIZE_MAX, + CCU_PER_GPU_COUNTER_Q_SIZE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed with status: 0x%x \r\n", status); + return status; + } + + // Allocate shared buffer for each mig gpu instance + for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) + { + status = _kccuAllocMemory(pGpu, pKernelCcu, idx, CCU_MIG_INST_SHARED_BUFFER_SIZE_MAX, + CCU_MIG_INST_COUNTER_Q_SIZE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed for idx(%u) with status: 0x%x \r\n", + idx, status); + + // Free shared buffer & mem desc, for earlier mig inst & device + _kccuUnmapAndFreeMemory(pGpu, pKernelCcu); + break; + } + + } + + return status; +} + +/*! + * State Load + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] flags Type of transition + * + * @return NV_OK + * @return NV_ERR_INVALID_STATE + */ +NV_STATUS kccuStateLoad_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 flags +) +{ + NvU32 idx = 0; + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS inParams = { 0 }; + + NV_PRINTF(LEVEL_INFO, "KernelCcu: State load \n"); + + // Create shared buffer + status = _kccuInitSharedBuffer(pGpu, pKernelCcu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to init shared buffer(status: %u) \n", status); + return status; + } + + for (idx = 0; idx < CCU_SHRBUF_COUNT_MAX; idx++) + { + if (pKernelCcu->pMemDesc[idx] != NULL) + { + inParams.phyAddr[idx] = memdescGetPhysAddr(pKernelCcu->pMemDesc[idx], AT_GPU, 0); + } + } + + // Internal RM api ctrl call to physical RM to map shared buffer memdesc + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CCU_MAP, + &inParams, + sizeof(inParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdesc map request failed with status: 0x%x \r\n", status); + return status; + } + + return status; +} + +/*! + * State Unload + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] flags Type of transition + * + * @return NV_OK + * @return NV_ERR_INVALID_STATE + */ +NV_STATUS kccuStateUnload_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + NV_PRINTF(LEVEL_INFO, "KernelCcu: State unload \n"); + + // Free shared buffer & mem desc + _kccuUnmapAndFreeMemory(pGpu, pKernelCcu); + + return status; +} + +/*! + * Get the shared buffer memory descriptor for buffer index + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] idx Shared buffer index + * @param[out] MEMORY_DESCRIPTOR Location of pMemDesc + * + * @return NV_OK + * @return NV_ERR_INVALID_ARGUMENT + */ +NV_STATUS kccuMemDescGetForShrBufId_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 idx, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + NV_PRINTF(LEVEL_INFO, "KernelCcu: Get memdesc for idx(%u) \n", idx); + + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (idx >= CCU_SHRBUF_COUNT_MAX) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdesc get failed for input idx(%u). Invalid index.\r\n", + idx); + + return NV_ERR_INVALID_ARGUMENT; + } + + *ppMemDesc = pKernelCcu->pMemDesc[idx]; + + return NV_OK; +} + +/*! + * Get the shared buffer memory descriptor for swizz id + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] swizzId Mig inst swizz-id + * @param[out] MEMORY_DESCRIPTOR Location of pMemDesc + * + * @return NV_OK + * @return NV_ERR_INVALID_ARGUMENT + */ +NV_STATUS kccuMemDescGetForSwizzId_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU8 swizzId, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + NvU32 idx = 0; + + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) + { + if (*pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId == swizzId) + { + *ppMemDesc = pKernelCcu->pMemDesc[idx]; + break; + } + } + + if (idx >= CCU_SHRBUF_COUNT_MAX) + { + NV_PRINTF(LEVEL_ERROR, "KernelCcu: memdesc get failed for input swizzId(%u) \r\n", + swizzId); + + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * Get counter block size + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] bDevCounter Device counter + * + * @return counter block size + */ +NvU32 kccuCounterBlockSizeGet_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvBool bDevCounter +) +{ + NV_PRINTF(LEVEL_INFO, "KernelCcu: Get counter block size \n"); + // For device counter block + if (bDevCounter) + { + return CCU_PER_GPU_COUNTER_Q_SIZE; + } + + return CCU_MIG_INST_COUNTER_Q_SIZE; +} diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c new file mode 100644 index 000000000..27deca510 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c @@ -0,0 +1,353 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Kernel Ccu Api Object Module * + * * + \**************************************************************************/ + +#include "gpu/gpu.h" +#include "gpu/ccu/kernel_ccu_api.h" +#include "gpu/ccu/kernel_ccu.h" +#include "rmapi/client.h" +#include "gpu/mig_mgr/kernel_mig_manager.h" + +NV_STATUS +kccuapiConstruct_IMPL +( + KernelCcuApi *pKernelCcuApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: Construct\n"); + + return NV_OK; +} + +void +kccuapiDestruct_IMPL +( + KernelCcuApi *pKernelCcuApi +) +{ + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: Destruct\n"); + return; +} + +static NV_STATUS +_kccuapiMemdescGet +( + KernelCcuApi *pKernelCcuApi, + RmClient *pClient, + NvHandle hClient, + MEMORY_DESCRIPTOR **pMemDesc +) +{ + MIG_INSTANCE_REF ref; + NV_STATUS status = NV_OK; + NvU32 ciGpcCount = 0; + NvU32 giGpcCount = 0; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); + KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: Get memdesc info\n"); + + if (pKernelCcu == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + if (!IS_MIG_ENABLED(pGpu)) + { + return kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, pMemDesc); + } + + // In case of MIG + status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + if (status != NV_OK) + { + // Check if client is allowed to query for device counters + if (rmclientIsCapable(pClient, NV_RM_CAP_SYS_SMC_MONITOR)) + { + return kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, pMemDesc); + } + + // Permission denied + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + giGpcCount = ref.pKernelMIGGpuInstance ? ref.pKernelMIGGpuInstance->resourceAllocation.gpcCount : 0; + ciGpcCount = ref.pMIGComputeInstance ? ref.pMIGComputeInstance->resourceAllocation.gpcCount : 0; + + // Check if Gpu inst's gpc-count is valid + NV_ASSERT_OR_RETURN(giGpcCount != 0, NV_ERR_INVALID_DATA); + + if (giGpcCount == ciGpcCount) + { + // Fetch the shared buffer memdesc for the swizzId + return kccuMemDescGetForSwizzId(pGpu, pKernelCcu, ref.pKernelMIGGpuInstance->swizzId, pMemDesc); + } + + // Permission denied + return NV_ERR_INSUFFICIENT_PERMISSIONS; +} + +NV_STATUS +kccuapiMap_IMPL +( + KernelCcuApi *pKernelCcuApi, + CALL_CONTEXT *pCallContext, + RS_CPU_MAP_PARAMS *pParams, + RsCpuMapping *pCpuMapping +) +{ + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NV_STATUS status = NV_OK; + NvBool bKernel = NV_FALSE; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + NvHandle hClient = pCallContext->pClient->hClient; + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: memdesc map\n"); + + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), + pCpuMapping->flags, + &bKernel); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Kernel mapping validation failed with status: 0x%x\n", status); + return status; + } + + pCpuMapping->processId = osGetCurrentProcess(); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Shared buffer memdesc is NULL\n"); + return NV_ERR_INVALID_OBJECT; + } + + // Map entire buffer (no offsets supported) + status = memdescMap(pMemDesc, + 0, + pMemDesc->Size, + bKernel, + pCpuMapping->pPrivate->protect, + &pCpuMapping->pLinearAddress, + &pCpuMapping->pPrivate->pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "kernelCcuApi shared buffer memdescMap failed with status: 0x%x\n", status); + return status; + } + + return NV_OK; +} + +NV_STATUS +kccuapiUnmap_IMPL +( + KernelCcuApi *pKernelCcuApi, + CALL_CONTEXT *pCallContext, + RsCpuMapping *pCpuMapping +) +{ + NV_STATUS status = NV_OK; + NvBool bKernel = NV_FALSE; + NvHandle hClient = pCallContext->pClient->hClient; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: memdesc unmap\n"); + + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), + pCpuMapping->flags, + &bKernel); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Kernel mapping validation failed with status: 0x%x\n", status); + return status; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Shared buffer memdesc is NULL\n"); + return NV_ERR_INVALID_OBJECT; + } + + memdescUnmap(pMemDesc, + bKernel, + pCpuMapping->processId, + pCpuMapping->pLinearAddress, + pCpuMapping->pPrivate->pPriv); + + return status; +} + +NV_STATUS +kccuapiGetMapAddrSpace_IMPL +( + KernelCcuApi *pKernelCcuApi, + CALL_CONTEXT *pCallContext, + NvU32 mapFlags, + NV_ADDRESS_SPACE *pAddrSpace +) +{ + NV_ADDRESS_SPACE addrSpace = 0; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvHandle hClient = pCallContext->pClient->hClient; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: get memdesc address-space\n"); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Shared buffer memdesc is NULL\n"); + return NV_ERR_INVALID_OBJECT; + } + + NV_ASSERT_OK_OR_RETURN(rmapiGetEffectiveAddrSpace(pGpu, pMemDesc, mapFlags, &addrSpace)); + + *pAddrSpace = addrSpace; + + return NV_OK; +} + +NV_STATUS +kccuapiGetMemoryMappingDescriptor_IMPL +( + KernelCcuApi *pKernelCcuApi, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelCcuApi); + RmClient *pClient = dynamicCast(RES_GET_CLIENT(pKernelCcuApi), RmClient); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: get memdesc\n"); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Shared buffer memdesc is NULL\n"); + return NV_ERR_INVALID_OBJECT; + } + + *ppMemDesc = pMemDesc; + + return NV_OK; +} + +NV_STATUS +kccuapiCtrlCmdSubscribe_IMPL +( + KernelCcuApi *pKernelCcuApi, + NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS *pParams +) +{ + MIG_INSTANCE_REF ref; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelCcuApi); + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); + KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); + RmClient *pClient = dynamicCast(RES_GET_CLIENT(pKernelCcuApi), RmClient); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: CCU subscribe request\n"); + + if (pKernelCcu == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + if (!IS_MIG_ENABLED(pGpu)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, &pMemDesc)); + + if (pMemDesc == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pParams->counterBlockSize = kccuCounterBlockSizeGet(pGpu, pKernelCcu, NV_TRUE); + pParams->bufferSize = memdescGetSize(pMemDesc); + + return status; + } + + // In case of MIG + status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + if (status != NV_OK) + { + // Check if client is allowed to query for device counters or not + if (!rmclientIsCapable(pClient, NV_RM_CAP_SYS_SMC_MONITOR)) + { + // Return if the client is not allowed + return status; + } + + // Get device counter block size + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, &pMemDesc)); + pParams->counterBlockSize = kccuCounterBlockSizeGet(pGpu, pKernelCcu, NV_TRUE); + } + else + { + // Get counter block size for mig gpu inst + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kccuMemDescGetForSwizzId(pGpu, pKernelCcu, ref.pKernelMIGGpuInstance->swizzId, &pMemDesc)); + pParams->counterBlockSize = kccuCounterBlockSizeGet(pGpu, pKernelCcu, NV_FALSE); + } + + if (pMemDesc == NULL) + { + return NV_ERR_NO_MEMORY; + } + pParams->bufferSize = memdescGetSize(pMemDesc); + + return NV_OK; +} + +NV_STATUS +kccuapiCtrlCmdUnsubscribe_IMPL +( + KernelCcuApi *pKernelCcuApi +) +{ + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: CCU unsubscribe request\n"); + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c index 31dac69e8..cb29e7acf 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c @@ -34,7 +34,6 @@ #include "published/ampere/ga100/dev_nv_xve.h" #include "published/ampere/ga100/dev_nv_xve_addendum.h" -#define MAX_CE_CNT 18 #define NV_CE_INVALID_TOPO_IDX 0xFFFF // Ampere + @@ -62,50 +61,6 @@ static void _ceGetAlgorithmPceIndex(OBJGPU *, KernelCE*, NvU32 *, NvU32 *, NvBool *, NvU8 *); -/* - * sysmemLinks - * Represents the number of sysmem links detected - * This affects how many PCEs LCE0(sysmem read CE) - * and LCE1(sysmem write CE) should be mapped to - * maxLinksPerPeer - * Represents the maximum number of peer links - * between this GPU and all its peers. This affects - * how many PCEs LCE3(P2P CE) should be mapped to - * numPeers - * Represents the number of Peer GPUs discovered so far - * bSymmetric - * Represents whether the topology detected so far - * is symmetric i.e. has same number of links to all - * peers connected through nvlink. This affects how - * many PCEs to assign to LCEs3-5 (nvlink P2P CEs) - * bSwitchConfig - * Represents whether the config listed is intended - * for use with nvswitch systems - * pceLceMap - * Value of NV_CE_PCE2LCE_CONFIG0 register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * grceConfig - * Value of NV_CE_GRCE_CONFIG register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * exposeCeMask - * Mask of CEs to expose to clients for the above - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - */ -typedef struct NVLINK_CE_AUTO_CONFIG_TABLE -{ - NvU32 sysmemLinks; - NvU32 maxLinksPerPeer; - NvU32 numPeers; - NvBool bSymmetric; - NvBool bSwitchConfig; - NvU32 pceLceMap[MAX_CE_CNT]; - NvU32 grceConfig[MAX_CE_CNT]; - NvU32 exposeCeMask; -} NVLINK_CE_AUTO_CONFIG_TABLE; - /* * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented * using the algorithm because the config does not conform to the algorithm's set @@ -199,50 +154,58 @@ kceGetNvlinkAutoConfigCeValues_GA100 NvU32 grceConfigSize1 = kceGetGrceConfigSize1_HAL(pKCe); NvBool bEntryExists; NvU32 pceIdx, grceIdx, i; - NVLINK_TOPOLOGY_PARAMS currentTopo; + NVLINK_TOPOLOGY_PARAMS *pCurrentTopo = portMemAllocNonPaged(sizeof(*pCurrentTopo)); + NvU32 *pLocalPceLceMap = NULL, *pLocalGrceConfig = NULL; - NV_ASSERT_OR_RETURN(!RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN(pCurrentTopo != NULL, NV_ERR_NO_MEMORY); if ((pPceLceMap == NULL) || (pGrceConfig == NULL) || (pExposeCeMask == NULL)) { - return NV_ERR_INVALID_ARGUMENT; + status = NV_ERR_INVALID_ARGUMENT; + goto done; } - if (pKernelNvlink == NULL) + if (pKernelNvlink == NULL && pGpu->getProperty(pGpu, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK)) { - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto done; } - portMemSet(¤tTopo, 0, sizeof(currentTopo)); + portMemSet(pCurrentTopo, 0, sizeof(*pCurrentTopo)); - // Initialize pPceLceMap with no mappings - for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) + // Bug 200283711: Use the largest of all chips in allocating these arrays + pLocalPceLceMap = portMemAllocNonPaged(sizeof(NvU32[NV2080_CTRL_MAX_PCES])); + pLocalGrceConfig = portMemAllocNonPaged(sizeof(NvU32[NV2080_CTRL_MAX_GRCES])); + NvU32 localExposeCeMask = 0; + + if (pLocalPceLceMap == NULL || pLocalGrceConfig == NULL) { - pPceLceMap[pceIdx] = NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE; + status = NV_ERR_NO_MEMORY; + goto done; } - // Bug 200283711: Use the largest of all chips in allocating these arrays - NvU32 localPceLceMap[NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX]; - NvU32 localGrceConfig[MAX_CE_CNT]; - NvU32 localExposeCeMask = 0; + for (i = 0; i < NV2080_CTRL_MAX_PCES; i++) + { + pLocalPceLceMap[i] = NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE; + } - // Initialize to ASSIGNED_LCE_NONE - for (i = 0; i < pce2lceConfigSize1; i++) + for (i = 0; i < NV2080_CTRL_MAX_GRCES; i++) { - localPceLceMap[i] = NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE; + pLocalGrceConfig[i] = NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE; } - sysmemLinks = knvlinkGetNumLinksToSystem(pGpu, pKernelNvlink); + sysmemLinks = pKernelNvlink ? knvlinkGetNumLinksToSystem(pGpu, pKernelNvlink) : 0; if (gpuGetNumCEs(pGpu) == 0) { - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto done; } (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); // Get the max{nvlinks/peer, for all connected peers} - while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + while ((pKernelNvlink != NULL) && ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL)) { NvU32 numLinksToPeer = knvlinkGetNumLinksToPeer(pGpu, pKernelNvlink, pRemoteGpu); @@ -269,17 +232,17 @@ kceGetNvlinkAutoConfigCeValues_GA100 } } - currentTopo.sysmemLinks = sysmemLinks; - currentTopo.maxLinksPerPeer = maxLinksPerPeer; - currentTopo.numPeers = numPeers; - currentTopo.bSymmetric = bSymmetric; - currentTopo.bSwitchConfig = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); + pCurrentTopo->sysmemLinks = sysmemLinks; + pCurrentTopo->maxLinksPerPeer = maxLinksPerPeer; + pCurrentTopo->numPeers = numPeers; + pCurrentTopo->bSymmetric = bSymmetric; + pCurrentTopo->bSwitchConfig = pKernelNvlink ? knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink) : NV_FALSE; // // Check if the current config exists in the table // Here, we only fill exposeCeMask. // - bEntryExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, ¤tTopo, nvLinkCeAutoConfigTable_GA100, + bEntryExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, pCurrentTopo, nvLinkCeAutoConfigTable_GA100, NV_ARRAY_ELEMENTS(nvLinkCeAutoConfigTable_GA100), &topoIdx, &localExposeCeMask); if (bEntryExists) @@ -287,11 +250,11 @@ kceGetNvlinkAutoConfigCeValues_GA100 // Since entry exists, fill local variables with the associated table entry for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) { - localPceLceMap[pceIdx] = nvLinkCeAutoConfigTable_GA100[topoIdx].pceLceMap[pceIdx]; + pLocalPceLceMap[pceIdx] = nvLinkCeAutoConfigTable_GA100[topoIdx].pceLceMap[pceIdx]; } for (grceIdx = 0; grceIdx < grceConfigSize1; grceIdx++) { - localGrceConfig[grceIdx] = nvLinkCeAutoConfigTable_GA100[topoIdx].grceConfig[grceIdx]; + pLocalGrceConfig[grceIdx] = nvLinkCeAutoConfigTable_GA100[topoIdx].grceConfig[grceIdx]; } } else @@ -301,15 +264,15 @@ kceGetNvlinkAutoConfigCeValues_GA100 // Here the currentTopo struct comes with pce-lce & grce mappings & exposeCeMask // - status = kceGetMappings_HAL(pGpu, pKCe, ¤tTopo, - localPceLceMap, localGrceConfig, &localExposeCeMask); + status = kceGetMappings_HAL(pGpu, pKCe, pCurrentTopo, + pLocalPceLceMap, pLocalGrceConfig, &localExposeCeMask); } // Get the largest topology that has been cached - bEntryExists = gpumgrGetSystemNvlinkTopo(gpuGetDBDF(pGpu), ¤tTopo); + bEntryExists = gpumgrGetSystemNvlinkTopo(gpuGetDBDF(pGpu), pCurrentTopo); // Is this the largest topology that we've ever seen compared to the cached one? - bCurrentTopoMax = kceIsCurrentMaxTopology_HAL(pGpu, pKCe, ¤tTopo, &localExposeCeMask, &topoIdx); + bCurrentTopoMax = kceIsCurrentMaxTopology_HAL(pGpu, pKCe, pCurrentTopo, &localExposeCeMask, &topoIdx); if (bCurrentTopoMax) { @@ -321,25 +284,25 @@ kceGetNvlinkAutoConfigCeValues_GA100 // for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) { - currentTopo.maxPceLceMap[pceIdx] = localPceLceMap[pceIdx]; + pCurrentTopo->maxPceLceMap[pceIdx] = pLocalPceLceMap[pceIdx]; } for (grceIdx = 0; grceIdx < grceConfigSize1; grceIdx++) { - currentTopo.maxGrceConfig[grceIdx] = localGrceConfig[grceIdx]; + pCurrentTopo->maxGrceConfig[grceIdx] = pLocalGrceConfig[grceIdx]; } - currentTopo.maxExposeCeMask = localExposeCeMask; + pCurrentTopo->maxExposeCeMask = localExposeCeMask; if (topoIdx != NV_CE_INVALID_TOPO_IDX) { // Only if we used table to determine config, store this value - currentTopo.maxTopoIdx = topoIdx; - currentTopo.sysmemLinks = nvLinkCeAutoConfigTable_GA100[topoIdx].sysmemLinks; - currentTopo.maxLinksPerPeer = nvLinkCeAutoConfigTable_GA100[topoIdx].maxLinksPerPeer; - currentTopo.numPeers = nvLinkCeAutoConfigTable_GA100[topoIdx].numPeers; - currentTopo.bSymmetric = nvLinkCeAutoConfigTable_GA100[topoIdx].bSymmetric; - currentTopo.bSwitchConfig = nvLinkCeAutoConfigTable_GA100[topoIdx].bSwitchConfig; + pCurrentTopo->maxTopoIdx = topoIdx; + pCurrentTopo->sysmemLinks = nvLinkCeAutoConfigTable_GA100[topoIdx].sysmemLinks; + pCurrentTopo->maxLinksPerPeer = nvLinkCeAutoConfigTable_GA100[topoIdx].maxLinksPerPeer; + pCurrentTopo->numPeers = nvLinkCeAutoConfigTable_GA100[topoIdx].numPeers; + pCurrentTopo->bSymmetric = nvLinkCeAutoConfigTable_GA100[topoIdx].bSymmetric; + pCurrentTopo->bSwitchConfig = nvLinkCeAutoConfigTable_GA100[topoIdx].bSwitchConfig; } - gpumgrUpdateSystemNvlinkTopo(gpuGetDBDF(pGpu), ¤tTopo); + gpumgrUpdateSystemNvlinkTopo(gpuGetDBDF(pGpu), pCurrentTopo); } NV_PRINTF(LEVEL_INFO, "GPU%d : RM Configured Values for CE Config\n", gpuGetInstance(pGpu)); @@ -347,13 +310,13 @@ kceGetNvlinkAutoConfigCeValues_GA100 // Now, fill up the information to return. We'll always return max config information. for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) { - pPceLceMap[pceIdx] = currentTopo.maxPceLceMap[pceIdx]; + pPceLceMap[pceIdx] = pCurrentTopo->maxPceLceMap[pceIdx]; NV_PRINTF(LEVEL_INFO, "PCE-LCE map: PCE %d LCE 0x%x\n", pceIdx, pPceLceMap[pceIdx]); } for (grceIdx = 0; grceIdx < grceConfigSize1; grceIdx++) { - NvU32 grceSharedLce = currentTopo.maxGrceConfig[grceIdx]; + NvU32 grceSharedLce = pCurrentTopo->maxGrceConfig[grceIdx]; if (grceSharedLce != 0xF) { @@ -369,9 +332,14 @@ kceGetNvlinkAutoConfigCeValues_GA100 NV_PRINTF(LEVEL_INFO, "GRCE Config: GRCE %d LCE 0x%x\n", grceIdx, pGrceConfig[grceIdx]); } - *pExposeCeMask = currentTopo.maxExposeCeMask; + *pExposeCeMask = pCurrentTopo->maxExposeCeMask; NV_PRINTF(LEVEL_INFO, "exposeCeMask = 0x%x\n", *pExposeCeMask); +done: + portMemFree(pCurrentTopo); + portMemFree(pLocalPceLceMap); + portMemFree(pLocalGrceConfig); + return status; } @@ -518,6 +486,12 @@ kceGetMappings_GA100 NvU32 fbPceMask = 0; NV_STATUS status = NV_OK; NvU32 pceIndex, lceIndex, grceIdx; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (!pKernelNvlink || knvlinkIsForcedConfig(pGpu, pKernelNvlink)) + { + return NV_OK; + } // Prepare the per-HSHUB/FBHUB available PCE mask status = kceGetAvailableHubPceMask(pGpu, pTopoParams); @@ -560,6 +534,9 @@ kceGetMappings_GA100 for (grceIdx = 0; grceIdx < NV_CE_MAX_GRCE; grceIdx++) { + // We should have fbhub PCEs left to assign, but avoid an invalid pceIndex if we do not + NV_ASSERT_OR_ELSE(fbPceMask != 0, break); + // // Check if we are sharing GRCEs // On Ampere, GRCEs can only use FBHUB PCEs @@ -575,7 +552,7 @@ kceGetMappings_GA100 pLocalGrceMap[grceIdx] = DRF_NUM(_CE, _GRCE_CONFIG, _SHARED, 1) | DRF_NUM(_CE, _GRCE_CONFIG, _SHARED_LCE, lceIndex); - if ((kceIsGen4orHigherSupported_HAL(pGpu, pKCe)) || (pKCe->bUseGen4Mapping == NV_TRUE)) + if ((kceIsGenXorHigherSupported_HAL(pGpu, pKCe, 4)) || (pKCe->bUseGen4Mapping == NV_TRUE)) { kceApplyGen4orHigherMapping_HAL(pGpu, pKCe, &pLocalPceLceMap[0], @@ -635,12 +612,12 @@ kceMapPceLceForSysmemLinks_GA100 NvU32 lceIndex, pceIndex; NvU32 linkId, i; NvU8 hshubId; - NV_STATUS status; + NV_STATUS status = NV_OK; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS paramsNvlinkMask; - NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS paramsHshubId; + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *pParamsHshubId = NULL; NV_ASSERT_OR_RETURN(pKernelNvlink != NULL, NV_ERR_NOT_SUPPORTED); @@ -682,21 +659,25 @@ kceMapPceLceForSysmemLinks_GA100 // If sysmem is over NVlink, assign HSHUB PCEs numPcePerLink = NV_CE_MIN_PCE_PER_SYS_LINK; - portMemSet(¶msHshubId, 0, sizeof(paramsHshubId)); - paramsHshubId.linkMask = paramsNvlinkMask.sysmemLinkMask; + pParamsHshubId = portMemAllocNonPaged(sizeof(*pParamsHshubId)); + + NV_ASSERT_OR_RETURN(pParamsHshubId != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pParamsHshubId, 0, sizeof(*pParamsHshubId)); + pParamsHshubId->linkMask = paramsNvlinkMask.sysmemLinkMask; status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, - (void *)¶msHshubId, sizeof(paramsHshubId)); + pParamsHshubId, sizeof(*pParamsHshubId)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to determine Hshub Id for sysmem links"); - return status; + goto done; } FOR_EACH_INDEX_IN_MASK(32, linkId, paramsNvlinkMask.sysmemLinkMask) { - hshubId = paramsHshubId.hshubIds[linkId]; + hshubId = pParamsHshubId->hshubIds[linkId]; pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); bFirstIter = NV_TRUE; for (i = 0; i < numPcePerLink; i++) @@ -732,7 +713,10 @@ kceMapPceLceForSysmemLinks_GA100 *pLocalExposeCeMask |= lceMask; } - return NV_OK; +done: + portMemFree(pParamsHshubId); + + return status; } /** @@ -792,14 +776,17 @@ kceMapPceLceForNvlinkPeers_GA100 NvU32 lceIndex, pceIndex; NvU32 linkId, gpuMask, gpuInstance = 0, i; NvU8 hshubId, prevHshubId; - - NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *pParams = NULL; if (pKernelNvlink == NULL) { return NV_WARN_NOTHING_TO_DO; } + pParams = portMemAllocNonPaged(sizeof(*pParams)); + + NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); + peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) @@ -854,17 +841,17 @@ kceMapPceLceForNvlinkPeers_GA100 numPcePerLink = NV_CE_MIN_PCE_PER_PEER_LINK; prevHshubId = 0xFF; - portMemSet(¶ms, 0, sizeof(params)); - params.linkMask = peerLinkMask; + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->linkMask = peerLinkMask; status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, - (void *)¶ms, sizeof(params)); + pParams, sizeof(*pParams)); NV_ASSERT_OK_OR_RETURN(status); FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMask) { - hshubId = params.hshubIds[linkId]; + hshubId = pParams->hshubIds[linkId]; if (hshubId != prevHshubId) { pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); @@ -917,6 +904,7 @@ kceMapPceLceForNvlinkPeers_GA100 status = NV_WARN_NOTHING_TO_DO; } + portMemFree(pParams); return status; } @@ -1041,17 +1029,18 @@ kceGetGrceSupportedLceMask_GA100 /** * @brief This function checks for root port gen speed or GPU - * gen speed to determine if we should apply gen4+ mapping - * or gen3- mapping + * gen speed to determine if we should apply genX+ mapping * * @param[in] pGpu OBJGPU pointer - * @param[in] pKCe KernelCE pointer + * @param[in] pKCe KernelCE pointer + * @param[in] checkGen genX for query */ NvBool -kceIsGen4orHigherSupported_GA100 +kceIsGenXorHigherSupported_GA100 ( OBJGPU *pGpu, - KernelCE *pKCe + KernelCE *pKCe, + NvU32 checkGen ) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -1059,7 +1048,7 @@ kceIsGen4orHigherSupported_GA100 OBJCL *pCl = SYS_GET_CL(pSys); NvU8 genSpeed = 0; NV_STATUS status = NV_OK; - NvBool bIsGen4orHigher = NV_FALSE; + NvBool bIsGenXorHigher = NV_FALSE; NvU32 regVal; if (IS_PASSTHRU(pGpu) && (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_PCIE_GEN4_CAPABLE))) @@ -1078,7 +1067,7 @@ kceIsGen4orHigherSupported_GA100 NvU32 rootPortSpeed = DRF_VAL(_XVE, _PASSTHROUGH_EMULATED_CONFIG, _ROOT_PORT_SPEED, passthroughEmulatedConfig); // 0 means the config is not being emulated and we assume gen4 - bIsGen4orHigher = (rootPortSpeed == 0 || rootPortSpeed >= 4); + bIsGenXorHigher = ((rootPortSpeed == 0 && checkGen <= 4) || rootPortSpeed >= checkGen); if (rootPortSpeed != 0) { @@ -1097,12 +1086,12 @@ kceIsGen4orHigherSupported_GA100 } NV_PRINTF(LEVEL_INFO, "Gen Speed = %d\n", genSpeed); - if ((genSpeed >= 0x4)) + if ((genSpeed >= checkGen)) { - bIsGen4orHigher = NV_TRUE; + bIsGenXorHigher = NV_TRUE; } } - return bIsGen4orHigher; + return bIsGenXorHigher; } /** diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c new file mode 100644 index 000000000..993a919fd --- /dev/null +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -0,0 +1,703 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "gpu/ce/kernel_ce_private.h" +#include "gpu/bif/kernel_bif.h" +#include "platform/chipset/chipset.h" + +#include "published/hopper/gh100/dev_ce.h" +#include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" + +// Defines for PCE-LCE mapping algorithm +#define NV_CE_MAX_HSHUBS 5 +#define NV_CE_LCE_MASK_INIT 0xFFFFFFFF +#define NV_CE_GRCE_ALLOWED_LCE_MASK 0x03 +#define NV_CE_MAX_GRCE 2 +#define NV_CE_EVEN_ASYNC_LCE_MASK 0x55555550 +#define NV_CE_ODD_ASYNC_LCE_MASK 0xAAAAAAA0 +#define NV_CE_MAX_LCE_MASK 0x3FF +#define NV_CE_PCE_PER_HSHUB 4 +#define NV_CE_NUM_FBPCE 4 +#define NV_CE_NUM_PCES_NO_LINK_CASE 12 +#define NV_CE_MAX_PCE_PER_GRCE 2 + + + +/*! + * @brief Returns the size of the PCE2LCE register array + * + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pCe OBJCE pointer + * + * @return NV_CE_PCE2LCE_CONFIG__SIZE_1 + * + */ +NvU32 +kceGetPce2lceConfigSize1_GH100 +( + KernelCE *pKCe +) +{ + return NV_CE_PCE2LCE_CONFIG__SIZE_1; +} + +/** + * @brief This function takes in a link mask and returns the minimum number + * of PCE connections required. This is decided based on a round up approach + * where each PCE can handle 1.5 links. + */ +NvU32 +kceGetNumPceRequired +( + NvU32 numLinks +) +{ + switch(numLinks) + { + case 6: + return 4; + case 5: + case 4: + return 3; + case 3: + return 2; + case 2: + case 1: + default: + return 1; + } +} + +/** + * @brief This function returns the pceIndex for a particular link ID + * Must always be called with the hshub ID for the calling link ID + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pceIndex Pointer to caller pceIndex + * @param[out] pHshubId Pointer to caller HSHUB ID + */ +static void +_ceGetAlgorithmPceIndex +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pceIndex, + NvU8 *pHshubId +) +{ + NvU8 pHshubIdRequested; + NvU32 i; + + if (!(NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId])) + { + // + // 1. We couldn't find an applicable strided PCE in given HSHUB + // So, we'll assign the next consecutive PCE on the same HSHUB + // + *pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[*pHshubId]); + if (!(NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId])) + { + // 2. If this is not a valid PCE on given HSHUB, assign PCE from alternative HSHUB + pHshubIdRequested = *pHshubId; + for (i = pHshubIdRequested + 1; i != pHshubIdRequested; i++) { + if (i > 4) { + i = 1; + continue; + } + + *pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[i]); + if (NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId]) { + break; + } + } + + if (i == pHshubIdRequested) + { + // If we've reached this point, then we have no more available PCEs to assign + NV_PRINTF(LEVEL_ERROR, "No more available PCEs to assign!\n"); + NV_ASSERT(0); + } + } + } + return; +} + +/** + * @brief This function assigns LCE 2 and 3 mappings for C2C cases. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pLocalPceLceMap Pointer to PCE-LCE array + * @param[out] pLocalExposeCeMask Pointer to LCE Mask + */ +NV_STATUS +kceMapPceLceForC2C_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalExposeCeMask +) +{ + NV_STATUS status = NV_OK; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvU32 pceIndex, i, hshubId, lceMask, lceIndex; + NvU32 numNvLinkPeers = 0; + NvU32 selectPcePerHshub = 2; + NvBool c2cEnabled = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP); + + numNvLinkPeers = pKCe->nvlinkNumPeers; + if (gpuIsCCFeatureEnabled(pGpu) || (c2cEnabled && numNvLinkPeers == 0 && IS_MIG_IN_USE(pGpu))) + { + lceMask = NVBIT32(2) | NVBIT32(3); + *pLocalExposeCeMask |= lceMask; + + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + pceIndex = NVBIT32(0); + pLocalPceLceMap[pceIndex] = lceIndex; + lceMask &= (~(NVBIT32(lceIndex))); + + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + pceIndex = NVBIT32(1); + pLocalPceLceMap[pceIndex] = lceIndex; + } + else if (c2cEnabled && numNvLinkPeers == 0) + { + lceMask = NVBIT32(2); + *pLocalExposeCeMask |= lceMask; + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + + for (hshubId = 2; hshubId < NV_CE_MAX_HSHUBS; hshubId++) + { + for (i = 0; i < selectPcePerHshub; i++) + { + pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } + } + + lceMask = NVBIT32(4); + *pLocalExposeCeMask |= lceMask; + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + + for (hshubId = 2; hshubId < NV_CE_MAX_HSHUBS; hshubId++) + { + for (i = 0; i < selectPcePerHshub; i++) + { + pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } + } + } + else + { + status = NV_WARN_NOTHING_TO_DO; + } + + return status; +} + +/** + * @brief This function checks for root port gen speed or GPU + * gen speed to determine if we should apply genX+ mapping + * or genX- mapping + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] checkGen gen X for query + */ +NvBool +kceIsGenXorHigherSupported_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 checkGen +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + NvU8 genSpeed = 0; + NvU32 busSpeed = 0; + NV_STATUS status = NV_OK; + NvBool bIsGenXorHigher = NV_FALSE; + + status = clPcieGetRootGenSpeed(pGpu, pCl, &genSpeed); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Could not get root gen speed - check for GPU gen speed!\n"); + // Check for GPU gen speed + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_LINK_CONTROL_STATUS, &busSpeed) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_LINK_CONTROL_STATUS from config space.\n"); + return bIsGenXorHigher; + } + genSpeed = GPU_DRF_VAL(_EP_PCFG_GPU, _LINK_CONTROL_STATUS, _CURRENT_LINK_SPEED, busSpeed); + } + NV_PRINTF(LEVEL_INFO, "Gen Speed = %d\n", genSpeed); + + if ((genSpeed >= checkGen)) + { + bIsGenXorHigher = NV_TRUE; + } + + return bIsGenXorHigher; +} + +/** + * @brief This function assigns PCE-LCE mappings for GRCE LCEs 0 and 1. + * This function additionally takes care of mappings for LCE 2 and 3 + * in the default case. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pLocalPceLceMap Pointer to PCE-LCE array + * @param[out] pLocalExposeCeMask Pointer to LCE Mask + */ +void +kceMapPceLceForGRCE_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalExposeCeMask, + NvU32 *pLocalGrceMap, + NvU32 fbPceMask +) +{ + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvU32 grceIdx, pceIndex, i; + NvU32 lceIndex = 0; + NvU32 lceMask = 0; + NvU32 numNvLinkPeers = 0; + NvU32 grceMappings[NV_CE_NUM_FBPCE] = {12, 14, 13, 15}; + NvBool gen5OrHigher = kceIsGenXorHigherSupported_HAL(pGpu, pKCe, 5); + NvBool c2cEnabled = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP); + + numNvLinkPeers = pKCe->nvlinkNumPeers; + + if (gpuIsCCFeatureEnabled(pGpu) || (c2cEnabled && numNvLinkPeers == 0)) + { + lceMask = NVBIT32(0) | NVBIT32(1); + *pLocalExposeCeMask |= lceMask; + + for (grceIdx = 0; grceIdx < NV_CE_MAX_GRCE; grceIdx++) + { + for (i = 0; i < NV_CE_MAX_PCE_PER_GRCE; i++) + { + pceIndex = grceMappings[grceIdx * 2 + i]; + + // + // floorswept PCE or + // PCIe <= Gen4 experience high latency and requires a + // different mapping for LCE2 and LCE3 compared to Gen5. + // In PCIe <= Gen4 cases, only link 1 PCE to LCE by + // skipping every other PCE in the grceMappings array. + // + if (pceIndex == 0 || (!gen5OrHigher && (i % 2 == 1))) + continue; + + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + pLocalPceLceMap[pceIndex] = lceIndex; + } + + lceMask &= (~(NVBIT32(lceIndex))); + } + } + else + { + // Default case which will result in sharing LCE 2 and 3 with LCE 0 and 1 + lceMask = NVBIT32(2) | NVBIT32(3); + *pLocalExposeCeMask |= lceMask; + for (grceIdx = 0; grceIdx < NV_CE_MAX_GRCE; grceIdx++) + { + for (i = 0; i < NV_CE_MAX_PCE_PER_GRCE; i++) + { + pceIndex = grceMappings[grceIdx * 2 + i]; + + // floorswept PCE or account for PCIe latency in Gen <= 4 + if (pceIndex == 0 || (!gen5OrHigher && (i % 2 == 1))) + continue; + + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + pLocalPceLceMap[pceIndex] = lceIndex; + } + + // update lceMask now that all PCEs are assigned to this LCE + lceMask &= (~(NVBIT32(lceIndex))); + } + + // GRCE Cases + lceMask = kceGetGrceSupportedLceMask_HAL(pGpu, pKCe); + *pLocalExposeCeMask |= lceMask; + + for (grceIdx = 0; grceIdx < NV_CE_MAX_GRCE; grceIdx++) + { + for (i = 0; i < NV_CE_MAX_PCE_PER_GRCE; i++) + { + pceIndex = grceMappings[grceIdx * 2 + i]; + fbPceMask &= (~(NVBIT32(pceIndex))); + + // floorswept PCE + if (pceIndex == 0 || (!gen5OrHigher && (i % 2 == 1))) + continue; + + // Sharing use case + if ((NVBIT32(pLocalPceLceMap[pceIndex])) & *pLocalExposeCeMask) + { + // GRCE is shared - set the status and shared LCE # in register field + lceIndex = pLocalPceLceMap[pceIndex]; + pLocalGrceMap[grceIdx] = DRF_NUM(_CE, _GRCE_CONFIG, _SHARED, 1) | + DRF_NUM(_CE, _GRCE_CONFIG, _SHARED_LCE, lceIndex); + } + else + { + // GRCE got its own FBHUB PCE + // Store the LCE in the associated PCE for GRCE + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + pLocalPceLceMap[pceIndex] = lceIndex; + // Reflect non-sharing status in register field + pLocalGrceMap[grceIdx] = DRF_NUM(_CE, _GRCE_CONFIG, _SHARED, 0) | + DRF_DEF(_CE, _GRCE_CONFIG, _SHARED_LCE, _NONE); + } + } + + // update lceMask now that all PCEs are assigned to this LCE + lceMask &= (~(NVBIT32(lceIndex))); + } + } +} + +/** + * @brief This function assigns PCE-LCE mappings for NVLink peers + * Based on HSHUBs that the links associated with a peer connect to, + * algorithm will attempt to assign a PCE from associated HSHUB taking into + * account striding as well. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pLocalPceLceMap Pointer to PCE-LCE array + * @param[out] pLocalExposeCeMask Pointer to LCE Mask + * + * Returns NV_OK if successful in assigning PCEs and LCEs for each of the NVLink peers + */ +NV_STATUS +kceMapPceLceForNvlinkPeers_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalExposeCeMask +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = NV_OK; + NvU32 lceMask = 0; + NvU32 pceMask = 0; + NvU32 peerLinkMask = 0; + KernelCE *pKCeLce = NULL; + NvBool bPeerAssigned = NV_FALSE; + NvU32 peerAvailableLceMask = NV_CE_LCE_MASK_INIT; + OBJGPU *pRemoteGpu; + NvU32 numPcePerLink; + NvU32 lceIndex, pceIndex; + NvU8 hshubId = 0, i; + NvU32 linkId, gpuMask, gpuInstance = 0, j; + + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + + peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); + pKCe->nvlinkNumPeers = 0; + + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + // + // On NVSwitch systems, we only create 1 aperture for all p2p connections. + // For PCE2LCE mapping, we should only assign 1 LCE for this connection. + // + // Since we mark the loopback connections in peerLinkMasks with the appropriate + // links (see _nvlinkUpdateSwitchLinkMasks), we can use that to calculate + // the PCE2LCE config. + // + gpuMask = NVBIT32(pGpu->gpuInstance); + } + else + { + // On direct connected systems, we'll loop over each GPU in the system + // and assign a peer LCE for each connection + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + } + + while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + NvU32 numLinksToPeer = knvlinkGetNumLinksToPeer(pGpu, pKernelNvlink, + pRemoteGpu); + if (numLinksToPeer == 0) + { + continue; + } + + pceMask = 0; + lceMask = 0; + + if (peerAvailableLceMask == 0) + { + // + // peerAvailableLceMask is initialized to even async LCEs at the + // top of the function. + // As a result, if at any point in the loop, this mask == 0, + // it implies we have used up all even async LCEs and should move to + // using odd async LCEs. + // + peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); + } + + // Each peer gets 1 LCE + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); + lceMask |= NVBIT32(lceIndex); + + pKCe->nvlinkNumPeers++; + + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + + peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + + portMemSet(¶ms, 0, sizeof(params)); + params.linkMask = peerLinkMask; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + // Iterate through links by HSHUB + NvU32 linksPerHshub[NV_CE_MAX_HSHUBS] = {0}; + + FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMask) + { + hshubId = params.hshubIds[linkId]; + // Update link count for this hshub + linksPerHshub[hshubId]++; + } + FOR_EACH_INDEX_IN_MASK_END; + + for (i = 0; i < NV_CE_MAX_HSHUBS; i++) + { + if (linksPerHshub[i] == 0) + continue; + + pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[i]); + numPcePerLink = kceGetNumPceRequired(linksPerHshub[i]); + + for (j = 0; j < numPcePerLink; j++) + { + _ceGetAlgorithmPceIndex(pGpu, pKCe, pceAvailableMaskPerHshub, &pceIndex, &i); + pceMask |= NVBIT32(pceIndex); + // Clear out the assigned PCE + pceAvailableMaskPerHshub[i] &= (~(NVBIT32(pceIndex))); + } + + } + + // Now, assign the PCE-LCE association for the current peer + if (pceMask != 0) + { + // We just need at least one peer to set this to TRUE + bPeerAssigned = NV_TRUE; + + FOR_EACH_INDEX_IN_MASK(32, pceIndex, pceMask) + { + pLocalPceLceMap[pceIndex] = lceIndex; + NV_PRINTF(LEVEL_INFO, "GPU%d <-> GPU%d PCE Index: %d LCE Index: %d\n", + pGpu->gpuInstance, pRemoteGpu->gpuInstance, pceIndex, lceIndex); + } + FOR_EACH_INDEX_IN_MASK_END; + + // Store lceMask in the exposeCeMask before moving on + *pLocalExposeCeMask |= lceMask; + } + + pKCeLce = GPU_GET_KCE(pGpu, lceIndex); + pKCeLce->nvlinkPeerMask |= NVBIT(pRemoteGpu->gpuInstance); + + // + // Bug 200659256 - Looping over GPUs rather than peers (CL 28776130) + // does not handle multi-GPUs/Peer as is the case on switch systems. + // We must only take this loop once on switch systems to account for this. + // If we need to support multiple peer connections with switch systems + // in the future, this code must be revisited + // + if (pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) + { + break; + } + + } + + if (bPeerAssigned == NV_FALSE) + { + status = NV_WARN_NOTHING_TO_DO; + } + + return status; +} + +/** + * @brief Some clients rely on LCE 4 also being turned on when there + * are no NVLink peers. This function sets up the default links. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pLocalPceLceMap Pointer to PCE-LCE array + * @param[out] pLocalExposeCeMask Pointer to LCE Mask + * + * Returns NV_OK if successful in assigning PCEs to a default async LCE (>= 4) + */ +NV_STATUS +kceMapAsyncLceDefault_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalExposeCeMask, + NvU32 numDefaultPces +) +{ + NvU32 peerAvailableLceMask = NV_CE_LCE_MASK_INIT; + NvU32 lceMask = 0; + NvU32 pceMask = 0; + NvU32 lceIndex, pceIndex, hshubId, i; + + peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); + hshubId = 1; + + // + // If no peers were found, then no async LCEs (>= 4) will be turned on. + // However, some clients rely on LCE 4 being present even without any + // NVLink peers being found. So, turn on the 1st available async LCE (>= 4) + // Reference bug 3042556 + // + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); + lceMask |= NVBIT32(lceIndex); + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + + // Assign PCEs to this LCE based on input request + for (i = 0; i < numDefaultPces; i++) + { + if (i % NV_CE_PCE_PER_HSHUB == 0) + hshubId++; + + pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); + pceMask |= NVBIT32(pceIndex); + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + } + + FOR_EACH_INDEX_IN_MASK(32, pceIndex, pceMask) + { + pLocalPceLceMap[pceIndex] = lceIndex; + NV_PRINTF(LEVEL_INFO, "GPU%d <-> GPU%d PCE Index: %d LCE Index: %d\n", + pGpu->gpuInstance, pGpu->gpuInstance, pceIndex, lceIndex); + } + FOR_EACH_INDEX_IN_MASK_END; + + // Store lceMask in the exposeCeMask before moving on + *pLocalExposeCeMask |= lceMask; + + return NV_OK; + +} + +NV_STATUS +kceGetMappings_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NVLINK_TOPOLOGY_PARAMS *pTopoParams, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalGrceMap, + NvU32 *pExposeCeMask +) +{ + NV_STATUS status = NV_OK; + NV_STATUS statusC2C = NV_OK; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + //Prepare the per-HSHUB/FBHUB available PCE mask + kceGetAvailableHubPceMask(pGpu, pTopoParams); + + // Assign PCEs to "PEER"s if nvlink is enabled + if (pKernelNvlink && !knvlinkIsForcedConfig(pGpu, pKernelNvlink)) + { + status = kceMapPceLceForNvlinkPeers_HAL(pGpu, pKCe, + pTopoParams->pceAvailableMaskPerHshub, + pLocalPceLceMap, + pExposeCeMask); + } + else + { + status = NV_WARN_NOTHING_TO_DO; + } + + // Special C2C cases for LCE 2 and 3 + statusC2C = kceMapPceLceForC2C_HAL(pGpu, pKCe, + pTopoParams->pceAvailableMaskPerHshub, + pLocalPceLceMap, pExposeCeMask); + + // Assign PCEs for GRCE case + kceMapPceLceForGRCE_HAL(pGpu, pKCe, + pTopoParams->pceAvailableMaskPerHshub, + pLocalPceLceMap, pExposeCeMask, pLocalGrceMap, pTopoParams->fbhubPceMask); + + if ((status == NV_WARN_NOTHING_TO_DO && statusC2C == NV_WARN_NOTHING_TO_DO) || + (status == NV_ERR_NOT_SUPPORTED && statusC2C == NV_ERR_NOT_SUPPORTED)) + { + // If there's no NVLink peers available, still expose an additional async LCE + status = kceMapAsyncLceDefault_HAL(pGpu, pKCe, + pTopoParams->pceAvailableMaskPerHshub, + pLocalPceLceMap, + pExposeCeMask, + NV_CE_NUM_PCES_NO_LINK_CASE); + } + + NV_PRINTF(LEVEL_INFO, "status = %d, statusC2C = %d\n", status, statusC2C); + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c b/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c index 815320d14..bde9f9032 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c @@ -167,16 +167,19 @@ kceGetNvlinkMaxTopoForTable_GP100 NvU32 currentTopoIdx = 0; NvBool bCachedIdxExists, bCurrentIdxExists; NvU32 currentExposeCeMask, cachedExposeCeMask; - NVLINK_TOPOLOGY_PARAMS cachedTopo; + NvBool result = NV_FALSE; + NVLINK_TOPOLOGY_PARAMS *pCachedTopo = portMemAllocNonPaged(sizeof(*pCachedTopo)); + + NV_ASSERT_OR_RETURN(pCachedTopo != NULL, result); // // If exposeCeMask from current config is a subset of the cached topology, // then use the cached topology data. // We do this to ensure that we don't revoke CEs that we have exposed prevously. // - gpumgrGetSystemNvlinkTopo(gpuGetDBDF(pGpu), &cachedTopo); + gpumgrGetSystemNvlinkTopo(gpuGetDBDF(pGpu), pCachedTopo); - bCachedIdxExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, &cachedTopo, + bCachedIdxExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, pCachedTopo, pAutoConfigTable, autoConfigNumEntries, &cachedTopoIdx, &cachedExposeCeMask); @@ -225,8 +228,13 @@ kceGetNvlinkMaxTopoForTable_GP100 else { // Neither are in table - return NV_FALSE; + result = NV_FALSE; + goto done; } - return NV_TRUE; + result = NV_TRUE; + +done: + portMemFree(pCachedTopo); + return result; } diff --git a/src/nvidia/src/kernel/gpu/ce/arch/turing/kernel_ce_tu102.c b/src/nvidia/src/kernel/gpu/ce/arch/turing/kernel_ce_tu102.c index 765d1e481..fe07c1437 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/turing/kernel_ce_tu102.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/turing/kernel_ce_tu102.c @@ -32,52 +32,6 @@ #define NVLINK_CE_AUTO_CONFIG_TABLE_DEFAULT_ENTRY 0 -#define MAX_CE_CNT 15 - -/* - * sysmemLinks - * Represents the number of sysmem links detected - * This affects how many PCEs LCE0(sysmem read CE) - * and LCE1(sysmem write CE) should be mapped to - * maxLinksPerPeer - * Represents the maximum number of peer links - * between this GPU and all its peers. This affects - * how many PCEs LCE3(P2P CE) should be mapped to - * numPeers - * Represents the number of Peer GPUs discovered so far - * bSymmetric - * Represents whether the topology detected so far - * is symmetric i.e. has same number of links to all - * peers connected through nvlink. This affects how - * many PCEs to assign to LCEs3-5 (nvlink P2P CEs) - * bSwitchConfig - * Represents whether the config listed is intended - * for use with nvswitch systems - * pceLceMap - * Value of NV_CE_PCE2LCE_CONFIG0 register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * grceConfig - * Value of NV_CE_GRCE_CONFIG register with the - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - * exposeCeMask - * Mask of CEs to expose to clients for the above - * above values for sysmemLinks, maxLinksPerPeer, - * numLinks and bSymmetric - */ -typedef struct -{ - NvU32 sysmemLinks; - NvU32 maxLinksPerPeer; - NvU32 numPeers; - NvBool bSymmetric; - NvBool bSwitchConfig; - NvU32 pceLceMap[MAX_CE_CNT]; - NvU32 grceConfig[MAX_CE_CNT]; - NvU32 exposeCeMask; -} NVLINK_CE_AUTO_CONFIG_TABLE; - /* * Table for setting the PCE2LCE mapping */ @@ -132,29 +86,31 @@ kceGetNvlinkAutoConfigCeValues_TU102 NvU32 grceConfigSize1 = kceGetGrceConfigSize1_HAL(pKCe); NvBool bEntryExists; NvU32 pceIdx, grceIdx; - NVLINK_TOPOLOGY_PARAMS currentTopo = { 0 }; + NVLINK_TOPOLOGY_PARAMS *pCurrentTopo = NULL; if ((pPceLceMap == NULL) || (pGrceConfig == NULL) || (pExposeCeMask == NULL)) { - return NV_ERR_INVALID_ARGUMENT; + status = NV_ERR_INVALID_ARGUMENT; + goto done; } if (pKernelNvlink == NULL) { - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto done; } - // Initialize pPceLceMap with no mappings - for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) - { - pPceLceMap[pceIdx] = NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE; - } + pCurrentTopo = portMemAllocNonPaged(sizeof(*pCurrentTopo)); + NV_ASSERT_OR_RETURN(pCurrentTopo != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pCurrentTopo, 0, sizeof(*pCurrentTopo)); sysmemLinks = knvlinkGetNumLinksToSystem(pGpu, pKernelNvlink); if (gpuGetNumCEs(pGpu) == 0) { - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto done; } (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); @@ -187,14 +143,14 @@ kceGetNvlinkAutoConfigCeValues_TU102 } } - currentTopo.sysmemLinks = sysmemLinks; - currentTopo.maxLinksPerPeer = maxLinksPerPeer; - currentTopo.numPeers = numPeers; - currentTopo.bSymmetric = bSymmetric; - currentTopo.bSwitchConfig = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); + pCurrentTopo->sysmemLinks = sysmemLinks; + pCurrentTopo->maxLinksPerPeer = maxLinksPerPeer; + pCurrentTopo->numPeers = numPeers; + pCurrentTopo->bSymmetric = bSymmetric; + pCurrentTopo->bSwitchConfig = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); // Use largest topology seen by this GPU - bEntryExists = kceGetNvlinkMaxTopoForTable_HAL(pGpu, pKCe, ¤tTopo, nvLinkCeAutoConfigTable_TU102, + bEntryExists = kceGetNvlinkMaxTopoForTable_HAL(pGpu, pKCe, pCurrentTopo, nvLinkCeAutoConfigTable_TU102, NV_ARRAY_ELEMENTS(nvLinkCeAutoConfigTable_TU102), &topoIdx); if (!bEntryExists) @@ -210,13 +166,13 @@ kceGetNvlinkAutoConfigCeValues_TU102 // info across GPU loads. // Preserving across GPU loads enables UVM to optimize perf // - currentTopo.sysmemLinks = nvLinkCeAutoConfigTable_TU102[topoIdx].sysmemLinks; - currentTopo.maxLinksPerPeer = nvLinkCeAutoConfigTable_TU102[topoIdx].maxLinksPerPeer; - currentTopo.numPeers = nvLinkCeAutoConfigTable_TU102[topoIdx].numPeers; - currentTopo.bSymmetric = nvLinkCeAutoConfigTable_TU102[topoIdx].bSymmetric; - currentTopo.bSwitchConfig = nvLinkCeAutoConfigTable_TU102[topoIdx].bSwitchConfig; + pCurrentTopo->sysmemLinks = nvLinkCeAutoConfigTable_TU102[topoIdx].sysmemLinks; + pCurrentTopo->maxLinksPerPeer = nvLinkCeAutoConfigTable_TU102[topoIdx].maxLinksPerPeer; + pCurrentTopo->numPeers = nvLinkCeAutoConfigTable_TU102[topoIdx].numPeers; + pCurrentTopo->bSymmetric = nvLinkCeAutoConfigTable_TU102[topoIdx].bSymmetric; + pCurrentTopo->bSwitchConfig = nvLinkCeAutoConfigTable_TU102[topoIdx].bSwitchConfig; - gpumgrUpdateSystemNvlinkTopo(gpuGetDBDF(pGpu), ¤tTopo); + gpumgrUpdateSystemNvlinkTopo(gpuGetDBDF(pGpu), pCurrentTopo); for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) { @@ -252,6 +208,8 @@ kceGetNvlinkAutoConfigCeValues_TU102 nvLinkCeAutoConfigTable_TU102[topoIdx].grceConfig[0], *pExposeCeMask, gpuMask); +done: + portMemFree(pCurrentTopo); return status; } diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index aaf76c203..860eccf19 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -128,7 +128,8 @@ NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, NvU32 engineType, // Since some CE capabilities depend on the nvlink topology, // trigger topology detection before updating the CE caps // - if (pKernelNvlink != NULL && !knvlinkIsForcedConfig(pGpu, pKernelNvlink)) + if ((pKernelNvlink != NULL) && !knvlinkIsForcedConfig(pGpu, pKernelNvlink) && + kmigmgrIsMIGNvlinkP2PSupported(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu))) { knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); } @@ -181,7 +182,8 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL // Since some CE capabilities depend on the nvlink topology, // trigger topology detection before updating the CE caps // - if (pKernelNvlink != NULL && !knvlinkIsForcedConfig(pGpu, pKernelNvlink)) + if ((pKernelNvlink != NULL) && !knvlinkIsForcedConfig(pGpu, pKernelNvlink) && + kmigmgrIsMIGNvlinkP2PSupported(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu))) { knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); } @@ -370,13 +372,10 @@ kceServiceNotificationInterrupt_IMPL MODS_ARCH_REPORT(NV_ARCH_EVENT_NONSTALL_CE, "%s", "processing CE nonstall interrupt\n"); - NV_ASSERT(NV2080_NOTIFIERS_CE(pKCe->publicID)); - kceNonstallIntrCheckAndClear_HAL(pGpu, pKCe, pParams->pThreadState); // Wake up channels waiting on this event - engineNonStallIntrNotify(pGpu, - NV2080_ENGINE_TYPE_COPY0 + NV2080_NOTIFIERS_CE(pKCe->publicID) - NV2080_NOTIFIERS_CE0); + engineNonStallIntrNotify(pGpu, NV2080_ENGINE_TYPE_COPY(pKCe->publicID)); return NV_OK; } @@ -388,7 +387,7 @@ NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, KernelCE *pKCe) NvU32 exposeCeMask = 0; NvBool bUpdateNvlinkPceLce = NV_FALSE; NV_STATUS status = NV_OK; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 i; // // Sync class DB before proceeding with the algorithm. @@ -396,35 +395,38 @@ NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, KernelCE *pKCe) // NV_ASSERT_OK_OR_RETURN(kceUpdateClassDB_HAL(pGpu, pKCe)); - if (pKernelNvlink && !knvlinkIsForcedConfig(pGpu, pKernelNvlink)) - { - // - // If not GSP-RM, get the auto-config PCE-LCE mappings for NVLink topology. - // This should work fine on CPU-RM and monolithic RM. - // + for (i = 0; i < NV2080_CTRL_MAX_PCES; i++) + pceLceMap[i] = NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE; - // Set bUpdateNvlinkPceLce to auto-config status - bUpdateNvlinkPceLce = pKCe->bIsAutoConfigEnabled; + for (i = 0; i < NV2080_CTRL_MAX_GRCES; i++) + grceConfig[i] = NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE; - if (bUpdateNvlinkPceLce) + // + // If not GSP-RM, get the auto-config PCE-LCE mappings for NVLink topology. + // This should work fine on CPU-RM and monolithic RM. + // + + // Set bUpdateNvlinkPceLce to auto-config status + bUpdateNvlinkPceLce = pKCe->bIsAutoConfigEnabled; + + if (bUpdateNvlinkPceLce) + { + status = kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, pceLceMap, + grceConfig, &exposeCeMask); + if (status == NV_ERR_NOT_SUPPORTED) { - status = kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, pceLceMap, - grceConfig, &exposeCeMask); - if (status == NV_ERR_NOT_SUPPORTED) - { - NV_PRINTF(LEVEL_INFO, - "CE AutoConfig is not supported. Skipping PCE2LCE update\n"); + NV_PRINTF(LEVEL_INFO, + "CE AutoConfig is not supported. Skipping PCE2LCE update\n"); - bUpdateNvlinkPceLce = NV_FALSE; - } - else + bUpdateNvlinkPceLce = NV_FALSE; + } + else + { + if (status != NV_OK) { - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to get auto-config PCE-LCE mappings. Return\n"); - return status; - } + NV_PRINTF(LEVEL_ERROR, + "Failed to get auto-config PCE-LCE mappings. Return\n"); + return status; } } } diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c index bacdf251e..e86a4692f 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c @@ -41,6 +41,7 @@ #include "class/clc6b5sw.h" #include "class/clc7b5.h" +#include "class/clc8b5.h" /* * This function returns an engine descriptor corresponding to the class * and engine instance passed in. @@ -92,6 +93,7 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo case AMPERE_DMA_COPY_A: case AMPERE_DMA_COPY_B: + case HOPPER_DMA_COPY_A: { NVB0B5_ALLOCATION_PARAMETERS *pNvA0b5CreateParms = pAllocParams; diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c b/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c index 5010082ef..0d3e5558f 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c @@ -46,9 +46,9 @@ NvU32 kheadReadPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead if (!FLD_IDX_TEST_DRF(_PDISP, _FE_RM_INTR_DISPATCH, _HEAD_TIMING, pKernelHead->PublicId, _PENDING, intr)) return headIntrMask; - - intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId)); - + + intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(pKernelHead->PublicId)); + if (FLD_TEST_DRF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _PENDING, intr)) { headIntrMask |= headIntr_vblank; diff --git a/src/nvidia/src/kernel/gpu/disp/disp_channel.c b/src/nvidia/src/kernel/gpu/disp/disp_channel.c index b2c1c8de3..167cd57be 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_channel.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_channel.c @@ -411,25 +411,9 @@ void kdispUnbindUnmapDispChannel_IMPL RsClient *pClient = RES_GET_CLIENT(pDispChannel); RmClient *pRmClient = dynamicCast(pClient, RmClient); RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilege(pRmClient); - RS_ITERATOR ContextDmaIt; - // Unbind all context dmas bound to this channel - ContextDmaIt = clientRefIter(pClient, RES_GET_REF(GPU_RES_GET_DEVICE(pDispChannel)), classId(ContextDma), RS_ITERATE_DESCENDANTS, NV_TRUE); - while (clientRefIterNext(ContextDmaIt.pClient, &ContextDmaIt)) - { - ContextDma *pContextDma; - - pContextDma = dynamicCast(ContextDmaIt.pResourceRef->pResource, ContextDma); - if (pContextDma == NULL) - continue; - - // Quickly skip unbound ContextDmas - if (ctxdmaIsBound(pContextDma)) - { - // Ignore unbind status as the ContextDma may not be bound to this channel - (void)dispchnUnbindCtx(pDispChannel, pGpu, pContextDma); - } - } + // Unbind all ContextDmas from this channel + dispchnUnbindAllCtx(pGpu, pDispChannel); // Unmap the channel osUnmapGPU(pGpu->pOsGpuInfo, privLevel, pDispChannel->pControl, @@ -590,15 +574,25 @@ dispchnGetByHandle_IMPL NV_STATUS dispchnBindCtx_IMPL ( - DispChannel *pDispChannel, OBJGPU *pGpu, - ContextDma *pContextDma + ContextDma *pContextDma, + NvHandle hChannel ) { + RsClient *pClient = RES_GET_CLIENT(pContextDma); + DispChannel *pDispChannel = NULL; NV_STATUS rmStatus = NV_OK; KernelDisplay *pKernelDisplay; DisplayInstanceMemory *pInstMem; + // Look-up channel + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + dispchnGetByHandle(pClient, hChannel, &pDispChannel)); + + // Ensure ContextDma and DisplayChannel are on the save device + NV_CHECK_OR_RETURN(LEVEL_ERROR, pContextDma->pDevice == GPU_RES_GET_DEVICE(pDispChannel), + NV_ERR_INVALID_DEVICE); + // // Enforce alignment requirements // ISO ctx dmas need to be a multiple of 256B and 256B aligned @@ -633,16 +627,26 @@ dispchnBindCtx_IMPL NV_STATUS dispchnUnbindCtx_IMPL ( - DispChannel *pDispChannel, OBJGPU *pGpu, - ContextDma *pContextDma + ContextDma *pContextDma, + NvHandle hChannel ) { + RsClient *pClient = RES_GET_CLIENT(pContextDma); + DispChannel *pDispChannel = NULL; NV_STATUS rmStatus = NV_OK; KernelDisplay *pKernelDisplay; DisplayInstanceMemory *pInstMem; NvBool bFound = NV_FALSE; + // Look-up channel given by client + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + dispchnGetByHandle(pClient, hChannel, &pDispChannel)); + + // Ensure ContextDma and DisplayChannel are on the save device + NV_CHECK_OR_RETURN(LEVEL_ERROR, pContextDma->pDevice == GPU_RES_GET_DEVICE(pDispChannel), + NV_ERR_INVALID_DEVICE); + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); pInstMem = KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay); @@ -658,6 +662,50 @@ dispchnUnbindCtx_IMPL return bFound ? NV_OK : NV_ERR_INVALID_STATE; } +/*! + * @brief Unbind all ContextDmas from the given channel + */ +void +dispchnUnbindAllCtx_IMPL +( + OBJGPU *pGpu, + DispChannel *pDispChannel +) +{ + KernelDisplay *pKernelDisplay; + DisplayInstanceMemory *pInstMem; + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + pInstMem = KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay); + + instmemUnbindDispChannelContextDmas(pGpu, pInstMem, pDispChannel); + + SLI_LOOP_END +} + +/*! + * @brief Unbind ContextDma from all display channels + */ +void +dispchnUnbindCtxFromAllChannels_IMPL +( + OBJGPU *pGpu, + ContextDma *pContextDma +) +{ + KernelDisplay *pKernelDisplay; + DisplayInstanceMemory *pInstMem; + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + pInstMem = KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay); + + instmemUnbindContextDmaFromAllChannels(pGpu, pInstMem, pContextDma); + + SLI_LOOP_END +} + NV_STATUS kdispSetPushBufferParamsToPhysical_IMPL ( diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c index 515e53a58..99cb36616 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -540,6 +540,44 @@ _instmemFreeContextDma return NV_OK; } +static void +_instmemClearHashEntry +( + OBJGPU *pGpu, + DisplayInstanceMemory *pInstMem, + NvU32 htEntry +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE dest = {0}; + NvU32 entryOffset; + DISP_HW_HASH_TABLE_ENTRY entry; + + pInstMem->pHashTable[htEntry].pContextDma = NULL; + pInstMem->pHashTable[htEntry].pDispChannel = NULL; + + // + // If we found the entry, clear the inst mem copy of the entry + // Start with offset of base of inst mem + // Add offset of base of hash table from base of inst mem + // Add the offset of entry from base of hash table + // + entryOffset = pInstMem->hashTableBaseAddr + + (sizeof(DISP_HW_HASH_TABLE_ENTRY) * htEntry); + + dest.pMemDesc = pInstMem->pInstMemDesc; + dest.offset = entryOffset; + + entry.ht_ObjectHandle = 0; + entry.ht_Context = instmemGenerateHashTableData_HAL(pGpu, pInstMem, + 0 /* client id */, + 0 /* NV_UDISP_HASH_TBL_INSTANCE_INVALID */, + 0 /* dispChannelNum */); + + NV_ASSERT_OK(memmgrMemWrite(pMemoryManager, &dest, &entry, sizeof(entry), + TRANSFER_FLAGS_NONE)); +} + static NV_STATUS _instmemRemoveHashEntry ( @@ -549,40 +587,14 @@ _instmemRemoveHashEntry DispChannel *pDispChannel ) { - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU32 htEntry, entryOffset; - TRANSFER_SURFACE dest = {0}; - DISP_HW_HASH_TABLE_ENTRY entry; + NvU32 htEntry; for (htEntry = 0; htEntry < pInstMem->nHashTableEntries; htEntry++) { if ( (pInstMem->pHashTable[htEntry].pContextDma == pContextDma) && (pInstMem->pHashTable[htEntry].pDispChannel == pDispChannel)) { - pInstMem->pHashTable[htEntry].pContextDma = NULL; - pInstMem->pHashTable[htEntry].pDispChannel = NULL; - - // - // If we found the entry, clear the inst mem copy of the entry - // Start with offset of base of inst mem - // Add offset of base of hash table from base of inst mem - // Add the offset of entry from base of hash table - // - entryOffset = pInstMem->hashTableBaseAddr + - (sizeof(DISP_HW_HASH_TABLE_ENTRY) * htEntry); - - dest.pMemDesc = pInstMem->pInstMemDesc; - dest.offset = entryOffset; - - entry.ht_ObjectHandle = 0; - entry.ht_Context = instmemGenerateHashTableData_HAL(pGpu, pInstMem, - 0 /* client id */, - 0 /* NV_UDISP_HASH_TBL_INSTANCE_INVALID */, - 0 /* dispChannelNum */); - - NV_ASSERT_OK_OR_RETURN(memmgrMemWrite(pMemoryManager, &dest, &entry, sizeof(entry), - TRANSFER_FLAGS_NONE)); - + _instmemClearHashEntry(pGpu, pInstMem, htEntry); return NV_OK; } } @@ -844,6 +856,34 @@ instmemBindContextDma_IMPL return status; } +/*! + * @brief Remove reference to an instance allocation. Free after last reference. + */ +void +_instmemRemoveReference +( + OBJGPU *pGpu, + DisplayInstanceMemory *pInstMem, + ContextDma *pContextDma +) +{ + NvU32 gpuSubDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + NV_ASSERT(pContextDma->InstRefCount[gpuSubDevInst]); + if (pContextDma->InstRefCount[gpuSubDevInst]) + { + pContextDma->InstRefCount[gpuSubDevInst]--; + + // Remove DMA object if this is the last binding + if (pContextDma->InstRefCount[gpuSubDevInst] == 0) + { + instmemDecommitContextDma_HAL(pGpu, pInstMem, pContextDma); + _instmemFreeContextDma(pGpu, pInstMem, pContextDma->Instance[gpuSubDevInst]); + pContextDma->Instance[gpuSubDevInst] = 0; + } + } +} + /*! * @brief Unbind the ContextDma from the given Display Channel */ @@ -856,29 +896,66 @@ instmemUnbindContextDma_IMPL DispChannel *pDispChannel ) { - NvU32 gpuSubDevInst; NV_STATUS status; - gpuSubDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - // If ContextDma is not bound to this subdevice, there is no bookkeeping to do status = _instmemRemoveHashEntry(pGpu, pInstMem, pContextDma, pDispChannel); if (status == NV_OK) { - NV_ASSERT(pContextDma->InstRefCount[gpuSubDevInst]); - if (pContextDma->InstRefCount[gpuSubDevInst]) + _instmemRemoveReference(pGpu, pInstMem, pContextDma); + } + + return status; +} + +/*! + * @brief Unbind the ContextDma from all Display channels on the given context + */ +void +instmemUnbindContextDmaFromAllChannels_IMPL +( + OBJGPU *pGpu, + DisplayInstanceMemory *pInstMem, + ContextDma *pContextDma +) +{ + NvU32 htEntry; + + // Check all entries in the hash table + for (htEntry = 0; htEntry < pInstMem->nHashTableEntries; htEntry++) + { + if (pInstMem->pHashTable[htEntry].pContextDma == pContextDma) { - pContextDma->InstRefCount[gpuSubDevInst]--; + _instmemClearHashEntry(pGpu, pInstMem, htEntry); + _instmemRemoveReference(pGpu, pInstMem, pContextDma); + } + } - // Remove DMA object if this is the last binding - if (pContextDma->InstRefCount[gpuSubDevInst] == 0) - { - instmemDecommitContextDma_HAL(pGpu, pInstMem, pContextDma); - _instmemFreeContextDma(pGpu, pInstMem, pContextDma->Instance[gpuSubDevInst]); - pContextDma->Instance[gpuSubDevInst] = 0; - } +} + +/*! + * @brief Unbind the ContextDma from all Display channels on the given context + */ +void +instmemUnbindDispChannelContextDmas_IMPL +( + OBJGPU *pGpu, + DisplayInstanceMemory *pInstMem, + DispChannel *pDispChannel +) +{ + NvU32 htEntry; + + // Check all entries in the hash table + for (htEntry = 0; htEntry < pInstMem->nHashTableEntries; htEntry++) + { + if (pInstMem->pHashTable[htEntry].pDispChannel == pDispChannel) + { + ContextDma *pContextDma = pInstMem->pHashTable[htEntry].pContextDma; + + _instmemClearHashEntry(pGpu, pInstMem, htEntry); + _instmemRemoveReference(pGpu, pInstMem, pContextDma); } } - return status; } diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 166499604..1c949b81b 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -74,6 +74,8 @@ #include "class/clc67d.h" #include "class/clc67e.h" +#include "class/clc77d.h" + #include "gpu/disp/rg_line_callback/rg_line_callback.h" NV_STATUS @@ -400,6 +402,7 @@ kdispGetIntChnClsForHwCls_IMPL case NVC37D_CORE_CHANNEL_DMA: case NVC57D_CORE_CHANNEL_DMA: case NVC67D_CORE_CHANNEL_DMA: + case NVC77D_CORE_CHANNEL_DMA: *pDispChnClass = dispChnClass_Core; break; @@ -840,8 +843,6 @@ kdispServiceVblank_KERNEL return; } - NVRM_TRACE('VBLK'); - // // Although we have separate handlers for each head, attempt to process all // interrupting heads now. What about DPCs schedule already? @@ -856,7 +857,7 @@ kdispServiceVblank_KERNEL } // Process the callback list for this Head... - kheadProcessVblankCallbacks_HAL(pGpu, pKernelHead, state); + kheadProcessVblankCallbacks(pGpu, pKernelHead, state); } // @@ -894,7 +895,6 @@ kdispServiceVblank_KERNEL } return; - NVRM_TRACE('vblk'); } NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, THREAD_STATE_NODE *pThreadState) diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c index a4a78f5b7..beda24579 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c @@ -415,7 +415,7 @@ kheadProcessVblankCallbacks_IMPL VBLANKCALLBACK **ppPrev = NULL; NvBool done = NV_FALSE; NvBool removed = NV_FALSE; - NvBool queueDPC = NV_FALSE; + NvBool bQueueDpc = NV_FALSE; NvU32 newstate; NvU32 Count = 0; NvU64 time = 0; @@ -504,7 +504,7 @@ kheadProcessVblankCallbacks_IMPL pCallback->Param1, pCallback->Param2, pCallback->Status); - queueDPC = NV_TRUE; + bQueueDpc = NV_TRUE; } else { @@ -548,7 +548,7 @@ kheadProcessVblankCallbacks_IMPL pCallback->Param1, pCallback->Param2, pCallback->Status); - queueDPC = NV_TRUE; + bQueueDpc = NV_TRUE; } else { @@ -562,7 +562,7 @@ kheadProcessVblankCallbacks_IMPL pCallback->Param1, pCallback->Param2, pCallback->Status); - queueDPC = NV_TRUE; + bQueueDpc = NV_TRUE; } } @@ -630,8 +630,9 @@ kheadProcessVblankCallbacks_IMPL } } - if (queueDPC) + if (bQueueDpc) { + osQueueDpc(pGpu); } // After all of that, if the callback lists are null and the vblank is ENABLED, move it to AVAILABLE now. diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c index 3e604e7dc..4eaef1bd8 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c @@ -136,16 +136,21 @@ vblcbCtrlSetVBlankNotification_IMPL NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS *pParams ) { - NV_STATUS status = NV_ERR_INVALID_ARGUMENT; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVblankCallback); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVblankCallback->LogicalHead); + NV_STATUS status = NV_ERR_INVALID_ARGUMENT; if (pVblankCallback->CallBack.Proc != NULL) { if (pParams->bSetVBlankNotifyEnable) { pVblankCallback->CallBack.bIsVblankNotifyEnable = NV_TRUE; + kheadAddVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); } else { pVblankCallback->CallBack.bIsVblankNotifyEnable = NV_FALSE; + kheadDeleteVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); } status = NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c b/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c index 980b95f2a..db20a28c0 100644 --- a/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c +++ b/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c @@ -143,7 +143,9 @@ kflcnPreResetWait_GA10X { NvU32 hwcfg2; RMTIMEOUT timeout; - NvU32 flags = GPU_TIMEOUT_FLAGS_DEFAULT | GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG; + NvU32 flags = (GPU_TIMEOUT_FLAGS_TMR | + GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | + GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG); if (!IS_SILICON(pGpu) && !IS_EMULATION(pGpu)) { diff --git a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c index a51ca68c5..b52b07bee 100644 --- a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c +++ b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c @@ -434,24 +434,3 @@ kflcnMaskDmemAddr_TU102 return (addr & (DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_OFFS) | DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_BLK))); } - -void gkflcnNonstallIntrCheckAndClear_TU102(OBJGPU *pGpu, GenericKernelFalcon *pGKF, THREAD_STATE_NODE *pThreadState) -{ - NvU32 registerBase = staticCast(pGKF, KernelFalcon)->registerBase; - NvU32 intr, clearBits; - - NV_ASSERT(registerBase != 0); - - intr = GPU_REG_RD32_EX(pGpu, registerBase + NV_PFALCON_FALCON_IRQSTAT, - pThreadState); - - if (DRF_VAL( _PFALCON_FALCON, _IRQSTAT, _SWGEN1, intr)) - { - NV_PRINTF(LEVEL_INFO, "Handling Trap Interrupt\n"); - - // Clear interrupt - clearBits = DRF_NUM(_PFALCON_FALCON, _IRQSTAT, _SWGEN1, 1); - GPU_REG_WR32_EX(pGpu, registerBase + NV_PFALCON_FALCON_IRQSCLR, - clearBits, pThreadState); - } -} diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index b1bfea398..1f31038e2 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -22,7 +22,6 @@ */ #include "gpu/falcon/kernel_falcon.h" #include "gpu/sec2/kernel_sec2.h" -#include "gpu/nvdec/kernel_nvdec.h" #include "gpu/gsp/kernel_gsp.h" #include "gpu/fifo/kernel_fifo.h" @@ -64,7 +63,6 @@ KernelFalcon *kflcnGetKernelFalconForEngine_IMPL(OBJGPU *pGpu, ENGDESCRIPTOR phy // this list is mirrored in subdeviceCtrlCmdInternalGetConstructedFalconInfo_IMPL case ENG_SEC2: return staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); case ENG_GSP: return staticCast(GPU_GET_KERNEL_GSP(pGpu), KernelFalcon); - case ENG_NVDEC(0): return staticCast(GPU_GET_KERNEL_NVDEC(pGpu), KernelFalcon); default: return staticCast(gpuGetGenericKernelFalconForEngine(pGpu, physEngDesc), KernelFalcon); } @@ -359,8 +357,6 @@ NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFal NV_ASSERT_OR_RETURN(idx2080 != NV2080_ENGINE_TYPE_NULL, NV_ERR_INVALID_STATE); - gkflcnNonstallIntrCheckAndClear_HAL(pGpu, pGenericKernelFalcon, pParams->pThreadState); - // Wake up channels waiting on this event engineNonStallIntrNotify(pGpu, idx2080); diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c new file mode 100644 index 000000000..64da8cf2d --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" + +/*! + * @brief Creates a memory descriptor to be used for creating a GPU mapped MMIO + * region for a given channel. + */ +NV_STATUS +kchannelCreateUserMemDesc_GA10B +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NV_STATUS status; + MEMORY_DESCRIPTOR *pSubDevInstMemDesc = NULL; + MEMORY_DESCRIPTOR **ppMemDesc = + &pKernelChannel->pInstSubDeviceMemDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]; + + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + + status = kfifoChannelGetFifoContextMemDesc_HAL(pGpu, pKernelFifo, pKernelChannel, + FIFO_CTX_INST_BLOCK, &pSubDevInstMemDesc); + + if (status != NV_OK) + return status; + + NV_ASSERT_OR_RETURN(pSubDevInstMemDesc != NULL, NV_ERR_OBJECT_NOT_FOUND); + + status = memdescCreate(ppMemDesc, pGpu, RM_PAGE_SIZE, 0, + memdescGetContiguity(pSubDevInstMemDesc, AT_GPU), + memdescGetAddressSpace(pSubDevInstMemDesc), + memdescGetCpuCacheAttrib(pSubDevInstMemDesc), + MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); + + if (status != NV_OK) + return status; + + NV_ASSERT_OR_RETURN(*ppMemDesc != NULL, NV_ERR_NO_MEMORY); + + memdescDescribe(*ppMemDesc, memdescGetAddressSpace(pSubDevInstMemDesc), + memdescGetPhysAddr(pSubDevInstMemDesc, AT_GPU, 0), RM_PAGE_SIZE); + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c new file mode 100644 index 000000000..5d34accfa --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/fifo/kernel_channel.h" +#include "published/hopper/gh100/dev_ram.h" + +/** + * @brief Verify that the given userd physical address is of the correct size + * + * @param[in] pKernelChannel KernelChannel pointer + * @param[in] userdAddrLo low USERD physical address bits + * @param[in] userdAddrHi high USERD physical address bits + * + * @returns NV_TRUE if the given userd physical address is of the correct size + NV_FALSE otherwise + */ +NvBool +kchannelIsUserdAddrSizeValid_GH100 +( + KernelChannel *pKernelChannel, + NvU32 userdAddrLo, + NvU32 userdAddrHi +) +{ + return ((userdAddrLo & SF_MASK(NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO)) == userdAddrLo) && + ((userdAddrHi & SF_MASK(NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW)) == userdAddrHi); +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c new file mode 100644 index 000000000..7dc36150f --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c @@ -0,0 +1,139 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "published/hopper/gh100/dev_vm.h" +#include "kernel/gpu/mem_mgr/virt_mem_allocator.h" + +/*! + * Checks the USERD and GPFIFO/PushBuffer location attributes + * to make sure that when USERD is in sysmem, GPFIFO or + * PushBuffer is not in vidmem. + * + * @param[in] pKernelFifo KernelFifo pointer + * @param[in] userdAddrSpace USERD address space + * @param[in] pushBuffAddrSpace PushBuffer address space + * @param[in] gpFifoAddrSpace GPFIFO address space + * + */ +NV_STATUS +kfifoCheckChannelAllocAddrSpaces_GH100 +( + KernelFifo *pKernelFifo, + NV_ADDRESS_SPACE userdAddrSpace, + NV_ADDRESS_SPACE pushBuffAddrSpace, + NV_ADDRESS_SPACE gpFifoAddrSpace +) +{ + if ((userdAddrSpace == ADDR_SYSMEM) && + ((pushBuffAddrSpace == ADDR_FBMEM || gpFifoAddrSpace == ADDR_FBMEM))) + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} + +/* + * Returns VA alloc flags to be passed into dmaMapBuffer. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer + * @param[in] engine engine tells us which engine's ctx buffer are we getting the flags for + * @param[out] pflags NvU32* returned alloc flags to pass into dmaMapBuffer. + */ +void +kfifoGetCtxBufferMapFlags_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engine, + NvU32 *pflags +) +{ + if (IS_GR(engine)) + *pflags |= DMA_VA_LIMIT_57B; + + return; +} + +/*! + * @brief Get offset to create GMMU internal MMIO mapping with for access to VF Pages. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer + * @param[in] bPriv Whether PRIV offset or regular VF offset is desired + */ +NvU64 +kfifoGetMmioUsermodeOffset_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvBool bPriv +) +{ + return bPriv ? DRF_BASE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_BASE(NV_VIRTUAL_FUNCTION); +} + +/*! + * @brief Get size of either one of the VF pages, for use with GMMU internal MMIO mapping. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer + * @param[in] bPriv Whether PRIV size or regular VF size is desired + */ +NvU64 +kfifoGetMmioUsermodeSize_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvBool bPriv +) +{ + return bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); +} + +/** + * @brief Returns the maximum possible number of runlists. + * + * Returns a number which represents the limit of any runlistId indexed + * registers in hardware. Does not necessarily return how many runlists are + * active. In the range of 0..kfifoGetMaxNumRunlists() there may be runlists + * that are not used. + * + * @param pGpu + * @param pKernelFifo + */ +NvU32 +kfifoGetMaxNumRunlists_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + + // We use bit-masks of these values + NV_ASSERT(pEngineInfo->maxNumRunlists <= 36); + + return pEngineInfo->maxNumRunlists; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c new file mode 100644 index 000000000..4a1348bcf --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/fifo/usermode_api.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/bus/kern_bus.h" + +#include "class/clc661.h" // HOPPER_USERMODE_A +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED + +NV_STATUS +usrmodeConstructHal_GH100 +( + UserModeApi *pUserModeApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Memory *pMemory = staticCast(pUserModeApi, Memory); + NvU32 hClass = pCallContext->pResourceRef->externalClassId; + NvBool bBar1Mapping = NV_FALSE; + NvBool bPriv = NV_FALSE; + NV_HOPPER_USERMODE_A_PARAMS *pAllocParams = (NV_HOPPER_USERMODE_A_PARAMS*)pParams->pAllocParams; + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + OBJGPU *pGpu = pMemory->pGpu; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 offset = 0; + NvU32 size = 0; + NvU32 attr = 0; + NvU32 attr2 = 0; + + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); + + attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); + + if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL) + { + bBar1Mapping = pAllocParams->bBar1Mapping; + bPriv = pAllocParams->bPriv; + } + + // BAR1/2 is not used on coherent platforms like SHH, so use BAR0 path instead + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + bBar1Mapping = NV_FALSE; + } + + // + // If we are in inst_in_sys mode, BAR1 page tables are not used so we cannot + // support internal MMIO for work submission. + // It is safe to return BAR0 mapping here because USERD cannot be in vidmem + // anyway so UMDs can use this mapping transparently. + // TODO: we should rename bBar1Mapping to accommodate cases where RM + // transparently gives out BAR0 mappings instead. + // + if (bBar1Mapping && pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + NV_ASSERT_OR_RETURN(kbusIsBar1PhysicalModeEnabled(pKernelBus), + NV_ERR_INVALID_STATE); + bBar1Mapping = NV_FALSE; + } + + if (bPriv && pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) + { + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); + + if (bBar1Mapping) + { + offset = kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, bPriv); + size = kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, bPriv); + } + + status = memCreateMemDesc(pGpu, &pMemDesc, bBar1Mapping ? ADDR_SYSMEM : ADDR_REGMEM, + offset, size, attr, attr2); + + if (bBar1Mapping) + { + memdescSetPteKind(pMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); + } + else + { + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); + } + + status = memConstructCommon(pMemory, bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, + 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c index 0f2836df2..8a735c55d 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -103,7 +103,7 @@ kchangrpAllocFaultMethodBuffers_GV100 // Allocate and initialize MEMDESC status = memdescCreate(&(pFaultMthdBuf->pMemDesc), pGpu, bufSizeInBytes, 0, - NV_FALSE, faultBufApert, faultBufAttr, memDescFlags); + NV_TRUE, faultBufApert, faultBufAttr, memDescFlags); if (status != NV_OK) { DBG_BREAKPOINT(); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index 8e0b03ceb..cdb6e8560 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -61,9 +61,12 @@ #include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A #include "class/clc56fsw.h" // AMPERE_CHANNEL_GPFIFO_A #include "class/clc572.h" // PHYSICAL_CHANNEL_GPFIFO +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A +#include "class/clc86fsw.h" // HOPPER_CHANNEL_GPFIFO_A #include "ctrl/ctrl906f.h" #include "ctrl/ctrlc46f.h" +#include "ctrl/ctrlc86f.h" #include "Nvcm.h" #include "libraries/resserv/resserv.h" @@ -533,14 +536,6 @@ kchannelConstruct_IMPL _INTERNALFLAGS, _ECC_ERROR_NOTIFIER_TYPE, pChannelGpfifoParams->internalFlags); - errContextMemDescFlags = MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; - if (gpuIsSriovEnabled(pGpu) && - IS_GFID_VF(callingContextGfid) && - !pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bIsCallingContextVgpuPlugin) - { - errContextMemDescFlags |= MEMDESC_FLAGS_GUEST_ALLOCATED; - } - if (pKernelChannel->errorContextType != ERROR_NOTIFIER_TYPE_NONE) { NV_ASSERT_OK_OR_GOTO(status, @@ -558,6 +553,7 @@ kchannelConstruct_IMPL pChannelGpfifoParams->errorNotifierMem.base, pChannelGpfifoParams->errorNotifierMem.size); } + if (pKernelChannel->eccErrorContextType != ERROR_NOTIFIER_TYPE_NONE) { NV_ASSERT_OK_OR_GOTO(status, @@ -1405,6 +1401,16 @@ CliGetChannelClassInfo pClassInfo->classType = CHANNEL_CLASS_TYPE_GPFIFO; break; } + case HOPPER_CHANNEL_GPFIFO_A: + { + pClassInfo->notifiersMaxCount = NVC86F_NOTIFIERS_MAXCOUNT; + pClassInfo->eventActionDisable = NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + pClassInfo->eventActionSingle = NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE; + pClassInfo->eventActionRepeat = NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; + pClassInfo->rcNotifierIndex = NVC86F_NOTIFIERS_RC; + pClassInfo->classType = CHANNEL_CLASS_TYPE_GPFIFO; + break; + } // // Does not make sense. Call with the class type from the client not the diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c new file mode 100644 index 000000000..f3e542916 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -0,0 +1,1203 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * + * @file kern_fsp_gh100.c + * @brief Provides the implementation for HOPPER chip specific FSP HAL + * interfaces. + */ +#include "gpu/fsp/kern_fsp.h" +#include "gpu/fsp/kern_fsp_retval.h" +#include "gpu/gsp/kernel_gsp.h" + +#include "published/hopper/gh100/dev_fsp_pri.h" +#include "published/hopper/gh100/dev_fsp_addendum.h" +#include "published/hopper/gh100/dev_gc6_island_addendum.h" +#include "published/hopper/gh100/dev_therm.h" +#include "published/hopper/gh100/dev_therm_addendum.h" +#include "os/os.h" +#include "nvRmReg.h" + +#if RMCFG_MODULE_ENABLED (FSP) +#include "hopper/gh100/dev_gsp.h" +#include "gpu/gsp/gsp.h" +#include "gsp/memmap.h" +#include "objfsp.h" +#include "objflcnable.h" +#endif + + +/*! + * @brief Update command queue head and tail pointers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] queueHead Offset to write to command queue head + * @param[in] queueTail Offset to write to command queue tail + */ +void +kfspUpdateQueueHeadTail_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 queueHead, + NvU32 queueTail +) +{ + // The write to HEAD needs to happen after TAIL because it will interrupt FSP + GPU_REG_WR32(pGpu, NV_PFSP_QUEUE_TAIL(FSP_EMEM_CHANNEL_RM), queueTail); + GPU_REG_WR32(pGpu, NV_PFSP_QUEUE_HEAD(FSP_EMEM_CHANNEL_RM), queueHead); +} + +/*! + * @brief Read command queue head and tail pointers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[out] pQueueHead Pointer where we write command queue head + * @param[out] pQueueTail Pointer where we write command queue tail + */ +void +kfspGetQueueHeadTail_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 *pQueueHead, + NvU32 *pQueueTail +) +{ + *pQueueHead = GPU_REG_RD32(pGpu, NV_PFSP_QUEUE_HEAD(FSP_EMEM_CHANNEL_RM)); + *pQueueTail = GPU_REG_RD32(pGpu, NV_PFSP_QUEUE_TAIL(FSP_EMEM_CHANNEL_RM)); +} + +/*! + * @brief Update message queue head and tail pointers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] msgqHead Offset to write to message queue head + * @param[in] msgqTail Offset to write to message queue tail + */ +void +kfspUpdateMsgQueueHeadTail_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 msgqHead, + NvU32 msgqTail +) +{ + GPU_REG_WR32(pGpu, NV_PFSP_MSGQ_TAIL(FSP_EMEM_CHANNEL_RM), msgqTail); + GPU_REG_WR32(pGpu, NV_PFSP_MSGQ_HEAD(FSP_EMEM_CHANNEL_RM), msgqHead); +} + +/*! + * @brief Read message queue head and tail pointers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[out] pMsgqHead Pointer where we write message queue head + * @param[out] pMsgqTail Pointer where we write message queue tail + */ +void +kfspGetMsgQueueHeadTail_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 *pMsgqHead, + NvU32 *pMsgqTail +) +{ + *pMsgqHead = GPU_REG_RD32(pGpu, NV_PFSP_MSGQ_HEAD(FSP_EMEM_CHANNEL_RM)); + *pMsgqTail = GPU_REG_RD32(pGpu, NV_PFSP_MSGQ_TAIL(FSP_EMEM_CHANNEL_RM)); +} + +/*! + * @brief Get size of RM's channel in FSP EMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return RM channel size in bytes + */ +NvU32 +kfspGetRmChannelSize_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + // + // Channel size is hardcoded to 1K for now. Later we will use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + return FSP_EMEM_CHANNEL_RM_SIZE; +} + +/*! + * @brief Retreive SEID based on NVDM type + * + * For now, SEIDs are only needed for use-cases that send multi-packet RM->FSP + * messages. The SEID is used in these cases to route packets to the correct + * task as FSP receives them. Single-packet use-cases are given SEID 0. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] nvdmType NVDM message type + * + * @return SEID corresponding to passed-in NVDM type + */ +NvU8 +kfspNvdmToSeid_GH100 +( + POBJGPU pGpu, + KernelFsp *pKernelFsp, + NvU8 nvdmType +) +{ + NvU8 seid; + + switch (nvdmType) + { + case NVDM_TYPE_INFOROM: + seid = 1; + break; + case NVDM_TYPE_HULK: + default: + seid = 0; + break; + } + + return seid; +} + +/*! + * @brief Create MCTP header + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] som Start of Message flag + * @param[in] eom End of Message flag + * @param[in] tag Message tag + * @param[in] seq Packet sequence number + * + * @return Constructed MCTP header + */ +NvU32 +kfspCreateMctpHeader_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 som, + NvU8 eom, + NvU8 seid, + NvU8 seq +) +{ + return REF_NUM(MCTP_HEADER_SOM, (som)) | + REF_NUM(MCTP_HEADER_EOM, (eom)) | + REF_NUM(MCTP_HEADER_SEID, (seid)) | + REF_NUM(MCTP_HEADER_SEQ, (seq)); +} + +/*! + * @brief Create NVDM payload header + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] nvdmType NVDM type to include in header + * + * @return Constructed NVDM payload header + */ +NvU32 +kfspCreateNvdmHeader_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 nvdmType +) +{ + return REF_DEF(MCTP_MSG_HEADER_TYPE, _VENDOR_PCI) | + REF_DEF(MCTP_MSG_HEADER_VENDOR_ID, _NV) | + REF_NUM(MCTP_MSG_HEADER_NVDM_TYPE, (nvdmType)); +} + +/*! + * @brief Retrieve and validate info in packet's MCTP headers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pBuffer Buffer containing packet + * @param[in] size Size of buffer in bytes + * @param[out] pPacketState Pointer where we write packet state + * @param[out] pTag Pointer where we write packet's MCTP tag + * + * @return NV_OK or NV_ERR_INVALID_DATA + */ +NV_STATUS +kfspGetPacketInfo_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size, + MCTP_PACKET_STATE *pPacketState, + NvU8 *pTag +) +{ + NvU32 mctpHeader; + NvU8 som, eom; + NV_STATUS status = NV_OK; + + mctpHeader = ((NvU32 *)pBuffer)[0]; + + som = REF_VAL(MCTP_HEADER_SOM, mctpHeader); + eom = REF_VAL(MCTP_HEADER_EOM, mctpHeader); + + if ((som == 1) && (eom == 0)) + { + *pPacketState = MCTP_PACKET_STATE_START; + } + else if ((som == 0) && (eom == 1)) + { + *pPacketState = MCTP_PACKET_STATE_END; + } + else if ((som == 1) && (eom == 1)) + { + *pPacketState = MCTP_PACKET_STATE_SINGLE_PACKET; + } + else + { + *pPacketState = MCTP_PACKET_STATE_INTERMEDIATE; + } + + if ((*pPacketState == MCTP_PACKET_STATE_START) || + (*pPacketState == MCTP_PACKET_STATE_SINGLE_PACKET)) + { + // Packet contains payload header, check it + status = kfspValidateMctpPayloadHeader_HAL(pGpu, pKernelFsp, pBuffer, size); + } + + *pTag = REF_VAL(MCTP_HEADER_TAG, mctpHeader); + + return status; +} + +/*! + * @brief Validate packet's MCTP payload header + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pBuffer Buffer containing packet + * @param[in] size Size of buffer in bytes + * + * @return NV_OK or NV_ERR_INVALID_DATA + */ +NV_STATUS +kfspValidateMctpPayloadHeader_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 mctpPayloadHeader; + NvU16 mctpVendorId; + NvU8 mctpMessageType; + + mctpPayloadHeader = ((NvU32 *)pBuffer)[1]; + + mctpMessageType = REF_VAL(MCTP_MSG_HEADER_TYPE, mctpPayloadHeader); + if (mctpMessageType != MCTP_MSG_HEADER_TYPE_VENDOR_PCI) + { + NV_PRINTF(LEVEL_ERROR, "Invalid MCTP Message type 0x%0x, expecting 0x7e (Vendor Defined PCI)\n", + mctpMessageType); + return NV_ERR_INVALID_DATA; + } + + mctpVendorId = REF_VAL(MCTP_MSG_HEADER_VENDOR_ID, mctpPayloadHeader); + if (mctpVendorId != MCTP_MSG_HEADER_VENDOR_ID_NV) + { + NV_PRINTF(LEVEL_ERROR, "Invalid PCI Vendor Id 0x%0x, expecting 0x10de (Nvidia)\n", + mctpVendorId); + return NV_ERR_INVALID_DATA; + } + + if (size < (sizeof(MCTP_HEADER) + sizeof(NvU8))) + { + NV_PRINTF(LEVEL_ERROR, "Packet doesn't contain NVDM type in payload header\n"); + return NV_ERR_INVALID_DATA; + } + + return NV_OK; +} + +/*! + * @brief Process NVDM payload + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pBuffer Buffer containing packet data + * @param[in] Size Buffer size + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +kfspProcessNvdmMessage_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU8 nvdmType; + NV_STATUS status = NV_OK; + + nvdmType = pBuffer[0]; + + switch (nvdmType) + { + case NVDM_TYPE_FSP_RESPONSE: + case NVDM_TYPE_SMBPBI: + status = kfspProcessCommandResponse_HAL(pGpu, pKernelFsp, pBuffer, size); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unknown or unsupported NVDM type received: 0x%0x\n", + nvdmType); + status = NV_ERR_NOT_SUPPORTED; + break; + } + + return status; +} + +/*! + * @brief Process FSP command response + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pBuffer Buffer containing packet data + * @param[in] Size Buffer size + * + * @return NV_OK or NV_ERR_INVALID_DATA + */ +NV_STATUS +kfspProcessCommandResponse_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size +) +{ + NVDM_PAYLOAD_COMMAND_RESPONSE *pCmdResponse; + NvU32 headerSize = sizeof(NvU8); // NVDM type + NV_STATUS status = NV_OK; + + if (size < (headerSize + sizeof(NVDM_PAYLOAD_COMMAND_RESPONSE))) + { + NV_PRINTF(LEVEL_ERROR, "Expected FSP command response, but packet is not big enough for payload. Size: 0x%0x\n", size); + return NV_ERR_INVALID_DATA; + } + + pCmdResponse = (NVDM_PAYLOAD_COMMAND_RESPONSE *)&(pBuffer[1]); + + NV_PRINTF(LEVEL_INFO, "Received FSP command response. Task ID: 0x%0x Command type: 0x%0x Error code: 0x%0x\n", + pCmdResponse->taskId, pCmdResponse->commandNvdmType, pCmdResponse->errorCode); + + status = kfspErrorCode2NvStatusMap_HAL(pGpu, pKernelFsp, pCmdResponse->errorCode); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Last command was processed by FSP successfully!\n"); + } + else if (status != NV_ERR_OBJECT_NOT_FOUND) + { + + NV_PRINTF(LEVEL_ERROR, "FSP response reported error. Task ID: 0x%0x Command type: 0x%0x Error code: 0x%0x\n", + pCmdResponse->taskId, pCmdResponse->commandNvdmType, pCmdResponse->errorCode); + } + + return status; +} + +/*! + * @brief Configure EMEMC for RM's queue in FSP EMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] offset Offset to write to EMEMC in DWORDS + * @param[in] bAincw Flag to set auto-increment on writes + * @param[in] bAincr Flag to set auto-increment on reads + * + * @return NV_OK + */ +NV_STATUS +kfspConfigEmemc_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 offset, + NvBool bAincw, + NvBool bAincr +) +{ + NvU32 offsetBlks, offsetDwords; + NvU32 reg32 = 0; + + // + // EMEMC offset is encoded in terms of blocks (64 DWORDS) and DWORD offset + // within a block, so calculate each. + // + offsetBlks = offset / 64; + offsetDwords = offset % 64; + + reg32 = FLD_SET_DRF_NUM(_PFSP, _EMEMC, _OFFS, offsetDwords, reg32); + reg32 = FLD_SET_DRF_NUM(_PFSP, _EMEMC, _BLK, offsetBlks, reg32); + + if (bAincw) + { + reg32 = FLD_SET_DRF(_PFSP, _EMEMC, _AINCW, _TRUE, reg32); + } + if (bAincr) + { + reg32 = FLD_SET_DRF(_PFSP, _EMEMC, _AINCR, _TRUE, reg32); + } + + GPU_REG_WR32(pGpu, NV_PFSP_EMEMC(FSP_EMEM_CHANNEL_RM), reg32); + return NV_OK; +} + +/*! + * @brief Write data in buffer to RM channel in FSP's EMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pBuffer Buffer with data to write to EMEM + * @param[in] Size Size of buffer in bytes, assumed DWORD aligned + * + * @return NV_OK + */ +NV_STATUS +kfspWriteToEmem_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 i, reg32; + NvU32 ememOffsetEnd; + + // + // First configure EMEMC, RM always writes 0 to the offset, which is OK + // because RM's channel starts at 0 on GH100 and we always start from the + // beginning for each packet. It should be improved later to use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + kfspConfigEmemc_HAL(pGpu, pKernelFsp, 0, NV_TRUE, NV_FALSE); + + NV_PRINTF(LEVEL_INFO, "About to send data to FSP, ememcOff=0, size=0x%x\n", size); + if (!NV_IS_ALIGNED(size, sizeof(NvU32))) + { + NV_PRINTF(LEVEL_WARNING, "Size=0x%x is not DWORD-aligned, data will be truncated!\n", size); + } + + // Now write to EMEMD + for (i = 0; i < (size / 4); i++) + { + GPU_REG_WR32(pGpu, NV_PFSP_EMEMD(FSP_EMEM_CHANNEL_RM), ((NvU32*)(void*)pBuffer)[i]); + } + + // Sanity check offset. If this fails, the autoincrement did not work + reg32 = GPU_REG_RD32(pGpu, NV_PFSP_EMEMC(FSP_EMEM_CHANNEL_RM)); + ememOffsetEnd = DRF_VAL(_PFSP, _EMEMC, _OFFS, reg32); + + // Blocks are 64 DWORDS + ememOffsetEnd += DRF_VAL(_PFSP, _EMEMC, _BLK, reg32) * 64; + NV_PRINTF(LEVEL_INFO, "After sending data, ememcOff = 0x%x\n", ememOffsetEnd); + + NV_ASSERT((ememOffsetEnd) == (size / sizeof(NvU32))); + return NV_OK; +} + +/*! + * @brief Read data to buffer from RM channel in FSP's EMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in/out] pBuffer Buffer where we copy data from EMEM + * @param[in] size Size to read in bytes, assumed DWORD aligned + * + * @return NV_OK + */ +NV_STATUS +kfspReadFromEmem_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 i, reg32; + NvU32 ememOffsetEnd; + + // + // First configure EMEMC, RM always writes 0 to the offset, which is OK + // because RM's channel starts at 0 on GH100 and we always start from the + // beginning for each packet. It should be improved later to use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + kfspConfigEmemc_HAL(pGpu, pKernelFsp, 0, NV_FALSE, NV_TRUE); + + NV_PRINTF(LEVEL_INFO, "About to read data from FSP, ememcOff=0, size=0x%x\n", size); + if (!NV_IS_ALIGNED(size, sizeof(NvU32))) + { + NV_PRINTF(LEVEL_WARNING, "Size=0x%x is not DWORD-aligned, data will be truncated!\n", size); + } + + // Now read from EMEMD + for (i = 0; i < (size / 4); i++) + { + ((NvU32*)(void*)pBuffer)[i] = GPU_REG_RD32(pGpu, NV_PFSP_EMEMD(FSP_EMEM_CHANNEL_RM)); + } + + // Sanity check offset. If this fails, the autoincrement did not work + reg32 = GPU_REG_RD32(pGpu, NV_PFSP_EMEMC(FSP_EMEM_CHANNEL_RM)); + ememOffsetEnd = DRF_VAL(_PFSP, _EMEMC, _OFFS, reg32); + + // Blocks are 64 DWORDS + ememOffsetEnd += DRF_VAL(_PFSP, _EMEMC, _BLK, reg32) * 64; + NV_PRINTF(LEVEL_INFO, "After reading data, ememcOff = 0x%x\n", ememOffsetEnd); + + NV_ASSERT((ememOffsetEnd) == (size / sizeof(NvU32))); + return NV_OK; +} + +NV_STATUS +kfspWaitForSecureBoot_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + + // + // Polling for FSP boot complete + // In Hopper, Bootfsm triggers FSP execution out of chip reset. + // FSP writes 0xFF value in NV_THERM_I2CS_SCRATCH register after completion of boot + // FBFalcon training during devinit alone takes 2 seconds, up to 3 on HBM3, + // but the default threadstate timeout on windows is 1800 ms. Increase to 4 seconds + // for this wait to match MODS GetGFWBootTimeoutMs. + // For flags, this must not timeout due to aforementioned threadstate timeout, + // and we must not use the GPU TMR since it is inaccessible. + // + gpuSetTimeout(pGpu, NV_MAX(gpuScaleTimeout(pGpu, 4000000), pGpu->timeoutData.defaultus), + &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + + while(!GPU_FLD_TEST_DRF_DEF(pGpu, _THERM_I2CS_SCRATCH, _FSP_BOOT_COMPLETE, _STATUS, _SUCCESS)) + { + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "Timout while polling for FSP boot complete I2CS_SCRATCH : %x\n", + GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE)); + break; + } + } + + return status; +} + +/*! + * @brief Check if GSP-FMC Inst_in_sys ucode needs to be booted. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_TRUE if GSP Inst_in_sys FMC needs to be booted, or NV_FALSE otherwise + */ +NvBool +kfspCheckGspSecureScratch_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + + return NV_FALSE; +} + +static const BINDATA_ARCHIVE * +kfspGetGspUcodeArchive +( + POBJGPU pGpu, + KernelFsp *pKernelFsp +) +{ + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + NV_PRINTF(LEVEL_ERROR, "Loading GSP-RM image using FSP.\n"); + if (kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp)) + { + return kgspGetBinArchiveGspRmCcGfwDebugSigned_HAL(pKernelGsp); + } + else + { + return kgspGetBinArchiveGspRmCcGfwProdSigned_HAL(pKernelGsp); + } + } +#if RMCFG_MODULE_ENABLED (GSP) + else + { + Gsp *pGsp = GPU_GET_GSP(pGpu); + + NV_PRINTF(LEVEL_INFO, "Loading GSP image for monolithic RM using FSP.\n"); + if (gspIsDebugModeEnabled_HAL(pGpu, pGsp)) + { + if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) + { + return gspGetBinArchiveGspCcInstInSysGfwDebugSigned_HAL(pGsp); + } + + if (pGsp->getProperty(pGsp, PDB_PROP_GSP_DISABLE_RESIDENT_IMAGE)) + { + // + // Non Resident (GspCcGfw)Image will have just the FMC in it. + // When GSP-RM is not enabled, we will need to load GSP RM Proxy. + // We will prepare the GSP-Proxy Image in SYSMEM And pass that + // into to the FMC. FMC will then boot the RM Proxy. + // + NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + return gspGetBinArchiveGspCcGfwDebugSigned_HAL(pGsp); + } + else + { + return gspGetBinArchiveGspCcResidentGfwDebugSigned_HAL(pGsp); + } + } + else + { + if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) + { + return gspGetBinArchiveGspCcInstInSysGfwProdSigned_HAL(pGsp); + } + + if (!pGsp->getProperty(pGsp, PDB_PROP_GSP_DISABLE_RESIDENT_IMAGE)) + { + return gspGetBinArchiveGspCcResidentGfwProdSigned_HAL(pGsp); + } + else + { + // There is no production signed non-resident image yet + NV_PRINTF(LEVEL_ERROR, "Cannot load GSP non-resident prod image on monolithic RM.\n"); + return NULL; + } + } + } +#endif + + // + // It does not make sense to boot monolithic RM when physical FSP module + // does not exist + // + return NULL; +} + +static NV_STATUS +kfspGetGspBootArgs +( + POBJGPU pGpu, + KernelFsp *pKernelFsp, + RmPhysAddr *pBootArgsGspSysmemOffset +) +{ + NV_STATUS status = NV_OK; + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + // Ensure bootArgs have been set up before + NV_ASSERT_OR_RETURN(pKernelGsp->pGspFmcArgumentsCached != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(memdescGetAddressSpace(pKernelGsp->pGspFmcArgumentsDescriptor) == ADDR_SYSMEM, NV_ERR_INVALID_STATE); + *pBootArgsGspSysmemOffset = memdescGetPhysAddr(pKernelGsp->pGspFmcArgumentsDescriptor, AT_GPU, 0); + } + + return status; +} + + +/*! + * @brief Set up GSP-FMC and boot args for FSP command + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK, or error if failed + */ +static NV_STATUS +kfspSetupGspImages +( + POBJGPU pGpu, + KernelFsp *pKernelFsp, + NVDM_PAYLOAD_COT *pCotPayload +) +{ + NV_STATUS status = NV_OK; + + const BINDATA_ARCHIVE *pBinArchive; + PBINDATA_STORAGE pGspImage; + PBINDATA_STORAGE pGspImageHash; + PBINDATA_STORAGE pGspImageSignature; + PBINDATA_STORAGE pGspImagePublicKey; + NvU32 pGspImageSize; + NvU32 pGspImageMapSize; + NvP64 pVaKernel = NULL; + NvP64 pPrivKernel = NULL; + + // Detect the mode of operation for GSP and fetch the right image to boot + pBinArchive = kfspGetGspUcodeArchive(pGpu, pKernelFsp); + if (pBinArchive == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto failed; + } + + // Set up the structures to send GSP-FMC + pGspImage = (PBINDATA_STORAGE)bindataArchiveGetStorage(pBinArchive, "ucode_image"); + pGspImageHash = (PBINDATA_STORAGE)bindataArchiveGetStorage(pBinArchive, "ucode_hash"); + pGspImageSignature = (PBINDATA_STORAGE)bindataArchiveGetStorage(pBinArchive, "ucode_sig"); + pGspImagePublicKey = (PBINDATA_STORAGE)bindataArchiveGetStorage(pBinArchive, "ucode_pkey"); + + if ((pGspImage == NULL) || (pGspImageHash == NULL) || + (pGspImageSignature == NULL) || (pGspImagePublicKey == NULL)) + { + status = NV_ERR_NOT_SUPPORTED; + goto failed; + } + + pGspImageSize = bindataGetBufferSize(pGspImage); + pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); + + status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + status = memdescAlloc(pKernelFsp->pGspFmcMemdesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + status = memdescMap(pKernelFsp->pGspFmcMemdesc, 0, pGspImageMapSize, NV_TRUE, + NV_PROTECT_READ_WRITE, &pVaKernel, &pPrivKernel); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + portMemSet(pVaKernel, 0, pGspImageMapSize); + + status = bindataWriteToBuffer(pGspImage, pVaKernel, pGspImageSize); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + // Clean up CPU side resources since they are not needed anymore + memdescUnmap(pKernelFsp->pGspFmcMemdesc, NV_TRUE, 0, pVaKernel, pPrivKernel); + + pCotPayload->gspFmcSysmemOffset = memdescGetPhysAddr(pKernelFsp->pGspFmcMemdesc, AT_GPU, 0); + + status = bindataWriteToBuffer(pGspImageHash, (NvU8*)pCotPayload->hash384, sizeof(pCotPayload->hash384)); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + status = bindataWriteToBuffer(pGspImageSignature, (NvU8*)pCotPayload->signature, sizeof(pCotPayload->signature)); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + status = bindataWriteToBuffer(pGspImagePublicKey, (NvU8*)pCotPayload->publicKey, sizeof(pCotPayload->publicKey)); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + // Set up boot args based on the mode of operation + status = kfspGetGspBootArgs(pGpu, pKernelFsp, &pCotPayload->gspBootArgsSysmemOffset); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + return NV_OK; + +failed: + if (pKernelFsp->pGspFmcMemdesc != NULL) + { + memdescDestroy(pKernelFsp->pGspFmcMemdesc); + pKernelFsp->pGspFmcMemdesc = NULL; + } + + return status; +} + +static NV_STATUS +_kfspCheckGspBootStatus +( + POBJGPU pGpu, + KernelFsp *pKernelFsp +) +{ +#if RMCFG_MODULE_ENABLED (FSP) + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + Gsp *pGsp = GPU_GET_GSP(pGpu); + Falcon *pFlcn = ENG_GET_FLCN(pGsp); + + pFlcn->bBootstrapped = NV_TRUE; + + // In Inst_in_sys mode GSP-FMC will write status to NV_PGSP_MAILBOX(0). + if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) + { + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while(FLD_TEST_DRF_NUM(_PGSP, _MAILBOX, _DATA, GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS , GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)))) + { + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP Inst_in_sys ucode to boot\n"); + DBG_BREAKPOINT(); + break; + } + osSpinLoop(); + } + // Read GSP mailbox to check if it is booted successfully. + if (GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)) != GSP_INST_IN_SYS_COMPLETION_STATUS_OK) + { + NV_PRINTF(LEVEL_ERROR, "GSP Inst_in_sys ucode boot failed with GSP status 0x%x\n", GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0))); + DBG_BREAKPOINT(); + } + return status; + } + + // Ensure priv lockdown is released before polling interrupts + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + if (flcnIsRiscvLockdownReleased_HAL(pGpu, pFlcn)) + { + status = NV_OK; + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for priv lockdown release.\n"); + DBG_BREAKPOINT(); + break; + } + osSpinLoop(); + } while (1); + + // Ensure GSP can send back init ack interrupt to CPU + do + { + gspServiceEarlyInterrupt_HAL(pGpu, pGsp); + + if (pFlcn->bOSReady) + { + status = NV_OK; + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP ucode to boot.\n"); + DBG_BREAKPOINT(); + break; + } + osSpinLoop(); + } while (1); + + return status; +#else + // On GSP-RM, the kgsp code path will check for GSP boot status + return NV_OK; +#endif +} + +/*! + * @brief Dump debug registers for FSP + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK, or error if failed + */ +void +kfspDumpDebugState_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0) = 0x%x\n", + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0))); + NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1) = 0x%x\n", + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1))); + NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2) = 0x%x\n", + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2))); + NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3) = 0x%x\n", + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3))); +} + +/*! + * @brief Checks whether GSP_FMC is enforced on this + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_TRUE, if GspFmc is enforced. + */ +NvBool +kfspGspFmcIsEnforced_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + return NV_TRUE; +} + +/*! + * @brief Send GSP-FMC and FRTS info to FSP + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK, or error if failed + */ +NV_STATUS +kfspSendBootCommands_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; + NvU32 frtsSize = 0; + NVDM_PAYLOAD_COT *pCotPayload = NULL; + NvP64 pVaKernel = NULL; + NvP64 pPrivKernel = NULL; + + + if (!IS_EMULATION(pGpu) && !IS_SILICON(pGpu)) + { + // + // FSP managment partition is only enabled when secure boot is enabled + // on silicon and certain emulation configs + // + return NV_OK; + } + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_IS_MISSING)) + { + if (IS_SILICON(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "RM cannot boot with FSP missing on silicon.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + NV_PRINTF(LEVEL_WARNING, "Secure boot is disabled due to missing FSP.\n"); + return NV_OK; + } + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK)) + { + NV_PRINTF(LEVEL_ERROR, "Cannot send FSP boot commands multiple times.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // Confirm FSP secure boot partition is done + status = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP secure boot partition timed out.\n"); + return status; + } + + // Enforce GSP-FMC can only be booted by FSP on silicon. + if (IS_SILICON(pGpu) && + kfspGspFmcIsEnforced_HAL(pGpu, pKernelFsp) && + pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) + { + NV_PRINTF(LEVEL_ERROR, "Chain-of-trust (GSP-FMC) cannot be disabled on silicon.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM) && + pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM) && + pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) + { + NV_PRINTF(LEVEL_WARNING, "Chain-of-trust is disabled via regkey\n"); + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_TRUE); + return NV_OK; + } + + pCotPayload = portMemAllocNonPaged(sizeof(NVDM_PAYLOAD_COT)); + portMemSet(pCotPayload, 0, sizeof(NVDM_PAYLOAD_COT)); + + frtsSize = NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K << 12; + NV_ASSERT(frtsSize != 0); + + pCotPayload->version = 1; + pCotPayload->size = sizeof(NVDM_PAYLOAD_COT); + + // Set up sysmem for FRTS copy + if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM)) + { + status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + status = memdescAlloc(pKernelFsp->pSysmemFrtsMemdesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + // Set up a kernel mapping for future use in RM + status = memdescMap(pKernelFsp->pSysmemFrtsMemdesc, 0, frtsSize, NV_TRUE, + NV_PROTECT_READ_WRITE, &pVaKernel, &pPrivKernel); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + portMemSet(pVaKernel, 0, frtsSize); + + memdescSetKernelMapping(pKernelFsp->pSysmemFrtsMemdesc, pVaKernel); + memdescSetKernelMappingPriv(pKernelFsp->pSysmemFrtsMemdesc, pPrivKernel); + + pCotPayload->frtsSysmemOffset = memdescGetPhysAddr(pKernelFsp->pSysmemFrtsMemdesc, AT_GPU, 0); + pCotPayload->frtsSysmemSize = frtsSize; + } + + // Set up vidmem for FRTS copy + if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM)) + { + // + // Since we are very early in the boot path, we cannot know how much + // vidmem reservation RM will need at the end of FB. For now use an + // estimated value to leave enough space for buffers such as vga + // workspace, BAR instance blocks and BAR page directories which will + // be allocated at the end of FB. If more reservations are added in the + // future, this code will need to be updated. + // Bug 200711957 has more info and tracks longer term improvements. + // + const NvU32 ESTIMATED_RESERVE_FB = 0x200000; + + // Offset from end of FB to be used by FSP + pCotPayload->frtsVidmemOffset = ESTIMATED_RESERVE_FB; + pCotPayload->frtsVidmemSize = frtsSize; + } + + pCotPayload->gspFmcSysmemOffset = (NvU64)-1; + pCotPayload->gspBootArgsSysmemOffset = (NvU64)-1; + + // Set up GSP-FMC for FSP to boot GSP + if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) + { + status = kfspSetupGspImages(pGpu, pKernelFsp, pCotPayload); + if (status!= NV_OK) + { + goto failed; + } + + } + + status = kfspSendAndReadMessage(pGpu, pKernelFsp, (NvU8 *)pCotPayload, + sizeof(NVDM_PAYLOAD_COT), NVDM_TYPE_COT, NULL, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Sent following content to FSP: \n"); + NV_PRINTF(LEVEL_ERROR, "version=0x%x, size=0x%x, gspFmcSysmemOffset=0x%llx\n", + pCotPayload->version, pCotPayload->size, pCotPayload->gspFmcSysmemOffset); + NV_PRINTF(LEVEL_ERROR, "frtsSysmemOffset=0x%llx, frtsSysmemSize=0x%x\n", + pCotPayload->frtsSysmemOffset, pCotPayload->frtsSysmemSize); + NV_PRINTF(LEVEL_ERROR, "frtsVidmemOffset=0x%llx, frtsVidmemSize=0x%x\n", + pCotPayload->frtsVidmemOffset, pCotPayload->frtsVidmemSize); + NV_PRINTF(LEVEL_ERROR, "gspBootArgsSysmemOffset=0x%llx\n", + pCotPayload->gspBootArgsSysmemOffset); + + goto failed; + } + + // + // Need to check if GSP has been booted here so that we can skip booting + // GSP again later in ACR code path. On GSP-RM, the calling code path (kgsp) + // will check for GSP boot status. + // + if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC) && + !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + status = _kfspCheckGspBootStatus(pGpu, pKernelFsp); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + } + + // Set property to indicate we only support secure boot at this point + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_TRUE); + pKernelFsp->pCotPayload = pCotPayload; + return NV_OK; + +failed: + NV_PRINTF(LEVEL_ERROR, "FSP boot cmds failed. RM cannot boot.\n"); + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + + if (pKernelFsp->pSysmemFrtsMemdesc != NULL) + { + memdescDestroy(pKernelFsp->pSysmemFrtsMemdesc); + pKernelFsp->pSysmemFrtsMemdesc = NULL; + } + + portMemFree(pCotPayload); + + return status; +} + +NV_STATUS +kfspErrorCode2NvStatusMap_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU32 errorCode +) +{ + switch (errorCode) + { + case FSP_OK: + return NV_OK; + + case FSP_ERR_IFR_FILE_NOT_FOUND: + return NV_ERR_OBJECT_NOT_FOUND; + + case FSP_ERR_IFS_ERR_INVALID_STATE: + case FSP_ERR_IFS_ERR_INVALID_DATA: + return NV_ERR_INVALID_DATA; + + default: + return NV_ERR_GENERIC; + } +} diff --git a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c new file mode 100644 index 000000000..1d37587dd --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c @@ -0,0 +1,609 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /*! + * + * @file kern_fsp.c + * @brief Provides all kernel side interfaces for tracking the FSP state, + * submitting commands and parsing replies needed from the CPU. + */ +#include "gpu/gpu.h" +#include "gpu/fsp/kern_fsp.h" +#include "nvrm_registry.h" + +#if RMCFG_MODULE_ENABLED (GSP) +#include "gpu/gsp/gsp.h" +#include "objflcnable.h" +#endif + +/*! +* Local object related functions +*/ +static void kfspInitRegistryOverrides(OBJGPU *, KernelFsp *); + +static NV_STATUS kfspReadMessage(OBJGPU *pGpu, KernelFsp *pKernelFsp, NvU8 *pPayloadBuffer, NvU32 payloadBufferSize); + +NV_STATUS +kfspConstructEngine_IMPL(OBJGPU *pGpu, KernelFsp *pKernelFsp, ENGDESCRIPTOR engDesc) +{ + + // Initialize based on registry keys + kfspInitRegistryOverrides(pGpu, pKernelFsp); + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_IS_MISSING)) + { + NV_PRINTF(LEVEL_WARNING, "KernelFsp is disabled\n"); + return NV_ERR_OBJECT_NOT_FOUND; + } + return NV_OK; +} + +/*! + * Initialize all registry overrides for this object + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelFsp KernelFsp object pointer + */ +static void +kfspInitRegistryOverrides +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NvU32 data = 0; + + if (((osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_FSP, &data) == NV_OK) && + (data == NV_REG_STR_RM_DISABLE_FSP_YES) && IS_EMULATION(pGpu)) || + IS_FMODEL(pGpu)) + { + // + // Force disable FSP engine, used only on emulation because some + // emulation netlists stub out FSP but leave the engine in PTOP + // + NV_PRINTF(LEVEL_WARNING, "FSP disabled due to regkey override.\n"); + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_IS_MISSING, NV_TRUE); + } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_COT_CMD, &data) == NV_OK) + { + // Assume non-zero value only has NV_REG_STR_RM_DISABLE_COT_CMD_YES + if (data & DRF_SHIFTMASK(NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_SYSMEM)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM, NV_TRUE); + } + + if (data & DRF_SHIFTMASK(NV_REG_STR_RM_DISABLE_COT_CMD_FRTS_VIDMEM)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM, NV_TRUE); + } + + if (data & DRF_SHIFTMASK(NV_REG_STR_RM_DISABLE_COT_CMD_GSPFMC)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC, NV_TRUE); + } + } + + // Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM, NV_TRUE); + } +} + + +/*! + * @brief FSP State Initialization. + * + * Initializes all software states including allocating the dbg memory surface + * and the initialization of FSP HAL layer. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelFsp FSP object pointer + * + * @return 'NV_OK' if state-initialization was successful. + * @return other bubbles up errors from @ref kfspStateInitHal_HAL on failure + */ +NV_STATUS +kfspStateInitUnlocked_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + return NV_OK; +} + +/*! + * @brief Destroy FSP state + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelFsp FSP object pointer + * + * @return 'NV_OK' if the FSP state was successfully destroyed + */ +void +kfspStateDestroy_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + if (pKernelFsp->pCotPayload != NULL) + { + portMemFree(pKernelFsp->pCotPayload); + pKernelFsp->pCotPayload = NULL; + } + + if (pKernelFsp->pSysmemFrtsMemdesc != NULL) + { + memdescUnmap(pKernelFsp->pSysmemFrtsMemdesc, NV_TRUE, 0, + memdescGetKernelMapping(pKernelFsp->pSysmemFrtsMemdesc), + memdescGetKernelMappingPriv(pKernelFsp->pSysmemFrtsMemdesc)); + memdescFree(pKernelFsp->pSysmemFrtsMemdesc); + memdescDestroy(pKernelFsp->pSysmemFrtsMemdesc); + pKernelFsp->pSysmemFrtsMemdesc = NULL; + } + + if (pKernelFsp->pVidmemFrtsMemdesc != NULL) + { + memdescFree(pKernelFsp->pVidmemFrtsMemdesc); + memdescDestroy(pKernelFsp->pVidmemFrtsMemdesc); + pKernelFsp->pVidmemFrtsMemdesc = NULL; + } + + if (pKernelFsp->pGspFmcMemdesc != NULL) + { + memdescFree(pKernelFsp->pGspFmcMemdesc); + memdescDestroy(pKernelFsp->pGspFmcMemdesc); + pKernelFsp->pGspFmcMemdesc = NULL; + } + + if (pKernelFsp->pGspBootArgsMemdesc != NULL) + { + memdescFree(pKernelFsp->pGspBootArgsMemdesc); + memdescDestroy(pKernelFsp->pGspBootArgsMemdesc); + pKernelFsp->pGspBootArgsMemdesc = NULL; + } + +} + +/*! + * @brief Override default behaviour of reset + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelFsp FSP object pointer + * + * @return + */ +void +kfspSecureReset_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + // Should not reset FSP + NV_PRINTF(LEVEL_ERROR, "FSP cannot be reset by CPU.\n"); + NV_ASSERT(0); + return; +} + + +/*! + * @brief Check if FSP RM command queue is empty + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_TRUE if queue is empty, NV_FALSE otherwise + */ +NvBool +kfspIsQueueEmpty_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NvU32 cmdqHead, cmdqTail; + + kfspGetQueueHeadTail_HAL(pGpu, pKernelFsp, &cmdqHead, &cmdqTail); + + // FSP will set QUEUE_HEAD = TAIL after each packet is received + return (cmdqHead == cmdqTail); +} + +/*! + * @brief Wait for FSP RM command queue to be empty + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK, or NV_ERR_TIMEOUT + */ +NV_STATUS +kfspPollForQueueEmpty_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + RMTIMEOUT timeout; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (!kfspIsQueueEmpty(pGpu, pKernelFsp)) + { + // + // For now we assume that any response from FSP before RM message send is complete + // indicates an error and we should abort. + // + if (!kfspIsMsgQueueEmpty(pGpu, pKernelFsp)) + { + kfspReadMessage(pGpu, pKernelFsp, NULL, 0); + NV_PRINTF(LEVEL_ERROR, "Received error message from FSP while waiting for CMDQ to be empty.\n"); + return NV_ERR_GENERIC; + } + + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for FSP command queue to be empty.\n"); + return NV_ERR_TIMEOUT; + } + osSpinLoop(); + } + + return NV_OK; +} + +/*! + * @brief Check if FSP RM message queue is empty + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_TRUE if queue is empty, NV_FALSE otherwise + */ +NvBool +kfspIsMsgQueueEmpty_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NvU32 msgqHead, msgqTail; + + kfspGetMsgQueueHeadTail_HAL(pGpu, pKernelFsp, &msgqHead, &msgqTail); + return (msgqHead == msgqTail); +} + +/*! + * @brief Poll for response from FSP via RM message queue + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK, or NV_ERR_TIMEOUT + */ +NV_STATUS +kfspPollForResponse_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + // Poll for message queue to wait for FSP's reply + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (kfspIsMsgQueueEmpty(pGpu, pKernelFsp)) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "FSP command timed out\n"); + return NV_ERR_TIMEOUT; + } + + osSpinLoop(); + } + + return status; +} + +/*! + * @brief Read and process message from FSP via RM message queue. + * + * Supports both single and multi-packet message. For multi-packet messages, this + * loops until all packets are received, polling at each iteration for the next + * packet to come in. If a buffer is provided, the message payload will be + * returned there. + * + * @note: For multi-packet messages, a buffer in which the message payload will + * be reconstructed must be provided. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in/out] pPayloadBuffer Buffer in which to return message payload + * @param[in] payloadBufferSize Payload buffer size + * + * @return NV_OK, NV_ERR_INVALID_DATA, NV_ERR_INSUFFICIENT_RESOURCES, or errors + * from functions called within + */ +static NV_STATUS +kfspReadMessage +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pPayloadBuffer, + NvU32 payloadBufferSize +) +{ + NvU8 *pPacketBuffer; + NV_STATUS status; + NvU32 totalPayloadSize = 0; + MCTP_PACKET_STATE packetState = MCTP_PACKET_STATE_START; + + if (kfspIsMsgQueueEmpty(pGpu, pKernelFsp)) + { + NV_PRINTF(LEVEL_WARNING, "Tried to read FSP response but MSG queue is empty\n"); + return NV_OK; + } + + pPacketBuffer = portMemAllocNonPaged(kfspGetRmChannelSize_HAL(pGpu, pKernelFsp)); + + while ((packetState != MCTP_PACKET_STATE_END) && (packetState != MCTP_PACKET_STATE_SINGLE_PACKET)) + { + NvU32 msgqHead, msgqTail; + NvU32 packetSize; + NvU32 curPayloadSize; + NvU8 curHeaderSize; + NvU8 tag; + + // Wait for next packet + status = kfspPollForResponse(pGpu, pKernelFsp); + if (status != NV_OK) + { + goto done; + } + + kfspGetMsgQueueHeadTail_HAL(pGpu, pKernelFsp, &msgqHead, &msgqTail); + + // Tail points to last DWORD in packet, not DWORD immediately following it + packetSize = (msgqTail - msgqHead) + sizeof(NvU32); + + if ((packetSize < sizeof(NvU32)) || + (packetSize > kfspGetRmChannelSize_HAL(pGpu, pKernelFsp))) + { + NV_PRINTF(LEVEL_ERROR, "FSP response packet is invalid size: size=0x%x bytes\n", packetSize); + status = NV_ERR_INVALID_DATA; + goto done; + } + + kfspReadFromEmem_HAL(pGpu, pKernelFsp, pPacketBuffer, packetSize); + + status = kfspGetPacketInfo_HAL(pGpu, pKernelFsp, pPacketBuffer, packetSize, &packetState, &tag); + if (status != NV_OK) + { + goto done; + } + + if ((packetState == MCTP_PACKET_STATE_START) || (packetState == MCTP_PACKET_STATE_SINGLE_PACKET)) + { + // Packet contains payload header + curHeaderSize = sizeof(MCTP_HEADER); + } + else + { + curHeaderSize = sizeof(NvU32); + } + + curPayloadSize = packetSize - curHeaderSize; + + if ((pPayloadBuffer == NULL) && (packetState != MCTP_PACKET_STATE_SINGLE_PACKET)) + { + NV_PRINTF(LEVEL_ERROR, "No buffer provided when receiving multi-packet message. Buffer needed to reconstruct message\n"); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto done; + } + + if (pPayloadBuffer != NULL) + { + if (payloadBufferSize < (totalPayloadSize + curPayloadSize)) + { + NV_PRINTF(LEVEL_ERROR, "Buffer provided for message payload too small. Payload size: 0x%x Buffer size: 0x%x\n", + totalPayloadSize + curPayloadSize, payloadBufferSize); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto done; + } + portMemCopy(pPayloadBuffer + totalPayloadSize, payloadBufferSize - totalPayloadSize , + pPacketBuffer + curHeaderSize, curPayloadSize); + } + totalPayloadSize += curPayloadSize; + + // Set TAIL = HEAD to indicate CPU received message + kfspUpdateMsgQueueHeadTail_HAL(pGpu, pKernelFsp, msgqHead, msgqHead); + } + + NvU8 *pMessagePayload = (pPayloadBuffer == NULL) ? (pPacketBuffer + sizeof(MCTP_HEADER)) : pPayloadBuffer; + + status = kfspProcessNvdmMessage_HAL(pGpu, pKernelFsp, pMessagePayload, totalPayloadSize); + +done: + portMemFree(pPacketBuffer); + return status; +} + +/*! + * @brief Send one MCTP packet to FSP via EMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pPacket MCTP packet + * @param[in] packetSize MCTP packet size in bytes + * + * @return NV_OK, or NV_ERR_INSUFFICIENT_RESOURCES + */ +NV_STATUS +kfspSendPacket_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pPacket, + NvU32 packetSize +) +{ + NvU32 paddedSize; + NvU8 *pBuffer = NULL; + NV_STATUS status = NV_OK; + + // Check that queue is ready to receive data + status = kfspPollForQueueEmpty(pGpu, pKernelFsp); + if (status != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + // Pad to align size to 4-bytes boundary since EMEMC increments by DWORDS + paddedSize = NV_ALIGN_UP(packetSize, sizeof(NvU32)); + pBuffer = portMemAllocNonPaged(paddedSize); + portMemSet(pBuffer, 0, paddedSize); + portMemCopy(pBuffer, paddedSize, pPacket, paddedSize); + + kfspWriteToEmem_HAL(pGpu, pKernelFsp, pBuffer, paddedSize); + + // Update HEAD and TAIL with new EMEM offset; RM always starts at offset 0. + kfspUpdateQueueHeadTail_HAL(pGpu, pKernelFsp, 0, paddedSize - sizeof(NvU32)); + + portMemFree(pBuffer); + return status; +} + +/*! + * @brief Send a MCTP message to FSP via EMEM, and read response + * + * + * Response payload buffer is optional if response fits in a single packet. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * @param[in] pPayload Pointer to message payload + * @param[in] size Message payload size + * @param[in] nvdmType NVDM type of message being sent + * @param[in] pResponsePayload Buffer in which to return response payload + * @param[in] responseBufferSize Response payload buffer size + * + * @return NV_OK, or NV_ERR_* + */ +NV_STATUS +kfspSendAndReadMessage_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp, + NvU8 *pPayload, + NvU32 size, + NvU32 nvdmType, + NvU8 *pResponsePayload, + NvU32 responseBufferSize +) +{ + NvU32 dataSent, dataRemaining; + NvU32 packetPayloadCapacity; + NvU32 curPayloadSize; + NvU32 headerSize; + NvU32 fspEmemRmChannelSize; + NvBool bSinglePacket; + NV_STATUS status; + NvU8 *pBuffer = NULL; + NvU8 seq = 0; + NvU8 seid = 0; + + // Allocate buffer of same size as channel + fspEmemRmChannelSize = kfspGetRmChannelSize_HAL(pGpu, pKernelFsp); + pBuffer = portMemAllocNonPaged(fspEmemRmChannelSize); + portMemSet(pBuffer, 0, fspEmemRmChannelSize); + + // + // Check if message will fit in single packet + // We lose 2 DWORDS to MCTP and NVDM headers + // + headerSize = 2 * sizeof(NvU32); + packetPayloadCapacity = fspEmemRmChannelSize - headerSize; + bSinglePacket = (size <= packetPayloadCapacity); + + // First packet + seid = kfspNvdmToSeid_HAL(pGpu, pKernelFsp, nvdmType); + ((NvU32 *)pBuffer)[0] = kfspCreateMctpHeader_HAL(pGpu, pKernelFsp, 1, (NvU8)bSinglePacket, seid, seq); // SOM=1,EOM=?,SEID,SEQ=0 + ((NvU32 *)pBuffer)[1] = kfspCreateNvdmHeader_HAL(pGpu, pKernelFsp, nvdmType); + + curPayloadSize = NV_MIN(size, packetPayloadCapacity); + portMemCopy(pBuffer + headerSize, packetPayloadCapacity, pPayload, curPayloadSize); + + status = kfspSendPacket(pGpu, pKernelFsp, pBuffer, curPayloadSize + headerSize); + if (status != NV_OK) + { + goto failed; + } + + if (!bSinglePacket) + { + // Multi packet case + dataSent = curPayloadSize; + dataRemaining = size - dataSent; + headerSize = sizeof(NvU32); // No longer need NVDM header + packetPayloadCapacity = fspEmemRmChannelSize - headerSize; + + while (dataRemaining > 0) + { + NvBool bLastPacket = (dataRemaining <= packetPayloadCapacity); + curPayloadSize = (bLastPacket) ? dataRemaining : packetPayloadCapacity; + + portMemSet(pBuffer, 0, fspEmemRmChannelSize); + ((NvU32 *)pBuffer)[0] = kfspCreateMctpHeader_HAL(pGpu, pKernelFsp, 0, (NvU8)bLastPacket, seid, (++seq) % 4); + + portMemCopy(pBuffer + headerSize, packetPayloadCapacity, + pPayload + dataSent, curPayloadSize); + + status = kfspSendPacket(pGpu, pKernelFsp, pBuffer, curPayloadSize + headerSize); + if (status != NV_OK) + { + goto failed; + } + + dataSent += curPayloadSize; + dataRemaining -= curPayloadSize; + } + + } + + status = kfspPollForResponse(pGpu, pKernelFsp); + if (status != NV_OK) + { + goto failed; + } + status = kfspReadMessage(pGpu, pKernelFsp, pResponsePayload, responseBufferSize); + +failed: + portMemFree(pBuffer); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 275fcb0c5..ec7dfc61d 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -49,7 +49,6 @@ #include -#include "gpu/nvdec/kernel_nvdec.h" #include "gpu/sec2/kernel_sec2.h" #include "gpu/gsp/kernel_gsp.h" #include "platform/platform.h" @@ -89,7 +88,7 @@ static NV_STATUS gpuStatePostLoad(OBJGPU *, NvU32); static NV_STATUS gpuStatePreUnload(OBJGPU *, NvU32); static NV_STATUS gpuStatePostUnload(OBJGPU *, NvU32); static void gpuXlateHalImplToArchImpl(OBJGPU *, HAL_IMPLEMENTATION, NvU32 *, NvU32 *); -static NvBool gpuSatisfiesTemporalOrder(OBJGPU *, HAL_IMPLEMENTATION, NvU32, NvU32); +static NvBool gpuSatisfiesTemporalOrder(OBJGPU *, HAL_IMPLEMENTATION); static NvBool gpuSatisfiesTemporalOrderMaskRev(OBJGPU *, HAL_IMPLEMENTATION, NvU32, NvU32, NvU32); static NvBool gpuIsT124ImplementationOrBetter(OBJGPU *); static NvBool gpuShouldCreateObject(PGPUCHILDINFO, PENGDESCRIPTOR, NvU32); @@ -355,6 +354,11 @@ gpuPostConstruct_IMPL // has been setup to allow for GPU specific settings gpuDeterminePersistantIllumSettings(pGpu); +#if NVCPU_IS_PPC64LE + // Skip PCI Express Host Bridge initialization on PPC64 platforms + _setPlatformNoHostbridgeDetect(NV_TRUE); +#endif + // Construct and update the engine database rmStatus = gpuConstructEngineTable(pGpu); if (rmStatus != NV_OK) @@ -2755,7 +2759,7 @@ gpuIsImplementationOrBetter_IMPL gpuXlateHalImplToArchImpl(pGpu, halImpl, &gpuArch, &gpuImpl); // "is implementation or better" is only defined between 2 gpus within - // the same "gpu series" as defined in config/Gpus.pm and gpuarch.h + // the same "gpu series" as defined in config/Chips.pm and nv_arch.h chipArch = gpuGetChipArch(pGpu); if (DRF_VAL(GPU, _ARCHITECTURE, _SERIES, chipArch) == DRF_VAL(GPU, _ARCHITECTURE, _SERIES, gpuArch)) @@ -2768,7 +2772,7 @@ gpuIsImplementationOrBetter_IMPL else { // In case there is a temporal ordering we need to account for - result = gpuSatisfiesTemporalOrder(pGpu, halImpl, gpuArch, gpuImpl); + result = gpuSatisfiesTemporalOrder(pGpu, halImpl); } } @@ -3004,6 +3008,34 @@ gpuXlateHalImplToArchImpl } + case HAL_IMPL_AD102: + { + *gpuArch = GPU_ARCHITECTURE_ADA; + *gpuImpl = GPU_IMPLEMENTATION_AD102; + break; + } + + case HAL_IMPL_AD103: + { + *gpuArch = GPU_ARCHITECTURE_ADA; + *gpuImpl = GPU_IMPLEMENTATION_AD103; + break; + } + + case HAL_IMPL_AD104: + { + *gpuArch = GPU_ARCHITECTURE_ADA; + *gpuImpl = GPU_IMPLEMENTATION_AD104; + break; + } + + case HAL_IMPL_GH100: + { + *gpuArch = GPU_ARCHITECTURE_HOPPER; + *gpuImpl = GPU_IMPLEMENTATION_GH100; + break; + } + default: { *gpuArch = 0; @@ -3016,8 +3048,10 @@ gpuXlateHalImplToArchImpl } // -// default Logic: If arch is greater than requested --> NV_TRUE -// OR If arch is = requested AND impl is >= requested --> NV_TRUE +// default Logic: If halImpl is equal or greater than requested --> NV_TRUE +// +// Arch and impl IDs are not guaranteed to be ordered. +// "halImpl" is used here to match the ordering in chip-config/NVOC // // NOTE: only defined for gpus within same gpu series // @@ -3025,9 +3059,7 @@ static NvBool gpuSatisfiesTemporalOrder ( OBJGPU *pGpu, - HAL_IMPLEMENTATION halImpl, - NvU32 gpuArch, - NvU32 gpuImpl + HAL_IMPLEMENTATION halImpl ) { NvBool result = NV_FALSE; @@ -3047,12 +3079,11 @@ gpuSatisfiesTemporalOrder } default: { - NvU32 chipArch = gpuGetChipArch(pGpu); - NvU32 chipImpl = gpuGetChipImpl(pGpu); + HAL_IMPLEMENTATION chipImpl = pGpu->halImpl; + NV_ASSERT(chipImpl < HAL_IMPL_MAXIMUM); + + result = (chipImpl >= halImpl); - result = ((chipArch > gpuArch) || - ((chipArch == gpuArch) && - (chipImpl >= gpuImpl))); break; } } @@ -3156,6 +3187,9 @@ static const EXTERN_TO_INTERNAL_ENGINE_ID rmClientEngineTable[] = { NV2080_ENGINE_TYPE_NVDEC2, classId(OBJBSP) , 2, NV_TRUE }, { NV2080_ENGINE_TYPE_NVDEC3, classId(OBJBSP) , 3, NV_TRUE }, { NV2080_ENGINE_TYPE_NVDEC4, classId(OBJBSP) , 4, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVDEC5, classId(OBJBSP) , 5, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVDEC6, classId(OBJBSP) , 6, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVDEC7, classId(OBJBSP) , 7, NV_TRUE }, { NV2080_ENGINE_TYPE_CIPHER, classId(OBJCIPHER) , 0, NV_TRUE }, { NV2080_ENGINE_TYPE_NVENC0, classId(OBJMSENC) , 0, NV_TRUE }, { NV2080_ENGINE_TYPE_NVENC1, classId(OBJMSENC) , 1, NV_TRUE }, @@ -3163,6 +3197,13 @@ static const EXTERN_TO_INTERNAL_ENGINE_ID rmClientEngineTable[] = { NV2080_ENGINE_TYPE_SW, classId(OBJSWENG) , 0, NV_TRUE }, { NV2080_ENGINE_TYPE_SEC2, classId(OBJSEC2) , 0, NV_TRUE }, { NV2080_ENGINE_TYPE_NVJPEG0, classId(OBJNVJPG) , 0, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG1, classId(OBJNVJPG) , 1, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG2, classId(OBJNVJPG) , 2, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG3, classId(OBJNVJPG) , 3, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG4, classId(OBJNVJPG) , 4, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG5, classId(OBJNVJPG) , 5, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG6, classId(OBJNVJPG) , 6, NV_TRUE }, + { NV2080_ENGINE_TYPE_NVJPEG7, classId(OBJNVJPG) , 7, NV_TRUE }, { NV2080_ENGINE_TYPE_OFA, classId(OBJOFA) , 0, NV_TRUE }, { NV2080_ENGINE_TYPE_DPU, classId(OBJDPU) , 0, NV_FALSE }, { NV2080_ENGINE_TYPE_PMU, classId(Pmu) , 0, NV_FALSE }, diff --git a/src/nvidia/src/kernel/gpu/gpu_timeout.c b/src/nvidia/src/kernel/gpu/gpu_timeout.c index 4a0d26e55..ba9873dae 100644 --- a/src/nvidia/src/kernel/gpu/gpu_timeout.c +++ b/src/nvidia/src/kernel/gpu/gpu_timeout.c @@ -363,8 +363,11 @@ _checkTimeout if (current >= pTimeout->timeout) { - NV_PRINTF(LEVEL_ERROR, "ptmr elapsed %llx >= %llx\n", - current, pTimeout->timeout); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_ERROR, "ptmr elapsed %llx >= %llx\n", + current, pTimeout->timeout); + } status = NV_ERR_TIMEOUT; } } @@ -382,7 +385,10 @@ _checkTimeout if (pTimeout->timeout == 0) { - NV_PRINTF(LEVEL_INFO, "ptmr timeout == 0\n"); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_INFO, "ptmr timeout == 0\n"); + } status = NV_ERR_TIMEOUT; } } diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index e044b23f4..404619dda 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -708,7 +708,6 @@ nvEventBufferFecsCallback NvU32 fecsReadOffsetPrev; NvU64 fecsBufferSize; NvU32 fecsRecordSize; - NvU64 watermark; NvU32 i, j; NvU8 *pFecsBufferMapping; MEMORY_DESCRIPTOR *pFecsMemDesc = NULL; @@ -826,12 +825,7 @@ nvEventBufferFecsCallback } } - // - // In order to avoid register accesses, only synchronize the position - // with hardware when the buffer exceeds a watermark level - // - watermark = (3 * fecsBufferSize) / 4; - if (pFecsTraceInfo->fecsTraceCounter > watermark) + if (pFecsTraceInfo->fecsTraceCounter > 0) { NvHandle hClient; NvHandle hSubdevice; @@ -1189,39 +1183,53 @@ fecsBufferReset MEMORY_DESCRIPTOR *pFecsMemDesc = NULL; NV_STATUS status; KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo = kgraphicsGetFecsTraceInfo(pGpu, pKernelGraphics); + NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS getHwEnableParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvHandle hClient; + NvHandle hSubdevice; NV_ASSERT_OR_RETURN_VOID(pFecsTraceInfo != NULL); if (pFecsTraceInfo->pFecsBufferMapping == NULL) return; + NV_ASSERT_OK_OR_ELSE( + status, + _fecsLoadInternalRoutingInfo(pGpu, + pKernelGraphics, + &hClient, + &hSubdevice, + &getHwEnableParams.grRouteInfo), + return); + + NV_ASSERT_OK_OR_ELSE( + status, + pRmApi->Control(pRmApi, + hClient, + hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE, + &getHwEnableParams, + sizeof(getHwEnableParams)), + return); + status = _getFecsMemDesc(pGpu, pKernelGraphics, &pFecsMemDesc); - if ((status == NV_OK) && (pFecsMemDesc != NULL)) + if ((status == NV_OK) && (pFecsMemDesc != NULL) && (getHwEnableParams.bEnable != NV_TRUE)) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NvHandle hClient; - NvHandle hSubdevice; NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS traceWrOffsetParams; NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS traceRdOffsetParams; - NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS hwEnableParams; - - portMemSet(pFecsTraceInfo->pFecsBufferMapping, (NvU8)(NV_FECS_TRACE_MAGIC_INVALIDATED & 0xff), memdescGetSize(pFecsMemDesc)); + NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS setHwEnableParams; - traceWrOffsetParams.offset = 0; - NV_ASSERT_OK_OR_ELSE( - status, - _fecsLoadInternalRoutingInfo(pGpu, - pKernelGraphics, - &hClient, - &hSubdevice, - &traceWrOffsetParams.grRouteInfo), - return); + portMemSet(pFecsTraceInfo->pFecsBufferMapping, + (NvU8)(NV_FECS_TRACE_MAGIC_INVALIDATED & 0xff), + memdescGetSize(pFecsMemDesc)); // Routing info is the same for all future calls in this series - traceRdOffsetParams.grRouteInfo = traceWrOffsetParams.grRouteInfo; - hwEnableParams.grRouteInfo = traceWrOffsetParams.grRouteInfo; + traceWrOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; + traceRdOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; + setHwEnableParams.grRouteInfo = getHwEnableParams.grRouteInfo; + traceWrOffsetParams.offset = 0; NV_ASSERT_OK_OR_ELSE( status, pRmApi->Control(pRmApi, @@ -1244,15 +1252,15 @@ fecsBufferReset return); pFecsTraceInfo->fecsTraceRdOffset = 0; - hwEnableParams.bEnable = NV_TRUE; + setHwEnableParams.bEnable = NV_TRUE; NV_ASSERT_OK_OR_ELSE( status, pRmApi->Control(pRmApi, hClient, hSubdevice, NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE, - &hwEnableParams, - sizeof(hwEnableParams)), + &setHwEnableParams, + sizeof(setHwEnableParams)), return); } } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index cde65f1e7..b76724104 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -53,6 +53,7 @@ #include "class/clc5c0.h" #include "class/clc6c0.h" #include "class/clc7c0.h" +#include "class/clcbc0.h" #include "class/cl0080.h" #include "class/cl2080.h" @@ -65,6 +66,7 @@ #include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A #include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A #include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A #include "class/clc637.h" #include "class/clc638.h" @@ -1802,6 +1804,10 @@ kgraphicsCreateGoldenImageChannel_IMPL { ctrlSize = sizeof(Nvc56fControl); } + else if (gpuIsClassSupported(pGpu, HOPPER_CHANNEL_GPFIFO_A)) + { + ctrlSize = sizeof(Nvc86fControl); + } else { status = NV_ERR_NOT_SUPPORTED; @@ -2443,19 +2449,21 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; NvU32 i; LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); - if (pKernelGraphicsManager == NULL) + if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { return NV_ERR_NOT_SUPPORTED; } - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); - + else + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + } // Verify static info is available pStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2487,13 +2495,21 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; NvU32 i; LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + { + return NV_ERR_NOT_SUPPORTED; + } + else + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + } // Verify static info is available pStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -2512,7 +2528,7 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL pParams->globalSmId[i].localTpcId = pStaticInfo->globalSmOrder.globalSmId[i].localTpcId; pParams->globalSmId[i].localSmId = pStaticInfo->globalSmOrder.globalSmId[i].localSmId; pParams->globalSmId[i].globalTpcId = pStaticInfo->globalSmOrder.globalSmId[i].globalTpcId; - pParams->globalSmId[i].virtualGpcId = pStaticInfo->globalSmOrder.globalSmId[i].virtualGpcId; + pParams->globalSmId[i].virtualGpcId = pStaticInfo->globalSmOrder.globalSmId[i].virtualGpcId; pParams->globalSmId[i].migratableTpcId = pStaticInfo->globalSmOrder.globalSmId[i].migratableTpcId; } @@ -3477,3 +3493,36 @@ subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL return status; } +/*! + * subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo + * + * Lock Requirements: + * Assert that API lock and GPUs lock held on entry + */ +NV_STATUS +subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KernelGraphics *pKernelGraphics; + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + + LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + + // Verify static info is available + pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); + + pParams->physGfxGpcMask = pKernelGraphicsStaticInfo->floorsweepingMasks.physGfxGpcMask; + pParams->numGfxTpc = pKernelGraphicsStaticInfo->floorsweepingMasks.numGfxTpc; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index 751375752..095c348b2 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -39,6 +39,8 @@ #include "class/clc5c0.h" #include "class/clc6c0.h" #include "class/clc7c0.h" +#include "class/clc9c0.h" +#include "class/clcbc0.h" // GFX #include "class/clb097.h" #include "class/clb197.h" @@ -48,6 +50,8 @@ #include "class/clc597.h" #include "class/clc697.h" #include "class/clc797.h" +#include "class/clc997.h" +#include "class/clcb97.h" // TWOD #include "class/cl902d.h" @@ -99,6 +103,8 @@ kgrmgrGetGrObjectType_IMPL case TURING_COMPUTE_A: case AMPERE_COMPUTE_A: case AMPERE_COMPUTE_B: + case ADA_COMPUTE_A: + case HOPPER_COMPUTE_A: *pObjectType = GR_OBJECT_TYPE_COMPUTE; break; case MAXWELL_A: @@ -109,6 +115,8 @@ kgrmgrGetGrObjectType_IMPL case TURING_A: case AMPERE_A: case AMPERE_B: + case ADA_A: + case HOPPER_A: *pObjectType = GR_OBJECT_TYPE_3D; break; case FERMI_TWOD_A: @@ -636,7 +644,7 @@ kgrmgrAllocVeidsForGrIdx_IMPL // We statically assign VEIDs to a GR based on the number of GPCs connected to it maxVeidsForThisGr = maxVeidsPerGpc * gpcCount; - reqVeidMask = NVBIT64(maxVeidsForThisGr) - 1; + reqVeidMask = DRF_SHIFTMASK64((maxVeidsForThisGr - 1):0); // Create a mask for VEIDs associated with this GPU instance GPUInstanceVeidEnd = pKernelMIGGPUInstance->resourceAllocation.veidOffset + pKernelMIGGPUInstance->resourceAllocation.veidCount - 1; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c new file mode 100644 index 000000000..45613742e --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -0,0 +1,592 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides GH100+ specific KernelGsp HAL implementations. + */ + +#include "rmconfig.h" +#include "gpu/fsp/kern_fsp.h" +#include "gpu/gsp/kernel_gsp.h" +#include "gsp/gspifpub.h" +#include "vgpu/rpc.h" + +#include "published/hopper/gh100/dev_falcon_v4.h" +#include "published/hopper/gh100/dev_gsp.h" +#include "published/hopper/gh100/dev_riscv_pri.h" + +#define RISCV_BR_ADDR_ALIGNMENT (8) + +/*! + * Helper Function for kgspResetHw_GH100 + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pVoid unused void pointer + * + * @return NvBool NV_TRUE if reset FSM reports ASSERTED + */ +static NvBool +_kgspWaitForAsserted +( + OBJGPU *pGpu, + void *pVoid +) +{ + return GPU_FLD_TEST_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET_STATUS, + _ASSERTED); +} + + +/*! + * Helper Function for kgspResetHw_GH100 + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pVoid unused void pointer + * + * @return NvBool NV_TRUE if reset FSM reports DEASSERTED + */ +static NvBool +_kgspWaitForDeasserted +( + OBJGPU *pGpu, + void *pVoid +) +{ + return GPU_FLD_TEST_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET_STATUS, + _DEASSERTED); +} + +/*! + * Reset the GSP HW + * + * @return NV_OK if the GSP HW was properly reset + */ +NV_STATUS +kgspResetHw_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + + // + // Add a delay for 10us. This is a worst case estimate. + // See bug 200636529 comment 20 + // Use PTIMER instead of the default ostimer since it is much faster than the + // former and hence does not cause sufficient delay. + // + gpuSetTimeout(pGpu, 10, &timeout, GPU_TIMEOUT_FLAGS_TMR); + + GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _ASSERT); + status = gpuTimeoutCondWait(pGpu, _kgspWaitForAsserted, NULL, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP falcon reset to assert\n"); + DBG_BREAKPOINT(); + } + + // Reset timeout + gpuSetTimeout(pGpu, 10, &timeout, GPU_TIMEOUT_FLAGS_TMR); + + GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _DEASSERT); + status = gpuTimeoutCondWait(pGpu, _kgspWaitForDeasserted, NULL, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP falcon reset to deassert\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +NV_STATUS +kgspAllocBootArgs_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NvP64 pVa = NvP64_NULL; + NvP64 pPriv = NvP64_NULL; + NV_STATUS nvStatus = NV_OK; + + // Allocate GSP-FMC arguments + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pKernelGsp->pGspFmcArgumentsDescriptor, + pGpu, sizeof(GSP_CC_BOOT_PARAMS), 0x1000, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, + MEMDESC_FLAGS_NONE), + _kgspAllocBootArgs_exit_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescAlloc(pKernelGsp->pGspFmcArgumentsDescriptor), + _kgspAllocBootArgs_exit_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pKernelGsp->pGspFmcArgumentsDescriptor, 0, + memdescGetSize(pKernelGsp->pGspFmcArgumentsDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + _kgspAllocBootArgs_exit_cleanup); + + pKernelGsp->pGspFmcArgumentsCached = (GSP_CC_BOOT_PARAMS *)NvP64_VALUE(pVa); + pKernelGsp->pGspFmcArgumentsMappingPriv = pPriv; + + return kgspAllocBootArgs_TU102(pGpu, pKernelGsp); + +_kgspAllocBootArgs_exit_cleanup: + kgspFreeBootArgs_HAL(pGpu, pKernelGsp); + return nvStatus; +} + +void +kgspFreeBootArgs_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + kgspFreeBootArgs_TU102(pGpu, pKernelGsp); + + // release wpr meta data resources + if (pKernelGsp->pGspFmcArgumentsCached != NULL) + { + memdescUnmap(pKernelGsp->pGspFmcArgumentsDescriptor, + NV_TRUE, osGetCurrentProcess(), + (void *)pKernelGsp->pGspFmcArgumentsCached, + pKernelGsp->pGspFmcArgumentsMappingPriv); + pKernelGsp->pGspFmcArgumentsCached = NULL; + pKernelGsp->pGspFmcArgumentsMappingPriv = NULL; + } + if (pKernelGsp->pGspFmcArgumentsDescriptor != NULL) + { + memdescFree(pKernelGsp->pGspFmcArgumentsDescriptor); + memdescDestroy(pKernelGsp->pGspFmcArgumentsDescriptor); + pKernelGsp->pGspFmcArgumentsDescriptor = NULL; + } +} + +NV_STATUS +kgspWaitForGfwBootOk_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + return kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); +} + +/*! + * Calculate the FB layout. On Hopper, this consists of determining the + * minimum sizes of various regions that Client RM provides as inputs. + * The actual offsets are determined by secure ACR ucode and patched + * into the GspFwWprMeta structure provided to GSP-RM, so most of the + * structure is 0-initialized here. + * + * Firmware scrubs the last 256mb of FB, no memory outside of this region + * may be used until the FW RM has scrubbed the remainder of memory. + * + * ---------------------------- <- fbSize (end of FB, 1M aligned) + * | VGA WORKSPACE | + * ---------------------------- <- vbiosReservedOffset (64K? aligned) + * | (potential align. gap) | + * ---------------------------- <- gspFwWprEnd (128K aligned) + * | FRTS data | (frtsSize is 0 on GA100) + * | ------------------------ | <- frtsOffset + * | BOOT BIN (e.g. GSP-FMC) | + * ---------------------------- <- bootBinOffset + * | GSP FW ELF | + * ---------------------------- <- gspFwOffset + * | GSP FW (WPR) HEAP | + * ---------------------------- <- gspFwHeapOffset + * | ACR-placed metadata | + * | (struct GspFwWprMeta) | + * ---------------------------- <- gspFwWprStart (128K aligned) + * | GSP FW (non-WPR) HEAP | + * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart + * (GSP_CARVEOUT_SIZE bytes from end of FB) + * + * @param pGpu GPU object pointer + * @param pKernelGsp KernelGsp object pointer + * @param pGspFw Pointer to GSP-RM fw image. + * @param pFbRegionInfo Pointer to fb region table to fill in. + */ +NV_STATUS +kgspCalculateFbLayout_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + GspFwWprMeta *pWprMeta = pKernelGsp->pWprMeta; + RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; + + ct_assert(sizeof(*pWprMeta) == 256); + + NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); + + NV_ASSERT_OR_RETURN(pKernelGsp->pGspRmBootUcodeImage != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pKernelGsp->gspRmBootUcodeSize != 0, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pRiscvDesc != NULL, NV_ERR_INVALID_STATE); + + portMemSet(pWprMeta, 0, sizeof *pWprMeta); + + // + // We send this to FSP as the size to reserve above FRTS. + // The actual offset gets filled in by ACR ucode when it sets up WPR2. + // + pWprMeta->vgaWorkspaceSize = 128 * 1024; + + // Physical address and size of GSP-FMC ucode in system memory + pWprMeta->sizeOfBootloader = pKernelGsp->gspRmBootUcodeSize; + pWprMeta->sysmemAddrOfBootloader = + memdescGetPhysAddr(pKernelGsp->pGspRmBootUcodeMemdesc, AT_GPU, 0); + + // Physical address and size of GSP-RM firmware in system memory + pWprMeta->sizeOfRadix3Elf = pGspFw->size; + pWprMeta->sysmemAddrOfRadix3Elf = + memdescGetPhysAddr(pKernelGsp->pGspUCodeRadix3Descriptor, AT_GPU, 0); + + // Set necessary info from the GSP-FMC desc + pWprMeta->bootloaderCodeOffset = pRiscvDesc->monitorCodeOffset; + pWprMeta->bootloaderDataOffset = pRiscvDesc->monitorDataOffset; + pWprMeta->bootloaderManifestOffset = pRiscvDesc->manifestOffset; + + if (pKernelGsp->pSignatureMemdesc != NULL) + { + pWprMeta->sysmemAddrOfSignature = memdescGetPhysAddr(pKernelGsp->pSignatureMemdesc, AT_GPU, 0); + pWprMeta->sizeOfSignature = memdescGetSize(pKernelGsp->pSignatureMemdesc); + } + + // The non-WPR heap lives in front of the WPR region + pWprMeta->nonWprHeapSize = kgspGetNonWprHeapSize(pGpu, pKernelGsp); + + // + // The WPR heap size (gspFwHeapSize) is variable to also get any padding needed + // in the carveout to align the WPR start. We specify a minimum size here. + // + pWprMeta->gspFwHeapSize = 64 * 1024 * 1024; + + // Fill in the meta-metadata + pWprMeta->revision = GSP_FW_WPR_META_REVISION; + pWprMeta->magic = GSP_FW_WPR_META_MAGIC; + + return NV_OK; +} + +static GSP_DMA_TARGET _kgspMemdescToDmaTarget +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + switch (memdescGetAddressSpace(pMemDesc)) + { + case ADDR_SYSMEM: + return (NV_MEMORY_CACHED == memdescGetCpuCacheAttrib(pMemDesc)) ? GSP_DMA_TARGET_COHERENT_SYSTEM + : GSP_DMA_TARGET_NONCOHERENT_SYSTEM; + case ADDR_FBMEM: + return GSP_DMA_TARGET_LOCAL_FB; + default: + return GSP_DMA_TARGET_COUNT; + } +} + +/*! + * @brief Creates and populates the GSP-FMC/ACR arguments for booting GSP-RM. + */ +NV_STATUS +kgspSetupGspFmcArgs_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN(pKernelGsp->pGspFmcArgumentsCached != NULL, NV_ERR_INVALID_STATE); + + GSP_CC_BOOT_PARAMS *pGspCcBootParams = pKernelGsp->pGspFmcArgumentsCached; + + pGspCcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0); + pGspCcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta); + pGspCcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor); + + pGspCcBootParams->gspRmParams.bootArgsOffset = memdescGetPhysAddr(pKernelGsp->pLibosInitArgumentsDescriptor, AT_GPU, 0); + pGspCcBootParams->gspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pLibosInitArgumentsDescriptor); + + return NV_OK; +} + +/*! + * Determine if lockdown is released. + */ +static NvBool +_kgspIsLockdownReleased +( + OBJGPU *pGpu, + void *pVoid +) +{ + KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); + NvU32 reg; + + reg = kflcnRegRead_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), NV_PFALCON_FALCON_HWCFG2); + + return FLD_TEST_DRF(_PFALCON, _FALCON_HWCFG2, _RISCV_BR_PRIV_LOCKDOWN, + _UNLOCK, reg); +} + +/*! + * Determine if PRIV target mask is unlocked for GSP. + * This is temporary WAR for bug 3640831 until we have notification protocol in + * place (there is no HW mechanism for CPU to check if GSP is open other than + * reading 0xBADF41YY code). + */ +static NvBool +_kgspIsTargetMaskReleased +( + OBJGPU *pGpu, + void *pVoid +) +{ + KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + const NvU32 privErrTargetLocked = 0xBADF4100U; + const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it has extra error information + NvU32 reg; + + // + // This register is read with the raw OS read to avoid the 0xbadf sanity checking + // done by the usual register read utilities. + // + reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), + pKernelFalcon->registerBase + NV_PFALCON_FALCON_HWCFG2); + + return (reg & privErrTargetLockedMask) != privErrTargetLocked; +} + +static void +_kgspBootstrapGspFmc_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + RmPhysAddr physAddr; + + // Reset the GSP to prepare for RISCV bootstrap + kgspResetHw_HAL(pGpu, pKernelGsp); + + // Stuff the GSP-FMC arguments into the mailbox regs + physAddr = memdescGetPhysAddr(pKernelGsp->pGspFmcArgumentsDescriptor, AT_GPU, 0); + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0, NvU64_LO32(physAddr)); + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1, NvU64_HI32(physAddr)); + + // Bootstrap the GSP-FMC by pointing the GSP's BootROM at it + RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; + RmPhysAddr fmcPhysAddr = memdescGetPhysAddr(pKernelGsp->pGspRmBootUcodeMemdesc, AT_GPU, 0); + + // Program FMC code DMAADDR + physAddr = (fmcPhysAddr + pRiscvDesc->monitorCodeOffset) >> RISCV_BR_ADDR_ALIGNMENT; + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO, + NvU64_LO32(physAddr)); + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI, + NvU64_HI32(physAddr)); + + // Program FMC Data DMAADDR + physAddr = (fmcPhysAddr + pRiscvDesc->monitorDataOffset) >> RISCV_BR_ADDR_ALIGNMENT; + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO, + NvU64_LO32(physAddr)); + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI, + NvU64_HI32(physAddr)); + + // Program manifest DMAADDR + physAddr = (fmcPhysAddr + pRiscvDesc->manifestOffset) >> RISCV_BR_ADDR_ALIGNMENT; + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO, + NvU64_LO32(physAddr)); + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI, + NvU64_HI32(physAddr)); + + NvU32 target = NV_PRISCV_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM; + NvU32 dmaCfg = DRF_NUM(_PRISCV_RISCV, _BCR_DMACFG, _TARGET, target) | + DRF_DEF(_PRISCV_RISCV, _BCR_DMACFG, _LOCK, _LOCKED); + + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_BCR_DMACFG, dmaCfg); + + kflcnRiscvProgramBcr_HAL(pGpu, pKernelFalcon, NV_TRUE); + + // Start it + kflcnRiscvRegWrite_HAL(pGpu, pKernelFalcon, NV_PRISCV_RISCV_CPUCTL, + DRF_DEF(_PRISCV_RISCV, _CPUCTL, _STARTCPU, _TRUE)); +} + +/*! + * Boot GSP-RM. + * + * This routine handles the following: + * - prepares RISCV core to run GSP-RM + * - prepares libos initialization args + * - prepares GSP-RM initialization message + * - starts the RISCV core and passes control to boot binary image + * - waits for GSP-RM to complete initialization + * + * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelGsp GSP object pointer + * @param[in] pGspFw GSP_FIRMWARE image pointer + * + * @return NV_OK if GSP-RM RISCV boot was successful. + * Appropriate NV_ERR_xxx value otherwise. + */ +NV_STATUS +kgspBootstrapRiscvOSEarly_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + NV_STATUS status = NV_OK; + + // Only for GSP client builds + if (!IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "IS_GSP_CLIENT is not set.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // Setup the descriptors that GSP-FMC needs to boot GSP-RM + NV_ASSERT_OK_OR_RETURN(kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw)); + + kgspSetupLibosInitArgs(pGpu, pKernelGsp); + + // Fill in the GSP-RM message queue init parameters + kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, NULL); + + // + // Stuff the message queue with async init messages that will be run + // before OBJGPU is created. + // + NV_RM_RPC_GSP_SET_SYSTEM_INFO(pGpu, status); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); + goto exit; + } + + NV_RM_RPC_SET_REGISTRY(pGpu, status); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); + goto exit; + } + + if (pKernelFsp != NULL && !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) + { + NV_PRINTF(LEVEL_ERROR, "Starting to boot GSP via FSP.\n"); + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); + NV_ASSERT_OK_OR_RETURN(kfspSendBootCommands_HAL(pGpu, pKernelFsp)); + } + else + { + _kgspBootstrapGspFmc_GH100(pGpu, pKernelGsp); + } + + // Wait for target mask to be released. + status = gpuTimeoutCondWait(pGpu, _kgspIsTargetMaskReleased, pKernelGsp, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " + "This error may be caused by several reasons: Bootrom may have failed, " + "GSP init code may have failed or ACR failed to release target mask. " + "RM does not have access to information on which of those conditions happened.\n"); + + if (pKernelFsp != NULL && pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + } + + return status; + } + + // Wait for lockdown to be released. + status = gpuTimeoutCondWait(pGpu, _kgspIsLockdownReleased, pKernelGsp, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for lockdown release. It's also " + "possible that bootrom may have failed. RM may not have access to " + "the BR status to be able to say for sure what failed.\n"); + + if (pKernelFsp != NULL && pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + } + + NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX0 = 0x%x\n", + kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)); + NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n", + kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1)); + + return status; + } + + // Program FALCON_OS + RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_OS, pRiscvDesc->appVersion); + + // Ensure the CPU is started + if (kflcnIsRiscvActive_HAL(pGpu, pKernelFalcon)) + { + NV_PRINTF(LEVEL_INFO, "GSP ucode loaded and RISCV started.\n"); + } + else + { + NV_ASSERT_FAILED("Failed to boot GSP"); + status = NV_ERR_NOT_READY; + goto exit; + } + + NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); + + // Link the status queue. + NV_ASSERT_OK_OR_GOTO(status, GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), + exit); + + NV_ASSERT_OK_OR_GOTO(status, kgspWaitForRmInitDone(pGpu, pKernelGsp), + exit); + + NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); + +exit: + NV_ASSERT(status == NV_OK); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c index 14a27e9f4..7760352f2 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c @@ -31,7 +31,6 @@ #include "gpu/gpu.h" #include "gpu/falcon/kernel_falcon.h" #include "gpu/sec2/kernel_sec2.h" -#include "gpu/nvdec/kernel_nvdec.h" #include "rmflcnbl.h" #include "published/turing/tu102/dev_falcon_v4.h" diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 53961a1be..07e60c743 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -835,9 +835,18 @@ _kgspRpcRecvPoll NV_ASSERT(portSafeMulU32(GSP_SCALE_TIMEOUT_EMU_SIM, 1500000, &timeoutResult)); timeoutUs = timeoutResult; } + else + { + // We should only ever timeout this when GSP is in really bad state, so if it just + // happens to timeout on default timeout it should be OK for us to give it a little + // more time - make this timeout 1.5 of the default to allow some leeway. + NvU32 defaultus = pGpu->timeoutData.defaultus; + + timeoutUs = defaultus + defaultus / 2; + } NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - gpuSetTimeout(pGpu, timeoutUs, &timeout, 0); + gpuSetTimeout(pGpu, timeoutUs, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); for (;;) { @@ -1323,6 +1332,14 @@ kgspInitRm_IMPL * Here we prepare the Booter ucode images in SYSMEM so they may be loaded onto * SEC2 (Load / Unload) and NVDEC0 (Unload). */ + if (pKernelGsp->bPartitionedFmc) + { + // + // The secure boot ucode is included in the partitioned FMC, no need for + // separate Booter ucodes. + // + } + else { if (pKernelGsp->pBooterLoadUcode == NULL) { @@ -1461,7 +1478,18 @@ kgspUnloadRm_IMPL // Dump GSP-RM logs and reset before invoking FWSEC-SB kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); - kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + + // + // Avoid cascading timeouts when attempting to invoke the below ucodes if + // we are unloading due to a GSP-RM timeout. + // + threadStateResetTimeout(pGpu); + + // Because of COT, RM cannot reset GSP-RISCV and FSP has exclusive access to reset and reboot GSP for next run. + if(!(pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_COT_ENABLED))) + { + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + } // Invoke FWSEC-SB to put back PreOsApps during driver unload status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); @@ -1471,6 +1499,15 @@ kgspUnloadRm_IMPL NV_ASSERT(0); } + if (pKernelGsp->bPartitionedFmc) + { + // + // GSP-RM invokes the partitioned FMC to unload directly as part of the + // NV_RM_RPC_UNLOADING_GUEST_DRIVER call above. + // + status = rpcStatus; + } + else { // After instructing GSP-RM to unload itself, run Booter Unload to teardown WPR2 status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp); diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 18e8764e1..76f53f618 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -267,7 +267,7 @@ NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI) int nRet = 0; int nRetries; RMTIMEOUT timeout; - NvU32 timeoutUs = 2000000; + NvU32 timeoutUs = 4000000; NvU32 timeoutFlags = GPU_TIMEOUT_FLAGS_DEFAULT; KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); @@ -290,7 +290,7 @@ NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI) gpuSetTimeout(pGpu, timeoutUs, &timeout, timeoutFlags); - // Wait other end of the queue to run msgqInit. Retry for up to 10 ms. + // Wait other end of the queue to run msgqInit. Retry until the timeout. for (nRetries = 0; ; nRetries++) { // Link in status queue @@ -430,7 +430,7 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) if ((uElementSize & 7) != 0) portMemSet(pSrc + uElementSize, 0, 8 - (uElementSize & 7)); - pCQE->seqNum = pMQI->txSeqNum++; + pCQE->seqNum = pMQI->txSeqNum; pCQE->checkSum = 0; pCQE->checkSum = _checkSum32(pSrc, uElementSize); @@ -489,6 +489,9 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) goto done; } + // Advance seq num only if we actually used it. + pMQI->txSeqNum++; + nvStatus = NV_OK; done: diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c index 0bf852603..4fcbe775b 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c @@ -93,7 +93,7 @@ profilerDevConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - PROFILER_CLIENT_PERMISSIONS clientPermissions; + PROFILER_CLIENT_PERMISSIONS clientPermissions = {0}; if (!profilerDevQueryCapabilities_HAL(pProfDev, pCallContext, pParams, &clientPermissions)) @@ -122,6 +122,7 @@ profilerDevQueryCapabilities_IMPL pClientPermissions->bMemoryProfilingPermitted = _isMemoryProfilingPermitted(pGpu, pProfBase, hClient); + pClientPermissions->bAdminProfilingPermitted = NV_FALSE; if (pSecInfo->privLevel >= RS_PRIV_LEVEL_USER_ROOT) { bAnyProfilingPermitted = NV_TRUE; @@ -132,7 +133,9 @@ profilerDevQueryCapabilities_IMPL _isDeviceProfilingPermitted(pGpu, pProfBase, pSecInfo); if (pClientPermissions->bDevProfilingPermitted) + { bAnyProfilingPermitted = NV_TRUE; + } return bAnyProfilingPermitted; } diff --git a/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c new file mode 100644 index 000000000..7b4a8fc28 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "kernel/gpu/intr/intr.h" +#include "gpu/gpu.h" +#include "os/os.h" + +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_vm_addendum.h" + +// Compile time asserts to make sure we don't write beyond the leaf register array + +ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); +ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); +ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); +ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); +ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); +ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); + +ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); +ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); + +/*! + * @brief Gets the stall subtree end index + */ +NvU32 +intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, Intr *pIntr) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + return NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + } + else + { + return NV_CPU_INTR_STALL_SUBTREE_LAST; + } +} + +/*! + * @brief Gets the number of leaf registers used + */ +NvU32 +intrGetNumLeaves_GH100(OBJGPU *pGpu, Intr *pIntr) +{ + ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1) <= NV_MAX_INTR_LEAVES); + return (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1); +} + +/*! + * @brief Gets the value of VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 + */ +NvU32 +intrGetLeafSize_GH100(OBJGPU *pGpu, Intr *pIntr) +{ + return NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1; +} + +/*! + * @brief Gets the mask of INTR_TOP that covers nonstall interrupts + */ +NvU32 +intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, Intr *pIntr) +{ + NvU32 nonStallMask; + + // Compile-time assert against the highest set bit that will be returned + #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5) + + ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); + ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); + ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); + + nonStallMask = NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0)); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + nonStallMask |= NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5)); + } + + return nonStallMask; +} + +/*! + * @brief Sanity check that the given stall engine interrupt vector is in the right tree + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + * @param[in] vector stall interrupt vector + */ +void +intrSanityCheckEngineIntrStallVector_GH100 +( + OBJGPU *pGpu, + Intr *pIntr, + NvU32 vector, + NvU16 mcEngine +) +{ + // + // The leafIndex must be within the engine stall tree: leaf 6 and 7 on Hopper. + // Try to catch this on pre-release drivers. Don't need this on release drivers since this + // is only to catch issues during code development. Should never happen in practice. + // + if ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(vector) != 6) && + (NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(vector) != 7)) + { + NV_PRINTF(LEVEL_ERROR, "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", mcEngine, vector); + DBG_BREAKPOINT(); + } +} + +/*! + * @brief Sanity check that the given notification engine interrupt vector is in the right tree + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + * @param[in] vector stall interrupt vector + */ +void +intrSanityCheckEngineIntrNotificationVector_GH100 +( + OBJGPU *pGpu, + Intr *pIntr, + NvU32 vector, + NvU16 mcEngine +) +{ + // + // The leafIndex must be within the engine notification tree: leaf 0 and 1 on Hopper. + // Try to catch this on pre-release drivers. Don't need this on release drivers since this + // is only to catch issues during code development. Should never happen in practice. + // + if ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(vector) != 0) && + (NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(vector) != 1)) + { + NV_PRINTF(LEVEL_ERROR, "MC_ENGINE_IDX %u has invalid notification intr vector %u\n", mcEngine, vector); + DBG_BREAKPOINT(); + } +} diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index 5bd1c0b4c..fb1e3a874 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -65,8 +65,6 @@ intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr) NvU16 nextEngine; NvU32 regReadValue; - NVRM_TRACE('MISR'); - // // If the GPU is off the BUS or surprise removed during servicing DPC for ISRs // we wont know about GPU state until after we start processing DPCs for every @@ -124,7 +122,7 @@ intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr) } exit: - NVRM_TRACE('misr'); + return; } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c index dbde26f9b..fa43770de 100644 --- a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c +++ b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c @@ -28,10 +28,16 @@ #include "diagnostics/nv_debug_dump.h" #include "gpu/bus/kern_bus.h" #include "gpu/mmu/kern_gmmu.h" +#include "kernel/gpu/bif/kernel_bif.h" +#include "nvRmReg.h" +#include "nv_ref.h" #include "lib/protobuf/prb_util.h" #include "g_nvdebug_pb.h" +static void _kmcInitPciRegistryOverrides(OBJGPU *, KernelMc *); +static NV_STATUS _kmcSetPciLatencyTimer(OBJGPU *, KernelMc *); + // // MC RM SubDevice Controls // @@ -200,6 +206,8 @@ kmcStateInitLocked_IMPL KernelMc *pKernelMc ) { + _kmcInitPciRegistryOverrides(pGpu, pKernelMc); + NvDebugDump *pNvd = GPU_GET_NVD(pGpu); if(pNvd != NULL) { @@ -211,5 +219,79 @@ kmcStateInitLocked_IMPL REF_DEF(NVD_ENGINE_FLAGS_SOURCE, _BOTH), (void *)pKernelMc); } + + return NV_OK; +} + +NV_STATUS +kmcStateLoad_IMPL +( + OBJGPU *pGpu, + KernelMc *pKernelMc, + NvU32 flags +) +{ + if (!RMCFG_FEATURE_PLATFORM_GSP && + kbifGetBusIntfType_HAL(GPU_GET_KERNEL_BIF(pGpu)) != + NV2080_CTRL_BUS_INFO_TYPE_AXI) + { + // Adjust the pci latency timer if needed + _kmcSetPciLatencyTimer(pGpu, pKernelMc); + } + + return NV_OK; +} + +static void +_kmcInitPciRegistryOverrides +( + OBJGPU *pGpu, + KernelMc *pKernelMc +) +{ + NvU32 data32; + + // Initialize pci latency timer control state + pKernelMc->LatencyTimerControl.DontModifyTimerValue = NV_FALSE; + pKernelMc->LatencyTimerControl.LatencyTimerValue = NV_CONFIG_PCI_NV_3_LATENCY_TIMER_248_CLOCKS; + + // See if there is a requested override + if (osReadRegistryDword(pGpu, + NV_REG_STR_PCI_LATENCY_TIMER_CONTROL, &data32) == NV_OK) + { + if(data32 == 0xFFFFFFFF) + { + pKernelMc->LatencyTimerControl.DontModifyTimerValue = NV_TRUE; + } + else + { + pKernelMc->LatencyTimerControl.LatencyTimerValue = (data32 >> 3) & 0x1F; + } + } +} + +static NV_STATUS +_kmcSetPciLatencyTimer +( + OBJGPU *pGpu, + KernelMc *pKernelMc +) +{ + NvU32 data; + + // Should we skip the set? + if(!(pKernelMc->LatencyTimerControl.DontModifyTimerValue) && !IS_VIRTUAL(pGpu)) + { + // No, so update with our cached value + // BUG 229902, use read and update, was trashing "cache line size", even though + // HW doc says that is not mapped. + if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_CONFIG_PCI_NV_3, &data)) + { + return NV_ERR_GENERIC; + } + data = FLD_SET_DRF_NUM(_CONFIG, _PCI_NV_3, _LATENCY_TIMER, pKernelMc->LatencyTimerControl.LatencyTimerValue, data); + GPU_BUS_CFG_WR32(pGpu, NV_CONFIG_PCI_NV_3, data); + } + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c new file mode 100644 index 000000000..f8cb53afe --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/heap.h" +#include "gpu/mem_mgr/mem_desc.h" + +#include "nvRmReg.h" + +#include "kernel/gpu/intr/intr.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/vgpu_events.h" + +/*! + * Returns the max context size + * + * @returns NvU64 + */ +NvU64 +memmgrGetMaxContextSize_AD102 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NvU64 size = memmgrGetMaxContextSize_GA100(pGpu, pMemoryManager); + + + if (RMCFG_FEATURE_PLATFORM_MODS) + { + size += 64 * 1024 * 1024; + } + return size; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c new file mode 100644 index 000000000..d30881ab5 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A + + +/*! + * Function to verify which memory scubber (fast/slow) has to use in Hopper+ for scrubbering + * + * @param[in] copyClass DMA ccopy class + * @param[in] bIsVirtualMemory Memory type + * @param[in] addr Offset of address + * @param[in] size Size of the region to scrub + * @param[in] dstAddressSpace DST address space + * + * @returns NV_TRUE - Use memory fast scrbber for scrubbing + * NV_FALSE - Use slow scrubber + */ +NvBool +memmgrMemUtilsCheckMemoryFastScrubEnable_GH100 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 copyClass, + NvBool bIsVirtualMemory, + RmPhysAddr addr, + NvU32 size, + NV_ADDRESS_SPACE dstAddressSpace +) +{ + if (!memmgrIsFastScrubberEnabled(pMemoryManager)) + { + return NV_FALSE; + } + + // + // Enable the memory fast scrubbing only when + // Class == HOPPER_DMA_COPY_A or later + // DstType == PHYSICAL + // DstPhysMode.target == LOCAL_FB + // Address is 4KB aligned + // LineLength is 4KB aligned + // + return ((copyClass == HOPPER_DMA_COPY_A + ) && + (!bIsVirtualMemory) && + (dstAddressSpace == ADDR_FBMEM) && + (NV_IS_ALIGNED64(addr, MEMUTIL_SCRUB_OFFSET_ALIGNMENT)) && + (NV_IS_ALIGNED(size, MEMUTIL_SCRUB_LINE_LENGTH_ALIGNMENT))); +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c new file mode 100644 index 000000000..9c6fe8779 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c @@ -0,0 +1,214 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/virt_mem_allocator.h" +#include "gpu/bus/kern_bus.h" +#include "published/hopper/gh100/dev_mmu.h" + +/*! + * @brief Setup mappings needed for a BAR1 P2P surface + * For BAR1 P2P surface mapping, RM needs to create an internal BAR1 mapping on the target GPU, and + * create a ADDR_SYSMEM mapping from the source GPU VA space to this newly created BAR1 region. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pDma VirtMemAllocator pointer + * @param[in/out] params BAR1 P2P mapping parameters + * + * @returns + * NV_OK if it creates the BAR1 P2P surface. + */ +NV_STATUS +dmaAllocBar1P2PMapping_GH100 +( + OBJGPU *pGpu, + VirtMemAllocator *pDma, + DMA_BAR1P2P_MAPPING_PRARAMS *params +) +{ + MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc = NULL; // The peer GPU BAR1 region mapped for BAR1 P2P + MEMORY_DESCRIPTOR *pBar1P2PPhysMemDesc = NULL; // The peer GPU vidmem sub region + NvU64 phyAddr = 0; // BAR1 offset of SPA addresses + NvU64 bar1PhyAddr = 0; // BAR1 aperture SPA addresses + NvU64 bar1ApertureLen = 0; // BAR1 aperture mapped lengths + OBJGPU *pPeerGpu = NULL; + KernelBus *pPeerKernelBus = NULL; + NvHandle hClient = NV01_NULL_OBJECT; + NV_STATUS status = NV_OK; + + if (params == NULL || + params->pVas == NULL || + params->pPeerGpu == NULL || + params->pPeerMemDesc == NULL || + params->pDmaMappingInfo == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pPeerGpu = params->pPeerGpu; + pPeerKernelBus = GPU_GET_KERNEL_BUS(pPeerGpu); + + // + // Step 1: + // Create sub memory descriptor from the memory source (on target GPU) that need to map. + // + status = memdescCreateSubMem(&pBar1P2PPhysMemDesc, params->pPeerMemDesc, pPeerGpu, params->offset, params->length); + if (status != NV_OK) + return status; + + bar1ApertureLen = params->length; + + // Setup special PTE type for this memory + memdescSetPteKind(pBar1P2PPhysMemDesc, NV_MMU_PTE_KIND_GENERIC_MEMORY); + + // + // Step 2: + // Create BAR1 mapping with MAP_BAR1_P2P flag on the target GPU. + // + status = kbusMapFbAperture_HAL(pPeerGpu, pPeerKernelBus, + pBar1P2PPhysMemDesc, + 0, + &phyAddr, + &bar1ApertureLen, + BUS_MAP_FB_FLAGS_MAP_UNICAST, + hClient); + if (status != NV_OK) + goto cleanup; + + bar1PhyAddr = gpumgrGetGpuPhysFbAddr(pPeerGpu) + phyAddr; + + NV_PRINTF(LEVEL_INFO, "bar1p2p surface mapped at bar1PhyAddr 0x%llx, len 0x%llx\n", + bar1PhyAddr, bar1ApertureLen); + + // + // Step 3: + // Create pGpu memory descriptor to describe the target BAR1 P2P region. + // Note: This sysmem mapping to IO device memory needs to be UNCACHED, non-coherent + // + status = memdescCreate(&pBar1P2PVirtMemDesc, + pPeerGpu, + bar1ApertureLen, + 0, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + if (status != NV_OK) + goto cleanup; + + // Copy the page size from the target/peer vidmem + memdescSetPageSize(pBar1P2PVirtMemDesc, VAS_ADDRESS_TRANSLATION(params->pVas), + memdescGetPageSize(pBar1P2PPhysMemDesc, VAS_ADDRESS_TRANSLATION(params->pVas))); + + // Set the PTE kind to be the peer mem PTE kind + memdescSetPteKind(pBar1P2PVirtMemDesc, memdescGetPteKind(pBar1P2PPhysMemDesc)); + + // Set the memory address and memory type as a SYSMEM + memdescDescribe(pBar1P2PVirtMemDesc, ADDR_SYSMEM, (RmPhysAddr)bar1PhyAddr, bar1ApertureLen); + + params->pDmaMappingInfo->pBar1P2PVirtMemDesc = pBar1P2PVirtMemDesc; + params->pDmaMappingInfo->pBar1P2PPhysMemDesc = pBar1P2PPhysMemDesc; + + // Save the MemDesc to be the newly created sysmem in the peer BAR1 aperture + params->pMemDescOut = pBar1P2PVirtMemDesc; + + // The sysmem MemDesc already added the requested offset. Set the offset to 0 + params->offsetOut = 0; + + // Override Mapping flags with PHYSICAL and no snoop + params->flagsOut = params->flags; + params->flagsOut = FLD_SET_DRF(OS46, _FLAGS, _PAGE_KIND, _PHYSICAL, params->flagsOut); + params->flagsOut = FLD_SET_DRF(OS46, _FLAGS, _CACHE_SNOOP, _DISABLE, params->flagsOut); + // It is a normal SYSMEM mapping from source GPU VA to the target GPU BAR1 region + params->flagsOut = FLD_SET_DRF(OS46, _FLAGS, _P2P_ENABLE, _NO, params->flagsOut); + + // Update the flags in the pDmaMappingInfo + params->pDmaMappingInfo->Flags = params->flagsOut; + + return NV_OK;; + +cleanup: + if (phyAddr != 0) + { + kbusUnmapFbAperture_HAL(pPeerGpu, pPeerKernelBus, + params->pPeerMemDesc, + phyAddr, + bar1ApertureLen, + BUS_MAP_FB_FLAGS_MAP_UNICAST); + } + + if (pBar1P2PPhysMemDesc) + { + memdescDestroy(pBar1P2PPhysMemDesc); + } + + if (pBar1P2PVirtMemDesc) + { + memdescDestroy(pBar1P2PVirtMemDesc); + } + + NV_PRINTF(LEVEL_ERROR, "Failed to create bar1p2p mapping\n"); + + return status; +} + +/*! + * @brief Free the resources for a BAR1 P2P surface + * + * @param[in] pDmaMappingInfo The Dma mapping info structure. + * + */ +void +dmaFreeBar1P2PMapping_GH100 +( + VirtMemAllocator *pDma, + CLI_DMA_MAPPING_INFO *pDmaMappingInfo +) +{ + if (pDmaMappingInfo == NULL) + return; + + if (pDmaMappingInfo->pBar1P2PPhysMemDesc != NULL && + pDmaMappingInfo->pBar1P2PVirtMemDesc != NULL) + { + OBJGPU *pPeerGpu = pDmaMappingInfo->pBar1P2PPhysMemDesc->pGpu; + KernelBus *pPeerKernelBus = GPU_GET_KERNEL_BUS(pPeerGpu); + NvU64 bar1PhysAddr = memdescGetPhysAddr(pDmaMappingInfo->pBar1P2PVirtMemDesc, AT_CPU, 0); + NvU64 bar1MapSize = memdescGetSize(pDmaMappingInfo->pBar1P2PVirtMemDesc); + + // Unmap the BAR1 mapping + kbusUnmapFbAperture_HAL(pPeerGpu, pPeerKernelBus, + pDmaMappingInfo->pBar1P2PPhysMemDesc, + bar1PhysAddr, + bar1MapSize, + BUS_MAP_FB_FLAGS_MAP_UNICAST); + + NV_PRINTF(LEVEL_INFO, "bar1p2p surface UN-mapped at 0x%llx + 0x%llx\n", bar1PhysAddr, bar1MapSize); + + // Destroy the source memory descriptor + memdescDestroy(pDmaMappingInfo->pBar1P2PPhysMemDesc); + + memdescDestroy(pDmaMappingInfo->pBar1P2PVirtMemDesc); + } +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index 339af8cfd..2cc940241 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -50,6 +50,7 @@ #include "class/clc637.h" // AMPERE_SMC_PARTITION_REF #include "class/cl00c2.h" // NV01_MEMORY_LOCAL_PHYSICAL #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A #include "class/cl0005.h" // NV01_EVENT #include "class/cl90f1.h" // FERMI_VASPACE_A @@ -2327,6 +2328,7 @@ _ceChannelPushMethodsBlock_GM107 NvU32 *ptr = *pPtr; NvU32 *pStartPtr = ptr; NvBool addReductionOp = channel->isChannelSynchronized; + NvBool bMemoryScrubEnable = NV_FALSE; NvU32 remapConstB = 0; NvU32 remapComponentSize = 0; @@ -2375,6 +2377,23 @@ _ceChannelPushMethodsBlock_GM107 } else { + bMemoryScrubEnable = memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pGpu, + pMemoryManager, + channel->hTdCopyClass, + channel->bUseVasForCeCopy, + dst, + NvU64_LO32(size), + dstAddressSpace); + if (bMemoryScrubEnable) + { + NV_PRINTF(LEVEL_INFO, "Using Fast memory scrubber\n"); + remapConstB = DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B); + PUSH_PAIR(NVA06F_SUBCHANNEL_COPY_ENGINE, NVB0B5_SET_REMAP_CONST_B, 0x00000000); + + remapComponentSize = DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE); + PUSH_PAIR(NVA06F_SUBCHANNEL_COPY_ENGINE, NVB0B5_LINE_LENGTH_IN, NvU64_LO32(size)); + } + else { remapComponentSize = DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _FOUR); PUSH_PAIR(NVA06F_SUBCHANNEL_COPY_ENGINE, NVB0B5_LINE_LENGTH_IN, NvU64_LO32(size >> 2)); @@ -2416,6 +2435,17 @@ _ceChannelPushMethodsBlock_GM107 launchParams |= DRF_DEF(B0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _NONE); } + if (bMemoryScrubEnable) + { + PUSH_PAIR(NVA06F_SUBCHANNEL_COPY_ENGINE, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, + DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); + + launchParams |= DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE); + launchParams |= DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE); + + PUSH_PAIR(NVA06F_SUBCHANNEL_COPY_ENGINE, NVC8B5_LAUNCH_DMA, launchParams); + } + else { if (!bMemcopy) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index 809f31514..458650147 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -1776,6 +1776,54 @@ dmaUpdateVASpace_GF100 } // Build PTE template + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfHw = 0; + NvU32 ptePcfSw = 0; + + // Set the new PTE PCF bits + if (valid) + { + nvFieldSetBool(&pFmt->pPte->fldValid, NV_TRUE, + mapIter.pteTemplate); + nvFieldSet32(&pFmt->pPte->fldAperture._enum.desc, + aperture, mapIter.pteTemplate); + nvFieldSet32(&pFmt->pPte->fldPeerIndex, peer, + mapIter.pteTemplate); + nvFieldSet32(&pFmt->pPte->fldKind, kindNoCompression, + mapIter.pteTemplate); + // + // Initializing the PTE V3 PCF bits whose default values are as follows: + // 1.Regular vs Privilege : Regular (controlled by the priv flag) + // 2.RO vs RW : RW (controlled by the readOnly flag) + // 3.Atomic Enabled vs Atomic Disabled : Atomic Enabled + // 4.Cached vs Uncached : Cached (controlled by the isVolatile flag) + // 5.ACE vs ACD : ACD + // + ptePcfSw |= isVolatile ? (1 << SW_MMU_PCF_UNCACHED_IDX) : 0; + ptePcfSw |= readOnly ? (1 << SW_MMU_PCF_RO_IDX) : 0; + ptePcfSw |= tlbLock ? (1 << SW_MMU_PCF_NOATOMIC_IDX) : 0; + ptePcfSw |= !priv ? (1 << SW_MMU_PCF_REGULAR_IDX) : 0; + } + else + { + // NV4K and NOMAPPING are not supported right now + if (bSparse) + { + ptePcfSw |= (1 << SW_MMU_PCF_SPARSE_IDX); + } + else + { + ptePcfSw |= (1 << SW_MMU_PCF_INVALID_IDX); + } + } + NV_CHECK_OR_RETURN(LEVEL_ERROR, + (kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, &ptePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + + nvFieldSet32(&pFmt->pPte->fldPtePcf, ptePcfHw, mapIter.pteTemplate); + } + else { if (bSparse) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c index aaf30691b..01dde98f9 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c @@ -51,7 +51,6 @@ static NV_STATUS _ctxdmaConstruct(ContextDma *pContextDma, RsClient *, NvHandle, NvU32, NvU32, RsResourceRef *, NvU64, NvU64); static NV_STATUS _ctxdmaDestruct(ContextDma *pContextDma, NvHandle hClient); -static void _ctxdmaDestroyBindings(RsClient *pClient, ContextDma *pContextDma, OBJGPU *pGpu); static void _ctxdmaDestroyFBMappings @@ -319,7 +318,6 @@ _ctxdmaDestruct NvHandle hClient ) { - RsClient *pClient = RES_GET_CLIENT(pContextDma); NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = NULL; @@ -344,7 +342,8 @@ _ctxdmaDestruct } // Clean-up the context, first unbind from display - _ctxdmaDestroyBindings(pClient, pContextDma, pGpu); + if (ctxdmaIsBound(pContextDma)) + dispchnUnbindCtxFromAllChannels(pGpu, pContextDma); // Handle unicast sysmem mapping mapping before _ctxdmaDestroyFBMappings() if (pContextDma->AddressSpace == ADDR_SYSMEM) @@ -374,41 +373,6 @@ _ctxdmaDestruct return rmStatus; } -static void -_ctxdmaDestroyBindings -( - RsClient *pClient, - ContextDma *pContextDma, - OBJGPU *pGpu -) -{ - NV_STATUS status; - DispObject *pDispObject; - DispChannel *pDispChannel; - RS_ITERATOR channelIt; - RsResourceRef *pResourceRef; - - if (!ctxdmaIsBound(pContextDma)) - return; - - status = dispobjGetByDevice(pClient, pContextDma->pDevice, &pDispObject); - if (status != NV_OK) - return; - - pResourceRef = RES_GET_REF(pDispObject); - - // Unbind the ctx dma from all disp channels - channelIt = clientRefIter(pClient, pResourceRef, classId(DispChannel), RS_ITERATE_CHILDREN, NV_FALSE); - - while (clientRefIterNext(channelIt.pClient, &channelIt)) - { - pDispChannel = dynamicCast(channelIt.pResourceRef->pResource, DispChannel); - - // Make sure we are not bound. Will return an error if not bound. - (void)dispchnUnbindCtx(pDispChannel, pGpu, pContextDma); - } -} - /*! * NOTE: this control call may be called at high IRQL with LOCK_BYPASS on WDDM. */ @@ -419,8 +383,6 @@ ctxdmaCtrlCmdBindContextdma_IMPL NV0002_CTRL_BIND_CONTEXTDMA_PARAMS *pBindCtxDmaParams ) { - DispChannel *pDispChannel = NULL; - RsClient *pClient = RES_GET_CLIENT(pContextDma); NvHandle hChannel = pBindCtxDmaParams->hChannel; gpuSetThreadBcState(pContextDma->pGpu, !pContextDma->bUnicast); @@ -437,23 +399,13 @@ ctxdmaCtrlCmdBindContextdma_IMPL } } - // Look-up channel given by client - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - dispchnGetByHandle(pClient, hChannel, &pDispChannel)); - - // Ensure ContextDma and DisplayChannel are on the save device - NV_CHECK_OR_RETURN(LEVEL_ERROR, pContextDma->pDevice == GPU_RES_GET_DEVICE(pDispChannel), - NV_ERR_INVALID_DEVICE); - API_GPU_FULL_POWER_SANITY_CHECK(pContextDma->pGpu, NV_TRUE, NV_FALSE); // - // Call the hal to alloc inst mem, write the ctxdma data, and write + // Call dispchn to alloc inst mem, write the ctxdma data, and write // the hash table entry. // - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, dispchnBindCtx(pDispChannel, pContextDma->pGpu, pContextDma)); - - return NV_OK; + return dispchnBindCtx(pContextDma->pGpu, pContextDma, hChannel); } /*! @@ -466,26 +418,11 @@ ctxdmaCtrlCmdUnbindContextdma_IMPL NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS *pUnbindCtxDmaParams ) { - DispChannel *pDispChannel = NULL; - RsClient *pClient = RES_GET_CLIENT(pContextDma); - NvHandle hChannel = pUnbindCtxDmaParams->hChannel; - gpuSetThreadBcState(pContextDma->pGpu, !pContextDma->bUnicast); - // Look-up channel given by client - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - dispchnGetByHandle(pClient, hChannel, &pDispChannel)); - - // Ensure ContextDma and DisplayChannel are on the save device - NV_CHECK_OR_RETURN(LEVEL_ERROR, pContextDma->pDevice == GPU_RES_GET_DEVICE(pDispChannel), - NV_ERR_INVALID_DEVICE); - API_GPU_FULL_POWER_SANITY_CHECK(pContextDma->pGpu, NV_TRUE, NV_FALSE); - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, - dispchnUnbindCtx(pDispChannel, pContextDma->pGpu, pContextDma)); - - return NV_OK; + return dispchnUnbindCtx(pContextDma->pGpu, pContextDma, pUnbindCtxDmaParams->hChannel); } static NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index 482fdc025..db4c2ce3a 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -4524,6 +4524,13 @@ heapStoreBlackList_IMPL for (i = 0; i < maxInputPages; i++) { + // + // Bug: 2999257 + // currently pre-Hopper we have 37b FB PA, whose PFN will be 25b + // From Hopper+ we have 52b PA, whose PFN will be 40b PA and hence + // the macro NV_INFOROM_BLACKLIST_PAGE_NUMBER width of 28b will not be + // sufficient to capture the entire address, this needs to be fixed. + // status = heapAddPageToBlackList(pGpu, pHeap, DRF_VAL64(_HEAP, _PAGE_OFFLINE, _PAGE_NUMBER, pPageNumbers[i]), (NvU32)DRF_VAL64(_HEAP, _PAGE_OFFLINE, _TYPE, pPageNumbers[i])); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index d20038188..cf9135261 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -895,9 +895,10 @@ _memdescAllocInternal goto done; } - memdescPrintMemdesc(pMemDesc, NV_TRUE, "memdesc allocated"); - done: + if (status == NV_OK) + memdescPrintMemdesc(pMemDesc, NV_TRUE, MAKE_NV_PRINTF_STR("memdesc allocated")); + portMemFree(pFbAllocPageFormat); portMemFree(pFbAllocInfo); @@ -951,6 +952,7 @@ memdescAlloc !gpuIsCacheOnlyModeEnabled(pGpu)) { status = NV_ERR_BROKEN_FB; + NV_PRINTF(LEVEL_ERROR, "Unsupported FB bound allocation on broken FB(0FB) platform\n"); DBG_BREAKPOINT(); } @@ -1266,7 +1268,7 @@ _memdescFreeInternal if (memdescHasSubDeviceMemDescs(pMemDesc)) return; - memdescPrintMemdesc(pMemDesc, NV_FALSE, "memdesc being freed"); + memdescPrintMemdesc(pMemDesc, NV_FALSE, MAKE_NV_PRINTF_STR("memdesc being freed")); // Bail our early in case this memdesc describes a MODS managed VPR region. if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_VPR_REGION_CLIENT_MANAGED)) @@ -2787,8 +2789,8 @@ memdescGetApertureString NV_ADDRESS_SPACE addressSpace ) { - static const char* ADDR_FBMEM_STR = "VIDEO MEMORY"; - static const char* ADDR_SYSMEM_STR = "SYSTEM MEMORY"; + static NV_PRINTF_STRING_SECTION const char ADDR_FBMEM_STR[] = "VIDEO MEMORY"; + static NV_PRINTF_STRING_SECTION const char ADDR_SYSMEM_STR[] = "SYSTEM MEMORY"; if (addressSpace == ADDR_FBMEM) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index a2c742b58..e34ad0ae7 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -33,6 +33,7 @@ #include "vgpu/rpc.h" #include "core/thread_state.h" #include "nvRmReg.h" +#include "gpu/fsp/kern_fsp.h" #include "gpu/mem_mgr/phys_mem_allocator/numa.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/rmapi/rs_utils.h" @@ -132,6 +133,12 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) pMemoryManager->bScrubOnFreeEnabled = NV_FALSE; } + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_FAST_SCRUBBER, + &data32) == NV_OK) && data32) + { + pMemoryManager->bFastScrubberEnabled = NV_FALSE; + } + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_SYSMEM_PAGE_SIZE, &data32)) { switch (data32) @@ -194,23 +201,6 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) pMemoryManager->bEnableFbsrPagedDma = !!data32; } - if (osReadRegistryDword(pGpu, - NV_REG_STR_RM_IGNORE_UPPER_MEMORY, - &data32) == NV_OK) - { - // Ignore upper memory. - pMemoryManager->bIgnoreUpperMemory = !!data32; - } - - // Allow increasing the RM reserved space. - if (osReadRegistryDword(pGpu, NV_REG_STR_BUG_1698088_WAR, &data32) == NV_OK) - { - if (data32 == NV_REG_STR_BUG_1698088_WAR_ENABLE) - { - pMemoryManager->bBug1698088IncreaseRmReserveMemoryWar = NV_TRUE; - } - } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_FBSR_FILE_MODE, &data32) == NV_OK) { if (data32 && RMCFG_FEATURE_PLATFORM_UNIX) @@ -218,31 +208,6 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) pMemoryManager->bEnableFbsrFileMode = NV_TRUE; } } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_NO_ECC_FB_SCRUB, - &data32) == NV_OK) - { - pMemoryManager->bEccScrubOverride = NV_TRUE; - } - - if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_INIT_SCRUB, - &data32) == NV_OK) && (data32)) - { - pMemoryManager->bScrubberInitialized = NV_TRUE; - } - - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_ASYNC_MEM_SCRUB, - &data32) == NV_OK) - { - // disable async scrub - pMemoryManager->bDisableAsyncScrubforMods = !!data32; - } - - if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_INCREASE_ECC_SCRUB_TIMEOUT, - &data32) == NV_OK) && (data32)) - { - // increase ECC scrub timeout - pMemoryManager->bBug1441072EccScrubWar = NV_TRUE; - } // // Override PMA enable. PDB_PROP_FB_PMA_ENABLED is reconciled with @@ -1459,6 +1424,7 @@ memmgrCalcReservedFbSpace_IMPL NvU32 idxISORegion = 0; NvU32 idxFastRegion = 0; NvU32 idxSlowRegion = 0; + NvBool bAllocProtected = NV_FALSE; // // This is a hack solely for Vista (on Vista the OS controls the majority of heap). @@ -1497,20 +1463,20 @@ memmgrCalcReservedFbSpace_IMPL // Check only non-reserved regions (which are typically unpopulated blackholes in address space) if ((!pFbRegion->bRsvdRegion) && - (!pFbRegion->bProtected) && + (bAllocProtected || !pFbRegion->bProtected) && (regionSize >= (rsvdFastSize + rsvdSlowSize + rsvdISOSize))) { // Find the fastest region if ((pFbRegion->performance > pMemoryManager->Ram.fbRegion[idxFastRegion].performance) || pMemoryManager->Ram.fbRegion[idxFastRegion].bRsvdRegion - || pMemoryManager->Ram.fbRegion[idxFastRegion].bProtected) + || (!bAllocProtected && pMemoryManager->Ram.fbRegion[idxFastRegion].bProtected)) { idxFastRegion = i; } // Find the slowest region if ((pFbRegion->performance < pMemoryManager->Ram.fbRegion[idxSlowRegion].performance) || pMemoryManager->Ram.fbRegion[idxSlowRegion].bRsvdRegion - || pMemoryManager->Ram.fbRegion[idxSlowRegion].bProtected) + || (!bAllocProtected && pMemoryManager->Ram.fbRegion[idxSlowRegion].bProtected)) { idxSlowRegion = i; } @@ -1519,7 +1485,7 @@ memmgrCalcReservedFbSpace_IMPL { if ((!pMemoryManager->Ram.fbRegion[idxISORegion].bSupportISO) || (pFbRegion->performance > pMemoryManager->Ram.fbRegion[idxISORegion].performance) - || pMemoryManager->Ram.fbRegion[idxISORegion].bProtected) + || (!bAllocProtected && pMemoryManager->Ram.fbRegion[idxISORegion].bProtected)) { idxISORegion = i; } @@ -1535,10 +1501,12 @@ memmgrCalcReservedFbSpace_IMPL NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxFastRegion].bRsvdRegion); NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxSlowRegion].bRsvdRegion); - // Can't put reserved memory in protected region - NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxISORegion].bProtected); - NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxFastRegion].bProtected); - NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxSlowRegion].bProtected); + if (!bAllocProtected) + { + NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxISORegion].bProtected); + NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxFastRegion].bProtected); + NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxSlowRegion].bProtected); + } // // Vista expects to be able to VidHeapControl allocate a cursor in ISO @@ -2407,6 +2375,7 @@ memmgrPageLevelPoolsCreate_IMPL (pFmt->version == GMMU_FMT_VERSION_1) ? POOL_CONFIG_GMMU_FMT_1 : POOL_CONFIG_GMMU_FMT_2); NV_ASSERT(NV_OK == status); + } return status; } @@ -3041,5 +3010,22 @@ memmgrReserveMemoryForFsp_IMPL MemoryManager *pMemoryManager ) { + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + + // + // If we sent FSP commands to boot ACR, we need to allocate the surfaces + // used by FSP and ACR as WPR/FRTS here from the reserved heap + // + if (pKernelFsp && (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM) && + (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK)))) + { + + // For GSP-RM flow, we don't need to allocate WPR since it is handled by CPU + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + return NV_OK; + } + + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c index b6dc6377f..676050f27 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c @@ -139,8 +139,18 @@ memmgrPreInitReservedMemory_FWCLIENT MemoryManager *pMemoryManager ) { - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvU64 tmpAddr = 0; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU64 tmpAddr = 0; + + if (pKernelDisplay) + { + // TODO: Determine the correct size of display instance memory + // via instmemGetSize_HAL(), as well as other parameters. + // I.e. refactor and leverage the code performing these tasks + // in memmgrPreInitReservedMemory_GM107() today. + tmpAddr += 0x10000; + } if (KBUS_BAR2_ENABLED(pKernelBus)) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index 28a8a61ca..3cd8674a4 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -52,6 +52,10 @@ #include "class/clc6b5.h" // AMPERE_DMA_COPY_A #include "class/clc7b5.h" // AMPERE_DMA_COPY_B +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A + +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A + static NvU64 _scrubCheckProgress(OBJMEMSCRUB *pScrubber); static void _scrubSetupChannelBufferSizes(OBJCHANNEL *pChannel, NvU32 numCopyBlocks); static NvU64 _searchScrubList(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size); @@ -145,6 +149,12 @@ scrubberConstruct pChannel->bUseVasForCeCopy = memmgrUseVasForCeMemoryOps(pMemoryManager); memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pChannel->hTdCopyClass); + if (((pChannel->hTdCopyClass == HOPPER_DMA_COPY_A) + ) && !pChannel->bUseVasForCeCopy) + { + pChannel->type = FAST_SCRUBBER_CHANNEL; + } + NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, &pChannel->hClient), freeChannelObject); @@ -1235,6 +1245,118 @@ _scrubFillPb return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); } +/** single helper function to fill the push buffer with the methods needed for + memsetting using fast memory scrubber in CE. This function is much more efficient than + normal CE scrubber operation + TODO: Add support for memcopy here based on channel type. + */ +static NvU32 +_fastscrubFillPb +( + OBJCHANNEL *pChannel, + RmPhysAddr base, + NvU32 size, + NvU32 payload, + NvBool bPipelined, + NV_ADDRESS_SPACE dstAddressSpace, + NvU32 dstCpuCacheAttrib, + NvBool bInsertFinishpayload, + NvBool bNonStallInterrupt, + NvU32 putIndex +) +{ + NvU32 semaValue = 0; + NvU32 pipelinedValue = 0; + NvU32 *pPtr = (NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + NvU32 *pStartPtr = pPtr; + NvU32 data = 0; + NvU64 pSemaAddr = 0; + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, + putIndex * pChannel->methodSizePerBlock); + + // SET OBJECT + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SET_OBJECT, pChannel->classEngineID); + + // Set Pattern for Memset + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_A, MEMSET_PATTERN); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_B, MEMSET_PATTERN); + + // Set Component Size to 1 + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_COMPONENTS, + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_DST_PHYS_MODE, + DRF_DEF(C8B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB)); + + semaValue = (bInsertFinishpayload) ? + DRF_DEF(C8B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; + + if (bPipelined) + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); + else + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); + + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, + DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(base)), + NVC8B5_OFFSET_OUT_LOWER, + DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(base))); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, size); + + if (semaValue) + { + NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, + DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_B, + DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_PAYLOAD, + payload); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, + DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LAUNCH_DMA, + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL) | + pipelinedValue | + semaValue); + + // + // This should always be at the bottom the push buffer segment, since this + // denotes that HOST has read all the methods needed for this memory operation + // and safely assume that this GPFIFO and PB entry can be reused. + // + data = DRF_DEF(C86F, _SEM_EXECUTE, _OPERATION, _RELEASE) | + DRF_DEF(C86F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | + DRF_DEF(C86F, _SEM_EXECUTE, _RELEASE_WFI, _DIS); + + pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); + + NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, + DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), + NVC86F_SEM_ADDR_HI, + DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), + NVC86F_SEM_PAYLOAD_LO, putIndex, + NVC86F_SEM_PAYLOAD_HI, 0); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SEM_EXECUTE, data); + + // typecasting to calculate the bytes consumed by this iteration. + return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); +} + /** helper function which waits for a PB & GPFIO entry to be read by HOST. * After the HOST reads GPFIFO and PB entry, the semaphore will be released. */ @@ -1358,6 +1480,7 @@ _scrubMemory NvU32 putIndex = 0; NV_STATUS status = NV_OK; NvU32 methodsLength = 0; + NvBool bFastScrubEnable = NV_FALSE; do { @@ -1367,6 +1490,21 @@ _scrubMemory putIndex = _scrubWaitForFreeEntry(pChannel); NV_PRINTF(LEVEL_INFO, "Put Index: %x\n", putIndex); + // Fill PB with methods + bFastScrubEnable = memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pChannel->pGpu, + GPU_GET_MEMORY_MANAGER(pChannel->pGpu), pChannel->hTdCopyClass, + pChannel->bUseVasForCeCopy, base, tempMemsetSize, + dstAddressSpace); + + if (bFastScrubEnable) + { + NV_PRINTF(LEVEL_INFO, "Fast Scrubber enabled!\n"); + methodsLength = _fastscrubFillPb(pChannel, base, tempMemsetSize, payload, + bFirstIteration, dstAddressSpace, + dstCpuCacheAttrib, (tempMemsetSize == size), + bNonStallInterrupt, putIndex); + } + else { NV_PRINTF(LEVEL_INFO, "Fast Scrubber not enabled!\n"); methodsLength = _scrubFillPb(pChannel, base, tempMemsetSize, payload, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index 3159626a8..b1847c5ba 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -861,7 +861,7 @@ _pmaPredictOutOfMemory /*! * @brief Internal function to intermittently free the blacklisted pages in the * range of allocation request. This will enable PMA to allow OS to manage those - * blacklisted pages after being allocated. + * blacklisted pages after being allocated. * * @param[in] pPma PMA Object * @param[in] regId PMA Region ID , where the allocation falls into diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index 57ab83ca7..83df1a5d0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -523,9 +523,19 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) } destroyMemDesc(pDevice, hVASpace); + if ((vaspaceGetFlags(pVaspaceApi->pVASpace) & VASPACE_FLAGS_FLA)) + { + if (GPU_GET_KERNEL_BUS(pGpu)->flaInfo.pFlaVAS == NULL) + { + NV_PRINTF(LEVEL_INFO, "Skipping Legacy FLA vaspace destruct, gpu:%x \n", + pGpu->gpuInstance); + goto skip_destroy; + } + } vmmDestroyVaspace(pVmm, pVaspaceApi->pVASpace); +skip_destroy: // // RS-TODO: Move out to freeWithResServ? // diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c new file mode 100644 index 000000000..5a79675cd --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -0,0 +1,493 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "os/os.h" +#include "kernel/gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/bus/kern_bus.h" + +#include "published/hopper/gh100/dev_fb.h" +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/pri_nv_xal_ep.h" +#include "published/hopper/gh100/dev_nv_xal_addendum.h" + +NV_STATUS +kmemsysDoCacheOp_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 reg, + NvU32 regValue, + NvU32 pollMask, + PRMTIMEOUT pTimeout +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 cnt = 0; + NV_STATUS timeoutStatus = NV_OK; + NvU32 tokenRangeMask = 0; + NvU32 startToken = 0; + NvU32 completedToken = 0; + NvBool bMemopBusy = NV_TRUE; + + if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) + { + // + // When the GPU is lost we cannot expect to successfully do cache + // maintenance (see Bug 1557278). + // + return rmStatus; + } + + switch (reg) + { + case NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY: + tokenRangeMask = DRF_MASK(NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN); + + startToken = GPU_REG_RD32(pGpu, NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY); + startToken = DRF_VAL( _XAL_EP_UFLUSH, _L2_FLUSH_DIRTY, _TOKEN, startToken); + break; + + case NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS: + tokenRangeMask = DRF_MASK(NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN); + + startToken = GPU_REG_RD32(pGpu, NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS); + startToken = DRF_VAL( _XAL_EP_UFLUSH, _L2_CLEAN_COMPTAGS, _TOKEN, startToken); + break; + + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE: + tokenRangeMask = DRF_MASK(NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN); + + startToken = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE); + startToken = DRF_VAL( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_SYSMEM_INVALIDATE, _TOKEN, startToken); + break; + + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE: + tokenRangeMask = DRF_MASK(NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN); + + startToken = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE); + startToken = DRF_VAL( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_PEERMEM_INVALIDATE, _TOKEN, startToken); + break; + + default: + return NV_ERR_NOT_SUPPORTED; + } + + while(1) + { + switch (reg) + { + case NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY: + completedToken = GPU_REG_RD32(pGpu, NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED); + + bMemopBusy = FLD_TEST_DRF(_XAL_EP_UFLUSH, _L2_FLUSH_DIRTY_COMPLETED, _STATUS, _BUSY, completedToken) + ? NV_TRUE : NV_FALSE; + + completedToken = DRF_VAL( _XAL_EP_UFLUSH, _L2_FLUSH_DIRTY_COMPLETED, _TOKEN, completedToken); + break; + + case NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS: + completedToken = GPU_REG_RD32(pGpu, NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED); + + bMemopBusy = FLD_TEST_DRF(_XAL_EP_UFLUSH, _L2_CLEAN_COMPTAGS_COMPLETED, _STATUS, _BUSY, completedToken) + ? NV_TRUE : NV_FALSE; + + completedToken = DRF_VAL( _XAL_EP_UFLUSH, _L2_CLEAN_COMPTAGS_COMPLETED, _TOKEN, completedToken); + break; + + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE: + completedToken = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED); + + bMemopBusy = FLD_TEST_DRF( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED, _STATUS, _BUSY, completedToken) + ? NV_TRUE : NV_FALSE; + + completedToken = DRF_VAL( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED, _TOKEN, completedToken); + break; + + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE: + completedToken = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED); + + bMemopBusy = FLD_TEST_DRF( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED, _STATUS, _BUSY, completedToken) + ? NV_TRUE : NV_FALSE; + + completedToken = DRF_VAL( _VIRTUAL_FUNCTION, _PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED, _TOKEN, completedToken); + break; + } + + if (bMemopBusy == NV_FALSE) + { + break; + } + + // + // When completedToken > startToken(including the wrapping around case), due to the nature + // of unsigned number, the value of "(startToken - completeToken) & tokenRangeMask" will be + // at top of token range which will be bigger than NV_XAL_EP_MEMOP_MAX_OUTSTANDING. So it + // will break out from the loop. + // + // The loop will wait only when completedToken in the range of + // [startToken-NV_XAL_EP_MEMOP_MAX_OUTSTANDING, startToken]. + // + if (((startToken - completedToken) & tokenRangeMask) > NV_XAL_EP_MEMOP_MAX_OUTSTANDING) + { + break; + } + + if (timeoutStatus == NV_ERR_TIMEOUT) + { + // + // This should not timeout, except for a HW bug. Famous last words. + // On !DEBUG we just keep trucking, it's the best we can do. + // + NV_PRINTF(LEVEL_ERROR, + "- timeout error waiting for reg 0x%x update cnt=%d\n", + reg, cnt); + rmStatus = NV_ERR_TIMEOUT; + DBG_BREAKPOINT(); + break; + } + else if ( API_GPU_IN_RESET_SANITY_CHECK(pGpu) || + !API_GPU_ATTACHED_SANITY_CHECK(pGpu)) + { + // + // The GPU is in full chip reset, or has fallen off the bus + // Just return + // + return NV_OK; + } + + timeoutStatus = gpuCheckTimeout(pGpu, pTimeout); + osSpinLoop(); + cnt++; + } + +#ifdef DEBUG + if (cnt > 1) + { + NvU32 intr0 = 0; + intr0 = GPU_REG_RD32(pGpu, NV_XAL_EP_INTR_0); + NV_ASSERT(DRF_VAL(_XAL_EP, _INTR_0, _FB_ACK_TIMEOUT, intr0) != NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING); + } +#endif // DEBUG + + return rmStatus; +} + +/** + * @brief L2 Cache management OPs + * + * GK20A/T124 have a writeback L2 cache, so the cache ops are slightly + * different than those of Fermi/Kepler. Specifically, we can write back dirty + * lines to system memory. + * + * @param pMemDesc + * @param targetMem + * @param cacheOp + */ +NV_STATUS +kmemsysCacheOp_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + PMEMORY_DESCRIPTOR pMemDesc, + FB_CACHE_MEMTYPE targetMem, + FB_CACHE_OP cacheOp +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout = {0, }; + NvU32 reg = 0; + + if ((targetMem == FB_CACHE_MEM_UNDEFINED) && pMemDesc) + { + targetMem = (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) ? + FB_CACHE_VIDEO_MEMORY : FB_CACHE_SYSTEM_MEMORY; + } + + if ((cacheOp == FB_CACHE_OP_UNDEFINED) || (targetMem == FB_CACHE_MEM_UNDEFINED)) + { + NV_PRINTF(LEVEL_ERROR, "called with null %s\n", + cacheOp ? "cache operation" : "memory target"); + DBG_BREAKPOINT(); + return status; // return NV_OK + } + + // For GK20A, an explicit sysmembar flush is needed before L2 cache flush operation. + // Refer GK20A LTC IAS (section 5.5) + kbusSendSysmembarSingle_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + // Wait for the flush to flow through + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + switch (targetMem) + { + case FB_CACHE_SYSTEM_MEMORY: + if (cacheOp == FB_CACHE_INVALIDATE) + { + NV_PRINTF(LEVEL_INFO, + "Invalidate not supported, promoting to an evict (writeback + " + "invalidate clean lines).\n"); + cacheOp = FB_CACHE_EVICT; + } + + if (cacheOp == FB_CACHE_WRITEBACK || cacheOp == FB_CACHE_EVICT) + { + reg = NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY; + status = kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, reg, 0, 0, &timeout); + } + + if (cacheOp == FB_CACHE_EVICT) + { + // + // Ideally we should use NV_UFLUSH_L2_INVALIDATE_CLEAN_LINES. + // But NV_UFLUSH_L2_INVALIDATE_CLEAN_LINES is not defined on desktop GPUs. + // NV_UFLUSH_L2_SYSMEM_INVALIDATE is same as NV_UFLUSH_L2_INVALIDATE_CLEAN_LINES, and is defined in all chips. + // For Hopper, it is changed to NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE + // + reg = NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE; + status = kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, reg, 0, 0, &timeout); + } + break; + + case FB_CACHE_VIDEO_MEMORY: + if (cacheOp == FB_CACHE_EVICT) + { + NvU32 flags = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | + NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flags); + } + else if (cacheOp == FB_CACHE_INVALIDATE) + { + NvU32 flags = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL; + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flags); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + break; + + case FB_CACHE_PEER_MEMORY: + // + // for GF100 - for sysmem cache only invalidate operation is supported + // evict = writeback+invalidate is reduced to invalidate for GF100 + // + if((cacheOp != FB_CACHE_INVALIDATE) && (cacheOp != FB_CACHE_EVICT)) + { + return NV_OK; + } + + reg = NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE; + status = kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, reg, 0, 0, &timeout); + break; + + case FB_CACHE_COMPTAG_MEMORY: + if(cacheOp != FB_CACHE_WRITEBACK && cacheOp != FB_CACHE_EVICT) + { + return NV_OK; + } + + // + // Beware of HW bug 545242. Graphics should be idle and flushed here + // or comp tag cache could be corrupted. When mods uses this call + // during verif, this should already be the case. + // + reg = NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS; + status = kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, reg, 0, 0, &timeout); + break; + + case FB_CACHE_DIRTY: + if(cacheOp != FB_CACHE_WRITEBACK && cacheOp != FB_CACHE_EVICT) + { + return NV_OK; + } + + reg = NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY; + status = kmemsysDoCacheOp_HAL(pGpu, pKernelMemorySystem, reg, 0, 0, &timeout); + break; + + case FB_CACHE_DIRTY_ALL: + if(cacheOp != FB_CACHE_EVICT) + { + return NV_OK; + } + + status = kmemsysSendFlushL2AllRamsAndCaches(pGpu, pKernelMemorySystem); + break; + + default: + // return OK for other memory targets + status = NV_OK; + break; + } + + return status; +} + +/*! + * @brief Write the sysmemFlushBuffer val into the NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR register + * + * @param[in] pGpu OBJGPU pointer + * @param[in[ pKernelMemorySystem KernelMemorySystem pointer + * + * @returns void + */ +void +kmemsysProgramSysmemFlushBuffer_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NvU32 alignedSysmemFlushBufferAddr = 0x0; + NvU32 alignedSysmemFlushBufferAddrHi = 0x0; + + NV_ASSERT(pKernelMemorySystem->sysmemFlushBuffer != 0); + + // alignedSysmemFlushBufferAddr will have the lower 32 bits of the buffer address + alignedSysmemFlushBufferAddr = NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer); + + // alignedSysmemFlushBufferAddrHi will have the upper 32 bits of the buffer address + alignedSysmemFlushBufferAddrHi = NvU64_HI32(pKernelMemorySystem->sysmemFlushBuffer); + + // Assert when Sysmem Flush buffer has more than 52-bit address + NV_ASSERT((alignedSysmemFlushBufferAddrHi & (~NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK)) == 0); + + alignedSysmemFlushBufferAddrHi &= NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK; + + GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, _ADR, alignedSysmemFlushBufferAddrHi); + GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO, _ADR, alignedSysmemFlushBufferAddr); +} + +/* + * @brief Initialize the sysmem flush buffer + * + * Setting up the sysmem flush buffer needs to be done very early in some cases + * as it's required for the GPU to perform a system flush. One such case is + * resetting GPU FALCONs and in particular resetting the PMU as part of VBIOS + * init. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + */ +NV_STATUS +kmemsysInitFlushSysmemBuffer_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NV_STATUS status; + + // + // In case of suspend/resume, the buffer might be already allocated, but + // the HW still needs to be programmed below. + // + if (pKernelMemorySystem->pSysmemFlushBufferMemDesc == NULL) + { + // + // Sysmem flush buffer + // The sysmembar flush does a zero byte read of sysmem if there was a + // sysmem write since the last flush. The actual memory does have + // to be valid and allocated at all times because an actual read may + // be issued (observed on e.g. GF108). + // + status = memdescCreate(&pKernelMemorySystem->pSysmemFlushBufferMemDesc, + pGpu, RM_PAGE_SIZE, + (1 << NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT), + NV_TRUE, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + if (status != NV_OK) + return status; + + status = memdescAlloc(pKernelMemorySystem->pSysmemFlushBufferMemDesc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Could not allocate sysmem flush buffer: %x\n", status); + DBG_BREAKPOINT(); + return status; + } + + pKernelMemorySystem->sysmemFlushBuffer = memdescGetPhysAddr(pKernelMemorySystem->pSysmemFlushBufferMemDesc, AT_GPU, 0); + } + + kmemsysProgramSysmemFlushBuffer_HAL(pGpu, pKernelMemorySystem); + return NV_OK; +} + +/*! + * @brief Validate the sysmemFlushBuffer val and assert + * + * @param[in] pGpu OBJGPU pointer + * @param[in[ pKernelMemorySystem KernelMemorySystem pointer + * + * @returns void + */ +void +kmemsysAssertSysmemFlushBufferValid_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NV_ASSERT((GPU_REG_RD_DRF(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO, _ADR) != 0) || + (GPU_REG_RD_DRF(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, _ADR) != 0)); +} + +/* + * @brief Function to map swizzId to VMMU Segments + */ +NV_STATUS +kmemsysSwizzIdToVmmuSegmentsRange_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 swizzId, + NvU32 vmmuSegmentSize, + NvU32 totalVmmuSegments +) +{ + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU64 startingVmmuSegment; + NvU64 memSizeInVmmuSegment; + + NV_ASSERT_OR_RETURN(swizzId < KMIGMGR_MAX_GPU_SWIZZID, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pStaticInfo->pSwizzIdFbMemPageRanges != NULL, NV_ERR_INVALID_STATE); + + startingVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; + memSizeInVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].hi - + pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; + NV_ASSERT_OR_RETURN((memSizeInVmmuSegment <= totalVmmuSegments), NV_ERR_INVALID_STATE); + + NV_ASSERT_OK_OR_RETURN( + kmemsysInitMIGGPUInstanceMemConfigForSwizzId(pGpu, pKernelMemorySystem, swizzId, startingVmmuSegment, memSizeInVmmuSegment)); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index 3252ccd94..83cb36924 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -31,6 +31,7 @@ #include "gpu/bus/kern_bus.h" #include "os/os.h" #include "nvRmReg.h" +#include "gpu/gsp/gsp_static_config.h" NV_STATUS kmemsysConstructEngine_IMPL @@ -582,10 +583,6 @@ kmemsysSetupCoherentCpuLink_IMPL NvU32 data32; NvBool bCpuMapping; - // - // Compute coherent link aperture range for SHH and P9 (!NV_VERIF_FEATURES) to enable - // FB access via coherent link(Nvlink/C2C) path - // { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, &pKernelMemorySystem->coherentCpuFbBase, @@ -638,8 +635,6 @@ kmemsysSetupCoherentCpuLink_IMPL // Switch the toggle for coherent link mapping only if migration is successful pGpu->setProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING, NV_TRUE); - NV_ASSERT_OK_OR_RETURN(kbusVerifyCoherentLink_HAL(pGpu, pKernelBus)); - // // TODO clean up with bug 2020982 // RM: Encapsulate NUMA-specific kernel code and logic in a new object diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c new file mode 100644 index 000000000..3b84ae462 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c @@ -0,0 +1,143 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/mem_mgr/heap.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" + +/*! + * @brief Function to determine whether gpu instance flags are valid + * for this GPU + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] gpuInstanceFlag NV2080_CTRL_GPU_PARTITION_FLAG_* + * + * @return Returns true if flags are valid + */ +NvBool +kmigmgrIsGPUInstanceFlagValid_GH100 +( + OBJGPU *pGpu, + KernelMIGManager *pGrMgr, + NvU32 gpuInstanceFlag +) +{ + NvU32 memSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, + _MEMORY_SIZE, gpuInstanceFlag); + NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, + _COMPUTE_SIZE, gpuInstanceFlag); + + switch (memSizeFlag) + { + case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL: + case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF: + case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER: + case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH: + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unrecognized GPU mem partitioning flag 0x%x\n", + memSizeFlag); + return NV_FALSE; + } + + switch (computeSizeFlag) + { + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unrecognized GPU compute partitioning flag 0x%x\n", + computeSizeFlag); + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Function to determine whether gpu instance flag combinations are valid + * for this GPU + */ +NvBool +kmigmgrIsGPUInstanceCombinationValid_GH100 +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 gpuInstanceFlag +) +{ + NvU32 memSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, gpuInstanceFlag); + NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, gpuInstanceFlag); + + if (!kmigmgrIsGPUInstanceFlagValid_HAL(pGpu, pKernelMIGManager, gpuInstanceFlag)) + { + return NV_FALSE; + } + + // JPG_OFA profile is only available on the smallest partition + if (FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA, _ENABLE, gpuInstanceFlag)) + { + if (computeSizeFlag != NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH) + { + return NV_FALSE; + } + } + + switch (computeSizeFlag) + { + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL, + NV_FALSE); + break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF, + NV_FALSE); + break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF, + NV_FALSE); + break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER, + NV_FALSE); + break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: + // TODO: Add in extra check once NVML supports MINI_QUARTER being broadcast + return NV_FALSE; + break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH, + NV_FALSE); + break; + default: + NV_ASSERT(0); + return NV_FALSE; + } + return NV_TRUE; +} diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index 57304bb03..1ea0f871a 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -33,6 +33,7 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/gpu/mem_mgr/heap.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" #include "rmapi/client.h" #include "rmapi/rs_utils.h" #include "rmapi/rmapi_utils.h" @@ -43,6 +44,7 @@ #include "kernel/core/locks.h" #include "nv_ref.h" #include "nvRmReg.h" +#include "class/cl503b.h" struct KERNEL_MIG_MANAGER_PRIVATE_DATA { @@ -610,6 +612,10 @@ kmigmgrDestruct_IMPL pKernelMIGManager->pPrivate->staticInfo.pProfiles = NULL; portMemFree(pKernelMIGManager->pPrivate->staticInfo.pSwizzIdFbMemPageRanges); pKernelMIGManager->pPrivate->staticInfo.pSwizzIdFbMemPageRanges = NULL; + portMemFree(pKernelMIGManager->pPrivate->staticInfo.pCIProfiles); + pKernelMIGManager->pPrivate->staticInfo.pCIProfiles = NULL; + portMemFree(pKernelMIGManager->pPrivate->staticInfo.pSkylineInfo); + pKernelMIGManager->pPrivate->staticInfo.pSkylineInfo = NULL; portMemFree(pKernelMIGManager->pPrivate); pKernelMIGManager->pPrivate = NULL; @@ -690,14 +696,39 @@ _kmigmgrHandlePostSchedulingEnableCallback NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memmgrSetPartitionableMem_HAL(pGpu, pMemoryManager)); - if (IS_MIG_ENABLED(pGpu)) + if (!IS_MIG_ENABLED(pGpu) && !IS_VIRTUAL(pGpu) && gpumgrIsSystemMIGEnabled(gpuGetDBDF(pGpu)) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) { - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS params; + + if ((pKernelMIGManager == NULL) || !kmigmgrIsMIGSupported(pGpu, pKernelMIGManager)) + { + NV_PRINTF(LEVEL_INFO, "MIG not supported on this GPU.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + portMemSet(¶ms, 0x0, sizeof(params)); + params.partitioningMode = NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE, + ¶ms, + sizeof(params))); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrSetPartitioningMode(pGpu, pKernelMIGManager)); + } + if (IS_MIG_ENABLED(pGpu)) + { // // Populate static GPU instance memory config which will be used to manage // GPU instance memory // + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); // Initialize static info derived from physical RM @@ -1064,6 +1095,22 @@ kmigmgrLoadStaticInfo_KERNEL sizeof(*pPrivate->staticInfo.pPartitionableEngines)), failed); + pPrivate->staticInfo.pSkylineInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSkylineInfo)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pPrivate->staticInfo.pSkylineInfo != NULL, + status = NV_ERR_NO_MEMORY; + goto failed;); + portMemSet(pPrivate->staticInfo.pSkylineInfo, 0x0, sizeof(*pPrivate->staticInfo.pSkylineInfo)); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO, + pPrivate->staticInfo.pSkylineInfo, + sizeof(*pPrivate->staticInfo.pSkylineInfo)), + failed); + pPrivate->staticInfo.pProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pProfiles)); NV_CHECK_OR_ELSE(LEVEL_ERROR, pPrivate->staticInfo.pProfiles != NULL, @@ -1106,6 +1153,22 @@ kmigmgrLoadStaticInfo_KERNEL NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, status, failed); } + pPrivate->staticInfo.pCIProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pCIProfiles)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pPrivate->staticInfo.pCIProfiles != NULL, + status = NV_ERR_NO_MEMORY; + goto failed;); + portMemSet(pPrivate->staticInfo.pCIProfiles, 0x0, sizeof(*pPrivate->staticInfo.pCIProfiles)); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES, + pPrivate->staticInfo.pCIProfiles, + sizeof(*pPrivate->staticInfo.pCIProfiles)), + failed); + return status; failed: @@ -1115,6 +1178,10 @@ kmigmgrLoadStaticInfo_KERNEL pPrivate->staticInfo.pProfiles = NULL; portMemFree(pPrivate->staticInfo.pSwizzIdFbMemPageRanges); pPrivate->staticInfo.pSwizzIdFbMemPageRanges = NULL; + portMemFree(pPrivate->staticInfo.pCIProfiles); + pPrivate->staticInfo.pCIProfiles = NULL; + portMemFree(pKernelMIGManager->pPrivate->staticInfo.pSkylineInfo); + pKernelMIGManager->pPrivate->staticInfo.pSkylineInfo = NULL; pPrivate->bInitialized = NV_FALSE; @@ -1851,7 +1918,7 @@ kmigmgrRestoreFromPersistence_PF cleanup); portMemSet(pExecPartImportParams, 0, sizeof(*pExecPartImportParams)); - pExecPartImportParams->id = CIIdx; + pExecPartImportParams->id = pComputeInstanceSave->id; portMemCopy(&pExecPartImportParams->info, sizeof(pExecPartImportParams->info), &pComputeInstanceSave->ciInfo, sizeof(pComputeInstanceSave->ciInfo)); @@ -2116,7 +2183,7 @@ kmigmgrIsClientUsingDeviceProfiling_IMPL subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice), return NV_FALSE; ); - NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + NV_CHECK_OK_OR_ELSE(status, LEVEL_SILENT, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription), return NV_FALSE; ); @@ -2193,7 +2260,7 @@ kmigmgrGetInstanceRefFromClient_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription)); @@ -2887,6 +2954,13 @@ kmigmgrSetPartitioningMode_IMPL { // Initialize static info derived from physical RM NV_ASSERT_OK_OR_RETURN(kmigmgrLoadStaticInfo_HAL(pGpu, pKernelMIGManager)); + + // + // Populate static GPU instance memory config which will be used to manage + // GPU instance memory + // + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); } return NV_OK; @@ -3084,16 +3158,17 @@ kmigmgrDescribeGPUInstances_IMPL pParams->partitionDescs[entryCount].memorySize = rangeLength(addrRange); } - pParams->partitionDescs[entryCount].partitionFlag = pStaticInfo->pProfiles->table[i].partitionFlag; - pParams->partitionDescs[entryCount].grCount = pStaticInfo->pProfiles->table[i].grCount; - pParams->partitionDescs[entryCount].gpcCount = pStaticInfo->pProfiles->table[i].gpcCount; - pParams->partitionDescs[entryCount].veidCount = pStaticInfo->pProfiles->table[i].veidCount; - pParams->partitionDescs[entryCount].smCount = pStaticInfo->pProfiles->table[i].smCount; - pParams->partitionDescs[entryCount].ceCount = pStaticInfo->pProfiles->table[i].ceCount; - pParams->partitionDescs[entryCount].nvEncCount = pStaticInfo->pProfiles->table[i].nvEncCount; - pParams->partitionDescs[entryCount].nvDecCount = pStaticInfo->pProfiles->table[i].nvDecCount; - pParams->partitionDescs[entryCount].nvJpgCount = pStaticInfo->pProfiles->table[i].nvJpgCount; - pParams->partitionDescs[entryCount].nvOfaCount = pStaticInfo->pProfiles->table[i].nvOfaCount; + pParams->partitionDescs[entryCount].partitionFlag = pStaticInfo->pProfiles->table[i].partitionFlag; + pParams->partitionDescs[entryCount].grCount = pStaticInfo->pProfiles->table[i].grCount; + pParams->partitionDescs[entryCount].gpcCount = pStaticInfo->pProfiles->table[i].gpcCount; + pParams->partitionDescs[entryCount].virtualGpcCount = pStaticInfo->pProfiles->table[i].virtualGpcCount; + pParams->partitionDescs[entryCount].veidCount = pStaticInfo->pProfiles->table[i].veidCount; + pParams->partitionDescs[entryCount].smCount = pStaticInfo->pProfiles->table[i].smCount; + pParams->partitionDescs[entryCount].ceCount = pStaticInfo->pProfiles->table[i].ceCount; + pParams->partitionDescs[entryCount].nvEncCount = pStaticInfo->pProfiles->table[i].nvEncCount; + pParams->partitionDescs[entryCount].nvDecCount = pStaticInfo->pProfiles->table[i].nvDecCount; + pParams->partitionDescs[entryCount].nvJpgCount = pStaticInfo->pProfiles->table[i].nvJpgCount; + pParams->partitionDescs[entryCount].nvOfaCount = pStaticInfo->pProfiles->table[i].nvOfaCount; entryCount++; } @@ -3222,6 +3297,7 @@ kmigmgrSwizzIdToResourceAllocation_IMPL pResourceAllocation->veidCount = info.veidCount; pResourceAllocation->veidOffset = info.veidOffset; + pResourceAllocation->virtualGpcCount = info.virtualGpcCount; bitVectorFromRaw(&pResourceAllocation->engines, info.enginesMask, sizeof(info.enginesMask)); @@ -3591,8 +3667,7 @@ kmigmgrCreateComputeInstances_VF pComputeResourceAllocation->veidOffset = pComputeResourceAllocation->veidOffset - pResourceAllocation->veidOffset; - pComputeResourceAllocation->veidCount = (pResourceAllocation->veidCount / pResourceAllocation->gpcCount) * - gpcCount; + pComputeResourceAllocation->veidCount = nvPopCount64(pKernelGraphicsManager->grIdxVeidMask[globalGrIdx]); } // Copy over the local cached compute instance info @@ -4291,6 +4366,7 @@ kmigmgrConfigureGPUInstance_IMPL i = 0; FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) { + NvU32 virtualGpcCount; NvU32 engineIdx; NvU32 gpcCount = pGpcCountPerGr[i]; @@ -4305,12 +4381,19 @@ kmigmgrConfigureGPUInstance_IMPL continue; } + // + // The virtualGpcCount here really specifies the numer of GPCs guarnateed + // to be present for a CI/GI. We limit the number of GPCs a CI can request + // VEIDs for to the GI's guarnatteed GPC count. + // + virtualGpcCount = NV_MIN(gpcCount, pKernelMIGGpuInstance->resourceAllocation.virtualGpcCount); + // Update the GR to VEID mapping NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgrmgrAllocVeidsForGrIdx(pGpu, pKernelGraphicsManager, engineIdx, - gpcCount, + virtualGpcCount, pKernelMIGGpuInstance), cleanup); @@ -4847,9 +4930,11 @@ kmigmgrSetMIGState_FWCLIENT ) { KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); NV_STATUS rmStatus = NV_OK; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvBool bPrevMIGState = pKernelMIGManager->bMIGEnabled; if (bEnable) { @@ -4863,6 +4948,39 @@ kmigmgrSetMIGState_FWCLIENT kmigmgrDisableWatchdog(pGpu, pKernelMIGManager), cleanup_disableWatchdog); + // Ensure NVLINK is shutdown before enabling MIG + if (!kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager) || + (bMemoryPartitioningNeeded)) + { + // + // Check for any alive P2P references to this GPU. P2P objects must + // be re-created after disabling MIG. If it is allowed for MIG to + // continue enablement without all P2P objects torn down, there is + // the possibility that P2P mappings and state will never be updated. + // + NV_CHECK_OR_ELSE(LEVEL_ERROR, + !kbusIsGpuP2pAlive(pGpu, GPU_GET_KERNEL_BUS(pGpu)), + rmStatus = NV_ERR_INVALID_STATE; + goto cleanup_disableWatchdog;); + + if ((pKernelNvlink != NULL) && pKernelNvlink->bEnableAli) + { + // Allow RM to continue even if the above functionality is not supported + rmStatus = knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, NV_TRUE); + if ((rmStatus != NV_OK) && (rmStatus != NV_ERR_NOT_SUPPORTED)) + goto cleanup_disableNvlink; + + // Reset status to NV_OK for when NV_ERR_NOT_SUPPORTED was returned + rmStatus = NV_OK; + } + + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + gpuDeleteClassFromClassDBByClassId(pGpu, NV50_P2P)); + + if (rmStatus != NV_OK) + goto cleanup_disableNvlink; + } + // Before enabling MIG, deconfigure GR0 in legacy mode kgraphicsInvalidateStaticInfo(pGpu, pKGr); @@ -4944,11 +5062,8 @@ kmigmgrSetMIGState_FWCLIENT // Populate static GPU instance memory config which will be used to manage // GPU instance memory // - if (!IsAMODEL(pGpu)) - { - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); - } + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); } else { @@ -4998,6 +5113,9 @@ kmigmgrSetMIGState_FWCLIENT } cleanup_destroyTopLevelScrubber: + // Set kmigmgr state to reflect MIG disabled while reconfiguring for NON-MIG + pKernelMIGManager->bMIGEnabled = NV_FALSE; + if (!bUnload) { KernelGraphics *pKGr = GPU_GET_KERNEL_GRAPHICS(pGpu, 0); @@ -5007,9 +5125,32 @@ kmigmgrSetMIGState_FWCLIENT kgraphicsLoadStaticInfo(pGpu, pKGr, KMIGMGR_SWIZZID_INVALID)); NV_ASSERT_OK( kmigmgrRestoreWatchdog(pGpu, pKernelMIGManager)); + + } + + // Add P2P class back to class DB as memory partitioning is disabled + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + gpuAddClassToClassDBByClassId(pGpu, NV50_P2P)); + + // + // Restore previous kmigmgr MIG state. kmigmgrSetMIGState should not + // permanently modify bMIGEnabled. Restore the value to whatever was + // present on entry to this function. + // + pKernelMIGManager->bMIGEnabled = bPrevMIGState; + +cleanup_disableNvlink: + if ((pKernelNvlink != NULL) && pKernelNvlink->bEnableAli) + { + // Bring Nvlinks back online before re-programming hshub + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + knvlinkPreTrainLinksToActiveAli(pGpu, pKernelNvlink, pKernelNvlink->enabledLinks, NV_FALSE)); + + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, pKernelNvlink->enabledLinks, NV_FALSE)); } -cleanup_disableWatchdog: +cleanup_disableWatchdog: goto done; } @@ -5187,7 +5328,12 @@ kmigmgrInitGPUInstancePool_IMPL NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance->pMemoryPartitionHeap != NULL, NV_ERR_INVALID_STATE); version = ((pFmt->version == GMMU_FMT_VERSION_1) ? POOL_CONFIG_GMMU_FMT_1 : POOL_CONFIG_GMMU_FMT_2); - return rmMemPoolSetup((void*)&pKernelMIGGpuInstance->pMemoryPartitionHeap->pmaObject, &pKernelMIGGpuInstance->pPageTableMemPool, version); + + NV_ASSERT_OK_OR_RETURN( + rmMemPoolSetup((void*)&pKernelMIGGpuInstance->pMemoryPartitionHeap->pmaObject, + &pKernelMIGGpuInstance->pPageTableMemPool, version)); + + return NV_OK; } /* @@ -5429,6 +5575,12 @@ kmigmgrSaveToPersistence_IMPL // Clear existing topology, if any. portMemSet(pTopologySave->saveGI, 0, sizeof(pTopologySave->saveGI)); + // Update the MIG enablement bit + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) + { + gpumgrSetSystemMIGEnabled(gpuGetDBDF(pGpu), pKernelMIGManager->bMIGEnabled); + } + // If there are no instances then don't bother checking anything. NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_IN_USE(pGpu), NV_OK); @@ -5449,6 +5601,7 @@ kmigmgrSaveToPersistence_IMPL } pGPUInstanceSave->giInfo.veidOffset = pKernelMIGGPUInstance->resourceAllocation.veidOffset; pGPUInstanceSave->giInfo.veidCount = pKernelMIGGPUInstance->resourceAllocation.veidCount; + pGPUInstanceSave->giInfo.virtualGpcCount = pKernelMIGGPUInstance->resourceAllocation.virtualGpcCount; NV_ASSERT_OK_OR_RETURN(kmigmgrSaveComputeInstances(pGpu, pKernelMIGManager, pKernelMIGGPUInstance, pGPUInstanceSave->saveCI)); @@ -6004,6 +6157,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].ceCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_COPY(0)); pParams->queryPartitionInfo[i].gpcCount = pResourceAllocation->gpcCount; + pParams->queryPartitionInfo[i].virtualGpcCount = pResourceAllocation->virtualGpcCount; pParams->queryPartitionInfo[i].nvDecCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_NVDEC(0)); pParams->queryPartitionInfo[i].nvEncCount = @@ -6030,6 +6184,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].gpcsPerGr[j] = rpcParams.queryPartitionInfo[i].gpcsPerGr[j]; pParams->queryPartitionInfo[i].veidsPerGr[j] = rpcParams.queryPartitionInfo[i].veidsPerGr[j]; + pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = rpcParams.queryPartitionInfo[i].virtualGpcsPerGr[j]; j++; } @@ -6191,3 +6346,54 @@ subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL return status; } +NV_STATUS +subdeviceCtrlCmdGpuGetComputeProfiles_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + NvU32 maxSmCount = NV_U32_MAX; + MIG_INSTANCE_REF ref; + NvU32 entryCount; + NvU32 i; + + if (!IS_MIG_ENABLED(pGpu)) + return NV_ERR_INVALID_STATE; + + // + // Grab MIG partition reference if available. The profile's SM count is used + // to filter out compute profiles which wouldn't fit on the GI anyway. This + // is not fatal as we still want to allow compute profiles for entire GPU view + // to be queried without a specific GPU instance. + // + if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref) == NV_OK) + { + maxSmCount = ref.pKernelMIGGpuInstance->pProfile->smCount; + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo->pCIProfiles != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT(pStaticInfo->pCIProfiles->profileCount <= NV_ARRAY_ELEMENTS(pParams->profiles)); + + entryCount = 0; + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++) + { + + if (pStaticInfo->pCIProfiles->profiles[i].smCount > maxSmCount) + continue; + + pParams->profiles[entryCount].computeSize = pStaticInfo->pCIProfiles->profiles[i].computeSize; + pParams->profiles[entryCount].gfxGpcCount = pStaticInfo->pCIProfiles->profiles[i].gfxGpcCount; + pParams->profiles[entryCount].gpcCount = pStaticInfo->pCIProfiles->profiles[i].gpcCount; + pParams->profiles[entryCount].smCount = pStaticInfo->pCIProfiles->profiles[i].smCount; + pParams->profiles[entryCount].veidCount = pStaticInfo->pCIProfiles->profiles[i].veidCount; + entryCount++; + } + pParams->profileCount = entryCount; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c new file mode 100644 index 000000000..3a24501b8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c @@ -0,0 +1,170 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#if !defined(SRT_BUILD) +#include "gpu/mmu/kern_gmmu.h" +#endif +#include "mmu/gmmu_fmt.h" +#include "published/hopper/gh100/dev_mmu.h" +#include "published/hopper/gh100/hwproject.h" + +/*! + * NUM_VA_BITS = 57 + * + * PD4[56] + * | + * v + * PD3 [55:47] + * | + * v + * PD2 [46:38] + * | + * v + * PD1 [37:29] / PT_512M [37:29] (512MB page) + * | + * v + * PD0 [28:21] / PT_LARGE [28:21] (2MB page) + * | \ + * | \ + * v v + * PT_SMALL PT_BIG (64KB page) + * [20:12] [20:16] + */ +void kgmmuFmtInitLevels_GH10X(KernelGmmu *pKernelGmmu, + MMU_FMT_LEVEL *pLevels, + const NvU32 numLevels, + const NvU32 version, + const NvU32 bigPageShift) +{ + NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); + NV_ASSERT_OR_RETURN_VOID(numLevels >= 7); + + // Page directory 4 (root). + pLevels[0].virtAddrBitHi = 56; + pLevels[0].virtAddrBitLo = 56; + pLevels[0].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[0].numSubLevels = 1; + pLevels[0].subLevels = pLevels + 1; + + // Page directory 3. + pLevels[1].virtAddrBitHi = 55; + pLevels[1].virtAddrBitLo = 47; + pLevels[1].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[1].numSubLevels = 1; + pLevels[1].subLevels = pLevels + 2; + + // Page directory 2. + pLevels[2].virtAddrBitHi = 46; + pLevels[2].virtAddrBitLo = 38; + pLevels[2].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[2].numSubLevels = 1; + pLevels[2].subLevels = pLevels + 3; + + // Page directory 1. + pLevels[3].virtAddrBitHi = 37; + pLevels[3].virtAddrBitLo = 29; + pLevels[3].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[3].numSubLevels = 1; + pLevels[3].subLevels = pLevels + 4; + // Page directory 1 can hold a PTE pointing to a 512MB Page + pLevels[3].bPageTable = NV_TRUE; + + // Page directory 0. + pLevels[4].virtAddrBitHi = 28; + pLevels[4].virtAddrBitLo = 21; + pLevels[4].entrySize = NV_MMU_VER3_DUAL_PDE__SIZE; + pLevels[4].numSubLevels = 2; + pLevels[4].bPageTable = NV_TRUE; + pLevels[4].subLevels = pLevels + 5; + + // Big page table. + pLevels[5].virtAddrBitHi = 20; + pLevels[5].virtAddrBitLo = (NvU8)bigPageShift; + pLevels[5].entrySize = NV_MMU_VER3_PTE__SIZE; + pLevels[5].bPageTable = NV_TRUE; + + // Small page table. + pLevels[6].virtAddrBitHi = 20; + pLevels[6].virtAddrBitLo = 12; + pLevels[6].entrySize = NV_MMU_VER3_PTE__SIZE; + pLevels[6].bPageTable = NV_TRUE; +} + +void kgmmuFmtInitPdeMulti_GH10X(KernelGmmu *pKernelGmmu, + GMMU_FMT_PDE_MULTI *pPdeMulti, + const NvU32 version, + const NV_FIELD_ENUM_ENTRY *pPdeApertures) +{ + GMMU_FMT_PDE *pPdeBig = &pPdeMulti->subLevels[0]; + GMMU_FMT_PDE *pPdeSmall = &pPdeMulti->subLevels[1]; + + NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); + + // Dual PDE - big part. + pPdeBig->version = GMMU_FMT_VERSION_3; + INIT_FIELD_APERTURE(&pPdeBig->fldAperture, NV_MMU_VER3_DUAL_PDE_APERTURE_BIG, + pPdeApertures); + INIT_FIELD_ADDRESS(&pPdeBig->fldAddr, NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG, + NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT); + INIT_FIELD_DESC32(&pPdeBig->fldPdePcf, NV_MMU_VER3_DUAL_PDE_PCF_BIG); + + // Dual PDE - small part. + pPdeSmall->version = GMMU_FMT_VERSION_3; + INIT_FIELD_APERTURE(&pPdeSmall->fldAperture, NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL, + pPdeApertures); + INIT_FIELD_ADDRESS(&pPdeSmall->fldAddr, NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL, + NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT); + INIT_FIELD_DESC32(&pPdeSmall->fldPdePcf, NV_MMU_VER3_DUAL_PDE_PCF_SMALL); +} + +void kgmmuFmtInitPde_GH10X(KernelGmmu *pKernelGmmu, + GMMU_FMT_PDE *pPde, + const NvU32 version, + const NV_FIELD_ENUM_ENTRY *pPdeApertures) +{ + NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); + + pPde->version = GMMU_FMT_VERSION_3; + INIT_FIELD_APERTURE(&pPde->fldAperture, NV_MMU_VER3_PDE_APERTURE, pPdeApertures); + INIT_FIELD_DESC32(&pPde->fldPdePcf, NV_MMU_VER3_PDE_PCF); + INIT_FIELD_ADDRESS(&pPde->fldAddr, NV_MMU_VER3_PDE_ADDRESS, NV_MMU_VER3_PDE_ADDRESS_SHIFT); +} + +void kgmmuFmtInitPte_GH10X(KernelGmmu *pKernelGmmu, + GMMU_FMT_PTE *pPte, + const NvU32 version, + const NV_FIELD_ENUM_ENTRY *pPteApertures, + const NvBool bUnifiedAperture) +{ + NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); + + pPte->version = GMMU_FMT_VERSION_3; + INIT_FIELD_BOOL(&pPte->fldValid, NV_MMU_VER3_PTE_VALID); + INIT_FIELD_APERTURE(&pPte->fldAperture, NV_MMU_VER3_PTE_APERTURE, pPteApertures); + INIT_FIELD_DESC32(&pPte->fldPeerIndex, NV_MMU_VER3_PTE_PEER_ID); + INIT_FIELD_DESC32(&pPte->fldKind, NV_MMU_VER3_PTE_KIND); + INIT_FIELD_DESC32(&pPte->fldPtePcf, NV_MMU_VER3_PTE_PCF); + + INIT_FIELD_ADDRESS(&pPte->fldAddrVidmem, NV_MMU_VER3_PTE_ADDRESS_VID, NV_MMU_VER3_PTE_ADDRESS_SHIFT); + INIT_FIELD_ADDRESS(&pPte->fldAddrPeer, NV_MMU_VER3_PTE_ADDRESS_PEER, NV_MMU_VER3_PTE_ADDRESS_SHIFT); + INIT_FIELD_ADDRESS(&pPte->fldAddrSysmem, NV_MMU_VER3_PTE_ADDRESS_SYS, NV_MMU_VER3_PTE_ADDRESS_SHIFT); +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c new file mode 100644 index 000000000..1c5e0dafd --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -0,0 +1,340 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/mem_mgr/mem_mgr.h" + +#include "mmu/gmmu_fmt.h" +#include "published/hopper/gh100/dev_mmu.h" +#include "published/hopper/gh100/dev_fault.h" + +/*! + * Check if a specific GMMU format version is supported. + */ +NvBool +kgmmuFmtIsVersionSupported_GH10X(KernelGmmu *pKernelGmmu, NvU32 version) +{ + return (version == GMMU_FMT_VERSION_3); +} + +/*! + * Initialize the GMMU format families. + */ +NV_STATUS +kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, KernelGmmu* pKernelGmmu) +{ + NvU32 i; + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + NvU32 ptePcfHw = 0; + NvU32 ptePcfSw = 0; + + // Initialize the sparse encoding in the PDE PCF field for V3 + GMMU_FMT_FAMILY *pFam = pKernelGmmu->pFmtFamilies[GMMU_FMT_VERSION_3 - 1]; + + if (pFam != NULL) + { + // 1.Initialize sparsePde + pdePcfSw |= (1 << SW_MMU_PCF_SPARSE_IDX); + pdePcfSw |= (1 << SW_MMU_PCF_ATS_ALLOWED_IDX); + NV_ASSERT_OR_RETURN((kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + gmmuFieldSetAperture(&pFam->pde.fldAperture, GMMU_APERTURE_INVALID, + pFam->sparsePde.v8); + nvFieldSet32(&pFam->pde.fldPdePcf, pdePcfHw, pFam->sparsePde.v8); + + // 2.Initialize sparsePdeMulti + for (i = 0; i < MMU_FMT_MAX_SUB_LEVELS; ++i) + { + const GMMU_FMT_PDE *pPdeFmt = &pFam->pdeMulti.subLevels[i]; + gmmuFieldSetAperture(&pPdeFmt->fldAperture, GMMU_APERTURE_INVALID, + pFam->sparsePdeMulti.v8); + // Set PDE PCF sparse bit only for sub-level 0 for PdeMulti + if (i == 0) + { + nvFieldSet32(&pPdeFmt->fldPdePcf, pdePcfHw, pFam->sparsePdeMulti.v8); + } + } + + // 3.Initialize nv4kPte + ptePcfSw |= (1 << SW_MMU_PCF_NV4K_IDX); + nvFieldSetBool(&pFam->pte.fldValid, NV_FALSE, pFam->nv4kPte.v8); + NV_ASSERT_OR_RETURN((kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, &ptePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pFam->pte.fldPtePcf, ptePcfHw, pFam->nv4kPte.v8); + + // 4.Initialize sparsePte + ptePcfSw = (1 << SW_MMU_PCF_SPARSE_IDX); + nvFieldSetBool(&pFam->pte.fldValid, NV_FALSE, pFam->sparsePte.v8); + NV_ASSERT_OR_RETURN((kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, &ptePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pFam->pte.fldPtePcf, ptePcfHw, pFam->sparsePte.v8); + } + + return NV_OK; +} + +#define PTE_PCF_INVALID_LIST(fn) \ + fn(INVALID) \ + fn(NO_VALID_4KB_PAGE) \ + fn(SPARSE) \ + fn(MAPPING_NOWHERE) + +#define PTE_PCF_VALID_LIST(fn) \ + fn(PRIVILEGE_RW_ATOMIC_CACHED_ACD) \ + fn(PRIVILEGE_RW_ATOMIC_CACHED_ACE) \ + fn(PRIVILEGE_RW_ATOMIC_UNCACHED_ACD) \ + fn(PRIVILEGE_RW_ATOMIC_UNCACHED_ACE) \ + fn(PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE) \ + fn(PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE) \ + fn(PRIVILEGE_RO_ATOMIC_UNCACHED_ACE) \ + fn(PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE) \ + fn(PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE) \ + fn(REGULAR_RW_ATOMIC_CACHED_ACD) \ + fn(REGULAR_RW_ATOMIC_CACHED_ACE) \ + fn(REGULAR_RW_ATOMIC_UNCACHED_ACD) \ + fn(REGULAR_RW_ATOMIC_UNCACHED_ACE) \ + fn(REGULAR_RW_NO_ATOMIC_CACHED_ACD) \ + fn(REGULAR_RW_NO_ATOMIC_CACHED_ACE) \ + fn(REGULAR_RW_NO_ATOMIC_UNCACHED_ACD) \ + fn(REGULAR_RW_NO_ATOMIC_UNCACHED_ACE) \ + fn(REGULAR_RO_ATOMIC_CACHED_ACD) \ + fn(REGULAR_RO_ATOMIC_CACHED_ACE) \ + fn(REGULAR_RO_ATOMIC_UNCACHED_ACD) \ + fn(REGULAR_RO_ATOMIC_UNCACHED_ACE) \ + fn(REGULAR_RO_NO_ATOMIC_CACHED_ACD) \ + fn(REGULAR_RO_NO_ATOMIC_CACHED_ACE) \ + fn(REGULAR_RO_NO_ATOMIC_UNCACHED_ACD) \ + fn(REGULAR_RO_NO_ATOMIC_UNCACHED_ACE) + +#define PTE_PCF_HW_FROM_SW(name) \ + case (SW_MMU_PTE_PCF_##name): \ + { \ + *pPtePcfHw = NV_MMU_VER3_PTE_PCF_##name; \ + break; \ + } + +#define PTE_PCF_SW_FROM_HW(name) \ + case (NV_MMU_VER3_PTE_PCF_##name): \ + { \ + *pPtePcfSw = SW_MMU_PTE_PCF_##name; \ + break; \ + } + +// +// Takes a SW PTE PCF and translates to HW PTE PCF +// If bit patterns is not supported by HW, return NV_ERR_NOT_SUPPORTED +// +NV_STATUS +kgmmuTranslatePtePcfFromSw_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 ptePcfSw, + NvU32 *pPtePcfHw +) +{ + switch (ptePcfSw) + { + PTE_PCF_INVALID_LIST(PTE_PCF_HW_FROM_SW) + PTE_PCF_VALID_LIST(PTE_PCF_HW_FROM_SW) + + default: + { + NV_PRINTF(LEVEL_ERROR, "Unsupported SW PTE PCF pattern requested : %x\n", ptePcfSw); + return NV_ERR_NOT_SUPPORTED; + } + } + + return NV_OK; +} + +NV_STATUS +kgmmuTranslatePtePcfFromHw_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 ptePcfHw, + NvBool bPteValid, + NvU32 *pPtePcfSw +) +{ + if (!bPteValid) + { + switch (ptePcfHw) + { + PTE_PCF_INVALID_LIST(PTE_PCF_SW_FROM_HW) + + default: return NV_ERR_NOT_SUPPORTED; + } + } + else + { + switch (ptePcfHw) + { + PTE_PCF_VALID_LIST(PTE_PCF_SW_FROM_HW) + + default: + { + NV_PRINTF(LEVEL_ERROR, "Unsupported HW PTE PCF pattern requested : %x\n", ptePcfHw); + return NV_ERR_NOT_SUPPORTED; + } + } + } + + return NV_OK; +} + +#define PDE_PCF_INVALID_LIST(fn) \ + fn(INVALID_ATS_ALLOWED) \ + fn(SPARSE_ATS_ALLOWED) \ + fn(INVALID_ATS_NOT_ALLOWED) \ + fn(SPARSE_ATS_NOT_ALLOWED) + +#define PDE_PCF_VALID_LIST(fn) \ + fn(VALID_CACHED_ATS_ALLOWED) \ + fn(VALID_CACHED_ATS_NOT_ALLOWED) \ + fn(VALID_UNCACHED_ATS_ALLOWED) \ + fn(VALID_UNCACHED_ATS_NOT_ALLOWED) + +#define PDE_PCF_HW_FROM_SW(name) \ + case (SW_MMU_PDE_PCF_##name): \ + { \ + *pPdePcfHw = NV_MMU_VER3_PDE_PCF_##name; \ + break; \ + } + +#define PDE_PCF_SW_FROM_HW(name) \ + case (NV_MMU_VER3_PDE_PCF_##name): \ + { \ + *pPdePcfSw = SW_MMU_PDE_PCF_##name; \ + break; \ + } + +// +// Takes a SW PDE PCF and translates to HW PDE PCF +// If a bit pattern is not supported by HW, return NV_ERR_NOT_SUPPORTED +// +NV_STATUS +kgmmuTranslatePdePcfFromSw_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 pdePcfSw, + NvU32 *pPdePcfHw +) +{ + switch (pdePcfSw) + { + PDE_PCF_INVALID_LIST(PDE_PCF_HW_FROM_SW) + PDE_PCF_VALID_LIST(PDE_PCF_HW_FROM_SW) + + default: return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} + +// +// Takes a HW PDE PCF and translates to SW PDE PCF +// If a bit pattern is not supported by SW, return NV_ERR_NOT_SUPPORTED +// +NV_STATUS +kgmmuTranslatePdePcfFromHw_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 pdePcfHw, + GMMU_APERTURE aperture, + NvU32 *pPdePcfSw +) +{ + if (!aperture) + { + switch (pdePcfHw) + { + PDE_PCF_INVALID_LIST(PDE_PCF_SW_FROM_HW) + + default: return NV_ERR_NOT_SUPPORTED; + } + } + else + { + switch (pdePcfHw) + { + PDE_PCF_VALID_LIST(PDE_PCF_SW_FROM_HW) + + default: return NV_ERR_NOT_SUPPORTED; + } + } + + return NV_OK; +} + +/* + * @brief Validates fabric base address. + * + * @param pKernelGmmu + * @param fabricBaseAddr + * + * @returns On success, NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +kgmmuValidateFabricBaseAddress_GH100 +( + KernelGmmu *pKernelGmmu, + NvU64 fabricBaseAddr +) +{ + OBJGPU *pGpu = ENG_GET_GPU(pKernelGmmu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 fbSizeBytes; + + fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; + + // + // Hopper SKUs will be paired with NVSwitches (Laguna Seca) supporting 2K + // mapslots that can cover 512GB each. Make sure that the fabric base + // address being used is valid to cover whole frame buffer. + // + + // Check if fabric address is aligned to mapslot size. + if (fabricBaseAddr & (NVBIT64(39) - 1)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Align fbSize to mapslot size. + fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(39)); + + return NV_OK; +} + +/*! + * @brief Get the engine ID associated with the Graphics Engine + */ +NvU32 +kgmmuGetGraphicsEngineId_GH100 +( + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_GRAPHICS; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index d2512b3a9..b346639a2 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -228,6 +228,9 @@ kgmmuDetermineMaxVASize_GM107 case GMMU_FMT_VERSION_2: pKernelGmmu->maxVASize = 1ULL << 49; break; + case GMMU_FMT_VERSION_3: + pKernelGmmu->maxVASize = 1ULL << 57; + break; default: pKernelGmmu->maxVASize = 1ULL << 40; } diff --git a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c index 1bcd37035..a3064aed9 100644 --- a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c @@ -326,6 +326,17 @@ _bar2WalkCBUpdatePde const NvU64 physAddr = memdescGetPhysAddr(pSubMemDesc, AT_GPU, 0); // Set fields within the temp PDE + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + + pdePcfSw |= memdescGetVolatility(pSubMemDesc) ? (1 << SW_MMU_PCF_UNCACHED_IDX) : 0; + NV_ASSERT_OR_RETURN((kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pPde->fldPdePcf, pdePcfHw, entry.v8); + } + else { nvFieldSetBool(&pPde->fldVolatile, memdescGetVolatility(pSubMemDesc), entry.v8); } diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c index d282abfc6..1f57ba860 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c @@ -273,6 +273,25 @@ _gmmuPrintPde _gmmuPrintPa(pa, aperture, 0); + if (pFmtGmmu->version == GMMU_FMT_VERSION_3) + { + NvU32 pdePcfSw = 0; + NvU32 pdePcfHw = 0; + + PRINT_FIELD_32("PdePcf=%d", pFmtPde, PdePcf, pGmmuEntry); + pdePcfHw = nvFieldGet32(&pFmtPde->fldPdePcf, pGmmuEntry->v8); + NV_ASSERT(kgmmuTranslatePdePcfFromHw_HAL(GPU_GET_KERNEL_GMMU(pGpu), + pdePcfHw, + aperture, + &pdePcfSw) == NV_OK); + NV_PRINTF_EX(NV_PRINTF_MODULE, + LEVEL_INFO, + "(Sparse=%d, Vol=%d, ATS=%d)", + ((pdePcfSw >> SW_MMU_PCF_SPARSE_IDX) & 0x1), + ((pdePcfSw >> SW_MMU_PCF_UNCACHED_IDX) & 0x1), + ((pdePcfSw >> SW_MMU_PCF_ATS_ALLOWED_IDX) & 0x1)); + } + else { PRINT_FIELD_BOOL("Vol=%d", pFmtPde, Volatile, pGmmuEntry); } @@ -369,6 +388,28 @@ _gmmuPrintPte NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "[0x%x]: ", index); _gmmuPrintPa(pa, aperture, peerIndex); + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfSw = 0; + NvU32 ptePcfHw = 0; + + PRINT_FIELD_BOOL("Vld=%d, ", pFmt, Valid, pGmmuEntry); + PRINT_FIELD_32("Kind=0x%x, ", pFmt, Kind, pGmmuEntry); + PRINT_FIELD_32("PtePcf=%d", pFmt, PtePcf, pGmmuEntry); + ptePcfHw = nvFieldGet32(&pFmt->fldPtePcf, pGmmuEntry->v8); + NV_ASSERT(kgmmuTranslatePtePcfFromHw_HAL(GPU_GET_KERNEL_GMMU(pGpu), + ptePcfHw, + nvFieldGetBool(&pFmt->fldValid, pGmmuEntry->v8), + &ptePcfSw) == NV_OK); + NV_PRINTF_EX(NV_PRINTF_MODULE, + LEVEL_INFO, "(Vol=%d, Priv=%d, RO=%d, Atomic=%d, ACE=%d)", + ((ptePcfSw >> SW_MMU_PCF_UNCACHED_IDX) & 0x1), + !((ptePcfSw >> SW_MMU_PCF_REGULAR_IDX) & 0x1), + ((ptePcfSw >> SW_MMU_PCF_RO_IDX) & 0x1), + !((ptePcfSw >> SW_MMU_PCF_NOATOMIC_IDX) & 0x1), + ((ptePcfSw >> SW_MMU_PCF_ACE_IDX) & 0x1)); + } + else { PRINT_FIELD_BOOL("Vld=%d, ", pFmt, Valid, pGmmuEntry); PRINT_FIELD_BOOL("Priv=%d, ", pFmt, Privilege, pGmmuEntry); @@ -402,6 +443,19 @@ _gmmuIsInvalidPdeOk const GMMU_ENTRY_VALUE *pGmmuEntry = (GMMU_ENTRY_VALUE*)pPde; NvBool bSparse = NV_FALSE; + if (pFmtGmmu->version == GMMU_FMT_VERSION_3) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + + pdePcfHw = nvFieldGet32(&pFmtPde->fldPdePcf, pGmmuEntry->v8); + NV_ASSERT(kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, pdePcfHw, + gmmuFieldGetAperture(&pFmtPde->fldAperture, pGmmuEntry->v8), + &pdePcfSw) == NV_OK); + bSparse = pdePcfSw & (1 << SW_MMU_PCF_SPARSE_IDX); + } + else { bSparse = nvFieldGetBool(&pFmtPde->fldVolatile, pGmmuEntry->v8); } @@ -472,9 +526,14 @@ _gmmuSwToHwLevel ) { const GMMU_FMT *pFmtGmmu = (GMMU_FMT*)pFmt; + NvU32 maxV3Levels = 0; switch (pFmtGmmu->version) { + case GMMU_FMT_VERSION_3: + maxV3Levels = (pFmtGmmu->pRoot->virtAddrBitHi == 56) ? 5 : 4; + NV_ASSERT_OR_RETURN(level < maxV3Levels, 0); + return (maxV3Levels - 1) - level; case GMMU_FMT_VERSION_2: NV_ASSERT_OR_RETURN(level < 4, 0); return 3 - level; diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c index 9adea807e..1a93c164f 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c @@ -192,6 +192,11 @@ _gmmuWalkCBLevelAlloc // Get the alignment from the parent PDE address shift. pPde = gmmuFmtGetPde(pFmt, pParent, subLevel); + if (pPde->version == GMMU_FMT_VERSION_3) + { + alignment = NVBIT(pPde->fldAddr.shift); + } + else { alignment = NVBIT(pPde->fldAddrSysmem.shift); } @@ -718,6 +723,19 @@ _gmmuWalkCBUpdatePde const GMMU_FIELD_ADDRESS *pFldAddr = gmmuFmtPdePhysAddrFld(pPde, aperture); const NvU64 physAddr = memdescGetPhysAddr(pSubMemDesc, AT_GPU, 0); + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + + pdePcfSw |= gvaspaceIsAtsEnabled(pGVAS) ? (1 << SW_MMU_PCF_ATS_ALLOWED_IDX) : 0; + pdePcfSw |= memdescGetVolatility(pSubMemDesc) ? (1 << SW_MMU_PCF_UNCACHED_IDX) : 0; + + NV_ASSERT_OR_RETURN((kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pPde->fldPdePcf, pdePcfHw, entry.v8); + } + else { nvFieldSetBool(&pPde->fldVolatile, memdescGetVolatility(pSubMemDesc), entry.v8); } diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 003c9a034..232a6dfac 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -1924,6 +1924,12 @@ kgmmuExtractPteInfo_IMPL pPteInfo->pteFlags = FLD_SET_DRF_NUM(0080_CTRL, _DMA_PTE_INFO, _PARAMS_FLAGS_VALID, bPteValid, pPteInfo->pteFlags); + if (pFmtPte->version != GMMU_FMT_VERSION_3) + { + pPteInfo->pteFlags = FLD_SET_DRF_NUM(0080_CTRL, _DMA_PTE_INFO, _PARAMS_FLAGS_ENCRYPTED, + nvFieldGetBool(&pFmtPte->fldEncrypted, pPte->v8), pPteInfo->pteFlags); + } + switch (gmmuFieldGetAperture(&pFmtPte->fldAperture, pPte->v8)) { case GMMU_APERTURE_VIDEO: @@ -1948,6 +1954,82 @@ kgmmuExtractPteInfo_IMPL break; } + if (pFmtPte->version == GMMU_FMT_VERSION_3) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 ptePcfHw; + NvU32 ptePcfSw = 0; + + // In Version 3, parse the PCF bits and return those + ptePcfHw = nvFieldGet32(&pFmtPte->fldPtePcf, pPte->v8); + NV_ASSERT(kgmmuTranslatePtePcfFromHw_HAL(pKernelGmmu, ptePcfHw, bPteValid, &ptePcfSw) == NV_OK); + + // Valid 2MB PTEs follow the same format as 64K and 4K PTEs + if (bPteValid) + { + if (!(ptePcfSw & (1 << SW_MMU_PCF_UNCACHED_IDX))) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_GPU_CACHED, _TRUE, pPteInfo->pteFlags); + } + if (ptePcfSw & (1 << SW_MMU_PCF_RO_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_READ_ONLY, _TRUE, pPteInfo->pteFlags); + } + if (ptePcfSw & (1 << SW_MMU_PCF_NOATOMIC_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_ATOMIC, _DISABLE, pPteInfo->pteFlags); + } + if (ptePcfSw & (1 << SW_MMU_PCF_REGULAR_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_PRIVILEGED, _FALSE, pPteInfo->pteFlags); + } + if (ptePcfSw & (1 << SW_MMU_PCF_ACE_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_ACCESS_COUNTING, _ENABLE, pPteInfo->pteFlags); + } + } + else + { + if (pLevelFmt->numSubLevels == 0) + { + if (ptePcfSw & (1 << SW_MMU_PCF_SPARSE_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_GPU_CACHED, _FALSE, pPteInfo->pteFlags); + } + else + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_GPU_CACHED, _TRUE, pPteInfo->pteFlags); + } + } + else + { + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + + pdePcfHw = nvFieldGet32(&pFmt->pPde->fldPdePcf, pPte->v8); + NV_ASSERT(kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, pdePcfHw, GMMU_APERTURE_INVALID, &pdePcfSw) == NV_OK); + if (pdePcfSw & (1 << SW_MMU_PCF_SPARSE_IDX)) + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_GPU_CACHED, _FALSE, pPteInfo->pteFlags); + } + else + { + pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, + _PARAMS_FLAGS_GPU_CACHED, _TRUE, pPteInfo->pteFlags); + } + + } + } + } + else { pPteInfo->pteFlags = FLD_SET_DRF_NUM(0080_CTRL, _DMA_PTE_INFO, _PARAMS_FLAGS_GPU_CACHED, !nvFieldGetBool(&pFmtPte->fldVolatile, pPte->v8), pPteInfo->pteFlags); diff --git a/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga100.c b/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga100.c deleted file mode 100644 index 7d2a2f953..000000000 --- a/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga100.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/nvdec/kernel_nvdec.h" - -#include "core/core.h" -#include "gpu/falcon/kernel_falcon.h" -#include "gpu/gpu.h" -#include "os/nv_memory_type.h" - -#include "published/ampere/ga100/dev_boot.h" -#include "published/ampere/ga100/dev_fuse.h" -#include "published/ampere/ga100/dev_nvdec_pri.h" -#include "published/ampere/ga100/dev_nvdec_addendum.h" - -void -knvdecConfigureFalcon_GA100 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - KernelFalconEngineConfig falconConfig; - - portMemSet(&falconConfig, 0, sizeof(falconConfig)); - - falconConfig.registerBase = DRF_BASE(NV_PNVDEC(0)); - falconConfig.riscvRegisterBase = 0; // RISC-V unused or unsupported - falconConfig.fbifBase = NV_PNVDEC_FBIF_BASE(0); - falconConfig.bBootFromHs = NV_FALSE; - falconConfig.pmcEnableMask = DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED); - falconConfig.bIsPmcDeviceEngine = NV_TRUE; - falconConfig.physEngDesc = ENG_NVDEC(0); - falconConfig.ctxAttr = NV_MEMORY_UNCACHED; - falconConfig.ctxBufferSize = FLCN_CTX_ENG_BUFFER_SIZE_HW; - falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); - - kflcnConfigureEngine(pGpu, staticCast(pKernelNvdec, KernelFalcon), &falconConfig); -} - -NvBool -knvdecIsEngineDisabled_GA100 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - NvU32 reg = GPU_REG_RD32(pGpu, NV_FUSE_OPT_NVDEC_DISABLE); - NvU32 field = DRF_VAL(_FUSE, _OPT_NVDEC_DISABLE, _DATA, reg); - // highest bit in field will read 1 if NVDEC0 is disabled - return (NVBIT(DRF_SIZE(NV_FUSE_OPT_NVDEC_DISABLE_DATA) - 1) & field) > 0; -} - -/*! - * Returns the NVDEC0 fuse version of the provided ucode id (1-indexed) - * - * @param pGpu OBJGPU pointer - * @param pKernelNvdec KernelNvdec pointer - * @param[in] ucodeId Ucode Id (1-indexed) to read fuse for - */ -NvU32 -knvdecReadUcodeFuseVersion_GA100 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec, - const NvU32 ucodeId -) -{ - NvU32 fuseVal = 0; - NvU32 index = ucodeId - 1; // adjust to 0-indexed - - // TODO: Bug 3519329: switch to indexed register once available - // if (index < NV_FUSE_OPT_FPF_NVDEC_UCODE_VERSION__SIZE_1) - if (index < 16) - { - // fuseVal = GPU_REG_IDX_RD_DRF(pGpu, _FUSE, _OPT_FPF_NVDEC_UCODE_VERSION, index, _DATA); - fuseVal = GPU_REG_RD32(pGpu, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION + (4 * index)); - - if (fuseVal) - { - HIGHESTBITIDX_32(fuseVal); - fuseVal = fuseVal + 1; - } - } - - return fuseVal; -} diff --git a/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga102.c b/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga102.c deleted file mode 100644 index 62ba012ee..000000000 --- a/src/nvidia/src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga102.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/nvdec/kernel_nvdec.h" - -#include "core/core.h" -#include "gpu/falcon/kernel_falcon.h" -#include "gpu/gpu.h" -#include "os/nv_memory_type.h" - -#include "published/ampere/ga102/dev_falcon_second_pri.h" -#include "published/ampere/ga100/dev_fuse.h" -#include "published/ampere/ga102/dev_boot.h" -#include "published/ampere/ga102/dev_nvdec_pri.h" -#include "published/ampere/ga102/dev_nvdec_addendum.h" - -void -knvdecConfigureFalcon_GA102 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - KernelFalconEngineConfig falconConfig; - - portMemSet(&falconConfig, 0, sizeof(falconConfig)); - - falconConfig.registerBase = DRF_BASE(NV_PNVDEC(0)); - falconConfig.riscvRegisterBase = NV_FALCON2_NVDEC0_BASE; - falconConfig.fbifBase = NV_PNVDEC_FBIF_BASE(0); - falconConfig.bBootFromHs = NV_TRUE; - falconConfig.pmcEnableMask = DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED); - falconConfig.bIsPmcDeviceEngine = NV_TRUE; - falconConfig.physEngDesc = ENG_NVDEC(0); - falconConfig.ctxAttr = NV_MEMORY_UNCACHED; - falconConfig.ctxBufferSize = FLCN_CTX_ENG_BUFFER_SIZE_HW; - falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); - - kflcnConfigureEngine(pGpu, staticCast(pKernelNvdec, KernelFalcon), &falconConfig); -} - -NvBool -knvdecIsEngineDisabled_GA102 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - NvU32 reg = GPU_REG_RD32(pGpu, NV_FUSE_OPT_NVDEC_DISABLE); - NvU32 field = DRF_VAL(_FUSE, _OPT_NVDEC_DISABLE, _DATA, reg); - // highest bit in field will read 1 if NVDEC0 is disabled - return (NVBIT(DRF_SIZE(NV_FUSE_OPT_NVDEC_DISABLE_DATA) - 1) & field) > 0; -} diff --git a/src/nvidia/src/kernel/gpu/nvdec/arch/turing/kernel_nvdec_tu102.c b/src/nvidia/src/kernel/gpu/nvdec/arch/turing/kernel_nvdec_tu102.c deleted file mode 100644 index 745a549f2..000000000 --- a/src/nvidia/src/kernel/gpu/nvdec/arch/turing/kernel_nvdec_tu102.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/nvdec/kernel_nvdec.h" - -#include "core/core.h" -#include "gpu/falcon/kernel_falcon.h" -#include "gpu/gpu.h" -#include "os/nv_memory_type.h" - -#include "published/turing/tu102/dev_falcon_v4.h" -#include "published/turing/tu102/dev_boot.h" -#include "published/turing/tu102/dev_fuse.h" -#include "published/turing/tu102/dev_nvdec_pri.h" -#include "published/turing/tu102/dev_nvdec_addendum.h" - -void -knvdecConfigureFalcon_TU102 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - KernelFalconEngineConfig falconConfig; - - portMemSet(&falconConfig, 0, sizeof(falconConfig)); - - falconConfig.registerBase = DRF_BASE(NV_PNVDEC(0)); - falconConfig.riscvRegisterBase = 0; // RISC-V unused or unsupported - falconConfig.fbifBase = NV_PNVDEC_FBIF_BASE(0); - falconConfig.bBootFromHs = NV_FALSE; - falconConfig.pmcEnableMask = DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED); - falconConfig.bIsPmcDeviceEngine = NV_FALSE; - falconConfig.physEngDesc = ENG_NVDEC(0); - falconConfig.ctxAttr = NV_MEMORY_UNCACHED; - falconConfig.ctxBufferSize = FLCN_CTX_ENG_BUFFER_SIZE_HW; - falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); - - kflcnConfigureEngine(pGpu, staticCast(pKernelNvdec, KernelFalcon), &falconConfig); -} - -NvBool -knvdecIsEngineDisabled_TU102 -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec -) -{ - NvU32 reg = GPU_REG_RD32(pGpu, NV_FUSE_OPT_NVDEC_DISABLE); - NvU32 field = DRF_VAL(_FUSE, _OPT_NVDEC_DISABLE, _DATA, reg); - // highest bit in field will read 1 if NVDEC0 is disabled - return (NVBIT(DRF_SIZE(NV_FUSE_OPT_NVDEC_DISABLE_DATA) - 1) & field) > 0; -} - -void knvdecNonstallIntrCheckAndClear_TU102(OBJGPU *pGpu, KernelNvdec *pKernelNvdec, THREAD_STATE_NODE *pThreadState) -{ - NvU32 registerBase = staticCast(pKernelNvdec, KernelFalcon)->registerBase; - NvU32 intr; - NvU32 clearBits; - - NV_ASSERT(registerBase != 0); - - intr = GPU_REG_RD32_EX(pGpu, registerBase + NV_PFALCON_FALCON_IRQSTAT, - pThreadState); - - if (DRF_VAL( _PFALCON_FALCON, _IRQSTAT, _SWGEN1, intr)) - { - NV_PRINTF(LEVEL_INFO, "Handling Trap Interrupt\n"); - - // Clear interrupt - clearBits = DRF_NUM(_PFALCON_FALCON, _IRQSTAT, _SWGEN1, 1); - GPU_REG_WR32_EX(pGpu, registerBase + NV_PFALCON_FALCON_IRQSCLR, - clearBits, pThreadState); - } -} diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec.c deleted file mode 100644 index bad851159..000000000 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/nvdec/kernel_nvdec.h" - -#include "core/core.h" -#include "gpu/eng_desc.h" -#include "gpu/falcon/kernel_falcon.h" -#include "gpu/gpu.h" - -NV_STATUS -knvdecConstructEngine_IMPL -( - OBJGPU *pGpu, - KernelNvdec *pKernelNvdec, - ENGDESCRIPTOR engDesc -) -{ - if (knvdecIsEngineDisabled_HAL(pGpu, pKernelNvdec)) - { - // fail construction of KernelNvdec if NVDEC0 engine is missing in HW - return NV_ERR_NOT_SUPPORTED; - } - - knvdecConfigureFalcon_HAL(pGpu, pKernelNvdec); - return NV_OK; -} - -void knvdecRegisterIntrService_IMPL(OBJGPU *pGpu, KernelNvdec *pKernelNvdec, IntrServiceRecord pRecords[MC_ENGINE_IDX_MAX]) -{ - KernelFalcon *pKernelFalcon = staticCast(pKernelNvdec, KernelFalcon); - NV_ASSERT_OR_RETURN_VOID(pKernelFalcon); - - NV_PRINTF(LEVEL_INFO, "physEngDesc 0x%x\n", pKernelFalcon->physEngDesc); - - NV_ASSERT(pKernelFalcon->physEngDesc == ENG_NVDEC(0)); - - NvU32 mcIdx = MC_ENGINE_IDX_NVDEC0; - - NV_ASSERT(pRecords[mcIdx].pNotificationService == NULL); - pRecords[mcIdx].bFifoWaiveNotify = NV_FALSE; - pRecords[mcIdx].pNotificationService = staticCast(pKernelNvdec, IntrService); -} - -NV_STATUS knvdecServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, KernelNvdec *pKernelNvdec, IntrServiceServiceNotificationInterruptArguments *pParams) -{ - NvU32 idxMc = pParams->engineIdx; - NvU32 idx2080 = NV2080_ENGINE_TYPE_NVDEC0; - - NV_PRINTF(LEVEL_INFO, "nonstall intr for MC 0x%x\n", idxMc); - - NV_ASSERT_OR_RETURN(idxMc == MC_ENGINE_IDX_NVDEC0, NV_ERR_INVALID_STATE); - - knvdecNonstallIntrCheckAndClear_HAL(pGpu, pKernelNvdec, pParams->pThreadState); - - // Wake up channels waiting on this event - engineNonStallIntrNotify(pGpu, idx2080); - - return NV_OK; -} diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c index 4a3b05f00..c1e01389e 100644 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c @@ -29,12 +29,14 @@ #include "class/cla0b0.h" // NVA0B0_VIDEO_DECODER #include "class/clb0b0.h" // NVB0B0_VIDEO_DECODER #include "class/clb6b0.h" // NVB6B0_VIDEO_DECODER +#include "class/clb8b0.h" // NVB8B0_VIDEO_DECODER #include "class/clc1b0.h" // NVC1B0_VIDEO_DECODER #include "class/clc2b0.h" // NVC2B0_VIDEO_DECODER #include "class/clc3b0.h" // NVC3B0_VIDEO_DECODER #include "class/clc4b0.h" // NVC4B0_VIDEO_DECODER #include "class/clc6b0.h" // NVC6B0_VIDEO_DECODER #include "class/clc7b0.h" // NVC7B0_VIDEO_DECODER +#include "class/clc9b0.h" // NVC9B0_VIDEO_DECODER /* * This function returns an engine descriptor corresponding to the class @@ -82,6 +84,8 @@ nvdecGetEngineDescFromAllocParams case NVC4B0_VIDEO_DECODER: case NVC6B0_VIDEO_DECODER: case NVC7B0_VIDEO_DECODER: + case NVC9B0_VIDEO_DECODER: + case NVB8B0_VIDEO_DECODER: engineInstance = pNvdecAllocParams->engineInstance; break; default: diff --git a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c index 1d1e627b1..e95a4726c 100644 --- a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c @@ -33,6 +33,7 @@ #include "class/clc4b7.h" #include "class/clb4b7.h" #include "class/clc7b7.h" +#include "class/clc9b7.h" /* * This function returns an engine descriptor corresponding to the class @@ -72,6 +73,7 @@ msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAl case NVC4B7_VIDEO_ENCODER: case NVB4B7_VIDEO_ENCODER: case NVC7B7_VIDEO_ENCODER: + case NVC9B7_VIDEO_ENCODER: engineInstance = pMsencAllocParms->engineInstance; break; default: diff --git a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c index b41bdb40d..7be2d38ae 100644 --- a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c @@ -27,6 +27,8 @@ #include "resserv/rs_server.h" #include "class/clc4d1.h" // NVC4D1_VIDEO_NVJPG +#include "class/clb8d1.h" // NVB8D1_VIDEO_NVJPG +#include "class/clc9d1.h" // NVC9D1_VIDEO_NVJPG /*! * This function returns an engine descriptor corresponding to the class @@ -66,6 +68,10 @@ nvjpgGetEngineDescFromAllocParams case NVC4D1_VIDEO_NVJPG: engineInstance = 0; break; + case NVB8D1_VIDEO_NVJPG: + case NVC9D1_VIDEO_NVJPG: + engineInstance = pNvjpgAllocParms->engineInstance; + break; default: DBG_BREAKPOINT(); return ENG_INVALID; diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c index e706aaaa7..b6f17f329 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c @@ -132,6 +132,8 @@ knvlinkRemoveMapping_GA100 ) { NV_STATUS status = NV_OK; + NvU32 peerId; + NvBool bBufferReady = NV_FALSE; NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); @@ -161,7 +163,35 @@ knvlinkRemoveMapping_GA100 // the MUX registers and the connection config registers. So, we have // to call nvlinkCurrentConfig instead of nvlinkUpdateHshubConfigRegs // - return knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + if (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK)) + { + FOR_EACH_INDEX_IN_MASK(32, peerId, peerMask) + { + if (pKernelNvlink->initializedLinks & pKernelNvlink->peerLinkMasks[peerId]) + { + bBufferReady = NV_TRUE; + break; + } + } FOR_EACH_INDEX_IN_MASK_END; + + if (!bBufferReady) + { + status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } + } + else + { + status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } + + return status; } /*! diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c new file mode 100644 index 000000000..1779cf960 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -0,0 +1,296 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "os/os.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/nvlink/kernel_ioctrl.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" + +/*! + * @brief Check if ALI is supported for the given device + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + */ +NV_STATUS +knvlinkIsAliSupported_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NvU32 status = NV_OK; + + NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + // Initialize to default settings + params.bEnableAli = NV_FALSE; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get ALI enablement status!\n"); + return status; + } + + pKernelNvlink->bEnableAli = params.bEnableAli; + + return status; +} + +/*! + * @brief Validates fabric base address. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] fabricBaseAddr Address to be validated + * + * @returns On success, NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +knvlinkValidateFabricBaseAddress_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU64 fabricBaseAddr +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 fbSizeBytes; + + fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; + + // + // Hopper SKUs will be paired with NVSwitches (Limerock-next) supporting 2K + // mapslots that can cover 512GB each. Make sure that the fabric base + // address being used is valid to cover whole frame buffer. + // + + // Check if fabric address is aligned to mapslot size. + if (fabricBaseAddr & (NVBIT64(39) - 1)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Align fbSize to mapslot size. + fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(39)); + + return NV_OK; +} + +/*! + * @brief Do post setup on nvlink peers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + */ +NV_STATUS +knvlinkPostSetupNvlinkPeer_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NvU32 status = NV_OK; + NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS postSetupNvlinkPeerParams; + + portMemSet(&postSetupNvlinkPeerParams, 0, sizeof(postSetupNvlinkPeerParams)); + + postSetupNvlinkPeerParams.peerMask = (1 << NVLINK_MAX_PEERS_SW) - 1; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER, + (void *)&postSetupNvlinkPeerParams, + sizeof(postSetupNvlinkPeerParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to program post active settings and bufferready!\n"); + return status; + } + + return status; +} + +/*! + * @brief Discover all links that are training or have been + * trained on both GPUs + * + * @param[in] pGpu OBJGPU pointer for local GPU + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] pPeerGpu OBJGPU pointer for remote GPU + * + * @return NV_OK if links are detected to be training + */ +NV_STATUS +knvlinkDiscoverPostRxDetLinks_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + OBJGPU *pPeerGpu +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + +#if defined(INCLUDE_NVLINK_LIB) + + OBJGPU *pGpu0 = pGpu; + OBJGPU *pGpu1 = pPeerGpu; + KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); + KernelNvlink *pKernelNvlink1 = NULL; + + if (pGpu1 == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid pPeerGpu.\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + else if ((pGpu0 == pGpu1) && + (pGpu0->getProperty(pGpu0, PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED))) + { + // P2P over loopback links are disabled through regkey overrides + NV_PRINTF(LEVEL_INFO, "loopback P2P on GPU%u disabled by regkey\n", + gpuGetInstance(pGpu0)); + + return NV_ERR_NOT_SUPPORTED; + } + else + { + pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); + } + + if (pKernelNvlink1 == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Input mask contains a GPU on which NVLink is disabled.\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + if ((IS_RTLSIM(pGpu) && !pKernelNvlink0->bForceEnableCoreLibRtlsims) || + (pKernelNvlink0->pNvlinkDev == NULL) || + !pKernelNvlink0->bEnableAli || + (pKernelNvlink1->pNvlinkDev == NULL) || + !pKernelNvlink1->bEnableAli) + { + NV_PRINTF(LEVEL_INFO, + "Not in ALI, checking PostRxDetLinks not supported.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // + // Initialize Mask of links that have made it past RxDet to 0 then + // request to get all links from the given GPU that have gotted past RxDet + // + pKernelNvlink0->postRxDetLinkMask = 0; + status = knvlinkUpdatePostRxDetectLinkMask(pGpu0, pKernelNvlink0); + if(status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Getting peer0's postRxDetLinkMask failed!\n"); + return NV_ERR_INVALID_STATE; + } + + // Only query if we are not in loopback + if (pKernelNvlink0 != pKernelNvlink1) + { + pKernelNvlink1->postRxDetLinkMask = 0; + status = knvlinkUpdatePostRxDetectLinkMask(pGpu1, pKernelNvlink1); + if(status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Getting peer1's postRxDetLinkMask failed!\n"); + return NV_ERR_INVALID_STATE; + } + } + + // + // If the current gpu has no actively training or trained link OR + // if the peer gpu has no actively training or trained links then + // return an error. If either side has 0 links passed RxDet then + // there is no chance that we will find links connecting the devices + // further into discovery. + // + if(pKernelNvlink0->postRxDetLinkMask == 0 || + pKernelNvlink1->postRxDetLinkMask == 0) + { + NV_PRINTF(LEVEL_ERROR, "Got 0 post RxDet Links!"); + return NV_ERR_NOT_READY; + } + +#endif + + return status; +} + +/*! + * @brief Check if floorsweeping is needed for this particular chip + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NvBool +knvlinkIsFloorSweepingNeeded_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 numActiveLinksPerIoctrl, + NvU32 numLinksPerIoctrl +) +{ + + // + // Only floorsweep down the given GPU if the following conditions are met: + // 1. if the number of links for the IP is > 0 + // + // 2. The number of active links allowed for the IOCTRL is less then the + // total number of links for the IOCTRL. No reason to spend time in code + // if the exectution of it will be a NOP + // + // 3. If the GPU has never been floorswept. An optimization to make sure RM + // doesn't burn cycles repeatedly running running code that will be a NOP + // + // 4. (temporary) Run only on Silicon chips. Fmodel currently doesn't support + // this feature + // + + if ((numLinksPerIoctrl > 0 && numActiveLinksPerIoctrl > 0) && + numActiveLinksPerIoctrl < numLinksPerIoctrl && + !pKernelNvlink->bFloorSwept && + IS_SILICON(pGpu)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c index d5d4ae29f..b79b7b11c 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c @@ -80,6 +80,74 @@ kioctrlMinionConstruct_GV100 break; } + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _CACHE_SEEDS, pKernelNvlink->minionControl)) + { + case NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_ENABLE: + { + NV_PRINTF(LEVEL_INFO, + "Regkey: Minion seed caching is force enabled\n"); + pKernelIoctrl->setProperty(pKernelIoctrl, PDB_PROP_KIOCTRL_MINION_CACHE_SEEDS, NV_TRUE); + break; + } + case NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_DISABLE: + { + NV_PRINTF(LEVEL_INFO, + "Regkey: Minion seed caching is force disabled\n"); + pKernelIoctrl->setProperty(pKernelIoctrl, PDB_PROP_KIOCTRL_MINION_CACHE_SEEDS, NV_FALSE); + break; + } + } + + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _ALI_TRAINING, pKernelNvlink->minionControl)) + { + case NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_ENABLE: + { + NV_PRINTF(LEVEL_INFO, + "Regkey: ALI training is force enabled\n"); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING, NV_TRUE); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING, NV_FALSE); + break; + } + case NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_DISABLE: + { + NV_PRINTF(LEVEL_INFO, + "Regkey: non-ALI training is force enabled\n"); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING, NV_TRUE); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING, NV_FALSE); + break; + } + default: + { + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING, NV_FALSE); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING, NV_FALSE); + break; + } + } + + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _GFW_BOOT_DISABLE, pKernelNvlink->minionControl)) + { + case NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DISABLE: + { + NV_PRINTF(LEVEL_INFO, + "Regkey: Minion boot from GFW disabled\n"); + pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT, NV_FALSE); + break; + } + default: + { + if (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + { + NV_PRINTF(LEVEL_INFO, + "Regkey: Minion boot from GFW enabled by default\n"); + } + else + { + NV_PRINTF(LEVEL_INFO, + "Regkey: Minion boot from GFW disabled by default\n"); + } + break; + } + } } // Flush the final minion enable setting diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index 8cdefd074..0cffe3181 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -349,7 +349,11 @@ knvlinkGetP2pConnectionStatus_IMPL } // Get the remote ends of the links of local GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of local GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu0, pKernelNvlink0, @@ -365,7 +369,11 @@ knvlinkGetP2pConnectionStatus_IMPL if (knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) != numPeerLinks) { // Get the remote ends of the links of remote GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of remote GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu1, pKernelNvlink1, @@ -484,12 +492,12 @@ knvlinkUpdateCurrentConfig_IMPL { pKCe = GPU_GET_KCE(pGpu, i); if (pKCe) + { + status = kceTopLevelPceLceMappingsUpdate(pGpu, pKCe); + if (status != NV_OK) { - status = kceTopLevelPceLceMappingsUpdate(pGpu, pKCe); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to update PCE-LCE mappings\n"); - } + NV_PRINTF(LEVEL_ERROR, "Failed to update PCE-LCE mappings\n"); + } break; } } @@ -729,7 +737,8 @@ NV_STATUS knvlinkPrepareForXVEReset_IMPL ( OBJGPU *pGpu, - KernelNvlink *pKernelNvlink + KernelNvlink *pKernelNvlink, + NvBool bForceShutdown ) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -766,7 +775,8 @@ knvlinkPrepareForXVEReset_IMPL if ((pRemoteGpu == pGpu) || (pRemoteKernelNvlink == NULL) || (knvlinkGetNumLinksToPeer(pRemoteGpu, pRemoteKernelNvlink, pGpu) == 0) || - API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) + API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu) || + pRemoteGpu->getProperty(pRemoteGpu, PDB_PROP_GPU_IS_LOST)) { continue; } @@ -804,6 +814,7 @@ knvlinkPrepareForXVEReset_IMPL } // Remove all NVLink mappings in HSHUB config registers to init values + if (!API_GPU_IN_RESET_SANITY_CHECK(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) status = knvlinkRemoveMapping_HAL(pGpu, pKernelNvlink, NV_TRUE, ((1 << NVLINK_MAX_PEERS_SW) - 1), NV_FALSE /* bL2Entry */); if (status != NV_OK) @@ -815,8 +826,17 @@ knvlinkPrepareForXVEReset_IMPL retStatus = (retStatus == NV_OK) ? status : retStatus; } + // + // If GFW is booted and running through link-training, then no need to tear-down the + // links to reset. Exit out early from the function + // + if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + { + return NV_OK; + } + // Pseudo-clean shutdown the links from this GPU - status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink); + status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, bForceShutdown); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1197,7 +1217,7 @@ knvlinkUpdateLinkConnectionStatus_IMPL #if defined(INCLUDE_NVLINK_LIB) - params.bConnected = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected; + params.bConnected = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected; params.remoteDeviceType = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.deviceType; params.remoteLinkNumber = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber; @@ -1221,6 +1241,96 @@ knvlinkUpdateLinkConnectionStatus_IMPL return NV_OK; } +/*! + * @brief Execute initial steps to Train links for ALI. + * + * @param[in] pGpu OBJGPU pointer for local GPU + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] linkMask Masks of links to enable + * @param[in] bSync Input sync boolean + * + */ +NV_STATUS +knvlinkPreTrainLinksToActiveAli_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 linkMask, + NvBool bSync +) +{ + NV_STATUS status = NV_OK; + + NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + params.linkMask = linkMask; + params.bSync = bSync; + + // Reset timeout to clear any accumulated timeouts from link init + if (IS_GSP_CLIENT(pGpu)) + { + threadStateResetTimeout(pGpu); + } + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to execute Pre Link Training ALI steps!\n"); + return status; + } + + return NV_OK; +} + +/*! + * @brief Train links to active for ALI. + * + * @param[in] pGpu OBJGPU pointer for local GPU + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] linkMask Masks of links to enable + * @param[in] bSync Input sync boolean + * + */ +NV_STATUS +knvlinkTrainLinksToActiveAli_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 linkMask, + NvBool bSync +) +{ + NV_STATUS status = NV_OK; + + NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + params.linkMask = linkMask; + params.bSync = bSync; + + // Reset timeout to clear any accumulated timeouts from link init + if (IS_GSP_CLIENT(pGpu)) + { + threadStateResetTimeout(pGpu); + } + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to change ALI Links to active!\n"); + return status; + } + + return NV_OK; +} + /*! * @brief Update the post Rx Detect link mask. * @@ -1604,6 +1714,72 @@ knvlinkSetUniqueFabricBaseAddress_IMPL return NV_OK; } +/*! + * @brief Get the number of active links allowed per IOCTRL + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On success, returns the number of active links per IOCTRL. + * On failure, returns 0. + */ +NvU32 +knvlinkGetNumActiveLinksPerIoctrl_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV_STATUS status; + NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get the number of active links per IOCTRL\n"); + return 0; + } + + return params.numActiveLinksPerIoctrl; +} + +/*! + * @brief Get the number of total links per IOCTRL + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On success, returns the number of total links per IOCTRL. + * On failure, returns 0. + */ +NvU32 +knvlinkGetTotalNumLinksPerIoctrl_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV_STATUS status; + NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get the total number of links per IOCTRL\n"); + return 0; + } + + return params.numLinksPerIoctrl; +} + /** * @brief Process the mask of init disabled links * diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c index 3bc34dfd5..c05bd97c2 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c @@ -137,6 +137,18 @@ knvlinkCtrlCmdBusGetNvlinkCaps switch (pKernelNvlink->ipVerNvlink) { + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L1); + break; + } case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: { pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1; @@ -229,6 +241,7 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL NvU32 r = 0; NvBool bPeerLink, bSysmemLink, bSwitchLink; NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS nvlinkLinkAndClockInfoParams; + NvBool bIsNvlinkReady = NV_TRUE; // // vGPU: @@ -269,21 +282,40 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - pParams->enabledLinkMask = pKernelNvlink->enabledLinks; - - r = pParams->enabledLinkMask; - while (r >>= 1 ) i++; - - NV_ASSERT(i <= NV2080_CTRL_NVLINK_MAX_LINKS); - // Get the remote ends of the links from the nvlink core if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink) && !(IS_RTLSIM(pGpu) && !pKernelNvlink->bForceEnableCoreLibRtlsims)) { // Get the nvlink connections for this device from the core knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + + + // + // Get the nvlink connections for this device from the core + // If the function fails then the corelib doesn't have enough + // info to validate connectivity so we should mark the API call + // as not ready + // + status = knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + if (status == NV_ERR_NOT_READY) + { + NV_PRINTF(LEVEL_INFO, "Nvlink is not ready yet!\n"); + bIsNvlinkReady = NV_FALSE; + } + else if (status != NV_OK) + { + return status; + } } + // If nvlink is not ready don't report back any links as being enabled + pParams->enabledLinkMask = (bIsNvlinkReady) ? pKernelNvlink->enabledLinks : 0x0; + + r = pParams->enabledLinkMask; + while (r >>= 1 ) i++; + + NV_ASSERT(i <= NV2080_CTRL_NVLINK_MAX_LINKS); + // // Some links might have passed receiver detect (bridge is present), // but might have failed to transition to safe mode (marginal links) @@ -294,6 +326,7 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL portMemSet(&nvlinkLinkAndClockInfoParams, 0, sizeof(nvlinkLinkAndClockInfoParams)); nvlinkLinkAndClockInfoParams.linkMask = pParams->enabledLinkMask; + nvlinkLinkAndClockInfoParams.bSublinkStateInst = pParams->bSublinkStateInst; status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO, @@ -360,6 +393,8 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); break; + + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: @@ -388,7 +423,10 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL switch (pKernelNvlink->ipVerNvlink) { - + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0; + break; case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1; pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c index 260bc6bfb..23d5d869d 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c @@ -207,6 +207,10 @@ knvlinkCoreAddDevice_IMPL dev->pciInfo.bars[0].baseAddr = pGpu->pKernelBus->pciBars[0]; dev->pciInfo.bars[0].barSize = pGpu->pKernelBus->pciBarSizes[0]; dev->initialized = 1; + dev->enableALI = pKernelNvlink->bEnableAli; + dev->numIoctrls = nvPopCount32(pKernelNvlink->ioctrlMask); + dev->numActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); + dev->numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); // Register the GPU in nvlink core if (nvlink_lib_register_device(dev) != 0) @@ -392,6 +396,7 @@ knvlinkCoreAddLink_IMPL link->tx_sublink_state = NVLINK_SUBLINK_STATE_TX_OFF; link->rx_sublink_state = NVLINK_SUBLINK_STATE_RX_OFF; link->bRxDetected = NV_FALSE; + link->bInitphase5Fails = NV_FALSE; link->version = pKernelNvlink->ipVerNvlink; link->dev = pKernelNvlink->pNvlinkDev; link->link_info = &(pKernelNvlink->nvlinkLinks[linkId]); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c index bff61d32b..662429f76 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c @@ -66,6 +66,8 @@ ct_assert(NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM == NVLINK_LINKSTATE_ENABLE_PM); ct_assert(NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM == NVLINK_LINKSTATE_DISABLE_PM); +ct_assert(NV2080_NVLINK_CORE_LINK_STATE_SLEEP == + NVLINK_LINKSTATE_SLEEP); ct_assert(NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE == NVLINK_LINKSTATE_SAVE_STATE); ct_assert(NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE == @@ -96,6 +98,12 @@ ct_assert(NV2080_NVLINK_CORE_LINK_STATE_CONTAIN == NVLINK_LINKSTATE_CONTAIN); ct_assert(NV2080_NVLINK_CORE_LINK_STATE_INITTL == NVLINK_LINKSTATE_INITTL); +ct_assert(NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 == + NVLINK_LINKSTATE_INITPHASE5); +ct_assert(NV2080_NVLINK_CORE_LINK_STATE_ALI == + NVLINK_LINKSTATE_ALI); +ct_assert(NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING == + NVLINK_LINKSTATE_ACTIVE_PENDING); /*! * Compile time asserts to ensure NV2080_NVLINK_CORE_SUBLINK_STATE_TX* == @@ -1300,6 +1308,35 @@ knvlinkCoreWriteDiscoveryTokenCallback pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + // + // If Nvlink4.0+ get the "token" values via SIDs stored + // by MINION + // + if (pNvlinkLink->ipVerDlPl >= NVLINK_VERSION_40) + { + NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); + params.linkId = pNvlinkLink->linkId; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating Local/Remote SID Info!\n"); + return status; + } + + link->remoteSid = + params.remoteLocalSidInfo.remoteSid; + link->remoteDeviceType = + params.remoteLocalSidInfo.remoteDeviceType; + link->remoteLinkId = + params.remoteLocalSidInfo.remoteLinkId; + link->localSid = + params.remoteLocalSidInfo.localSid; + } + else { NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS params; @@ -1377,6 +1414,12 @@ knvlinkCoreReadDiscoveryTokenCallback pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + // If Nvlink4.0+ then reading tokens is no longer supported + if (pNvlinkLink->ipVerDlPl >= NVLINK_VERSION_40) + { + status = NV_ERR_NOT_SUPPORTED; + } + else { params.linkId = pNvlinkLink->linkId; params.callbackType.type = @@ -1446,6 +1489,50 @@ knvlinkCoreTrainingCompleteCallback } } +/* + * @brief nvlinkCoreGetUphyLoadCallback send ALI training on the specified link + * + * @param[in] link nvlink_link pointer + */ +NvlStatus +knvlinkCoreAliTrainingCallback +( + nvlink_link *link +) +{ + KNVLINK_RM_LINK *pNvlinkLink = (KNVLINK_RM_LINK *) link->link_info; + POBJGPU pGpu = pNvlinkLink->pGpu; + KernelNvlink * pKernelNvlink = NULL; + NV_STATUS status; + + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Error processing link info!\n"); + return 1; + } + + pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + status = knvlinkPreTrainLinksToActiveAli(pGpu, pKernelNvlink, + BIT(pNvlinkLink->linkId), NV_TRUE); + if (status != NV_OK) + { + goto knvlinkCoreAliTrainingCallback_end; + } + + status = knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, NVBIT(pNvlinkLink->linkId), NV_FALSE); + +knvlinkCoreAliTrainingCallback_end: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to request Link %d to transition to active\n", pNvlinkLink->linkId); + return 1; + } + + return 0; +} + /*! * @brief nvlinkCoreGetUphyLoadCallback checks if uphy is locked * diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index 4c15f45c6..a64984e49 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -80,7 +80,10 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL NvBool bNvswitchProxyPresent = NV_FALSE; NvBool bUpdateConnStatus = NV_FALSE; NvBool bCheckDegradedMode = NV_FALSE; + nvlink_conn_info conn_info; NvU32 linkId; + NvU32 numActiveLinksPerIoctrl = 0; + NvU32 numLinksPerIoctrl = 0; // // Topology discovery should NOT be triggered in RTD3/FGC6 exit path if L2 is @@ -97,10 +100,42 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL bNvswitchProxyPresent = knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink); } + if (pKernelNvlink->bEnableAli) + { + // Update the post Rx Det link Mask for the GPU + knvlinkUpdatePostRxDetectLinkMask(pGpu, pKernelNvlink); + } + + if (pKernelNvlink->ipVerNvlink >= NVLINK_VERSION_40 && + !bNvswitchProxyPresent && + !pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED) && + pKernelNvlink->pNvlinkDev != NULL) + { + numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); + status = knvlinkFloorSweep(pGpu, pKernelNvlink, + numLinksPerIoctrl, &numActiveLinksPerIoctrl); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to floorsweep valid nvlink config!\n"); + return NV_ERR_NOT_READY; + } + } + // We only need to look at links that are still considered disconnected FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->disconnectedLinkMask) { - nvlink_conn_info conn_info = {0}; + // + // If we are using ALI training, make sure the + // disconneted link is a valid link that is progressing + // passed RxDet + // + if (pKernelNvlink->bEnableAli && + !(pKernelNvlink->postRxDetLinkMask & NVBIT(linkId))) + { + continue; + } + bUpdateConnStatus = NV_FALSE; if (pKernelNvlink->nvlinkLinks[linkId].core_link) @@ -322,9 +357,12 @@ knvlinkCheckTrainingIsComplete_IMPL NV_STATUS status = NV_OK; #if defined(INCLUDE_NVLINK_LIB) - OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 version = pKernelNvlink0->ipVerNvlink; KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); + NvU32 count = 0; + NvU32 i; if (pKernelNvlink1 == NULL) { @@ -334,6 +372,8 @@ knvlinkCheckTrainingIsComplete_IMPL return NV_ERR_INVALID_ARGUMENT; } + nvlink_link *pLinks[NVLINK_MAX_LINKS_SW] = { 0 }; + // Link training will be triggered from KMD in L2 exit path if (knvlinkPoweredUpForD3_HAL(pGpu0, pKernelNvlink0)) { @@ -373,6 +413,127 @@ knvlinkCheckTrainingIsComplete_IMPL return NV_OK; } + // + // If ALI then ensure it has completed + // Else run through training for legacy nvlink versions + // + if (pKernelNvlink0->bEnableAli || pKernelNvlink1->bEnableAli) + { + // polling for train complete is only allowed for NvLink 4.0+ + NV_ASSERT(version >= NVLINK_VERSION_40); + + // + // Check to make sure that the links for the first GPU have + // all completed training + // + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink0->postRxDetLinkMask) + { + pLinks[count] = pKernelNvlink0->nvlinkLinks[i].core_link; + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + + // If the return code is non-zero, links are still training + if (nvlink_lib_check_training_complete(pLinks, count) != 0) + { + if (pKernelNvlink0->bLinkTrainingDebugSpew) + { + NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); + } + return NV_ERR_GENERIC; + } + + // + // For all links in the postRxDetLinkMask, get it's peer + // links information + // + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink0->postRxDetLinkMask) + { + NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); + + params.linkId = i; + + status = knvlinkExecGspRmRpc(pGpu0, pKernelNvlink0, + NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating Local/Remote Sid Info!\n"); + return status; + } + + pKernelNvlink0->nvlinkLinks[i].core_link->remoteSid = + params.remoteLocalSidInfo.remoteSid; + pKernelNvlink0->nvlinkLinks[i].core_link->remoteDeviceType = + params.remoteLocalSidInfo.remoteDeviceType; + pKernelNvlink0->nvlinkLinks[i].core_link->remoteLinkId = + params.remoteLocalSidInfo.remoteLinkId; + pKernelNvlink0->nvlinkLinks[i].core_link->localSid = + params.remoteLocalSidInfo.localSid; + } + FOR_EACH_INDEX_IN_MASK_END; + + // Only enter if not in loopBack + if (pKernelNvlink0 != pKernelNvlink1) + { + // + // Check to make sure that the links for the second GPU have + // all completed training. Reset count for this GPU prior + // to querying for the links + // + count = 0; + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink1->postRxDetLinkMask) + { + pLinks[count] = pKernelNvlink1->nvlinkLinks[i].core_link; + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + + // If the return code is non-zero, links are still training + if (nvlink_lib_check_training_complete(pLinks, count) != 0) + { + if (pKernelNvlink1->bLinkTrainingDebugSpew) + { + NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); + } + + return NV_ERR_GENERIC; + } + + // + // For all links in the postRxDetLinkMask, get it's peer + // links information + // + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink1->postRxDetLinkMask) + { + NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); + + params.linkId = i; + + status = knvlinkExecGspRmRpc(pGpu1, pKernelNvlink1, + NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating Local/Remote Sid Info!\n"); + return status; + } + + pKernelNvlink1->nvlinkLinks[i].core_link->remoteSid = + params.remoteLocalSidInfo.remoteSid; + pKernelNvlink1->nvlinkLinks[i].core_link->remoteDeviceType = + params.remoteLocalSidInfo.remoteDeviceType; + pKernelNvlink1->nvlinkLinks[i].core_link->remoteLinkId = + params.remoteLocalSidInfo.remoteLinkId; + pKernelNvlink1->nvlinkLinks[i].core_link->localSid = + params.remoteLocalSidInfo.localSid; + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + #endif return status; @@ -838,7 +999,8 @@ NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL ( OBJGPU *pGpu, - KernelNvlink *pKernelNvlink + KernelNvlink *pKernelNvlink, + NvBool bForceShutdown ) { #if defined(INCLUDE_NVLINK_LIB) @@ -867,6 +1029,14 @@ knvlinkCoreShutdownDeviceLinks_IMPL return NV_OK; } + if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + { + NV_PRINTF(LEVEL_INFO, + "GFW boot is enabled. Link shutdown is not required, skipping\n"); + + return NV_OK; + } + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) { // Capture the links for lane shutdown through core lib if supported @@ -1109,6 +1279,140 @@ knvlinkRetrainLink_IMPL return status; } +/*! + * @brief Floorsweep the nvlink config for the chip + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] numLinksPerIp number of total links found in discovery + * @param[out] pNumLinkActive number of links needed to be active + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +knvlinkFloorSweep_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 numLinksPerIoctrl, + NvU32 *pNumActiveLinksPerIoctrl +) +{ + +#if defined(INCLUDE_NVLINK_LIB) + NV_STATUS status = NV_OK; + NvU32 linkId; + NvU32 tmpDisabledLinkMask = 0; + NvU32 tmpEnabledLinkMask = 0; + nvlink_conn_info conn_info; + + *pNumActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); + if (!knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, *pNumActiveLinksPerIoctrl, numLinksPerIoctrl)) + { + return NV_OK; + } + + // The path here is important not getting the connection info + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + nvlink_lib_discover_and_get_remote_conn_info( + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + } + FOR_EACH_INDEX_IN_MASK_END; + + // floorsweeping in corelib will update connection info that RM qill query below + (void)nvlink_lib_powerdown_floorswept_links_to_off(pKernelNvlink->pNvlinkDev); + + // + // If a link in the enabledLinkMask is not trained after floorsweeping then + // then add it to a tmp disabled linkMask + // + + // Get the link train status for the enabled link masks + NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS linkTrainedParams; + + portMemSet(&linkTrainedParams, 0, sizeof(linkTrainedParams)); + linkTrainedParams.linkMask = pKernelNvlink->enabledLinks; + linkTrainedParams.bActiveOnly = NV_TRUE; + + // Reset timeout to clear any accumulated timeouts from link init + if (IS_GSP_CLIENT(pGpu)) + { + threadStateResetTimeout(pGpu); + } + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED, + (void *)&linkTrainedParams, + sizeof(linkTrainedParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get the link train status for links\n"); + return status; + } + + // + // Create a temporary mask of all links that are now enabled: + // classified as a link in active + // + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + if (linkTrainedParams.bIsLinkActive[linkId]) + { + tmpEnabledLinkMask |= BIT(linkId); + } + else + { + tmpDisabledLinkMask |= BIT(linkId); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // Redo linkMasks based on the search above being the ground truth + pKernelNvlink->enabledLinks = tmpEnabledLinkMask; + + // + // remove any links not in active in the tmpEnabledLinkMask from all + // other link masks as these have been floorswept by the corelib + // + pKernelNvlink->disconnectedLinkMask = tmpEnabledLinkMask; + pKernelNvlink->initDisabledLinksMask = tmpDisabledLinkMask; + + + status = knvlinkProcessInitDisabledLinks(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + // Re-sync the link masks with GSP + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + // + // Assert that the number of links in active is always less then + // or equal to the number of active links on the chips + // + if(!(nvPopCount32(tmpEnabledLinkMask) <= *pNumActiveLinksPerIoctrl * nvPopCount32(pKernelNvlink->ioctrlMask))) + { + NV_PRINTF(LEVEL_INFO, + "Floorsweeping didn't work! enabledMaskCount: 0x%x and numActiveLinksTotal: 0x%x. Current link info cached in SW: discoveredLinks: 0x%x; enabledLinks:0x%x; disconnectedLinks:0x%x; initDisabledLinksMask:0x%x\n", + nvPopCount32(tmpEnabledLinkMask), *pNumActiveLinksPerIoctrl * nvPopCount32(pKernelNvlink->ioctrlMask), pKernelNvlink->discoveredLinks, pKernelNvlink->enabledLinks, pKernelNvlink->disconnectedLinkMask, pKernelNvlink->initDisabledLinksMask); + + return NV_ERR_NOT_READY; + } + + pKernelNvlink->bFloorSwept = NV_TRUE; +#endif //INCLUDE_NVLINK_LIB + return NV_OK; +} + /*! * @brief Retrain the link from OFF state * @@ -1647,12 +1951,69 @@ _knvlinkExitSleep ) { NvlStatus status = NVL_SUCCESS; + NvlStatus trainingStatus = NVL_SUCCESS; NvU32 linkId; NvU32 remoteLinkId; NvU32 gpuInst; + RMTIMEOUT timeout; + NvU32 linkTrainingTimeout = 10000000; + NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS programBufferRdyParams; NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS saveRestoreHshubStateParams; + pKernelNvlink->bL2Entry = NV_FALSE; + + // Kick-off ALI if it is enabled + if (pKernelNvlink->bEnableAli) + { + // + // For each link, request a change to active. + // Don't have to wait for the request to finish as links + // will be queries via DLSTAT to know their status and training + // progression. + // + FOR_EACH_INDEX_IN_MASK(32, linkId, linkMask) + { + status = knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, NVBIT(linkId), NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to request Link %d to transition to active\n", linkId); + } +#if defined(INCLUDE_NVLINK_LIB) + pKernelNvlink->nvlinkLinks[linkId].core_link->bStateSaved = NV_FALSE; +#endif + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // Get all links that are passed RxDet after L2 exit and poll on those + // links till they reach active + // + if (knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pGpu) == NV_OK) + { + gpuSetTimeout(pGpu, linkTrainingTimeout, &timeout, IS_SILICON(pGpu) ? + (GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | GPU_TIMEOUT_FLAGS_DEFAULT) : 0); + do + { + + status = gpuCheckTimeout(pGpu, &timeout); + trainingStatus = knvlinkCheckTrainingIsComplete(pGpu, pGpu, pKernelNvlink); + if (trainingStatus == NV_OK) + { + break; + } + osSpinLoop(); + } + while (status != NV_ERR_TIMEOUT); + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR,"Timedout while checking to see if training complete!\n"); + } + } + } + else { // Wakeup the mask of links of the device from sleep using legacy l2 exit status = nvlink_lib_train_links_from_L2_to_active(pKernelNvlink->pNvlinkDev, diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c index 9c5820a59..71b2ffb84 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c @@ -62,6 +62,9 @@ knvlinkApplyRegkeyOverrides_IMPL pKernelNvlink->bDisableSingleLaneMode = NV_FALSE; pKernelNvlink->bDisableL2Mode = NV_FALSE; + // Debug Settings + pKernelNvlink->bLinkTrainingDebugSpew = NV_FALSE; + // Registry overrides for forcing NVLINK on/off if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_NVLINK_CONTROL, &pKernelNvlink->registryControl)) @@ -152,6 +155,15 @@ knvlinkApplyRegkeyOverrides_IMPL { pKernelNvlink->bForceAutoconfig = NV_FALSE; } + + if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_CONTROL, _LINK_TRAINING_DEBUG_SPEW, _ON, + pKernelNvlink->registryControl)) + { + pKernelNvlink->bLinkTrainingDebugSpew = NV_TRUE; + NV_PRINTF(LEVEL_INFO, + "Link training debug spew turned on!\n"); + } + } else if (!knvlinkIsNvlinkDefaultEnabled(pGpu, pKernelNvlink)) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index 39bc94dec..7ac0cf748 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -209,6 +209,17 @@ knvlinkConstructEngine_IMPL } } + // + // If not Silicon or EMU then GFW boot is not + // possible so set the property to false as soon + // as possible + // + if (!(IS_SILICON(pGpu) || IS_EMULATION(pGpu))) + { + pKernelNvlink->setProperty(pKernelNvlink, + PDB_PROP_KNVLINK_MINION_GFW_BOOT, NV_FALSE); + } + return NV_OK; } @@ -367,6 +378,14 @@ knvlinkStateLoad_IMPL if (!knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink) && !bMIGNvLinkP2PDisabled) { + // Set the link training mode to be used by the device + status = knvlinkIsAliSupported_HAL(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get ALI status\n"); + goto knvlinkStateLoad_end; + } + // Add the NVGPU device to the nvlink core status = knvlinkCoreAddDevice(pGpu, pKernelNvlink); if (status != NV_OK) @@ -566,6 +585,62 @@ knvlinkStateLoad_IMPL } } + // + // If ALI or non-ALI training is forced, then shutdown the links and re-train as GFW + // will have already trained the links and the intent is for the driver + // to train up the links + // + if ((pKernelNvlink->getProperty(pKernelNvlink, + PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING) || + pKernelNvlink->getProperty(pKernelNvlink, + PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING)) && + pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + { + knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, NV_FALSE); + } + + if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink) && pKernelNvlink->bEnableAli && + (!pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT) || + pKernelNvlink->getProperty(pKernelNvlink, + PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING))) + { + status = knvlinkPreTrainLinksToActiveAli(pGpu, pKernelNvlink, + pKernelNvlink->enabledLinks, NV_TRUE); + if (status != NV_OK) + { + goto knvlinkStateLoad_end; + } + + // + // For each link, request a change to active. + // Don't have to wait for the request to finish as links + // will be queries via DLSTAT to know their status and training + // progression. + // + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink->enabledLinks) + { + status = knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, NVBIT(i), NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to request Link %d to transition to active\n", i); + } + + // + // Bug 3550098: the sleep has to be removed eventually as it + // isn't POR for RM to be waiting on sending these requests. + // Bug 3292497 references this as a WAR for EMU in the short term to + // help prevent starvation on MINION linkstate requests + // + if (IS_EMULATION(pGpu)) + { + // Delay the next set of links by 8 seconds + osDelayUs(8000000); + } + } + FOR_EACH_INDEX_IN_MASK_END; + } + knvlinkStateLoad_end: if (status != NV_OK) @@ -594,9 +669,13 @@ knvlinkStatePostLoad_IMPL ) { NV_STATUS status = NV_OK; + NV_STATUS trainingStatus = NV_OK; OBJGPU *pRemoteGpu = NULL; + NvU32 linkTrainingTimeout = 15000000; NvU32 gpuInstance; NvU32 gpuMask; + RMTIMEOUT timeout; + knvlinkCoreUpdateDeviceUUID(pGpu, pKernelNvlink); if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink)) @@ -607,7 +686,7 @@ knvlinkStatePostLoad_IMPL // done for ALI since topology discovery can only happen after // verification training is complete // - if ( + if ((!pKernelNvlink->bEnableAli) && (pKernelNvlink->bEnableSafeModeAtLoad || pKernelNvlink->bEnableTrainingAtLoad || pKernelNvlink->bVerifTrainingEnable)) { @@ -622,6 +701,33 @@ knvlinkStatePostLoad_IMPL // if (pKernelNvlink->bEnableTrainingAtLoad || pKernelNvlink->bVerifTrainingEnable) { + if (pKernelNvlink->bEnableAli && + knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pGpu) == NV_OK) + { + gpuSetTimeout(pGpu, linkTrainingTimeout, &timeout, IS_SILICON(pGpu) ? + (GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | GPU_TIMEOUT_FLAGS_DEFAULT) : 0); + do + { + + status = gpuCheckTimeout(pGpu, &timeout); + trainingStatus = knvlinkCheckTrainingIsComplete(pGpu, pGpu, pKernelNvlink); + if (trainingStatus == NV_OK) + { + break; + } + osSpinLoop(); + } + while (status != NV_ERR_TIMEOUT); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR,"Timedout while checking to see if training complete!\n"); + } + + // Need to get the renote Device Info for ALI + knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + } + else { status = gpumgrGetGpuAttachInfo(NULL, &gpuMask); NV_ASSERT_OR_RETURN(status == NV_OK, status); @@ -691,6 +797,9 @@ knvlinkStatePostUnload_IMPL { OBJSYS *pSys = SYS_GET_INSTANCE(); NV_STATUS status = NV_OK; +#if defined(INCLUDE_NVLINK_LIB) + NvU32 linkId = 0; +#endif if ((knvlinkGetNumLinksToSystem(pGpu, pKernelNvlink) != 0) && pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) @@ -774,7 +883,7 @@ knvlinkStatePostUnload_IMPL } // Shutdown all the links through pseudo-clean shutdown - status = knvlinkPrepareForXVEReset(pGpu, pKernelNvlink); + status = knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, NV_FALSE); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -784,6 +893,22 @@ knvlinkStatePostUnload_IMPL } } +#if defined(INCLUDE_NVLINK_LIB) + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + // Update remote GPU disconnectedLinkMasks + OBJGPU *pRemoteGpu = gpumgrGetGpuFromBusInfo(pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device); + if (!API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) + { + KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + pRemoteKernelNvlink->disconnectedLinkMask |= NVBIT(pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber); + } + } + FOR_EACH_INDEX_IN_MASK_END; +#endif + knvlinkStatePostUnload_end: _knvlinkPurgeState(pGpu, pKernelNvlink); @@ -814,9 +939,20 @@ _knvlinkPurgeState KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bMIGNvLinkP2PDisabled = ((pKernelMIGManager != NULL) && !kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); + + // RM disables NVLink at runtime in Hopper so device un-registration can't be skipped + if (!IsGH100orBetter(pGpu)) + { + // With MIG NvLink registration was skipped with core-lib + if (bMIGNvLinkP2PDisabled) + { + NV_PRINTF(LEVEL_INFO, + "Skipping device/link un-registration in MIG enabled path\n"); + goto _knvlinkPurgeState_end; + } + } - // With MIG NvLink registration was skipped with core-lib - if (knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink) || bMIGNvLinkP2PDisabled) + if (knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink)) { NV_PRINTF(LEVEL_INFO, "Skipping device/link un-registration in RTD3 GC6 entry path\n"); @@ -960,6 +1096,27 @@ _knvlinkProcessSysmemLinks knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); } #endif + + if (knvlinkIsForcedConfig(pGpu, pKernelNvlink) || pKernelNvlink->pLinkConnection) + { + // + // On Hopper+ chips we enable programming of MUX registers. However, + // we need to follow a strict sequence between updating the MUX registers, + // the CONFIG0 registers and setting buffer_rdy for the enabled links. + // BUFFER_RDY should always be set only after *all* HSHUB registers needed + // for traffic are programmed. Since we did not support this on pre-Hopper, + // we need to change the sequence of where we set BUFFER_RDY relative to + // the other HSHUB programming. + // + status = knvlinkPostSetupNvlinkPeer_HAL(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to perform NvLink post setup!\n"); + return status; + } + } + // Set Buffer ready for the sysmem links NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS programBufferRdyParams; diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c index a8c4a09e9..aa6011c7f 100644 --- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c +++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index 83df24000..0aafba2c9 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -180,9 +180,8 @@ _krcInitRegistryOverrides pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; } } - else if (IS_GSP_CLIENT(pGpu) || IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)) + else if (IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)) { - // GSPTODO: need to sort out RC watchdog for GSP pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; } diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index b769aa631..7a6af11d9 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -47,6 +47,7 @@ #include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A #include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A #include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A #include "deprecated/rmapi_deprecated.h" #include "nvRmReg.h" @@ -583,6 +584,7 @@ krcWatchdogInit_IMPL , {VOLTA_CHANNEL_GPFIFO_A, sizeof(Nvc36fControl)} , {TURING_CHANNEL_GPFIFO_A, sizeof(Nvc46fControl)} , {AMPERE_CHANNEL_GPFIFO_A, sizeof(Nvc56fControl)} + , {HOPPER_CHANNEL_GPFIFO_A, sizeof(Nvc86fControl)} }; NvU32 i; diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c index 98e2fb328..b5784855e 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,7 +179,6 @@ krcWatchdog_IMPL (WATCHDOG_RESET_QUEUE_SIZE - 1)); } - // If we are disabled or chip is in low power mode if ((WATCHDOG_FLAGS_DISABLED != (pKernelRc->watchdog.flags & WATCHDOG_FLAGS_DISABLED)) && gpuIsGpuFullPower(pGpu)) diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index 80abe75a2..754beb2a2 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -1773,19 +1773,6 @@ subdeviceCtrlCmdGpuGetPidInfo_IMPL return NV_OK; } -NV_STATUS -subdeviceCtrlCmdGpuInterruptFunction_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS *pParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - Intr *pIntr = GPU_GET_INTR(pGpu); - - return intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, pParams->gfid); -} - // Control call to fetch the Runlist pri base for the engine(s) specified NV_STATUS subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c new file mode 100644 index 000000000..64670d23c --- /dev/null +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "core/locks.h" +#include "gpu/gpu.h" +#include "compute/mps_api.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/rpc.h" +#include "vgpu/vgpu_events.h" +#include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/gr/kernel_graphics_manager.h" + +#include "class/clc637.h" + diff --git a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c new file mode 100644 index 000000000..f9a5c6d1f --- /dev/null +++ b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c @@ -0,0 +1,153 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/********************* Chip Specific HAL TMR Routines **********************\ +* * +* The GH100 specific HAL TMR routines reside in this file. * +* * +\***************************************************************************/ + +/* ------------------------- Includes --------------------------------------- */ +#include "gpu/gpu.h" +#include "objtmr.h" +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_timer.h" +#include "published/hopper/gh100/dev_gc6_island.h" +/* ------------------------- Datatypes -------------------------------------- */ +/* ------------------------- Macros ----------------------------------------- */ +/* ------------------------- Static Function Prototypes --------------------- */ +/* ------------------------- Public Functions ------------------------------ */ +/* + * @brief Sets the GPU time to the current wall-clock time. + * + * @param[in] pGpu- GPU Object pointer + * @param[in] pTmr- Timer Object pointer + * + * @return NV_OK + * @return NV_ERR_PRIV_SEC_VIOLATION - PTIMER_TIME is read-only. + */ +NV_STATUS tmrSetCurrentTime_GH100 +( + OBJGPU *pGpu, + OBJTMR *pTmr +) +{ + NV_STATUS status; + + // We can only set the time if level 0 is allowed to write + if (GPU_FLD_TEST_DRF_DEF(pGpu, _PTIMER, _TIME_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _ENABLE)) + { + NvU64 ns; + NvU32 seconds; + NvU32 useconds; + + osGetCurrentTime(&seconds, &useconds); + + NV_PRINTF(LEVEL_INFO, + "osGetCurrentTime returns 0x%x seconds, 0x%x useconds\n", + seconds, useconds); + + ns = ((NvU64)seconds * 1000000 + useconds) * 1000; + + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(ns)); + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(ns)); + + status = NV_OK; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "ERROR: Write to PTIMER attempted even though Level 0 PLM is disabled.\n"); + NV_ASSERT(0); + status = NV_ERR_PRIV_SEC_VIOLATION; + } + + return status; +} + +NV_STATUS +tmrSetCountdown_GH100 +( + POBJGPU pGpu, + POBJTMR pTmr, + NvU32 time, + NvU32 tmrId, + THREAD_STATE_NODE *pThreadState +) +{ + NV_ASSERT_OR_RETURN(tmrId < NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1, NV_ERR_NOT_SUPPORTED); + + GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_TIMER(tmrId), time, pThreadState); + return NV_OK; +} + +NvU64 +tmrGetTimeEx_GH100 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + THREAD_STATE_NODE *pThreadState +) +{ + NvU32 TimeLo = 0; + NvU32 TimeHi = 0; + NvU32 TimeHi2 = 0; + NvU32 i; + NvU64 Time; + + do + { + TimeHi = tmrReadTimeHiReg_HAL(pGpu, pTmr, pThreadState); + // Get a stable TIME_0 + for (i = 0; i < pTmr->retryTimes; ++i) + { + TimeLo = tmrReadTimeLoReg_HAL(pGpu, pTmr, pThreadState); + if ((TimeLo & ~DRF_SHIFTMASK(NV_PTIMER_TIME_0_NSEC)) == 0) + break; + } + + // Couldn't get a good value + if (i == pTmr->retryTimes) + { + // PTIMER returns bad bits after several read attempts + NV_PRINTF(LEVEL_ERROR, + "NVRM-RC: Consistently Bad TimeLo value %x\n", TimeLo); + + // + // On previous chips we would attempt to reinitialize the timer at this point + // On Hopper+ RM only handles setting the initial value of the timer at boot + // and is not allowed to reinitialize the timer afterwards + // + DBG_BREAKPOINT(); + + return 0; + } + + // Read TIME_1 again to detect wrap around. + TimeHi2 = tmrReadTimeHiReg_HAL(pGpu, pTmr, pThreadState); + } while (TimeHi != TimeHi2); + + // Convert to 64b + Time = (((NvU64)TimeHi) << 32) | TimeLo; + + return Time; +} diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index d77843220..aaef93e38 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -721,6 +721,13 @@ static NvBool _gpumgrIsRmFirmwareCapableChip(NvU32 pmcBoot42) } #undef NV_PMC_BOOT_42_ARCHITECTURE_TU100 +#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 +static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42) +{ + return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100); +} +#undef NV_PMC_BOOT_42_ARCHITECTURE_GH100 + NvBool gpumgrIsDeviceRmFirmwareCapable ( NvU16 devId, @@ -762,18 +769,29 @@ NvBool gpumgrIsDeviceRmFirmwareCapable if (!_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) return NV_FALSE; - for (i = 0; i < count; i++) + if (_gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) { - if (defaultGspRmGpus[i] == devId) + *pbEnabledByDefault = NV_TRUE; + } + else + { + for (i = 0; i < count; i++) { - NV_PRINTF(LEVEL_INFO, - "DevId 0x%x is GSP-RM enabled by default\n", - devId); - *pbEnabledByDefault = NV_TRUE; - break; + if (defaultGspRmGpus[i] == devId) + { + *pbEnabledByDefault = NV_TRUE; + break; + } } } + if (*pbEnabledByDefault) + { + NV_PRINTF(LEVEL_INFO, + "DevId 0x%x is GSP-RM enabled by default\n", + devId); + } + return NV_TRUE; } @@ -2998,6 +3016,9 @@ gpumgrAddSystemMIGInstanceTopo_IMPL { pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE; pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice; + + // Set MIG enablement to disabled by default + pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE; break; } } @@ -3050,6 +3071,78 @@ gpumgrGetSystemMIGInstanceTopo_IMPL return NV_FALSE; } +/*! + * @brief Retrieves the entry in the system partition topology save for the given GPU + * ID and returns value of bMIGEnabled. + * + * @param[in] domainBusDevice: the PCI DomainBusDevice for the gpu to be registered + * + * @returns NV_TRUE if entry found + * NV_FALSE otherwise + */ +NvBool +gpumgrIsSystemMIGEnabled_IMPL +( + NvU64 domainBusDevice +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvU32 i; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pGpuMgr->MIGTopologyInfo); i++) + { + // + // Choose the correct GPU by comparing PCI BusDomainDevice + // This ensures we are using the same GPU across gpu load/unload + // + if (pGpuMgr->MIGTopologyInfo[i].bValid && + (pGpuMgr->MIGTopologyInfo[i].domainBusDevice == domainBusDevice)) + { + return pGpuMgr->MIGTopologyInfo[i].bMIGEnabled; + } + } + + return NV_FALSE; +} + + +/*! + * @brief Retrieves the entry in the system partition topology save for the given GPU + * ID and sets value of bMIGEnabled. + * + * @param[in] DomainBusDevice: the PCI DomainBusDevice for the gpu to be registered + * @param[in] bMIGEnabled: The new MIG enablement state to be set + * + * @returns NV_TRUE if entry found + * NV_FALSE otherwise + */ +void +gpumgrSetSystemMIGEnabled_IMPL +( + NvU64 domainBusDevice, + NvBool bMIGEnabled +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvU32 i; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pGpuMgr->MIGTopologyInfo); i++) + { + // + // Choose the correct GPU by comparing PCI BusDomainDevice + // This ensures we are using the same GPU across gpu load/unload + // + if (pGpuMgr->MIGTopologyInfo[i].bValid && + (pGpuMgr->MIGTopologyInfo[i].domainBusDevice == domainBusDevice)) + { + pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = bMIGEnabled; + break; + } + } +} + static void _gpumgrUnregisterRmCapsForMIGCI(GPUMGR_SAVE_GPU_INSTANCE *pGPUInstanceSave) { diff --git a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c index 85cb7dc93..4b9a656e7 100644 --- a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c +++ b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c @@ -148,7 +148,11 @@ ctxBufPoolInit NV_PRINTF(LEVEL_ERROR, "Unsupported page size attr %d\n", i); return NV_ERR_INVALID_STATE; } - NV_ASSERT_OK_OR_GOTO(status, rmMemPoolSetup((void*)&pHeap->pmaObject, &pCtxBufPool->pMemPool[i], poolConfig), cleanup); + NV_ASSERT_OK_OR_GOTO(status, + rmMemPoolSetup((void*)&pHeap->pmaObject, &pCtxBufPool->pMemPool[i], + poolConfig), + cleanup); + } NV_PRINTF(LEVEL_INFO, "Ctx buf pool successfully initialized\n"); diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index 945117345..a09d174dc 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -168,13 +168,16 @@ _fabricvaspaceUnbindInstBlk // Unbind the instance block for fabric vaspace. NV_ASSERT(kbusSetupUnbindFla_HAL(pGpu, pKernelBus) == NV_OK); - // Instantiate the instance block for FLA vaspace. - NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, pKernelBus->flaInfo.pInstblkMemDesc, - pKernelBus->flaInfo.pFlaVAS, FIFO_PDB_IDX_BASE, - &instblkParams) == NV_OK); + if (pKernelBus->flaInfo.pFlaVAS != NULL) + { + // Instantiate the instance block for FLA vaspace. + NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, pKernelBus->flaInfo.pInstblkMemDesc, + pKernelBus->flaInfo.pFlaVAS, FIFO_PDB_IDX_BASE, + &instblkParams) == NV_OK); - // Bind the instance block for FLA vaspace. - NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, pFabricVAS->gfid) == NV_OK); + // Bind the instance block for FLA vaspace. + NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, pFabricVAS->gfid) == NV_OK); + } } NV_STATUS diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index e686c2219..542f51ca6 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -876,6 +876,37 @@ _gvaspaceBar1VaSpaceDestruct return status; } +static NV_STATUS +_gvaspaceFlaVaspaceDestruct +( + POBJGVASPACE pGVAS, + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + MMU_WALK_USER_CTX userCtx = {0}; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); + + gvaspaceUnpinRootPageDir(pGVAS, pGpu); + + gvaspaceWalkUserCtxAcquire(pGVAS, pGpu, NULL, &userCtx); + NV_ASSERT_OR_RETURN(NULL != userCtx.pGpuState, NV_OK); + + status = mmuWalkUnmap(userCtx.pGpuState->pWalk, vaspaceGetVaStart(pVAS), vaspaceGetVaLimit(pVAS)); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + gvaspaceWalkUserCtxRelease(pGVAS, &userCtx); + + NV_PRINTF(LEVEL_INFO, "Releasing legacy FLA VASPACE, gpu: %x \n", + pGpu->gpuInstance); + + pKernelBus->flaInfo.hFlaVASpace = NV01_NULL_OBJECT; + pKernelBus->flaInfo.pFlaVAS = NULL; + + return status; +} + static NV_STATUS _gvaspaceReleaseVaForServerRm ( @@ -936,17 +967,22 @@ gvaspaceDestruct_IMPL(OBJGVASPACE *pGVAS) OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); OBJGPU *pGpu = NULL; GVAS_GPU_STATE *pGpuState; + NV_STATUS status; FOR_EACH_GPU_IN_MASK_UC(32, pSys, pGpu, pVAS->gpuMask) { // Unsparsify entire VAS for BAR1. if (pGVAS->flags & VASPACE_FLAGS_BAR_BAR1) { - NV_STATUS status = NV_OK; - status = _gvaspaceBar1VaSpaceDestruct(pGVAS, pGpu); NV_ASSERT(NV_OK == status); } + + if (pGVAS->flags & VASPACE_FLAGS_FLA) + { + status = _gvaspaceFlaVaspaceDestruct(pGVAS, pGpu); + NV_ASSERT(NV_OK == status); + } } FOR_EACH_GPU_IN_MASK_UC_END @@ -2720,6 +2756,17 @@ NvBool isPteDowngrade(KernelGmmu *pKernelGmmu, const GMMU_FMT *pFmt, NvU32 pteIn _VALID, _TRUE, pteInputFlags) && nvFieldGetBool(&pFmt->pPte->fldValid, curPte.v8)); + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfHw = 0; + NvU32 ptePcfSw = 0; + + ptePcfHw = nvFieldGet32(&pFmt->pPte->fldPtePcf, curPte.v8); + NV_ASSERT_OR_RETURN((kgmmuTranslatePtePcfFromHw_HAL(pKernelGmmu, ptePcfHw, nvFieldGetBool(&pFmt->pPte->fldValid, curPte.v8), + &ptePcfSw) == NV_OK), NV_ERR_INVALID_ARGUMENT); + curPteReadOnly = ptePcfSw & (1 << SW_MMU_PCF_RO_IDX); + } + else { curPteReadOnly = nvFieldGetBool(&pFmt->pPte->fldReadOnly, curPte.v8); } @@ -2865,6 +2912,34 @@ gvaspaceSetPteInfo_IMPL _GPU_CACHED, _FALSE, pPteBlock->pteFlags); } + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfHw = 0; + NvU32 ptePcfSw = 0; + + if (bValid) + { + nvFieldSetBool(&pFmt->pPte->fldValid, NV_TRUE, pte.v8); + nvFieldSet32(&pFmt->pPte->fldAperture._enum.desc, aperture, pte.v8); + nvFieldSet32(&pFmt->pPte->fldKind, pPteBlock->kind, pte.v8); + ptePcfSw |= bVolatile ? (1 << SW_MMU_PCF_UNCACHED_IDX) : 0; + if (bReadOnly) + { + ptePcfSw |= 1 << SW_MMU_PCF_RO_IDX; + ptePcfSw |= 1 << SW_MMU_PCF_NOATOMIC_IDX; + } + ptePcfSw |= (1 << SW_MMU_PCF_REGULAR_IDX); + ptePcfSw |= (1 << SW_MMU_PCF_ACE_IDX); + } + else + { + ptePcfSw |= (1 << SW_MMU_PCF_INVALID_IDX); + } + NV_ASSERT_OR_RETURN((kgmmuTranslatePtePcfFromSw_HAL(GPU_GET_KERNEL_GMMU(pGpu), ptePcfSw, &ptePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pFmt->pPte->fldPtePcf, ptePcfHw, pte.v8); + } + else { nvFieldSetBool(&pFmt->pPte->fldValid, bValid, pte.v8); if (bValid) @@ -3603,6 +3678,46 @@ gvaspaceUpdatePde2_IMPL NVLINK_INVALID_FABRIC_ADDR), mapIter.entry.v8); + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 pdePcfHw = 0; + NvU32 pdePcfSw = 0; + PMEMORY_DESCRIPTOR pMemDesc = NULL; + NvU32 memSize = 0; + NvU8 *pMap = NULL; + GMMU_ENTRY_VALUE pde = {{0}}; + GMMU_APERTURE currAperture; + + NV_ASSERT_OK_OR_RETURN( + mmuWalkGetPageLevelInfo(pGpuState->pWalk, mapTarget.pLevelFmt, + (pParams->pdeIndex * mmuFmtLevelPageSize(mapTarget.pLevelFmt)), + (const MMU_WALK_MEMDESC**)&pMemDesc, &memSize)); + + pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); + NV_ASSERT_OR_RETURN(pMap != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + portMemCopy(pde.v8, mapTarget.pLevelFmt->entrySize, + pMap + (pParams->pdeIndex * mapTarget.pLevelFmt->entrySize), + mapTarget.pLevelFmt->entrySize); + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_FALSE); + + pdePcfHw = nvFieldGet32(&pPdeFmt->fldPdePcf, pde.v8); + currAperture = gmmuFieldGetAperture(&pPdeFmt->fldAperture, pde.v8); + + if (currAperture != GMMU_APERTURE_INVALID) + { + NV_ASSERT_OR_RETURN( + (kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, pdePcfHw, currAperture, &pdePcfSw) == NV_OK), NV_ERR_INVALID_ARGUMENT); + pdePcfSw |= 1 << SW_MMU_PCF_UNCACHED_IDX; + } + else + { + pdePcfSw = 1 << SW_MMU_PCF_UNCACHED_IDX; + } + NV_ASSERT_OR_RETURN( + (kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pPdeFmt->fldPdePcf, pdePcfHw, mapIter.entry.v8); + } + else { nvFieldSetBool(&pPdeFmt->fldVolatile, NV_TRUE, mapIter.entry.v8); } diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 3adc3c5b7..3b4061616 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -52,20 +52,10 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "ctrl/ctrl0041.h" #include "published/ampere/ga100/dev_mmu.h" -typedef struct -{ - // - // TODO: Only sticky non-partial mappings are supported currently, so all - // the fabric addrs are mapped to the single vidmem memory object. However, - // when partial mappings are supported, we will need a per-fabric memdesc - // tree to track the mappings for multiple vidmem memory objects. - // - NvHandle hDupedVidmem; -} FABRIC_MEMDESC_DATA; - static NvU32 _memoryfabricMemDescGetNumAddr ( @@ -638,6 +628,32 @@ memoryfabricConstruct_IMPL goto freeCallback; } + if (!(pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA)) + { + NV0041_CTRL_SURFACE_INFO surfaceInfo[2] = {0}; + NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParam = {0}; + + surfaceInfo[0].index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; + surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE; + surfaceInfoParam.surfaceInfoListSize = 2; + surfaceInfoParam.surfaceInfoList = NvP64_VALUE(&surfaceInfo); + + status = pRmApi->Control(pRmApi, + pFabricVAS->hClient, + pMemdescData->hDupedVidmem, + NV0041_CTRL_CMD_GET_SURFACE_INFO, + &surfaceInfoParam, + sizeof(surfaceInfoParam)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to query physical video memory info\n"); + goto freeDupedMem; + } + + pMemdescData->physAttrs.addressSpace = surfaceInfo[0].data; + pMemdescData->physAttrs.compressionCoverage = surfaceInfo[1].data; + } + status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], pVidMemDesc, pAllocParams->map.offset); if (status != NV_OK) @@ -654,7 +670,7 @@ memoryfabricConstruct_IMPL goto memFabricRemoveVaToGpaMap; } - pMemoryFabric->flags = pAllocParams->allocFlags; + pMemdescData->allocFlags = pAllocParams->allocFlags; pMemory->bRpcAlloc = pFabricVAS->bRpcAlloc; portMemFree(pAddr); @@ -744,6 +760,14 @@ memoryfabricCanExport_IMPL MemoryFabric *pMemoryFabric ) { + Memory *pMemory = staticCast(pMemoryFabric, Memory); + FABRIC_MEMDESC_DATA *pMemdescData; + + if (pMemory->pMemDesc == NULL) + return NV_ERR_INVALID_ARGUMENT; + + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); + // // Check if FLA->PA mappings are present. Only then allow export. // FLA->PA mappings are guaranteed for STICKY FLA mappings, which is only @@ -751,7 +775,7 @@ memoryfabricCanExport_IMPL // TODO: Re-visit this function when support for FLEXIBLE FLA mappings is // added. // - return !(pMemoryFabric->flags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); + return !(pMemdescData->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); } NV_STATUS @@ -781,13 +805,17 @@ memoryfabricCtrlGetInfo_IMPL ) { Memory *pMemory = staticCast(pMemoryFabric, Memory); + FABRIC_MEMDESC_DATA *pMemdescData; if (pMemory->pMemDesc == NULL) return NV_ERR_INVALID_ARGUMENT; + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); + pParams->size = memdescGetSize(pMemory->pMemDesc); pParams->pageSize = memdescGetPageSize(pMemory->pMemDesc, AT_GPU); - pParams->allocFlags = pMemoryFabric->flags; + pParams->allocFlags = pMemdescData->allocFlags; + pParams->physAttrs = pMemdescData->physAttrs; return NV_OK; } diff --git a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c index 0f2fc9a23..d4da7b36a 100644 --- a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c +++ b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c @@ -176,6 +176,11 @@ struct RM_POOL_ALLOC_MEM_RESERVE_INFO * Automatically trim memory pool when allocation is freed. */ NvBool bTrimOnFree; + + /*! + * Allocate pool in protected memory + */ + NvBool bProtected; }; /* ------------------------------------ Static functions --------------------------- */ @@ -215,6 +220,11 @@ allocUpstreamTopPool allocOptions.flags |= PMA_ALLOCATE_NO_ZERO; } + if (pMemReserveInfo->bProtected) + { + allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION; + } + status = pmaAllocatePages(pMemReserveInfo->pPma, (NvU32)(pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K), PMA_CHUNK_SIZE_64K, @@ -980,3 +990,14 @@ rmMemPoolGetChunkAndPageSize *pPageSize = poolAllocSizes[pMemReserveInfo->topmostPoolIndex]; return NV_OK; } + +void +rmMemPoolAllocateProtectedMemory +( + RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, + NvBool bProtected +) +{ + NV_ASSERT_OR_RETURN_VOID(pMemReserveInfo != NULL); + pMemReserveInfo->bProtected = bProtected; +} diff --git a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c index 0dd14a612..7567a405e 100644 --- a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c +++ b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c @@ -96,7 +96,11 @@ void vaListDestroy(VA_LIST *pVaList) DBG_BREAKPOINT(); } - if (mapCount(pVaList) != 0) + // + // Skip DBG_BREAKPOINT when we are in Physical RM. + // DBG_BREAKPOINT is the result of the lack of eviction of the context buffers from client RM. + // + if (!RMCFG_FEATURE_PLATFORM_GSP && mapCount(pVaList) != 0) { NV_PRINTF(LEVEL_ERROR, "non-zero mapCount(pVaList): 0x%x\n", mapCount(pVaList)); diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index e13bc6e4e..2e7f84a15 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -1222,10 +1222,10 @@ virtmemMapTo_IMPL NvBool bIsIndirectPeer = NV_FALSE; NvBool bEncrypted; NvBool bIsSysmem = NV_FALSE; - NvBool bBar1P2P = (p2p && kbusIsPcieBar1P2PMapping_HAL(pGpu, - GPU_GET_KERNEL_BUS(pGpu), - pSrcGpu, - GPU_GET_KERNEL_BUS(pSrcGpu))); + NvBool bBar1P2P = (p2p && kbusHasPcieBar1P2PMapping_HAL(pGpu, + GPU_GET_KERNEL_BUS(pGpu), + pSrcGpu, + GPU_GET_KERNEL_BUS(pSrcGpu))); // // Allow unicast on NV01_MEMORY_VIRTUAL object, but maintain the broadcast diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 0b18d0b3e..0663ccd5e 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -458,6 +458,27 @@ NvU32 vgpuDevReadReg032( return 0; } +NvU64 osGetMaxUserVa(void); + +/** + * @brief Get the Max User VA address shift + * + * The max user VA address shift may not be power-2 aligned, + * so do some math to round it up. + * + * @return max user VA address shift + */ +NvU32 +osGetCpuVaAddrShift(void) +{ + NvU64 maxUserVa = osGetMaxUserVa(); + + // + // Add 1 to account for kernel VA space, on the assumption + // that kernel VA space is the top half of the address space. + // + return (64 - portUtilCountLeadingZeros64(maxUserVa - 1)) + 1; +} /** * @brief Adds a filter to trap a certain CPU virtual address range diff --git a/src/nvidia/src/kernel/os/os_sanity.c b/src/nvidia/src/kernel/os/os_sanity.c index ca0694008..48a201725 100644 --- a/src/nvidia/src/kernel/os/os_sanity.c +++ b/src/nvidia/src/kernel/os/os_sanity.c @@ -139,7 +139,8 @@ static NV_STATUS _osVerifyInterrupts( // support required to run this interrupt sanity test has been brought up // yet for T234D SOC display. // - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_IGPU)) { // // Nothing to verify here for the time being diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 6d696a500..126c14e68 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -314,6 +314,83 @@ void stubOsInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId) return; } +#if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \ + (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) +NV_STATUS osTegraSocGpioGetPinState( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 *pArg3 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void osTegraSocGpioSetPinState( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 arg3 +) +{ +} + +NV_STATUS osTegraSocGpioSetPinDirection( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 arg3 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osTegraSocGpioGetPinDirection( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 *pArg3 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osTegraSocGpioGetPinNumber( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 *pArg3 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osTegraSocGpioGetPinInterruptStatus( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 arg3, + NvBool *pArg4 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osTegraSocGpioSetPinInterrupt( + OS_GPU_INFO *pArg1, + NvU32 arg2, + NvU32 arg3 +) +{ + return NV_ERR_NOT_SUPPORTED; +} +#endif + +NV_STATUS +osTegraSocParseFixedModeTimings +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 dcbIndex, + OS_FIXED_MODE_TIMINGS *pFixedModeTimings +) +{ + return NV_OK; +} + NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1) { @@ -476,11 +553,6 @@ NV_STATUS osInitGetAcpiTable(void) return NV_ERR_NOT_SUPPORTED; } -NvU32 osGetReleaseAssertBehavior(void) -{ - return 0; -} - void osDbgBugCheckOnAssert(void) { return; @@ -531,6 +603,68 @@ stubOsGetUefiVariable return NV_ERR_NOT_SUPPORTED; } +#if !RMCFG_FEATURE_PLATFORM_UNIX || \ + (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) +NV_STATUS +osTegraSocResetMipiCal +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +NV_STATUS +osTegraSocDsiParsePanelProps +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraSocDsiPanelEnable +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraSocDsiPanelReset +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +osTegraSocDsiPanelDisable +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return; +} + +void +osTegraSocDsiPanelCleanup +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return; +} +#endif + NvU32 osGetDynamicPowerSupportMask(void) { return 0; @@ -670,3 +804,21 @@ osTegraSocPmUnpowergate } #endif +NvBool +osTegraSocIsDsiPanelConnected +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +#if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ + (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) +NvU32 +osTegraSocFuseRegRead(NvU32 addr) +{ + return 0; +} +#endif + diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index e1b38bc52..e3e9f4fc3 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -783,6 +783,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI) CL_SYNC_PDB(PDB_PROP_CL_DISABLE_IOMAP_WC); CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE); CL_SYNC_PDB(PDB_PROP_CL_IS_EXTERNAL_GPU); + CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR); #undef CL_SYNC_PDB diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index f75f49491..6091a0c44 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -856,6 +856,25 @@ Intel_0685_setupFunc return NV_OK; } +// Intel Ice Lake platform +static NV_STATUS +Intel_IceLake_setupFunc +( + OBJCL *pCl +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + + // Intel IceLake + if ((pSys->cpuInfo.family == 0x6) && + (pSys->cpuInfo.model == 0x6a) && + (pSys->cpuInfo.stepping == 0x6)) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + return NV_OK; +} + // Intel Z590 platform (Rocket Lake) static NV_STATUS Intel_4381_setupFunc @@ -865,6 +884,16 @@ Intel_4381_setupFunc { pCl->setProperty(pCl, PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE, NV_TRUE); + // + // Apply the WAR to restrict the max target gen speed capable to previous gen + // on ASUS Z590 (Intel RKL-S) platform only + // Bug 3751839 + // + if (pCl->chipsetIDInfo.subvendorID == PCI_VENDOR_ID_ASUS) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR, NV_TRUE); + } + return NV_OK; } @@ -1088,6 +1117,16 @@ AMD_X370_setupFunc OBJCL *pCl ) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + + // AMD Milan + if (pSys->cpuInfo.family == 0x19 && + pSys->cpuInfo.model == 0x1 && + pSys->cpuInfo.stepping == 0x1) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + // Set ASPM L0S\L1 properties _Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE); diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index 014a2a9ed..d1bdc063d 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -73,6 +73,9 @@ static NV_STATUS objClGpuIs3DController(OBJGPU *); static void objClLoadPcieVirtualP2PApproval(OBJGPU *); static void objClCheckForExternalGpu(OBJGPU *, OBJCL *); static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *); +static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *); +static void _objClGetUpstreamAtomicRoutingCap(void *, NvU32, NvBool *); +static void _objClGetDownstreamAtomicRoutingCap(void *, NvU32, NvBool *); extern void _Set_ASPM_L0S_L1(OBJCL *, NvBool, NvBool); @@ -551,6 +554,187 @@ clCheckUpstreamLtrSupport_IMPL return status; } +/*! @brief Check PCIe Atomics capability throughout the hierarchy of + * switches in between root port and endpoint. + * + * @param[in] pGpu GPU object pointer + * @param[in] pCl Core logic object pointer + * @param[out] pAtomicMask Mask of supported atomic size, including one or more of: + * OS_PCIE_CAP_MASK_REQ_ATOMICS_32 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_64 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_128 + * + * @return NV_OK if PCIe Atomics is supported throughout the hierarchy, else + * NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +clGetAtomicTypesSupported_IMPL +( + NvU32 domain, + NvU8 bus, + OBJCL *pCl, + NvU32 *pAtomicMask +) +{ + NvU32 portCaps = 0; + NvBool bRoutingCap = NV_TRUE; + NV_STATUS status = NV_OK; + NvU32 PCIECapPtr; + void *pHandleUp; + NvU8 busUp, devUp, funcUp; + NvU16 vendorIDUp, deviceIDUp; + + do + { + // find virtual P2P bridge + pHandleUp = clFindP2PBrdg(pCl, domain, bus, + &busUp, &devUp, &funcUp, + &vendorIDUp, &deviceIDUp); + + // make sure handle was found + if (!pHandleUp) + { + status = NV_ERR_NOT_SUPPORTED; + goto clGetAtomicTypesSupported_exit; + } + + status = clSetPortPcieCapOffset(pCl, pHandleUp, &PCIECapPtr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Capability pointer not found.\n"); + status = NV_ERR_NOT_SUPPORTED; + goto clGetAtomicTypesSupported_exit; + } + + // Read PCIe Capability + portCaps = osPciReadDword(pHandleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + if (CL_IS_ROOT_PORT(portCaps)) + { + _objClGetDownstreamAtomicsEnabledMask(pHandleUp, PCIECapPtr, pAtomicMask); + } + else if (CL_IS_UPSTREAM_PORT(portCaps)) + { + _objClGetUpstreamAtomicRoutingCap(pHandleUp, PCIECapPtr, &bRoutingCap); + if (!bRoutingCap) + { + status = NV_ERR_NOT_SUPPORTED; + goto clGetAtomicTypesSupported_exit; + } + } + else if (CL_IS_DOWNSTREAM_PORT(portCaps)) + { + _objClGetDownstreamAtomicRoutingCap(pHandleUp, PCIECapPtr, &bRoutingCap); + if (!bRoutingCap) + { + status = NV_ERR_NOT_SUPPORTED; + goto clGetAtomicTypesSupported_exit; + } + } + else + { + // Invalid port + status = NV_ERR_NOT_SUPPORTED; + goto clGetAtomicTypesSupported_exit; + } + + bus = busUp; + } while (!CL_IS_ROOT_PORT(portCaps)); + +clGetAtomicTypesSupported_exit: + return status; +} + +/*! + * @brief Get the supported Atomics mask bit configuration for root port + * + * @param[in] pHandle Handle for the P2P bridge + * @param[in] PCIECapPtr PCIe Capability pointer + * @param[out] pAtomicMask Mask of supported atomic size + */ +static void +_objClGetDownstreamAtomicsEnabledMask +( + void *pHandle, + NvU32 PCIECapPtr, + NvU32 *pAtomicMask +) +{ + NvU32 devCap2; + + devCap2 = osPciReadDword(pHandle, + CL_PCIE_DEV_CAP_2 - CL_PCIE_BEGIN + PCIECapPtr); + if (CL_IS_32BIT_ATOMICS_SUPPORTED(devCap2)) + { + *pAtomicMask |= CL_ATOMIC_32BIT; + } + if (CL_IS_64BIT_ATOMICS_SUPPORTED(devCap2)) + { + *pAtomicMask |= CL_ATOMIC_64BIT; + } + if (CL_IS_128BIT_ATOMICS_SUPPORTED(devCap2)) + { + *pAtomicMask |= CL_ATOMIC_128BIT; + } +} + +/*! + * @brief Check if upstream port is capable of atomic routing + * and whether egress is blocked + * + * @param[in] pHandle Handle for the P2P bridge + * @param[in] PCIECapPtr PCIe Capability pointer + * @param[out] pbRoutingCap Atomic routing capable + */ +static void +_objClGetUpstreamAtomicRoutingCap +( + void *pHandle, + NvU32 PCIECapPtr, + NvBool *pbRoutingCap +) +{ + NvU32 devCap2; + NvU32 devCtrl2; + + devCap2 = osPciReadDword(pHandle, + CL_PCIE_DEV_CAP_2 - CL_PCIE_BEGIN + PCIECapPtr); + devCtrl2 = osPciReadDword(pHandle, + CL_PCIE_DEV_CTRL_2 - CL_PCIE_BEGIN + PCIECapPtr); + + if ((!CL_IS_ATOMICS_SUPPORTED(devCap2)) || + (CL_IS_ATOMICS_EGRESS_BLOCKED(devCtrl2))) + { + *pbRoutingCap = NV_FALSE; + } +} + +/*! + * @brief Check if downstream port is capable of atomic routing + * + * @param[in] pHandle Handle for the P2P bridge + * @param[in] PCIECapPtr PCIe Capability pointer + * @param[out] pbRoutingCap Atomic routing capable + */ +static void +_objClGetDownstreamAtomicRoutingCap +( + void *pHandle, + NvU32 PCIECapPtr, + NvBool *pbRoutingCap +) +{ + NvU32 devCap2; + + devCap2 = osPciReadDword(pHandle, + CL_PCIE_DEV_CAP_2 - CL_PCIE_BEGIN + PCIECapPtr); + + if (!CL_IS_ATOMICS_SUPPORTED(devCap2)) + { + *pbRoutingCap = NV_FALSE; + } +} + static void _objClAdjustTcVcMap(OBJGPU *pGpu, OBJCL *pCl, PORTDATA *pPort) { @@ -649,6 +833,14 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) // kbifInitPcieDeviceControlStatus(pGpu, pKernelBif); + // + // Probe root port PCIe atomic capabilities. + // kbifProbePcieReqAtomicCaps_HAL should be called from here instead of + // kbif construct because of the dependency on the chipset + // discovery to build the allow list for enabling PCIe atomics feature. + // + kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif); + // // Passthrough configurations do not typically present the upstream // bridge required for detecting multi-GPU boards. So for hypervisors @@ -718,6 +910,9 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) // The GPU's map can be more restrictive than the RP, but it can *never* // be larger. // + // Virtual channel capability is no longer supported for GH100 + // Bug 200570282, comment#41 + // if (pGpu->getProperty(pGpu, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED)) { _objClAdjustTcVcMap(pGpu, pCl, &pGpu->gpuClData.rootPort); @@ -4196,6 +4391,53 @@ clControlL0sL1LinkControlUpstreamPort_IMPL return NV_OK; } +/*! + * @brief: Enable L0s and L1 support from chipset + * Note: This function is used for force enabling ASPM and shouldn't be used + * for normal driver operations + * + * @param[in] pGpu GPU object pointer + * @param[in] pBif BIF object pointer + * @param[in] aspmState L0s/L1 state (enable/disable) + * + * @return NV_OK if ASPM state updated, else return error + */ +NV_STATUS +clChipsetAspmPublicControl_IMPL +( + OBJGPU *pGpu, + OBJCL *pCl, + NvU32 aspmState +) +{ + void *pHandle = pGpu->gpuClData.upstreamPort.addr.handle; + NvU32 PCIECapPtr = pGpu->gpuClData.upstreamPort.PCIECapPtr; + NvU32 linkControlRegOffset = PCIECapPtr + 0x10; + NvU32 regVal; + + if (aspmState > CL_PCIE_LINK_CTRL_STATUS_ASPM_MASK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid ASPM state passed.\n"); + return NV_ERR_INVALID_DATA; + } + + regVal = osPciReadDword(pHandle, linkControlRegOffset); + if (regVal == 0xFFFF) + { + NV_PRINTF(LEVEL_ERROR, + "Link Control register read failed for upstream port\n"); + return NV_ERR_GENERIC; + } + + // Mask all bits except ASPM control bits and update only ASPM bits (1:0) + regVal = (~CL_PCIE_LINK_CTRL_STATUS_ASPM_MASK) & regVal; + regVal |= aspmState; + + osPciWriteDword(pHandle, linkControlRegOffset, regVal); + + return NV_OK; +} + /*! * @brief: Returns the gen speed of the root node */ diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 987d14577..0a997a58e 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -531,8 +531,7 @@ _kp2pCapsGetStatusOverPcieBar1 KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pFirstGpu); NV_STATUS status = NV_OK; - if ((pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT) && - (pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) + if ((pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) { return NV_ERR_NOT_SUPPORTED; } @@ -545,8 +544,8 @@ _kp2pCapsGetStatusOverPcieBar1 while ((pGpuPeer = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) { - if (!kbusIsPcieBar1P2PCapable_HAL(pFirstGpu, GPU_GET_KERNEL_BUS(pFirstGpu), - pGpuPeer, GPU_GET_KERNEL_BUS(pGpuPeer))) + if (!kbusIsPcieBar1P2PMappingSupported_HAL(pFirstGpu, GPU_GET_KERNEL_BUS(pFirstGpu), + pGpuPeer, GPU_GET_KERNEL_BUS(pGpuPeer))) { status = NV_ERR_NOT_SUPPORTED; break; diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 697215580..cc0d324ec 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -1098,9 +1098,6 @@ rmapiAllocWithSecInfo NV_PRINTF(LEVEL_INFO, "client:0x%x parent:0x%x object:0x%x class:0x%x\n", hClient, hParent, *phObject, hClass); - NVRM_TRACE_API('ALOC', hParent, *phObject, hClass); - NVRM_TRACE(pAllocParams); - status = _rmAlloc(hClient, hParent, phObject, @@ -1128,7 +1125,6 @@ rmapiAllocWithSecInfo if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "allocation complete\n"); - NVRM_TRACE('aloc'); } else { @@ -1137,8 +1133,6 @@ rmapiAllocWithSecInfo NV_PRINTF(LEVEL_WARNING, "client:0x%x parent:0x%x object:0x%x class:0x%x\n", hClient, hParent, *phObject, hClass); - - NVRM_TRACE_ERROR('aloc', status); } portMemFree(pLockInfo); @@ -1282,8 +1276,6 @@ rmapiFreeWithSecInfo NV_PRINTF(LEVEL_INFO, "Nv01Free: client:0x%x object:0x%x\n", hClient, hObject); - NVRM_TRACE_API('FREE', hClient, hObject, 0); - status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) @@ -1314,7 +1306,6 @@ rmapiFreeWithSecInfo if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "Nv01Free: free complete\n"); - NVRM_TRACE('free'); } else { @@ -1323,7 +1314,6 @@ rmapiFreeWithSecInfo nvstatusToString(status), status); NV_PRINTF(LEVEL_WARNING, "Nv01Free: client:0x%x object:0x%x\n", hClient, hObject); - NVRM_TRACE_ERROR('free', status); } return status; diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index e2acc7ebd..f74a3bee2 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -415,7 +415,7 @@ CliGetSystemP2pCaps p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK] = NV0000_P2P_CAPS_STATUS_OK; } } - else if (connectivity == P2P_CONNECTIVITY_PCIE_BAR1 || (connectivity == P2P_CONNECTIVITY_PCIE)) + else if ((connectivity == P2P_CONNECTIVITY_PCIE_BAR1) || (connectivity == P2P_CONNECTIVITY_PCIE)) { if (p2pCaps != NULL) { @@ -449,7 +449,7 @@ CliGetSystemP2pCaps } } - if (gpuCount == 1) + if ((gpuCount == 1) && (connectivity == P2P_CONNECTIVITY_PCIE)) { if (p2pCaps != NULL) { @@ -1950,6 +1950,7 @@ cliresCtrlCmdSystemGetGpusPowerStatus_IMPL RM_API *pRmApi; NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS params = {0}; + pGpu = gpumgrGetSomeGpu(); if (pGpu == NULL) diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index 9d9f9de30..19cefeeb5 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -777,14 +777,11 @@ rmapiControlWithSecInfo "Nv04Control: hClient:0x%x hObject:0x%x cmd:0x%x params:" NvP64_fmt " paramSize:0x%x flags:0x%x\n", hClient, hObject, cmd, pParams, paramsSize, flags); - NVRM_TRACE_API('CTRL', hClient, hObject, cmd); - status = _rmapiRmControl(hClient, hObject, cmd, pParams, paramsSize, flags, pRmApi, pSecInfo); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "Nv04Control: control complete\n"); - NVRM_TRACE('ctrl'); } else { @@ -794,7 +791,6 @@ rmapiControlWithSecInfo NV_PRINTF(LEVEL_INFO, "Nv04Control: hClient:0x%x hObject:0x%x cmd:0x%x params:" NvP64_fmt " paramSize:0x%x flags:0x%x\n", hClient, hObject, cmd, pParams, paramsSize, flags); - NVRM_TRACE_ERROR('ctrl', status); } return status; diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index b8a24fd48..b7768eae6 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -52,6 +52,7 @@ #include "ctrl/ctrl0073.h" #include "ctrl/ctrlb06f.h" #include "ctrl/ctrl83de.h" +#include "ctrl/ctrla083.h" #ifdef USE_AMAPLIB #include "amap_v1.h" #endif @@ -313,23 +314,6 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt break; } - case NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES: - { - CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS); - - NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *pUserParams = (NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS*)pParams; - NvU32 featureDebugValuesSize = (pUserParams->pFeatureDebugValues != NULL) ? sizeof(NV0073_CTRL_DP_MSA_PROPERTIES_VALUES) - : 0; - - RMAPI_PARAM_COPY_INIT(paramCopies[0], - pUserParams->pFeatureDebugValues, - pUserParams->pFeatureDebugValues, - 1, featureDebugValuesSize); - paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; - paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; - - break; - } case NV0080_CTRL_CMD_HOST_GET_CAPS: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_HOST_GET_CAPS_PARAMS); @@ -919,12 +903,6 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC ((NV2080_CTRL_I2C_ACCESS_PARAMS*)pParams)->data = paramCopies[0].pUserParams; break; } - case NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES: - { - status = rmapiParamsRelease(¶mCopies[0]); - ((NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS*)pParams)->pFeatureDebugValues = NvP64_VALUE(paramCopies[0].pUserParams); - break; - } case NV2080_CTRL_CMD_GR_GET_INFO: { status = rmapiParamsRelease(¶mCopies[0]); diff --git a/src/nvidia/src/kernel/rmapi/entry_points.c b/src/nvidia/src/kernel/rmapi/entry_points.c index fcb7c61d0..5a2da8ac5 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.c +++ b/src/nvidia/src/kernel/rmapi/entry_points.c @@ -381,8 +381,8 @@ static void _nv04MapMemoryWithSecInfo { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); - pArgs->status = pRmApi->MapToCpuWithSecInfo(pRmApi, pArgs->hClient, pArgs->hDevice, pArgs->hMemory, pArgs->offset, - pArgs->length, &pArgs->pLinearAddress, pArgs->flags, &secInfo); + pArgs->status = pRmApi->MapToCpuWithSecInfoV2(pRmApi, pArgs->hClient, pArgs->hDevice, pArgs->hMemory, pArgs->offset, + pArgs->length, &pArgs->pLinearAddress, &pArgs->flags, &secInfo); } /* diff --git a/src/nvidia/src/kernel/rmapi/entry_points.h b/src/nvidia/src/kernel/rmapi/entry_points.h index aa3d9cbd4..75103d745 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.h +++ b/src/nvidia/src/kernel/rmapi/entry_points.h @@ -262,6 +262,20 @@ rmapiMapToCpuWithSecInfo API_SECURITY_INFO *pSecInfo ); +NV_STATUS +rmapiMapToCpuWithSecInfoV2 +( + RM_API *pRmApi, + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvU64 offset, + NvU64 length, + NvP64 *ppCpuVirtAddr, + NvU32 *flags, + API_SECURITY_INFO *pSecInfo +); + NV_STATUS rmapiMapToCpuWithSecInfoTls ( @@ -275,6 +289,19 @@ rmapiMapToCpuWithSecInfoTls NvU32 flags, API_SECURITY_INFO *pSecInfo ); +NV_STATUS +rmapiMapToCpuWithSecInfoTlsV2 +( + RM_API *pRmApi, + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvU64 offset, + NvU64 length, + NvP64 *ppCpuVirtAddr, + NvU32 *flags, + API_SECURITY_INFO *pSecInfo +); NV_STATUS rmapiUnmapFromCpu diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index 924d24e41..6ff69b172 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -310,6 +310,15 @@ eventGetEngineTypeFromSubNotifyIndex case NV2080_NOTIFIERS_NVDEC4: *engineIdx = NV2080_ENGINE_TYPE_NVDEC4; break; + case NV2080_NOTIFIERS_NVDEC5: + *engineIdx = NV2080_ENGINE_TYPE_NVDEC5; + break; + case NV2080_NOTIFIERS_NVDEC6: + *engineIdx = NV2080_ENGINE_TYPE_NVDEC6; + break; + case NV2080_NOTIFIERS_NVDEC7: + *engineIdx = NV2080_ENGINE_TYPE_NVDEC7; + break; case NV2080_NOTIFIERS_PDEC: *engineIdx = NV2080_ENGINE_TYPE_VP; break; @@ -330,6 +339,27 @@ eventGetEngineTypeFromSubNotifyIndex case NV2080_NOTIFIERS_NVJPEG0: *engineIdx = NV2080_ENGINE_TYPE_NVJPEG0; break; + case NV2080_NOTIFIERS_NVJPEG1: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG1; + break; + case NV2080_NOTIFIERS_NVJPEG2: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG2; + break; + case NV2080_NOTIFIERS_NVJPEG3: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG3; + break; + case NV2080_NOTIFIERS_NVJPEG4: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG4; + break; + case NV2080_NOTIFIERS_NVJPEG5: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG5; + break; + case NV2080_NOTIFIERS_NVJPEG6: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG6; + break; + case NV2080_NOTIFIERS_NVJPEG7: + *engineIdx = NV2080_ENGINE_TYPE_NVJPEG7; + break; case NV2080_NOTIFIERS_OFA: *engineIdx = NV2080_ENGINE_TYPE_OFA; break; diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index 150414847..682feae1c 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -152,6 +152,14 @@ rmapiGetEffectiveAddrSpace return NV_OK; } +// Asserts to check caching type matches across sdk and nv_memory_types +ct_assert(NVOS33_FLAGS_CACHING_TYPE_CACHED == NV_MEMORY_CACHED); +ct_assert(NVOS33_FLAGS_CACHING_TYPE_UNCACHED == NV_MEMORY_UNCACHED); +ct_assert(NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED == NV_MEMORY_WRITECOMBINED); +ct_assert(NVOS33_FLAGS_CACHING_TYPE_WRITEBACK == NV_MEMORY_WRITEBACK); +ct_assert(NVOS33_FLAGS_CACHING_TYPE_DEFAULT == NV_MEMORY_DEFAULT); +ct_assert(NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK == NV_MEMORY_UNCACHED_WEAK); + // // Map memory entry points. // @@ -218,12 +226,12 @@ memMap_IMPL // // CPU to directly access protected memory is allowed on MODS // - if ((pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED) && - (pMapParams->protect != NV_PROTECT_WRITEABLE) && - ! RMCFG_FEATURE_PLATFORM_MODS) - { - return NV_ERR_NOT_SUPPORTED; - } + if ((pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED) && + (pMapParams->protect != NV_PROTECT_WRITEABLE) && + ! RMCFG_FEATURE_PLATFORM_MODS) + { + return NV_ERR_NOT_SUPPORTED; + } if (!pMapParams->bKernel && FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, pMemoryInfo->Attr2) && @@ -487,6 +495,7 @@ memMap_IMPL // direct mapping. // pMapParams->flags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _REFLECTED, pMapParams->flags); + pMapParams->flags = FLD_SET_DRF_NUM(OS33, _FLAGS, _CACHING_TYPE, cachingType, pMapParams->flags); if (rmStatus != NV_OK) goto _rmMapMemory_pciFail; @@ -1061,7 +1070,6 @@ rmapiMapToCpu return status; } - /** * Call into Resource Server to register and execute a CPU mapping operation. * @@ -1076,7 +1084,7 @@ rmapiMapToCpu * 6. Release any locks taken */ NV_STATUS -rmapiMapToCpuWithSecInfo +rmapiMapToCpuWithSecInfoV2 ( RM_API *pRmApi, NvHandle hClient, @@ -1085,7 +1093,7 @@ rmapiMapToCpuWithSecInfo NvU64 offset, NvU64 length, NvP64 *ppCpuVirtAddr, - NvU32 flags, + NvU32 *flags, API_SECURITY_INFO *pSecInfo ) { @@ -1099,13 +1107,13 @@ rmapiMapToCpuWithSecInfo hDevice, hMemory); NV_PRINTF(LEVEL_INFO, "Nv04MapMemory: offset: %llx length: %llx flags:0x%x\n", - offset, length, flags); + offset, length, *flags); status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) return status; - NV_PRINTF(LEVEL_INFO, "MMU_PROFILER Nv04MapMemory 0x%x\n", flags); + NV_PRINTF(LEVEL_INFO, "MMU_PROFILER Nv04MapMemory 0x%x\n", *flags); portMemSet(&lockInfo, 0, sizeof(lockInfo)); rmapiInitLockInfo(pRmApi, hClient, &lockInfo); @@ -1122,7 +1130,7 @@ rmapiMapToCpuWithSecInfo rmMapParams.offset = offset; rmMapParams.length = length; rmMapParams.ppCpuVirtAddr = ppCpuVirtAddr; - rmMapParams.flags = flags; + rmMapParams.flags = *flags; rmMapParams.pLockInfo = &lockInfo; rmMapParams.pSecInfo = pSecInfo; @@ -1130,6 +1138,8 @@ rmapiMapToCpuWithSecInfo rmapiEpilogue(pRmApi, &rmApiContext); + *flags = rmMapParams.flags; + if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "Nv04MapMemory: complete\n"); @@ -1147,6 +1157,25 @@ rmapiMapToCpuWithSecInfo return status; } +NV_STATUS +rmapiMapToCpuWithSecInfo +( + RM_API *pRmApi, + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvU64 offset, + NvU64 length, + NvP64 *ppCpuVirtAddr, + NvU32 flags, + API_SECURITY_INFO *pSecInfo +) +{ + return rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, + hDevice, hMemory, offset, length, ppCpuVirtAddr, + &flags, pSecInfo); +} + NV_STATUS rmapiMapToCpuWithSecInfoTls ( @@ -1166,7 +1195,32 @@ rmapiMapToCpuWithSecInfoTls threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = rmapiMapToCpuWithSecInfo(pRmApi, hClient, hDevice, hMemory, offset, length, ppCpuVirtAddr, flags, pSecInfo); + status = rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, hDevice, hMemory, offset, length, ppCpuVirtAddr, &flags, pSecInfo); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + return status; +} +NV_STATUS +rmapiMapToCpuWithSecInfoTlsV2 +( + RM_API *pRmApi, + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvU64 offset, + NvU64 length, + NvP64 *ppCpuVirtAddr, + NvU32 *flags, + API_SECURITY_INFO *pSecInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS status; + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + status = rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, hDevice, hMemory, offset, length, ppCpuVirtAddr, flags, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index 13a31a3d3..c97007f67 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -65,6 +65,9 @@ #include #include #include +#include +#include +#include #include #include @@ -143,9 +146,8 @@ typedef struct typedef struct { - NvU64 vaStart; // Needs to be alinged to pagesize - NvBool bFixedAddressAllocate; // rangeBegin & rangeEnd both included - NvU32 pageSize; // default is 4k or 64k else use pagesize= 2M + NvU32 pageSize; // default is 4k or 64k else use pagesize = 2M. + NvU64 alignment; } gpuVaAllocInfo; typedef struct @@ -301,7 +303,7 @@ struct gpuRetainedChannel_struct deviceDesc *rmDevice; subDeviceDesc *rmSubDevice; struct gpuSession *session; - OBJGPU *pGpu; + OBJGPU *pGpu; MEMORY_DESCRIPTOR *instanceMemDesc; MEMORY_DESCRIPTOR *resourceMemDesc[UVM_GPU_CHANNEL_MAX_RESOURCES]; UVM_GPU_CHANNEL_ENGINE_TYPE channelEngineType; @@ -402,6 +404,9 @@ static NvU32 getNvlinkConnectionToNpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ST NvU32 *linkBandwidthMBps); static NvU32 getNvlinkConnectionToSwitch(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus, NvU32 *linkBandwidthMBps); +static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, + NvBool *connectedToCpu, + NvU32 *linkBandwidthMBps); static NV_STATUS nvGpuOpsGetMemoryByHandle(NvHandle hClient, NvHandle hMemory, Memory **ppMemory); static void _nvGpuOpsReleaseChannel(gpuRetainedChannel *retainedChannel); static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, @@ -1475,6 +1480,8 @@ static UVM_LINK_TYPE rmControlToUvmNvlinkVersion(NvU32 nvlinkVersion) else if (nvlinkVersion == NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 || nvlinkVersion == NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1) return UVM_LINK_TYPE_NVLINK_3; + else if (nvlinkVersion == NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0) + return UVM_LINK_TYPE_NVLINK_4; NV_ASSERT(0); return (NvU32)-1; @@ -1752,6 +1759,24 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, nvlinkStatus = NULL; break; } + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C: + { + NvBool c2cConnectedToCpu = NV_FALSE; + + status = getC2CConnectionToCpu(device, &c2cConnectedToCpu, &linkBandwidthMBps); + if (status != NV_OK) + goto cleanup_ecc; + + if (c2cConnectedToCpu == NV_FALSE) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_STATE; + goto cleanup_ecc; + } + + sysmemLink = UVM_LINK_TYPE_C2C; + break; + } case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: { sysmemLink = UVM_LINK_TYPE_PCIE; @@ -2275,6 +2300,33 @@ static NvU32 getNvlinkConnectionToGpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ST return version; } +static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, + NvBool *connectedToCpu, + NvU32 *linkBandwidthMBps) +{ + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS params = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + *connectedToCpu = NV_FALSE; + *linkBandwidthMBps = 0; + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + device->session->handle, + device->subhandle, + NV2080_CTRL_CMD_BUS_GET_C2C_INFO, + ¶ms, + sizeof(params))); + + if (params.bIsLinkUp == NV_TRUE && + (params.remoteType == NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU)) + { + *connectedToCpu = NV_TRUE; + *linkBandwidthMBps = params.nrLinks * params.perLinkBwMBps; + } + + return NV_OK; +} + // If the given NvLink connection has a NPU device as an endpoint, return the // version of the NvLink connection with that NPU , and the maximum // unidirectional bandwidth in megabytes per second. Otherwise, return @@ -3071,6 +3123,26 @@ nvGpuOpsBuildExternalAllocPtes if (!pteCount) return NV_ERR_BUFFER_TOO_SMALL; + if (pFmt->version == GMMU_FMT_VERSION_3) + { + NvU32 ptePcfSw = 0; + NvU32 ptePcfHw = 0; + + nvFieldSetBool(&pPteFmt->fldValid, NV_TRUE, pte.v8); + gmmuFieldSetAperture(&pPteFmt->fldAperture, aperture, pte.v8); + nvFieldSet32(&pPteFmt->fldKind, kind, pte.v8); + + ptePcfSw |= vol ? (1 << SW_MMU_PCF_UNCACHED_IDX) : 0; + ptePcfSw |= readOnly ? (1 << SW_MMU_PCF_RO_IDX) : 0; + ptePcfSw |= !atomic ? (1 << SW_MMU_PCF_NOATOMIC_IDX) : 0; + ptePcfSw |= !privileged ? (1 << SW_MMU_PCF_REGULAR_IDX) : 0; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + (kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, &ptePcfHw) == NV_OK), + NV_ERR_INVALID_ARGUMENT); + nvFieldSet32(&pPteFmt->fldPtePcf, ptePcfHw, pte.v8); + } + else { if (nvFieldIsValid32(&pPteFmt->fldValid.desc)) nvFieldSetBool(&pPteFmt->fldValid, NV_TRUE, pte.v8); @@ -3562,21 +3634,6 @@ static NV_STATUS nvGpuOpsAllocPhysical(struct gpuDevice *device, break; } - // Set the alignment - if (allocInfo->alignment) - { - memAllocParams.flags |= NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; - memAllocParams.alignment = allocInfo->alignment; - } - - // Do we have a range Hint ? - if (allocInfo->rangeBegin != allocInfo->rangeEnd) - { - memAllocParams.flags |= NVOS32_ALLOC_FLAGS_USE_BEGIN_END; - memAllocParams.rangeLo = allocInfo->rangeBegin; - memAllocParams.rangeHi = allocInfo->rangeEnd; - } - // Do we need to allocate at top of FB if (allocInfo->bMemGrowsDown) memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN; @@ -3640,17 +3697,11 @@ static NV_STATUS nvGpuOpsAllocVirtual(struct gpuAddressSpace *vaSpace, memAllocParams.owner = HEAP_OWNER_RM_KERNEL_CLIENT; memAllocParams.size = length; memAllocParams.type = NVOS32_TYPE_IMAGE; - memAllocParams.alignment = NV_GPU_SMALL_PAGESIZE; + memAllocParams.alignment = allocInfo->alignment ? allocInfo->alignment : NV_GPU_SMALL_PAGESIZE; memAllocParams.flags = NVOS32_ALLOC_FLAGS_VIRTUAL | NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE | NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED; - if (allocInfo->bFixedAddressAllocate) - { - memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; - memAllocParams.offset = allocInfo->vaStart; - } - // Set pageSize for VA-allocation. RM default is Big page size switch (allocInfo->pageSize) { @@ -3812,6 +3863,7 @@ static NV_STATUS nvGpuOpsGpuMalloc(struct gpuAddressSpace *vaSpace, paMemDescHandle = allocInfo->hPhysHandle; vaAllocInfo.pageSize = allocInfo->pageSize; + vaAllocInfo.alignment = allocInfo->alignment; status = nvGpuOpsAllocVirtual(vaSpace, length, &vaOffset, paMemDescHandle, flags, &vaAllocInfo); @@ -4163,6 +4215,19 @@ static NV_STATUS gpuDeviceMapUsermodeRegion(struct gpuDevice *device) RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); struct gpuSession *session = device->session; subDeviceDesc *rmSubDevice = device->rmSubDevice; + NvU32 usermodeClass = VOLTA_USERMODE_A; + void *pParams = NULL; + NV_HOPPER_USERMODE_A_PARAMS hopperParams = + { + .bBar1Mapping = NV_TRUE, + .bPriv = NV_FALSE + }; + + if (device->rmDevice->arch >= GPU_ARCHITECTURE_HOPPER) + { + usermodeClass = HOPPER_USERMODE_A; + pParams = &hopperParams; + } NV_ASSERT(isDeviceVoltaPlus(device)); NV_ASSERT(rmSubDevice->clientRegionHandle == 0 && rmSubDevice->clientRegionMapping == NULL); @@ -4172,8 +4237,8 @@ static NV_STATUS gpuDeviceMapUsermodeRegion(struct gpuDevice *device) session->handle, device->subhandle, ®ionHandle, - VOLTA_USERMODE_A, - NULL); + usermodeClass, + pParams); if (NV_OK != status) return status; @@ -5900,6 +5965,7 @@ NV_STATUS nvGpuOpsDupMemory(struct gpuDevice *device, NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace, NvU64 srcAddress, struct gpuAddressSpace *dstVaSpace, + NvU64 dstVaAlignment, NvU64 *dstAddress) { NV_STATUS status; @@ -5945,9 +6011,10 @@ NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace, goto cleanup_dup; } - // The virtual allocation and mapping use the size, and page size, of the - // destination memory descriptor + // The virtual allocation and mapping use the size, page size, and alignment + // of the destination memory descriptor. allocInfo.pageSize = gpuMemoryInfo.pageSize; + allocInfo.alignment = dstVaAlignment; status = nvGpuOpsAllocVirtual(dstVaSpace, gpuMemoryInfo.size, @@ -6080,8 +6147,12 @@ static NV_STATUS queryCopyEngines(struct gpuDevice *gpu, gpuCesCaps *cesCaps) NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS pceMaskParams = {0}; NvU8 rmCeCaps[NV2080_CTRL_CE_CAPS_TBL_SIZE] = {0}; UvmGpuCopyEngineCaps *ceCaps; + NvU32 ceIndex; - NvU32 ceIndex = engineList[i] - NV2080_ENGINE_TYPE_COPY0; + if (!NV2080_ENGINE_TYPE_IS_COPY(engineList[i])) + continue; + + ceIndex = NV2080_ENGINE_TYPE_COPY_IDX(engineList[i]); if (ceIndex >= NV2080_ENGINE_TYPE_COPY_SIZE) continue; @@ -6149,6 +6220,7 @@ static NvBool isClassCE(NvU32 class) case TURING_DMA_COPY_A: case AMPERE_DMA_COPY_A: case AMPERE_DMA_COPY_B: + case HOPPER_DMA_COPY_A: return NV_TRUE; default: @@ -6179,6 +6251,7 @@ static NvBool isClassCompute(NvU32 class) case TURING_COMPUTE_A: case AMPERE_COMPUTE_A: case AMPERE_COMPUTE_B: + case HOPPER_COMPUTE_A: return NV_TRUE; default: @@ -7574,23 +7647,20 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, goto error; } - channelInstanceInfo->workSubmissionToken = params.workSubmitToken; - channelInstanceInfo->workSubmissionOffset = - (NvU32 *)((NvU8*)rmSubDevice->clientRegionMapping + NVC361_NOTIFY_CHANNEL_PENDING); - // In Turing+ gpus, the CLEAR_FAULTED method requires a RM-provided handle // to identify the channel. // // TODO: Bug 1905719: We are currently using the channel handle that is - // used for the doorbell mechanism. However, the values may differ in the - // future, so we may need a dedicated API to get the channel handle for - // CLEAR_FAULTED in RM. - channelInstanceInfo->clearFaultedToken = channelInstanceInfo->workSubmissionToken; + // used for the work submission usermode doorbell mechanism. However, the + // values may differ in the future, so we may need a dedicated API to get + // the channel handle for CLEAR_FAULTED in RM. + channelInstanceInfo->clearFaultedToken = params.workSubmitToken; if (isDeviceAmperePlus(device)) { void *bar0Mapping = gpuBar0BaseAddress(pGpu); NvU32 chramPri; + NvU32 runlistPri; NV_ASSERT_OK_OR_GOTO(status, kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), @@ -7602,6 +7672,15 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, chramPri += NV_CHRAM_CHANNEL(pKernelChannel->ChID); channelInstanceInfo->pChramChannelRegister = (NvU32 *)((NvU8*)bar0Mapping + chramPri); + + NV_ASSERT_OK_OR_GOTO(status, kfifoEngineInfoXlate_HAL(pGpu, + GPU_GET_KERNEL_FIFO(pGpu), + ENGINE_INFO_TYPE_RUNLIST, + kchannelGetRunlistId(pKernelChannel), + ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, + &runlistPri), error); + + channelInstanceInfo->pRunlistPRIBaseRegister = (NvU32 *)((NvU8*)bar0Mapping + runlistPri); } status = _nvGpuOpsRetainChannelResources(device, diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 34b28fed0..752774de7 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -288,6 +288,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ HOPPER_CHANNEL_GPFIFO_A, + /* Internal Class */ KernelChannel, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ UVM_CHANNEL_RETAINER, /* Internal Class */ UvmChannelRetainer, @@ -589,6 +599,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ HOPPER_USERMODE_A, + /* Internal Class */ UserModeApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_OPTIONAL(NV_HOPPER_USERMODE_A_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC371_DISP_SF_USER, /* Internal Class */ DispSfUser, @@ -609,6 +629,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC771_DISP_SF_USER, + /* Internal Class */ DispSfUser, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ MMU_FAULT_BUFFER, /* Internal Class */ MmuFaultBuffer, @@ -690,6 +720,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC770_DISPLAY, + /* Internal Class */ NvDispApi, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Device)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC372_DISPLAY_SW, /* Internal Class */ DispSwObj, @@ -810,6 +850,7 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) + RS_ENTRY( NVC77D_CORE_CHANNEL_DMA, DispChannelDma, NV_TRUE, RS_LIST(classId(NvDispApi)), RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), RS_FREE_PRIORITY_DEFAULT, RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, RS_ACCESS_NONE ) RS_ENTRY( /* External Class */ NVC67E_WINDOW_CHANNEL_DMA, /* Internal Class */ DispChannelDma, @@ -829,6 +870,16 @@ RS_ENTRY( /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVC773_DISP_CAPABILITIES, + /* Internal Class */ DispCapabilities, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(NvDispApi)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE ) /* Classes allocated under channel: */ RS_ENTRY( @@ -931,6 +982,26 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ HOPPER_DMA_COPY_A, + /* Internal Class */ KernelCeContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVB8B0_VIDEO_DECODER, + /* Internal Class */ NvdecContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC4B0_VIDEO_DECODER, /* Internal Class */ NvdecContext, @@ -961,6 +1032,26 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC9B0_VIDEO_DECODER, + /* Internal Class */ NvdecContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVB8D1_VIDEO_NVJPG, + /* Internal Class */ NvjpgContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC4D1_VIDEO_NVJPG, /* Internal Class */ NvjpgContext, @@ -971,6 +1062,26 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC9D1_VIDEO_NVJPG, + /* Internal Class */ NvjpgContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVB8FA_VIDEO_OFA, + /* Internal Class */ OfaContext, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC6FA_VIDEO_OFA, /* Internal Class */ OfaContext, @@ -991,6 +1102,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC9FA_VIDEO_OFA, + /* Internal Class */ OfaContext, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC4B7_VIDEO_ENCODER, /* Internal Class */ MsencContext, @@ -1021,6 +1142,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC9B7_VIDEO_ENCODER, + /* Internal Class */ MsencContext, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ AMPERE_A, /* Internal Class */ KernelGraphicsObject, @@ -1061,6 +1192,46 @@ RS_ENTRY( /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ ADA_A, + /* Internal Class */ KernelGraphicsObject, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ ADA_COMPUTE_A, + /* Internal Class */ KernelGraphicsObject, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ HOPPER_A, + /* Internal Class */ KernelGraphicsObject, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ HOPPER_COMPUTE_A, + /* Internal Class */ KernelGraphicsObject, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ FERMI_TWOD_A, /* Internal Class */ KernelGraphicsObject, @@ -1151,6 +1322,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_COUNTER_COLLECTION_UNIT, + /* Internal Class */ KernelCcuApi, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) // Undefine the entry macro to simplify call sites #undef RS_ENTRY diff --git a/src/nvidia/src/kernel/rmapi/rmapi.c b/src/nvidia/src/kernel/rmapi/rmapi.c index 8827d5784..a07481dbc 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi.c +++ b/src/nvidia/src/kernel/rmapi/rmapi.c @@ -181,6 +181,7 @@ _rmapiInitInterface pRmApi->MapToCpu = rmapiMapToCpu; pRmApi->MapToCpuWithSecInfo = pRmApi->bTlsInternal ? rmapiMapToCpuWithSecInfo : rmapiMapToCpuWithSecInfoTls; + pRmApi->MapToCpuWithSecInfoV2 = pRmApi->bTlsInternal ? rmapiMapToCpuWithSecInfoV2 : rmapiMapToCpuWithSecInfoTlsV2; pRmApi->UnmapFromCpu = rmapiUnmapFromCpu; pRmApi->UnmapFromCpuWithSecInfo = pRmApi->bTlsInternal ? rmapiUnmapFromCpuWithSecInfo : rmapiUnmapFromCpuWithSecInfoTls; diff --git a/src/nvidia/src/kernel/rmapi/sharing.c b/src/nvidia/src/kernel/rmapi/sharing.c index a99a03c33..74956112d 100644 --- a/src/nvidia/src/kernel/rmapi/sharing.c +++ b/src/nvidia/src/kernel/rmapi/sharing.c @@ -111,8 +111,6 @@ rmapiDupObjectWithSecInfo "Nv04DupObject: hClientSrc:0x%x hObjectSrc:0x%x flags:0x%x\n", hClientSrc, hObjectSrc, flags); - NVRM_TRACE_API('DUPH', hClient, hObject, hObjectSrc); - status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) { @@ -145,7 +143,6 @@ rmapiDupObjectWithSecInfo if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "...handle dup complete\n"); - NVRM_TRACE('DUPH'); } else { @@ -244,8 +241,6 @@ rmapiShareWithSecInfo "Nv04Share: hClient:0x%x hObject:0x%x pSharePolicy:%p\n", hClient, hObject, pSharePolicy); - NVRM_TRACE_API('SHAR', hClient, hObject, 0); - status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) { @@ -270,7 +265,6 @@ rmapiShareWithSecInfo if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "...resource share complete\n"); - NVRM_TRACE('SHAR'); } else { diff --git a/src/nvidia/src/lib/base_utils.c b/src/nvidia/src/lib/base_utils.c index 9a02e3db9..8210f13a0 100644 --- a/src/nvidia/src/lib/base_utils.c +++ b/src/nvidia/src/lib/base_utils.c @@ -35,21 +35,10 @@ // NvU32 nvLogBase2(NvU64 val) { - NvU32 i; - - NV_ASSERT(((val)&(val-1)) == 0); - - for (i = 0; i < 64; i++) - { - if ((1ull << i) == val) - { - break; - } - } - - NV_ASSERT(i < 64); + NV_ASSERT(val != 0); + NV_ASSERT(((val) & (val - 1)) == 0); - return i; + return portUtilCountTrailingZeros64(val); } diff --git a/src/nvidia/src/libraries/mmu/gmmu_fmt.c b/src/nvidia/src/libraries/mmu/gmmu_fmt.c index 6f438adf1..db8545ece 100644 --- a/src/nvidia/src/libraries/mmu/gmmu_fmt.c +++ b/src/nvidia/src/libraries/mmu/gmmu_fmt.c @@ -31,6 +31,7 @@ const NvU32 g_gmmuFmtVersions[GMMU_FMT_MAX_VERSION_COUNT] = { GMMU_FMT_VERSION_1, GMMU_FMT_VERSION_2, + GMMU_FMT_VERSION_3, }; const NvU32 g_gmmuFmtBigPageShifts[GMMU_FMT_MAX_BIG_PAGE_SIZES] = @@ -91,6 +92,12 @@ gmmuFmtPdePhysAddrFld const GMMU_APERTURE aperture ) { + if (pPde->version == GMMU_FMT_VERSION_3) + { + // GMMU_FMT_VERSION_3 uses a unified PDE field + return &pPde->fldAddr; + } + else { switch (aperture) { diff --git a/src/nvidia/src/libraries/nvoc/src/runtime.c b/src/nvidia/src/libraries/nvoc/src/runtime.c index 29d517a00..d4df6aed7 100644 --- a/src/nvidia/src/libraries/nvoc/src/runtime.c +++ b/src/nvidia/src/libraries/nvoc/src/runtime.c @@ -176,6 +176,15 @@ NV_STATUS __nvoc_objCreateDynamic( const struct NVOC_CLASS_DEF *pClassDef = (const struct NVOC_CLASS_DEF*)pClassInfo; + if (pClassDef == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + else if (pClassDef->objCreatefn == NULL) + { + return NV_ERR_INVALID_CLASS; + } + va_start(args, createFlags); status = pClassDef->objCreatefn(ppNewObject, pParent, createFlags, args); va_end(args); diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index fd569476b..4af26f0d9 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -439,7 +439,7 @@ static void *_portMemAllocatorAllocNonPagedWrapper(PORT_MEM_ALLOCATOR *pAlloc, N static void _portMemAllocatorFreeWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); static void _portMemAllocatorReleaseWrapper(PORT_MEM_ALLOCATOR *pAlloc); -static PORT_MEM_ALLOCATOR *_portMemAllocatorCreateOnExistingBlock(void *pAlloc, NvLength blockSizeBytes, void *pSpinlock PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); +static PORT_MEM_ALLOCATOR *_portMemAllocatorCreateOnExistingBlock(void *pAlloc, NvLength blockSizeBytes, void *pSpinlock); static void *_portMemAllocatorAllocExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, NvLength length); static void _portMemAllocatorFreeExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); @@ -560,7 +560,7 @@ portMemShutdown(NvBool bForceSilent) { portMemPrintTrackingInfo(NULL); } -#endif +#endif PORT_MEM_LOG_DESTROY(); if (PORT_MEM_TRACK_USE_FENCEPOSTS) @@ -640,7 +640,7 @@ portMemAllocatorCreatePaged(PORT_MEM_CALLERINFO_TYPE_PARAM) portMemInitializeAllocatorTracking(pAllocator, &pAllocator->pImpl->tracking PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_PRINT_INFO("Acquired paged allocator %p ", pAllocator); + PORT_MEM_PRINT_INFO("Acquired paged allocator %p", pAllocator); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; @@ -663,7 +663,7 @@ portMemAllocatorCreateNonPaged(PORT_MEM_CALLERINFO_TYPE_PARAM) portMemInitializeAllocatorTracking(pAllocator, &pAllocator->pImpl->tracking PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_PRINT_INFO("Acquired nonpaged allocator %p ", pAllocator); + PORT_MEM_PRINT_INFO("Acquired nonpaged allocator %p", pAllocator); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } @@ -678,7 +678,7 @@ portMemAllocatorCreateOnExistingBlock ) { return _portMemAllocatorCreateOnExistingBlock(pPreallocatedBlock, blockSizeBytes, - NULL PORT_MEM_CALLERINFO_COMMA_PARAM); + NULL); } PORT_MEM_ALLOCATOR * @@ -691,7 +691,7 @@ portMemExAllocatorCreateLockedOnExistingBlock ) { return _portMemAllocatorCreateOnExistingBlock(pPreallocatedBlock, blockSizeBytes, - pSpinlock PORT_MEM_CALLERINFO_COMMA_PARAM); + pSpinlock); } void @@ -1029,7 +1029,7 @@ portMemExTrackingGetNext pHead = _portMemListGetHeader(pList); - // Advance iterator + // Advance itertator if (pList->pNext == pTracking->pFirstAlloc) *pIterator = NULL; else @@ -1174,7 +1174,6 @@ _portMemAllocatorCreateOnExistingBlock void *pPreallocatedBlock, NvLength blockSizeBytes, void *pSpinlock - PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { PORT_MEM_ALLOCATOR *pAllocator = (PORT_MEM_ALLOCATOR *)pPreallocatedBlock; @@ -1226,7 +1225,7 @@ _portMemAllocatorCreateOnExistingBlock } portMemSet(pBitVector->bits, 0, bitVectorSize); - PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes) ", pAllocator, (NvU64)blockSizeBytes); + PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes)", pAllocator, (NvU64)blockSizeBytes); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 26f646f51..807919149 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -60,12 +60,15 @@ SRCS += generated/g_journal_nvoc.c SRCS += generated/g_journal_pb.c SRCS += generated/g_kern_bus_nvoc.c SRCS += generated/g_kern_disp_nvoc.c +SRCS += generated/g_kern_fsp_nvoc.c SRCS += generated/g_kern_gmmu_nvoc.c SRCS += generated/g_kern_mem_sys_nvoc.c SRCS += generated/g_kern_perf_nvoc.c SRCS += generated/g_kern_perfbuffer_nvoc.c SRCS += generated/g_kern_pmu_nvoc.c SRCS += generated/g_kernel_bif_nvoc.c +SRCS += generated/g_kernel_ccu_api_nvoc.c +SRCS += generated/g_kernel_ccu_nvoc.c SRCS += generated/g_kernel_ce_context_nvoc.c SRCS += generated/g_kernel_ce_nvoc.c SRCS += generated/g_kernel_channel_group_api_nvoc.c @@ -84,7 +87,6 @@ SRCS += generated/g_kernel_ioctrl_nvoc.c SRCS += generated/g_kernel_mc_nvoc.c SRCS += generated/g_kernel_mig_manager_nvoc.c SRCS += generated/g_kernel_nvdec_ctx_nvoc.c -SRCS += generated/g_kernel_nvdec_nvoc.c SRCS += generated/g_kernel_nvenc_ctx_nvoc.c SRCS += generated/g_kernel_nvjpg_ctx_nvoc.c SRCS += generated/g_kernel_nvlink_nvoc.c @@ -261,15 +263,19 @@ SRCS += src/kernel/diagnostics/nvlog.c SRCS += src/kernel/diagnostics/nvlog_printf.c SRCS += src/kernel/diagnostics/profiler.c SRCS += src/kernel/disp/disp_sw.c +SRCS += src/kernel/gpu/arch/ada/kern_gpu_ad102.c SRCS += src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +SRCS += src/kernel/gpu/arch/hopper/kern_gpu_gh100.c SRCS += src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c SRCS += src/kernel/gpu/arch/turing/kern_gpu_tu102.c SRCS += src/kernel/gpu/audio/hda_codec_api.c SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c +SRCS += src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c SRCS += src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c SRCS += src/kernel/gpu/bif/kernel_bif.c SRCS += src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +SRCS += src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c SRCS += src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c SRCS += src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c SRCS += src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -282,8 +288,11 @@ SRCS += src/kernel/gpu/bus/p2p.c SRCS += src/kernel/gpu/bus/p2p_api.c SRCS += src/kernel/gpu/bus/third_party_p2p.c SRCS += src/kernel/gpu/bus/third_party_p2p_ctrl.c +SRCS += src/kernel/gpu/ccu/kernel_ccu.c +SRCS += src/kernel/gpu/ccu/kernel_ccu_api.c SRCS += src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c SRCS += src/kernel/gpu/ce/arch/ampere/kernel_ce_ga102.c +SRCS += src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c SRCS += src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c SRCS += src/kernel/gpu/ce/arch/turing/kernel_ce_tu102.c SRCS += src/kernel/gpu/ce/arch/volta/kernel_ce_gv100.c @@ -317,8 +326,12 @@ SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c SRCS += src/kernel/gpu/falcon/kernel_falcon.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga100.c +SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga102.c +SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c +SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c +SRCS += src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c @@ -340,6 +353,8 @@ SRCS += src/kernel/gpu/fifo/kernel_idle_channels.c SRCS += src/kernel/gpu/fifo/kernel_sched_mgr.c SRCS += src/kernel/gpu/fifo/usermode_api.c SRCS += src/kernel/gpu/fifo/uvm_channel_retainer.c +SRCS += src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +SRCS += src/kernel/gpu/fsp/kern_fsp.c SRCS += src/kernel/gpu/gpu.c SRCS += src/kernel/gpu/gpu_access.c SRCS += src/kernel/gpu/gpu_device_mapping.c @@ -366,6 +381,7 @@ SRCS += src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_falcon_ga102.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga100.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +SRCS += src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c SRCS += src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c SRCS += src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c SRCS += src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c @@ -382,6 +398,7 @@ SRCS += src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c SRCS += src/kernel/gpu/i2c/i2c_api.c SRCS += src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c SRCS += src/kernel/gpu/intr/arch/ampere/intr_ga100.c +SRCS += src/kernel/gpu/intr/arch/hopper/intr_gh100.c SRCS += src/kernel/gpu/intr/arch/maxwell/intr_gm107.c SRCS += src/kernel/gpu/intr/arch/pascal/intr_gp100.c SRCS += src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c @@ -395,9 +412,12 @@ SRCS += src/kernel/gpu/intrable/intrable.c SRCS += src/kernel/gpu/mc/arch/ampere/kernel_mc_ga100.c SRCS += src/kernel/gpu/mc/arch/maxwell/kernel_mc_gm107.c SRCS += src/kernel/gpu/mc/kernel_mc.c +SRCS += src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c SRCS += src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c SRCS += src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c SRCS += src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga102.c +SRCS += src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c +SRCS += src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c @@ -432,6 +452,7 @@ SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c SRCS += src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c SRCS += src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga102.c +SRCS += src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c SRCS += src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c SRCS += src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm200.c SRCS += src/kernel/gpu/mem_sys/arch/pascal/kern_mem_sys_gp102.c @@ -440,6 +461,7 @@ SRCS += src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c SRCS += src/kernel/gpu/mem_sys/kern_mem_sys.c SRCS += src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c SRCS += src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c +SRCS += src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c SRCS += src/kernel/gpu/mig_mgr/compute_instance_subscription.c SRCS += src/kernel/gpu/mig_mgr/gpu_instance_subscription.c SRCS += src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -447,6 +469,8 @@ SRCS += src/kernel/gpu/mig_mgr/mig_config_session.c SRCS += src/kernel/gpu/mig_mgr/mig_monitor_session.c SRCS += src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c SRCS += src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +SRCS += src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c +SRCS += src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c SRCS += src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm10x.c SRCS += src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm20x.c SRCS += src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -465,10 +489,6 @@ SRCS += src/kernel/gpu/mmu/mmu_fault_buffer.c SRCS += src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c SRCS += src/kernel/gpu/mmu/mmu_trace.c SRCS += src/kernel/gpu/mmu/uvm_sw.c -SRCS += src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga100.c -SRCS += src/kernel/gpu/nvdec/arch/ampere/kernel_nvdec_ga102.c -SRCS += src/kernel/gpu/nvdec/arch/turing/kernel_nvdec_tu102.c -SRCS += src/kernel/gpu/nvdec/kernel_nvdec.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_ctx.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c SRCS += src/kernel/gpu/nvenc/kernel_nvenc_ctx.c @@ -476,6 +496,7 @@ SRCS += src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c SRCS += src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c SRCS += src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c SRCS += src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c +SRCS += src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c SRCS += src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c SRCS += src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c SRCS += src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c @@ -516,12 +537,14 @@ SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_fla.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c +SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c SRCS += src/kernel/gpu/subdevice/subdevice_diag.c SRCS += src/kernel/gpu/sw_eng.c SRCS += src/kernel/gpu/sw_test.c SRCS += src/kernel/gpu/timed_semaphore.c SRCS += src/kernel/gpu/timer/arch/ampere/timer_ga100.c +SRCS += src/kernel/gpu/timer/arch/hopper/timer_gh100.c SRCS += src/kernel/gpu/timer/arch/maxwell/timer_gm107.c SRCS += src/kernel/gpu/timer/arch/maxwell/timer_gm200.c SRCS += src/kernel/gpu/timer/arch/turing/timer_tu102.c diff --git a/version.mk b/version.mk index f3d119595..cad40b17d 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 515.76 +NVIDIA_VERSION = 520.61.05 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))