From d09bc22681f5e6351b6e36f93167a4bc4f3a329b Mon Sep 17 00:00:00 2001
From: Diego Van Overberghe <36131808+Diegovano@users.noreply.github.com>
Date: Fri, 28 Oct 2022 11:05:46 +0100
Subject: [PATCH 1/3] Update Lab_1.md

Add missing semicolon in snippet.
---
 Lab_1.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Lab_1.md b/Lab_1.md
index 24b197b1..ffdd6360 100644
--- a/Lab_1.md
+++ b/Lab_1.md
@@ -263,7 +263,7 @@ module counter #(
 
 always_ff @ (posedge clk)
   if (rst) count <= {WIDTH{1'b0}};
-  else     count <= ld ? v : count + {{WIDTH-1{1'b0}},1'b1}
+  else     count <= ld ? v : count + {{WIDTH-1{1'b0}},1'b1};
 endmodule
 ```
 

From c1aa912b54bce53e8696ed0f299c56ef5790bc12 Mon Sep 17 00:00:00 2001
From: Diego Van Overberghe <36131808+Diegovano@users.noreply.github.com>
Date: Fri, 28 Oct 2022 11:08:40 +0100
Subject: [PATCH 2/3] Update Lab_1.md

Bump README version
---
 Lab_1.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Lab_1.md b/Lab_1.md
index ffdd6360..3b7f8110 100644
--- a/Lab_1.md
+++ b/Lab_1.md
@@ -6,7 +6,7 @@
 
 
 ## Lab 1 – Learning System Verilog with Verilator and Vbuddy
-##### *Peter Cheung, v1.2 - 28 Oct 2022*
+##### *Peter Cheung, v1.3 - 28 Oct 2022*
 
 ---
 ## Objectives

From 60627dd9d4619c2b20a8994aad92ab3459babb17 Mon Sep 17 00:00:00 2001
From: Diego Van Overberghe <36131808+Diegovano@users.noreply.github.com>
Date: Fri, 28 Oct 2022 11:22:32 +0100
Subject: [PATCH 3/3] Fix minor issues with README

---
 Lab_1.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Lab_1.md b/Lab_1.md
index 3b7f8110..9b96abe1 100644
--- a/Lab_1.md
+++ b/Lab_1.md
@@ -318,4 +318,4 @@ bin2bcd myDecoder (
 endmodule
 ```
 Modify the testbench file **_top_tb.cpp_** accordingly.  
-Modify the **_doit.sh_** file from task 3 to include all the modules (**_top.sv, counter.sv, bin2bcd.sv_** and **_top_tb.sv_**).  Compile and run the Verilated model.  Check that it works according to expectation.
+Modify the **_doit.sh_** file from task 3 to include all the modules (**_top.sv, counter.sv, bin2bcd.sv_** and **_top_tb.cpp_**).  Compile and run the Verilated model.  Check that it works according to expectation.