From 6c8f1816c8e1c22a4ebb684e2fe9ab514466b264 Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 14:38:07 +0200 Subject: [PATCH 1/9] Add saving and restoring the vtype and vl vector registers for RISC-V vector extension. This patch was authored at the Computer Architecture and VLSI Laboratory, Institute of Computer Sciense, Foundation of Reasearch and Technology, Hellas. It emmits the necessary instructions that handle saving and restoring the vl and vtype during the context switches, when using the vector extension of the RISC-V ISA. This is required, in order to use the use the vector extension correctly. --- core/arch/arch.h | 2 ++ core/arch/emit_utils_shared.c | 2 +- core/arch/riscv64/emit_utils.c | 34 +++++++++++++++++++ core/arch/riscv64/mangle.c | 62 ++++++++++++++++++++++++++++++++++ core/arch/riscv64/riscv64.asm | 4 +-- core/lib/mcxtx_api.h | 2 ++ 6 files changed, 103 insertions(+), 3 deletions(-) diff --git a/core/arch/arch.h b/core/arch/arch.h index bdafa029a5d..c45cedd909d 100644 --- a/core/arch/arch.h +++ b/core/arch/arch.h @@ -176,6 +176,8 @@ mixed_mode_enabled(void) # define XFLAGS_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, fcsr))) # define VSTART_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vstart))) # define VCSR_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vcsr))) +# define VL_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vl))) +# define VTYPE_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vtype))) # define SCRATCH_REG0 DR_REG_A0 # define SCRATCH_REG1 DR_REG_A1 # define SCRATCH_REG2 DR_REG_A2 diff --git a/core/arch/emit_utils_shared.c b/core/arch/emit_utils_shared.c index 14a34e5bcb6..e155c2f5673 100644 --- a/core/arch/emit_utils_shared.c +++ b/core/arch/emit_utils_shared.c @@ -4980,8 +4980,8 @@ emit_fcache_enter_gonative(dcontext_t *dcontext, generated_code_t *code, byte *p append_call_exit_dr_hook(dcontext, &ilist, absolute, shared); /* restore the original register state */ - append_restore_xflags(dcontext, &ilist, absolute); append_restore_simd_reg(dcontext, &ilist, absolute); + append_restore_xflags(dcontext, &ilist, absolute); append_restore_gpr(dcontext, &ilist, absolute); /* We need to restore the stolen reg, but we have no scratch registers. diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index cf9ee479a4c..656245e32bc 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -54,6 +54,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F +#define VL 0xC20 +#define VTYPE 0xC21 /* Instruction fixed bits constants. */ @@ -661,6 +663,20 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute) INSTR_CREATE_csrrw(dcontext, opnd_create_reg(DR_REG_ZERO), opnd_create_reg(DR_REG_A0), opnd_create_immed_int(VCSR, OPSZ_12b))); + + /* + * The code below is contributed and copyrighted by FORTH + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + */ + APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET)); + APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); + APP(ilist, + INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_A1))); + /* + * End of FORTH copyrighted section + */ } } @@ -877,6 +893,24 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute opnd_create_reg(DR_REG_ZERO), opnd_create_immed_int(VCSR, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VCSR_OFFSET)); + + /* + * The code below is contributed and copyrighted by FORTH + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + */ + APP(ilist, + INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), + opnd_create_reg(DR_REG_ZERO), + opnd_create_immed_int(VL, OPSZ_12b))); + APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET)); + APP(ilist, + INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), + opnd_create_reg(DR_REG_ZERO), + opnd_create_immed_int(VTYPE, OPSZ_12b))); + APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); + /* + * End of FORTH copyrighted section + */ } } diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 2ba2c6c183c..8aea5328306 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -45,6 +45,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F +#define VL 0xC20 +#define VTYPE 0xC21 /* TODO i#3544: Think of a better way to represent these fields in the IR. */ /* Volume I: RISC-V Unprivileged ISA V20191213. @@ -191,6 +193,45 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, } dstack_offs += XSP_SZ; + + /* + * The code below is contributed and copyrighted by FORTH + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + */ + if (proc_has_feature(FEATURE_VECTOR)) { + /* csrr a0, vl */ + PRE(ilist, instr, + INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_ZERO), + opnd_create_immed_int(VL, OPSZ_12b))); + + PRE(ilist, instr, + INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs), + opnd_create_reg(DR_REG_A0))); + } + + dstack_offs += XSP_SZ; + + /* + * The code below is contributed and copyrighted by FORTH + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + */ + if (proc_has_feature(FEATURE_VECTOR)) { + /* csrr a0, vtype */ + PRE(ilist, instr, + INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_ZERO), + opnd_create_immed_int(VTYPE, OPSZ_12b))); + + PRE(ilist, instr, + INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs), + opnd_create_reg(DR_REG_A0))); + } + + dstack_offs += 2*XSP_SZ; + /* + * End of FORTH copyrighted section + */ /* Push vector registers. */ if (proc_has_feature(FEATURE_VECTOR)) { @@ -309,6 +350,27 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist opnd_create_reg(DR_REG_SP), opnd_create_immed_int(DR_NUM_FPR_REGS * XSP_SZ, OPSZ_12b))); + current_offs -= 2*XSP_SZ; + + /* Uses c.[f]ldsp for some reason beyond my comprehension, same below. */ + if (proc_has_feature(FEATURE_VECTOR)) { + /* a0 = vl*/ + PRE(ilist, instr, + INSTR_CREATE_c_ldsp( + dcontext, opnd_create_reg(DR_REG_A0), + OPND_CREATE_MEM64(DR_REG_SP, current_offs - DR_NUM_FPR_REGS * XSP_SZ))); + /* a1 = vtype*/ + PRE(ilist, instr, + INSTR_CREATE_c_ldsp( + dcontext, opnd_create_reg(DR_REG_A1), + OPND_CREATE_MEM64(DR_REG_SP, current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ))); + /* vsetvl a0, a0, a1 */ + PRE(ilist, instr, + INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_A0), + opnd_create_reg(DR_REG_A1))); + } + /* Uses c.[f]ldsp to save space, same below. */ current_offs -= XSP_SZ; diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 19636fd8156..1ef01fed93d 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -42,7 +42,7 @@ START_FILE /* sizeof(priv_mcontext_t) rounded up to a multiple of 16 */ /* The reserved space for SIMD is also included. */ -#define PRIV_MCONTEXT_SIZE 0x620 +#define PRIV_MCONTEXT_SIZE 0x630 /* offset of priv_mcontext_t in dr_mcontext_t */ #define PRIV_MCONTEXT_OFFSET 16 @@ -52,7 +52,7 @@ START_FILE #endif /* offsetof(dcontext_t, dstack) */ -#define dstack_OFFSET 0x668 +#define dstack_OFFSET 0x678 /* offsetof(dcontext_t, is_exiting) */ #define is_exiting_OFFSET (dstack_OFFSET + 1 * ARG_SZ) diff --git a/core/lib/mcxtx_api.h b/core/lib/mcxtx_api.h index e112ca6cf1f..4174d2f5d28 100644 --- a/core/lib/mcxtx_api.h +++ b/core/lib/mcxtx_api.h @@ -566,6 +566,8 @@ reg_t fcsr; /**< Floating-Point Control Register. */ reg_t vstart; /**< Vector Start Index CSR. */ reg_t vcsr; /**< Vector Control and Status Register. */ + reg_t vl; + reg_t vtype; /** The Vector registers. */ dr_simd_t simd[MCXT_NUM_SIMD_SLOTS]; #else /* RISCV64 */ From 7bc9effbf9575aeb5eb5b86b7e3d925f741eb18f Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 15:06:33 +0200 Subject: [PATCH 2/9] Fixed identation Accidentally tabs were used somewhere, replaced with spaces --- core/arch/riscv64/emit_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index 656245e32bc..fe0d44c2183 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -674,7 +674,7 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute) INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1))); - /* + /* * End of FORTH copyrighted section */ } @@ -908,7 +908,7 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute opnd_create_reg(DR_REG_ZERO), opnd_create_immed_int(VTYPE, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); - /* + /* * End of FORTH copyrighted section */ } From 2410e00e06381bd1046b51a5dc3fafe5e8d7a2fe Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 15:11:12 +0200 Subject: [PATCH 3/9] Removed trailing spaces --- core/arch/riscv64/mangle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 8aea5328306..2ba8d625981 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -193,7 +193,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, } dstack_offs += XSP_SZ; - + /* * The code below is contributed and copyrighted by FORTH * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. From e219785e4f63a0adca812a6fdefcc253834e7937 Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 15:17:33 +0200 Subject: [PATCH 4/9] Split long lines of code in two --- core/arch/riscv64/emit_utils.c | 6 ++++-- core/arch/riscv64/mangle.c | 9 ++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index fe0d44c2183..c8c34dd38e2 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -666,7 +666,8 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute) /* * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. + * All other rights reserved. */ APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET)); APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); @@ -896,7 +897,8 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute /* * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. + * All other rights reserved. */ APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 2ba8d625981..63f6d6a952c 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -196,7 +196,8 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, /* * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. + * All other rights reserved. */ if (proc_has_feature(FEATURE_VECTOR)) { /* csrr a0, vl */ @@ -214,7 +215,8 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, /* * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. All other rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. + * All other rights reserved. */ if (proc_has_feature(FEATURE_VECTOR)) { /* csrr a0, vtype */ @@ -363,7 +365,8 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist PRE(ilist, instr, INSTR_CREATE_c_ldsp( dcontext, opnd_create_reg(DR_REG_A1), - OPND_CREATE_MEM64(DR_REG_SP, current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ))); + OPND_CREATE_MEM64(DR_REG_SP, + current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ))); /* vsetvl a0, a0, a1 */ PRE(ilist, instr, INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), From 870f65c83b1aef6381bcbda88577fc48f06645ba Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 15:26:49 +0200 Subject: [PATCH 5/9] Fixed formating --- core/arch/riscv64/emit_utils.c | 3 +-- core/arch/riscv64/mangle.c | 7 +++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index c8c34dd38e2..d3209457760 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -673,8 +673,7 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute) APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); APP(ilist, INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), - opnd_create_reg(DR_REG_A0), - opnd_create_reg(DR_REG_A1))); + opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1))); /* * End of FORTH copyrighted section */ diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 63f6d6a952c..c9eb97fcbc3 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -352,7 +352,7 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist opnd_create_reg(DR_REG_SP), opnd_create_immed_int(DR_NUM_FPR_REGS * XSP_SZ, OPSZ_12b))); - current_offs -= 2*XSP_SZ; + current_offs -= 2 * XSP_SZ; /* Uses c.[f]ldsp for some reason beyond my comprehension, same below. */ if (proc_has_feature(FEATURE_VECTOR)) { @@ -366,12 +366,11 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist INSTR_CREATE_c_ldsp( dcontext, opnd_create_reg(DR_REG_A1), OPND_CREATE_MEM64(DR_REG_SP, - current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ))); + current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ))); /* vsetvl a0, a0, a1 */ PRE(ilist, instr, INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), - opnd_create_reg(DR_REG_A0), - opnd_create_reg(DR_REG_A1))); + opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1))); } /* Uses c.[f]ldsp to save space, same below. */ From fbf3b8575e9d2bda8b05571164d7b7522a02407c Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Mon, 9 Dec 2024 15:28:55 +0200 Subject: [PATCH 6/9] More fixed formating --- core/arch/riscv64/mangle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index c9eb97fcbc3..a9c94d71554 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -230,7 +230,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, opnd_create_reg(DR_REG_A0))); } - dstack_offs += 2*XSP_SZ; + dstack_offs += 2 * XSP_SZ; /* * End of FORTH copyrighted section */ From c5fca47a984e79f9f8426e485485c54e51f37f13 Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Tue, 17 Dec 2024 14:31:22 +0200 Subject: [PATCH 7/9] i#3544 RV64: Preserve vtype and vl vector registers This patch was authored at the Computer Architecture and VLSI Laboratory, Institute of Computer Sciense, Foundation of Reasearch and Technology, Hellas. It emits the necessary instructions that handle saving and restoring the vl and vtype during the context switches, when using the vector extension of the RISC-V ISA. This is required, in order to use the vector extension correctly. Issue: #3544 --- core/arch/riscv64/emit_utils.c | 17 +---------------- core/arch/riscv64/mangle.c | 16 +--------------- core/lib/mcxtx_api.h | 4 ++-- 3 files changed, 4 insertions(+), 33 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index d3209457760..223446029f0 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -1,5 +1,6 @@ /* ********************************************************** * Copyright (c) 2022 Rivos, Inc. All rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. * **********************************************************/ /* @@ -664,19 +665,11 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute) opnd_create_reg(DR_REG_A0), opnd_create_immed_int(VCSR, OPSZ_12b))); - /* - * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. - * All other rights reserved. - */ APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET)); APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); APP(ilist, INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1))); - /* - * End of FORTH copyrighted section - */ } } @@ -894,11 +887,6 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute opnd_create_immed_int(VCSR, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VCSR_OFFSET)); - /* - * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. - * All other rights reserved. - */ APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_ZERO), @@ -909,9 +897,6 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute opnd_create_reg(DR_REG_ZERO), opnd_create_immed_int(VTYPE, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); - /* - * End of FORTH copyrighted section - */ } } diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index a9c94d71554..3fa898936a0 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -1,5 +1,6 @@ /* ********************************************************** * Copyright (c) 2022 Rivos, Inc. All rights reserved. + * Copyright (c) 2024 Foundation of Research and Technology, Hellas. * **********************************************************/ /* @@ -194,13 +195,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, dstack_offs += XSP_SZ; - /* - * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. - * All other rights reserved. - */ if (proc_has_feature(FEATURE_VECTOR)) { - /* csrr a0, vl */ PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), @@ -213,13 +208,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, dstack_offs += XSP_SZ; - /* - * The code below is contributed and copyrighted by FORTH - * Copyright (c) 2024 Foundation of Research and Technology, Hellas. - * All other rights reserved. - */ if (proc_has_feature(FEATURE_VECTOR)) { - /* csrr a0, vtype */ PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), @@ -231,9 +220,6 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, } dstack_offs += 2 * XSP_SZ; - /* - * End of FORTH copyrighted section - */ /* Push vector registers. */ if (proc_has_feature(FEATURE_VECTOR)) { diff --git a/core/lib/mcxtx_api.h b/core/lib/mcxtx_api.h index 4174d2f5d28..8682cab1b1b 100644 --- a/core/lib/mcxtx_api.h +++ b/core/lib/mcxtx_api.h @@ -566,8 +566,8 @@ reg_t fcsr; /**< Floating-Point Control Register. */ reg_t vstart; /**< Vector Start Index CSR. */ reg_t vcsr; /**< Vector Control and Status Register. */ - reg_t vl; - reg_t vtype; + reg_t vl; /**< Vector Length Register. */ + reg_t vtype; /**< Vector Type Register. */ /** The Vector registers. */ dr_simd_t simd[MCXT_NUM_SIMD_SLOTS]; #else /* RISCV64 */ From 549fb3d86dbac5fef4894bd0ba437a609c975338 Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Wed, 18 Dec 2024 07:59:20 +0200 Subject: [PATCH 8/9] i#3544 RV64: Preserve vtype and vl vector registers Fixxed issue about a comment Issue: #3544 --- core/arch/riscv64/mangle.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 3fa898936a0..bbebda34d5e 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -342,12 +342,10 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist /* Uses c.[f]ldsp for some reason beyond my comprehension, same below. */ if (proc_has_feature(FEATURE_VECTOR)) { - /* a0 = vl*/ PRE(ilist, instr, INSTR_CREATE_c_ldsp( dcontext, opnd_create_reg(DR_REG_A0), OPND_CREATE_MEM64(DR_REG_SP, current_offs - DR_NUM_FPR_REGS * XSP_SZ))); - /* a1 = vtype*/ PRE(ilist, instr, INSTR_CREATE_c_ldsp( dcontext, opnd_create_reg(DR_REG_A1), From 1a5e921a054949b403a498903560e93f51cd13fc Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Wed, 18 Dec 2024 18:38:54 +0200 Subject: [PATCH 9/9] i#3544 RV64: Preserve vtype and vl vector registers Renamed VL and VTYPE to CSR_VL and CSR_VTYPE Issue: #3544 --- core/arch/riscv64/emit_utils.c | 8 ++++---- core/arch/riscv64/mangle.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index 223446029f0..60d79ef65d2 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -55,8 +55,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F -#define VL 0xC20 -#define VTYPE 0xC21 +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 /* Instruction fixed bits constants. */ @@ -890,12 +890,12 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VL, OPSZ_12b))); + opnd_create_immed_int(CSR_VL, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET)); APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VTYPE, OPSZ_12b))); + opnd_create_immed_int(CSR_VTYPE, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); } } diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index bbebda34d5e..b7ce36e8472 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -46,8 +46,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F -#define VL 0xC20 -#define VTYPE 0xC21 +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 /* TODO i#3544: Think of a better way to represent these fields in the IR. */ /* Volume I: RISC-V Unprivileged ISA V20191213. @@ -199,7 +199,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VL, OPSZ_12b))); + opnd_create_immed_int(CSR_VL, OPSZ_12b))); PRE(ilist, instr, INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs), @@ -212,7 +212,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VTYPE, OPSZ_12b))); + opnd_create_immed_int(CSR_VTYPE, OPSZ_12b))); PRE(ilist, instr, INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),