i#7055: Migrate actions runner image from macOS 12 to macOS 13. (#7094)

The macOS 12 Actions runner image will begin deprecation on 10/7/24 and
will be fully unsupported by 12/3/24 for GitHub and ADO.

Please refer to actions/runner-images#10721
for details.

Updating the runner to macOS13 and DEVELOPER_DIR triggers
unused-but-set-variable warnings.
Changed code to address unused-but-set-variable warnings by moving code
under #ifdef, adding LOGs following CLIENT_ASSERT.

Fixes: #7055

.github/workflows/ci-osx.yml

@@ -1,5 +1,5 @@
 # **********************************************************
-# Copyright (c) 2020-2023 Google, Inc.  All rights reserved.
+# Copyright (c) 2020-2024 Google, Inc.  All rights reserved.
 # **********************************************************
 
 # Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,7 @@ defaults:
 jobs:
   # 64-bit OSX build with clang and run tests:
   osx-x86-64:
-    runs-on: macos-12
+    runs-on: macos-13
 
     steps:
     - uses: actions/checkout@v2
@@ -82,7 +82,7 @@ jobs:
         # https://github.community/t/selecting-an-xcode-version/16204/3
         # To find available versions, add the following as a step above:
         #  - run: ls -l /Applications
-        DEVELOPER_DIR: /Applications/Xcode_13.2.1.app/Contents/Developer
+        DEVELOPER_DIR: /Applications/Xcode_14.1.app/Contents/Developer
         CI_TRIGGER: ${{ github.event_name }}
         CI_BRANCH: ${{ github.ref }}
 

api/samples/instrace_x86.c

@@ -1,5 +1,5 @@
 /* ******************************************************************************
- * Copyright (c) 2011-2019 Google, Inc.  All rights reserved.
+ * Copyright (c) 2011-2024 Google, Inc.  All rights reserved.
  * Copyright (c) 2010 Massachusetts Institute of Technology  All rights reserved.
  * ******************************************************************************/
 
@@ -337,11 +337,8 @@ instrument_instr(void *drcontext, instrlist_t *ilist, instr_t *where)
     opnd_t opnd1, opnd2;
     reg_id_t reg1, reg2;
     drvector_t allowed;
-    per_thread_t *data;
     app_pc pc;
 
-    data = drmgr_get_tls_field(drcontext, tls_index);
-
     /* Steal two scratch registers.
      * reg2 must be ECX or RCX for jecxz.
      */
@@ -364,7 +361,6 @@ instrument_instr(void *drcontext, instrlist_t *ilist, instr_t *where)
      *    clean_call();
      */
     drmgr_insert_read_tls_field(drcontext, tls_index, ilist, where, reg2);
-    /* Load data->buf_ptr into reg2 */
     opnd1 = opnd_create_reg(reg2);
     opnd2 = OPND_CREATE_MEMPTR(reg2, offsetof(per_thread_t, buf_ptr));
     instr = INSTR_CREATE_mov_ld(drcontext, opnd1, opnd2);
@@ -392,7 +388,6 @@ instrument_instr(void *drcontext, instrlist_t *ilist, instr_t *where)
     instr = INSTR_CREATE_lea(drcontext, opnd1, opnd2);
     instrlist_meta_preinsert(ilist, where, instr);
 
-    /* Update the data->buf_ptr */
     drmgr_insert_read_tls_field(drcontext, tls_index, ilist, where, reg1);
     opnd1 = OPND_CREATE_MEMPTR(reg1, offsetof(per_thread_t, buf_ptr));
     opnd2 = opnd_create_reg(reg2);

api/samples/memtrace_x86.c

@@ -1,5 +1,5 @@
 /* ******************************************************************************
- * Copyright (c) 2011-2021 Google, Inc.  All rights reserved.
+ * Copyright (c) 2011-2024 Google, Inc.  All rights reserved.
  * Copyright (c) 2010 Massachusetts Institute of Technology  All rights reserved.
  * ******************************************************************************/
 
@@ -431,9 +431,6 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, app_pc pc,
     opnd_t ref, opnd1, opnd2;
     reg_id_t reg1, reg2;
     drvector_t allowed;
-    per_thread_t *data;
-
-    data = drmgr_get_tls_field(drcontext, tls_index);
 
     /* Steal two scratch registers.
      * reg2 must be ECX or RCX for jecxz.
@@ -467,7 +464,6 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, app_pc pc,
      *    clean_call();
      */
     drmgr_insert_read_tls_field(drcontext, tls_index, ilist, where, reg2);
-    /* Load data->buf_ptr into reg2 */
     opnd1 = opnd_create_reg(reg2);
     opnd2 = OPND_CREATE_MEMPTR(reg2, offsetof(per_thread_t, buf_ptr));
     instr = INSTR_CREATE_mov_ld(drcontext, opnd1, opnd2);
@@ -507,7 +503,6 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, app_pc pc,
     instr = INSTR_CREATE_lea(drcontext, opnd1, opnd2);
     instrlist_meta_preinsert(ilist, where, instr);
 
-    /* Update the data->buf_ptr */
     drmgr_insert_read_tls_field(drcontext, tls_index, ilist, where, reg1);
     opnd1 = OPND_CREATE_MEMPTR(reg1, offsetof(per_thread_t, buf_ptr));
     opnd2 = opnd_create_reg(reg2);

clients/drcachesim/common/utils.h

@@ -74,8 +74,10 @@ namespace drmemtrace {
 // XXX i#4399: DR should define a DEBUG-only assert.
 #ifdef DEBUG
 #    define ASSERT(x, msg) DR_ASSERT_MSG(x, msg)
+#    define IF_DEBUG(x) x
 #else
 #    define ASSERT(x, msg) /* Nothing. */
+#    define IF_DEBUG(x)    /* Nothing. */
 #endif
 
 #define BUFFER_SIZE_BYTES(buf) sizeof(buf)

clients/drcachesim/tests/core_sharded_test.cpp

@@ -1,5 +1,5 @@
 /* **********************************************************
- * Copyright (c) 2023 Google, Inc.  All rights reserved.
+ * Copyright (c) 2023-2024 Google, Inc.  All rights reserved.
  * **********************************************************/
 
 /*
@@ -62,9 +62,9 @@ run_analyzer(int argc, const char *args[])
     }
     analyzer_multi_t analyzer;
     assert(!!analyzer);
-    bool res = analyzer.run();
+    IF_DEBUG(bool res =) analyzer.run();
     assert(res);
-    res = analyzer.print_stats();
+    IF_DEBUG(res =) analyzer.print_stats();
     assert(res);
 
     std::cerr.rdbuf(prev_buf);

clients/drcachesim/tests/trace_interval_analysis_unit_tests.cpp

@@ -481,7 +481,7 @@ class test_analysis_tool_t : public analysis_tool_t {
     }
     bool
     finalize_interval_snapshots(
-        std::vector<interval_state_snapshot_t *> &interval_snapshots)
+        std::vector<interval_state_snapshot_t *> &interval_snapshots) override
     {
         for (auto snapshot : interval_snapshots) {
             if (snapshot == nullptr) {

core/arch/x86/mangle.c

@@ -1,5 +1,5 @@
 /* ******************************************************************************
- * Copyright (c) 2010-2023 Google, Inc.  All rights reserved.
+ * Copyright (c) 2010-2024 Google, Inc.  All rights reserved.
  * Copyright (c) 2010 Massachusetts Institute of Technology  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
  * ******************************************************************************/
@@ -1282,12 +1282,23 @@ mangle_direct_call(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
                    instr_t *next_instr, bool mangle_calls, uint flags)
 {
     ptr_uint_t retaddr;
-    app_pc target = NULL;
     opnd_t pushop = instr_get_dst(instr, 1);
     opnd_size_t pushsz = stack_entry_size(instr, opnd_get_size(pushop));
-    if (opnd_is_near_pc(instr_get_target(instr)))
+
+    if (!mangle_calls) {
+        /* off-trace call that will be executed natively */
+        /* relative target must be re-encoded */
+        instr_set_raw_bits_valid(instr, false);
+        return next_instr;
+    }
+
+    retaddr = get_call_return_address(dcontext, ilist, instr);
+
+#ifdef CHECK_RETURNS_SSE2
+    app_pc target = NULL;
+    if (opnd_is_near_pc(instr_get_target(instr))) {
         target = opnd_get_pc(instr_get_target(instr));
-    else if (opnd_is_instr(instr_get_target(instr))) {
+    } else if (opnd_is_instr(instr_get_target(instr))) {
         instr_t *tgt = opnd_get_instr(instr_get_target(instr));
         /* assumption: target's raw bits are meaningful */
         target = instr_get_raw_bits(tgt);
@@ -1300,16 +1311,6 @@ mangle_direct_call(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
     } else
         ASSERT_NOT_REACHED();
 
-    if (!mangle_calls) {
-        /* off-trace call that will be executed natively */
-        /* relative target must be re-encoded */
-        instr_set_raw_bits_valid(instr, false);
-        return next_instr;
-    }
-
-    retaddr = get_call_return_address(dcontext, ilist, instr);
-
-#ifdef CHECK_RETURNS_SSE2
     /* ASSUMPTION: a call to the next instr is not going to ever have a
      * matching ret! */
     if (target == (app_pc)retaddr) {
@@ -2633,7 +2634,7 @@ mangle_rel_addr(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
 {
     uint opc = instr_get_opcode(instr);
     app_pc tgt;
-    opnd_t dst, src;
+    opnd_t dst;
     ASSERT(instr_has_rel_addr_reference(instr));
     instr_get_rel_addr_target(instr, &tgt);
     STATS_INC(rip_rel_instrs);
@@ -2650,10 +2651,9 @@ mangle_rel_addr(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
             /* segment overrides are ignored on lea */
             opnd_t immed;
             dst = instr_get_dst(instr, 0);
-            src = instr_get_src(instr, 0);
             ASSERT(opnd_is_reg(dst));
-            ASSERT(opnd_is_rel_addr(src));
-            ASSERT(opnd_get_addr(src) == tgt);
+            ASSERT(opnd_is_rel_addr(instr_get_src(instr, 0)));
+            ASSERT(opnd_get_addr(instr_get_src(instr, 0)) == tgt);
             /* Replace w/ an absolute immed of the target app address, following Intel
              * Table 3-59 "64-bit Mode LEA Operation with Address and Operand Size
              * Attributes" */
@@ -3914,7 +3914,6 @@ set_selfmod_sandbox_offsets(dcontext_t *dcontext)
     instrlist_t ilist;
     patch_list_t patch;
     static byte buf[256];
-    uint len;
     /* We assume this is called at init, when .data is +w and we need no
      * synch on accessing buf */
     ASSERT(!dynamo_initialized);
@@ -3945,7 +3944,8 @@ set_selfmod_sandbox_offsets(dcontext_t *dcontext)
                         instr_set_target(inst, opnd_create_pc(buf));
                     }
                 }
-                len = encode_with_patch_list(dcontext, &patch, &ilist, buf);
+                IF_DEBUG(uint len =)
+                encode_with_patch_list(dcontext, &patch, &ilist, buf);
                 ASSERT(len < BUFFER_SIZE_BYTES(buf));
                 IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_uint(start_pc - buf)));
                 selfmod_copy_start_offs[i][j] IF_X64([k]) = (uint)(start_pc - buf);

core/arch/x86_code.c

@@ -336,7 +336,6 @@ new_bsdthread_setup(priv_mcontext_t *mc)
 {
     dcontext_t *dcontext;
     void *crec, *func_arg;
-    int rc;
     /* this is where a new thread first touches other than the dstack,
      * so we "enter" DR here
      */
@@ -348,7 +347,7 @@ new_bsdthread_setup(priv_mcontext_t *mc)
         "new_thread_setup: thread " TIDFMT ", dstack " PFX " clone record " PFX "\n",
         d_r_get_thread_id(), get_clone_record_dstack(crec), crec);
 
-    rc = dynamo_thread_init(get_clone_record_dstack(crec), mc, crec, false);
+    IF_DEBUG(int rc =) dynamo_thread_init(get_clone_record_dstack(crec), mc, crec, false);
     ASSERT(rc != -1); /* this better be a new thread */
     dcontext = get_thread_private_dcontext();
     ASSERT(dcontext != NULL);

core/ir/instr_shared.c

@@ -87,17 +87,17 @@
 instr_t *
 instr_create(void *drcontext)
 {
-    bool is_instr_isa_mode_set = false;
     dcontext_t *dcontext = (dcontext_t *)drcontext;
     instr_t *instr = (instr_t *)heap_alloc(dcontext, sizeof(instr_t) HEAPACCT(ACCT_IR));
     /* everything initializes to 0, even flags, to indicate
      * an uninitialized instruction */
     memset((void *)instr, 0, sizeof(instr_t));
 #if defined(X86) && defined(X64)
-    is_instr_isa_mode_set = instr_set_isa_mode(
-        instr, X64_CACHE_MODE_DC(dcontext) ? DR_ISA_AMD64 : DR_ISA_IA32);
+    IF_DEBUG(bool is_instr_isa_mode_set =)
+    instr_set_isa_mode(instr, X64_CACHE_MODE_DC(dcontext) ? DR_ISA_AMD64 : DR_ISA_IA32);
 #else
-    is_instr_isa_mode_set = instr_set_isa_mode(instr, dr_get_isa_mode(dcontext));
+    IF_DEBUG(bool is_instr_isa_mode_set =)
+    instr_set_isa_mode(instr, dr_get_isa_mode(dcontext));
 #endif
     CLIENT_ASSERT(is_instr_isa_mode_set, "setting instruction ISA mode unsuccessful");
     return instr;

core/ir/x86/decode.c

@@ -1,5 +1,5 @@
 /* **********************************************************
- * Copyright (c) 2011-2023 Google, Inc.  All rights reserved.
+ * Copyright (c) 2011-2024 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
  * **********************************************************/
 
@@ -791,10 +791,9 @@ static byte *
 read_evex(byte *pc, decode_info_t *di, byte instr_byte,
           const instr_info_t **ret_info DR_PARAM_INOUT, bool *is_evex)
 {
-    const instr_info_t *info;
     byte prefix_byte = 0, evex_pp = 0;
     ASSERT(ret_info != NULL && *ret_info != NULL && is_evex != NULL);
-    info = *ret_info;
+    IF_DEBUG(const instr_info_t *info = *ret_info);
 
     CLIENT_ASSERT(info->type == EVEX_PREFIX_EXT, "internal evex decoding error");
     /* If 32-bit mode and mod selects for memory, this is not evex */
@@ -805,7 +804,7 @@ read_evex(byte *pc, decode_info_t *di, byte instr_byte,
             return pc;
         }
         *is_evex = true;
-        info = &evex_prefix_extensions[0][1];
+        IF_DEBUG(info = &evex_prefix_extensions[0][1];)
     } else {
         /* not evex */
         *is_evex = false;