diff --git a/api/docs/release.dox b/api/docs/release.dox index b5a8d48961b..b2bda4aa551 100644 --- a/api/docs/release.dox +++ b/api/docs/release.dox @@ -161,6 +161,8 @@ changes: signature between AArch64 and RISC-V. - Renamed dr_get_sve_vector_length() to dr_get_vector_length() to share function signature between AArch64 and RISC-V. + - Changed the drcachesim -LL_miss_file option by adding a process ID field to the output. + This helps in better analyzing cache misses in multi-process environments. Further non-compatibility-affecting changes include: - Added DWARF-5 support to the drsyms library by linking in 4 static libraries diff --git a/clients/drcachesim/common/options.cpp b/clients/drcachesim/common/options.cpp index d13bab39233..64512728973 100644 --- a/clients/drcachesim/common/options.cpp +++ b/clients/drcachesim/common/options.cpp @@ -208,11 +208,11 @@ droption_t op_LL_miss_file( "Path for dumping LLC misses or prefetching hints", "If non-empty, when running the cache simulator, requests that " "every last-level cache miss be written to a file at the specified path. Each miss " - "is written in text format as a pair. If this tool is " - "linked with zlib, the file is written in gzip-compressed format. If non-empty, when " - "running the cache miss analyzer, requests that prefetching hints based on the miss " - "analysis be written to the specified file. Each hint is written in text format as a " - " tuple."); + "is written in text format as a tuple. If " + "this tool is linked with zlib, the file is written in gzip-compressed format. If " + "non-empty, when running the cache miss analyzer, requests that prefetching hints " + "based on the miss analysis be written to the specified file. Each hint is written " + "in text format as a tuple."); droption_t op_L0_filter_deprecated( DROPTION_SCOPE_CLIENT, "L0_filter", false, diff --git a/clients/drcachesim/simulator/cache_miss_analyzer.cpp b/clients/drcachesim/simulator/cache_miss_analyzer.cpp index 8228c7c0c31..83d68095ec2 100644 --- a/clients/drcachesim/simulator/cache_miss_analyzer.cpp +++ b/clients/drcachesim/simulator/cache_miss_analyzer.cpp @@ -83,6 +83,8 @@ cache_miss_stats_t::dump_miss(const memref_t &memref) return; } + // TODO i#6905: Consider incorporating PID information into the pc_cache_misses_ hash + // map and adjusting subsequent calculations that depend on this data. const addr_t pc = memref.data.pc; const addr_t addr = memref.data.addr / kLineSize; pc_cache_misses_[pc].push_back(addr); diff --git a/clients/drcachesim/simulator/caching_device_stats.cpp b/clients/drcachesim/simulator/caching_device_stats.cpp index 6feea91762a..81bf1150c3b 100644 --- a/clients/drcachesim/simulator/caching_device_stats.cpp +++ b/clients/drcachesim/simulator/caching_device_stats.cpp @@ -154,6 +154,7 @@ void caching_device_stats_t::dump_miss(const memref_t &memref) { addr_t pc, addr; + memref_pid_t pid; if (type_is_instr(memref.instr.type)) pc = memref.instr.addr; else { // data ref: others shouldn't get here @@ -163,10 +164,15 @@ caching_device_stats_t::dump_miss(const memref_t &memref) pc = memref.data.pc; } addr = memref.data.addr; + pid = memref.data.pid; + + // XXX: This writing method to the same file from multiple processes is racy. + // It works most of the time but consider using a directory with individual files + // per process as a future safer alternative. #ifdef HAS_ZLIB - gzprintf(file_, "0x%zx,0x%zx\n", pc, addr); + gzprintf(file_, "%lld,0x%zx,0x%zx\n", pid, pc, addr); #else - fprintf(file_, "0x%zx,0x%zx\n", pc, addr); + fprintf(file_, "%lld,0x%zx,0x%zx\n", pid, pc, addr); #endif }