Degate with dieshot only? #28
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All I have is a single high-resolution die-shot of an NMOS (~1980) chip I would like to work on reverse engineering. I can't quite figure out if I can use Degate for this, or if I have to start with something like Inkscape to trace-out layers first? |
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If it's a "standard"/common image format, and there is only one layer of the die in the image, you should be able to import it directly into Degate. And, if you have other images of different layers, you'll also be able to import them (if they are pre-aligned, if it's not the case you'll have to align them in another software, many are available on Github). After importing, you'll be able to identify gates in your die shot, trace wires and obtain VHDL/Verilog from that. An imperfect matching algorithm is also available to help you identify pre-analyzed gates if there are multiple instances of them. The documentation should be helpful: https://degate.readthedocs.io/en/latest/index.html. Also, if you have any issue/question, don't hesitate, and good luck. |
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Example of what I know to be 1-bit of a loadable counter, data-bus bit input on the far right, output bit on the far left. I'm just not sure if it is possible to reverse the actual transistors from this single image? The image is a 305MB jpeg, about 20K x 20K pixels (https://ftp.whtech.com/images/dieshots/9918_700x.jpg). The chip is VLSI NMOS. I did load it into degate and messed around a little, looked through the docs, etc. but I guess it was not clicking in my brain. I was not sure if the software requires each layer to already separated (which I don't have). I'll have another go at it. Thanks for the reply. |
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If it's a "standard"/common image format, and there is only one layer of the die in the image, you should be able to import it directly into Degate. And, if you have other images of different layers, you'll also be able to import them (if they are pre-aligned, if it's not the case you'll have to align them in another software, many are available on Github). After importing, you'll be able to identify gates in your die shot, trace wires and obtain VHDL/Verilog from that. An imperfect matching algorithm is also available to help you identify pre-analyzed gates if there are multiple instances of them.
The documentation should be helpful: https://degate.readthedocs.io/en/latest/index.html.
Al…