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culsans_xilinx.sv
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culsans_xilinx.sv
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright 2022 PlanV GmbH
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Xilinx FPGA top-level
module culsans_xilinx (
`ifdef GENESYSII
input logic sys_clk_p ,
input logic sys_clk_n ,
input logic cpu_resetn ,
inout wire [31:0] ddr3_dq ,
inout wire [ 3:0] ddr3_dqs_n ,
inout wire [ 3:0] ddr3_dqs_p ,
output logic [14:0] ddr3_addr ,
output logic [ 2:0] ddr3_ba ,
output logic ddr3_ras_n ,
output logic ddr3_cas_n ,
output logic ddr3_we_n ,
output logic ddr3_reset_n,
output logic [ 0:0] ddr3_ck_p ,
output logic [ 0:0] ddr3_ck_n ,
output logic [ 0:0] ddr3_cke ,
output logic [ 0:0] ddr3_cs_n ,
output logic [ 3:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
output wire eth_rst_n ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_txck ,
output wire eth_txctl ,
output wire [3:0] eth_txd ,
inout wire eth_mdio ,
output logic eth_mdc ,
output logic [ 7:0] led ,
input logic [ 7:0] sw ,
output logic fan_pwm ,
input logic trst_n ,
`elsif KC705
input logic sys_clk_p ,
input logic sys_clk_n ,
input logic cpu_reset ,
inout logic [63:0] ddr3_dq ,
inout logic [ 7:0] ddr3_dqs_n ,
inout logic [ 7:0] ddr3_dqs_p ,
output logic [13:0] ddr3_addr ,
output logic [ 2:0] ddr3_ba ,
output logic ddr3_ras_n ,
output logic ddr3_cas_n ,
output logic ddr3_we_n ,
output logic ddr3_reset_n,
output logic [ 0:0] ddr3_ck_p ,
output logic [ 0:0] ddr3_ck_n ,
output logic [ 0:0] ddr3_cke ,
output logic [ 0:0] ddr3_cs_n ,
output logic [ 7:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
output wire eth_rst_n ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_txck ,
output wire eth_txctl ,
output wire [3:0] eth_txd ,
inout wire eth_mdio ,
output logic eth_mdc ,
output logic [ 3:0] led ,
input logic [ 3:0] sw ,
output logic fan_pwm ,
input logic trst_n ,
`elsif VC707
input logic sys_clk_p ,
input logic sys_clk_n ,
input logic cpu_reset ,
inout wire [63:0] ddr3_dq ,
inout wire [ 7:0] ddr3_dqs_n ,
inout wire [ 7:0] ddr3_dqs_p ,
output logic [13:0] ddr3_addr ,
output logic [ 2:0] ddr3_ba ,
output logic ddr3_ras_n ,
output logic ddr3_cas_n ,
output logic ddr3_we_n ,
output logic ddr3_reset_n,
output logic [ 0:0] ddr3_ck_p ,
output logic [ 0:0] ddr3_ck_n ,
output logic [ 0:0] ddr3_cke ,
output logic [ 0:0] ddr3_cs_n ,
output logic [ 7:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
output wire eth_rst_n ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_txck ,
output wire eth_txctl ,
output wire [3:0] eth_txd ,
inout wire eth_mdio ,
output logic eth_mdc ,
output logic [ 7:0] led ,
input logic [ 7:0] sw ,
output logic fan_pwm ,
input logic trst ,
`elsif VCU118
input wire c0_sys_clk_p , // 250 MHz Clock for DDR
input wire c0_sys_clk_n , // 250 MHz Clock for DDR
input wire sys_clk_p , // 100 MHz Clock for PCIe
input wire sys_clk_n , // 100 MHz Clock for PCIE
input wire sys_rst_n , // PCIe Reset
input logic cpu_reset , // CPU subsystem reset
output wire [16:0] c0_ddr4_adr ,
output wire [1:0] c0_ddr4_ba ,
output wire [0:0] c0_ddr4_cke ,
output wire [0:0] c0_ddr4_cs_n ,
inout wire [7:0] c0_ddr4_dm_dbi_n,
inout wire [63:0] c0_ddr4_dq ,
inout wire [7:0] c0_ddr4_dqs_c ,
inout wire [7:0] c0_ddr4_dqs_t ,
output wire [0:0] c0_ddr4_odt ,
output wire [0:0] c0_ddr4_bg ,
output wire c0_ddr4_reset_n ,
output wire c0_ddr4_act_n ,
output wire [0:0] c0_ddr4_ck_c ,
output wire [0:0] c0_ddr4_ck_t ,
output wire [7:0] pci_exp_txp ,
output wire [7:0] pci_exp_txn ,
input wire [7:0] pci_exp_rxp ,
input wire [7:0] pci_exp_rxn ,
input logic trst_n ,
`endif
// SPI
output logic spi_mosi ,
input logic spi_miso ,
output logic spi_ss ,
output logic spi_clk_o ,
// common part
// input logic trst_n ,
input logic tck ,
input logic tms ,
input logic tdi ,
output wire tdo ,
input logic rx ,
output logic tx
);
// 24 MByte in 8 byte words
localparam NumWords = (24 * 1024 * 1024) / 8;
localparam NBSlave = 2; // debug, CCU_to_xbar
localparam AxiAddrWidth = 64;
localparam AxiDataWidth = 64;
localparam AxiIdWidthSlaves = culsans_pkg::IdWidthToXbar + $clog2(NBSlave);
localparam AxiUserWidth = ariane_pkg::AXI_USER_WIDTH;
`AXI_TYPEDEF_ALL(axi_slave,
logic [ AxiAddrWidth-1:0],
logic [AxiIdWidthSlaves-1:0],
logic [ AxiDataWidth-1:0],
logic [(AxiDataWidth/8)-1:0],
logic [ AxiUserWidth-1:0])
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( culsans_pkg::IdWidthToXbar ),
.AXI_USER_WIDTH ( AxiUserWidth )
) to_xbar[NBSlave-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master[ariane_soc::NB_PERIPHERALS-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( riscv::XLEN ),
.AXI_DATA_WIDTH ( riscv::XLEN ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_to_dm[0:0]();
// disable test-enable
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic [culsans_pkg::NB_CORES-1:0] debug_req_irq;
logic [culsans_pkg::NB_CORES-1:0] ipi;
logic [culsans_pkg::NB_CORES-1:0] timer_irq;
logic clk;
logic eth_clk;
logic spi_clk_i;
logic phy_tx_clk;
logic sd_clk_sys;
logic ddr_sync_reset;
logic ddr_clock_out;
logic rst_n, rst;
logic rtc;
// we need to switch reset polarity
`ifdef VCU118
logic cpu_resetn;
assign cpu_resetn = ~cpu_reset;
`elsif GENESYSII
logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
`elsif KC705
assign cpu_resetn = ~cpu_reset;
`elsif VC707
assign cpu_resetn = ~cpu_reset;
assign trst_n = ~trst;
`endif
logic pll_locked;
// ROM
logic rom_req;
logic [AxiAddrWidth-1:0] rom_addr;
logic [AxiDataWidth-1:0] rom_rdata;
// Debug
logic debug_req_valid;
logic debug_req_ready;
dm::dmi_req_t debug_req;
logic debug_resp_valid;
logic debug_resp_ready;
dm::dmi_resp_t debug_resp;
logic dmactive;
// IRQ
logic [culsans_pkg::NumTargets-1:0] irq;
assign test_en = 1'b0;
logic [NBSlave-1:0] pc_asserted;
rstgen i_rstgen_main (
.clk_i ( clk ),
.rst_ni ( pll_locked & (~ndmreset) ),
.test_mode_i ( test_en ),
.rst_no ( ndmreset_n ),
.init_no ( ) // keep open
);
assign rst_n = ~ddr_sync_reset;
assign rst = ddr_sync_reset;
// ---------------
// AXI Xbar
// ---------------
axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map;
assign addr_map = '{
'{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength },
'{ idx: ariane_soc::ROM, start_addr: ariane_soc::ROMBase, end_addr: ariane_soc::ROMBase + ariane_soc::ROMLength },
'{ idx: ariane_soc::CLINT, start_addr: ariane_soc::CLINTBase, end_addr: ariane_soc::CLINTBase + ariane_soc::CLINTLength },
'{ idx: ariane_soc::PLIC, start_addr: ariane_soc::PLICBase, end_addr: ariane_soc::PLICBase + ariane_soc::PLICLength },
'{ idx: ariane_soc::UART, start_addr: ariane_soc::UARTBase, end_addr: ariane_soc::UARTBase + ariane_soc::UARTLength },
'{ idx: ariane_soc::Timer, start_addr: ariane_soc::TimerBase, end_addr: ariane_soc::TimerBase + ariane_soc::TimerLength },
'{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength },
'{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength },
'{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength },
'{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength }
};
localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
NoSlvPorts: NBSlave,
NoMstPorts: ariane_soc::NB_PERIPHERALS,
MaxMstTrans: 1, // Probably requires update
MaxSlvTrans: 1, // Probably requires update
FallThrough: 1'b0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: culsans_pkg::IdWidthToXbar,
AxiIdUsedSlvPorts: culsans_pkg::IdWidthToXbar,
UniqueIds: 1'b0,
AxiAddrWidth: AxiAddrWidth,
AxiDataWidth: AxiDataWidth,
NoAddrRules: ariane_soc::NB_PERIPHERALS
};
axi_xbar_intf #(
.AXI_USER_WIDTH ( AxiUserWidth ),
.Cfg ( AXI_XBAR_CFG ),
.rule_t ( axi_pkg::xbar_rule_64_t )
) i_axi_xbar (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.test_i ( test_en ),
.slv_ports ( to_xbar ),
.mst_ports ( master ),
.addr_map_i ( addr_map ),
.en_default_mst_port_i ( '0 ),
.default_mst_port_i ( '0 )
);
// ---------------
// Debug Module
// ---------------
dmi_jtag i_dmi_jtag (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.dmi_rst_no ( ), // keep open
.testmode_i ( test_en ),
.dmi_req_valid_o ( debug_req_valid ),
.dmi_req_ready_i ( debug_req_ready ),
.dmi_req_o ( debug_req ),
.dmi_resp_valid_i ( debug_resp_valid ),
.dmi_resp_ready_o ( debug_resp_ready ),
.dmi_resp_i ( debug_resp ),
.tck_i ( tck ),
.tms_i ( tms ),
.trst_ni ( trst_n ),
.td_i ( tdi ),
.td_o ( tdo ),
.tdo_oe_o ( )
);
ariane_axi::req_t dm_axi_m_req;
ariane_axi::resp_t dm_axi_m_resp;
logic dm_slave_req;
logic dm_slave_we;
logic [riscv::XLEN-1:0] dm_slave_addr;
logic [riscv::XLEN/8-1:0] dm_slave_be;
logic [riscv::XLEN-1:0] dm_slave_wdata;
logic [riscv::XLEN-1:0] dm_slave_rdata;
logic dm_master_req;
logic [riscv::XLEN-1:0] dm_master_add;
logic dm_master_we;
logic [riscv::XLEN-1:0] dm_master_wdata;
logic [riscv::XLEN/8-1:0] dm_master_be;
logic dm_master_gnt;
logic dm_master_r_valid;
logic [riscv::XLEN-1:0] dm_master_r_rdata;
// debug module
dm_top #(
.NrHarts ( culsans_pkg::NB_CORES ),
.BusWidth ( riscv::XLEN )
) i_dm_top (
.clk_i ( clk ),
.rst_ni ( rst_n ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( dmactive ), // active debug session
.debug_req_o ( debug_req_irq ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
.slave_be_i ( dm_slave_be ),
.slave_wdata_i ( dm_slave_wdata ),
.slave_rdata_o ( dm_slave_rdata ),
.master_req_o ( dm_master_req ),
.master_add_o ( dm_master_add ),
.master_we_o ( dm_master_we ),
.master_wdata_o ( dm_master_wdata ),
.master_be_o ( dm_master_be ),
.master_gnt_i ( dm_master_gnt ),
.master_r_valid_i ( dm_master_r_valid ),
.master_r_rdata_i ( dm_master_r_rdata ),
.dmi_rst_ni ( rst_n ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
);
axi2mem #(
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_ADDR_WIDTH ( riscv::XLEN ),
.AXI_DATA_WIDTH ( riscv::XLEN ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_dm_axi2mem (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.slave ( master_to_dm[0] ),
.req_o ( dm_slave_req ),
.we_o ( dm_slave_we ),
.addr_o ( dm_slave_addr ),
.be_o ( dm_slave_be ),
.data_o ( dm_slave_wdata ),
.data_i ( dm_slave_rdata )
);
if (riscv::XLEN==32 ) begin
assign master_to_dm[0].aw_user = '0;
assign master_to_dm[0].w_user = '0;
assign master_to_dm[0].ar_user = '0;
assign master_to_dm[0].aw_id = dm_axi_m_req.aw.id;
assign master_to_dm[0].ar_id = dm_axi_m_req.ar.id;
assign master[ariane_soc::Debug].r_user ='0;
assign master[ariane_soc::Debug].b_user ='0;
xlnx_axi_dwidth_converter_dm_slave i_axi_dwidth_converter_dm_slave(
.s_axi_aclk(clk),
.s_axi_aresetn(ndmreset_n),
.s_axi_awid(master[ariane_soc::Debug].aw_id),
.s_axi_awaddr(master[ariane_soc::Debug].aw_addr[31:0]),
.s_axi_awlen(master[ariane_soc::Debug].aw_len),
.s_axi_awsize(master[ariane_soc::Debug].aw_size),
.s_axi_awburst(master[ariane_soc::Debug].aw_burst),
.s_axi_awlock(master[ariane_soc::Debug].aw_lock),
.s_axi_awcache(master[ariane_soc::Debug].aw_cache),
.s_axi_awprot(master[ariane_soc::Debug].aw_prot),
.s_axi_awregion(master[ariane_soc::Debug].aw_region),
.s_axi_awqos(master[ariane_soc::Debug].aw_qos),
.s_axi_awvalid(master[ariane_soc::Debug].aw_valid),
.s_axi_awready(master[ariane_soc::Debug].aw_ready),
.s_axi_wdata(master[ariane_soc::Debug].w_data),
.s_axi_wstrb(master[ariane_soc::Debug].w_strb),
.s_axi_wlast(master[ariane_soc::Debug].w_last),
.s_axi_wvalid(master[ariane_soc::Debug].w_valid),
.s_axi_wready(master[ariane_soc::Debug].w_ready),
.s_axi_bid(master[ariane_soc::Debug].b_id),
.s_axi_bresp(master[ariane_soc::Debug].b_resp),
.s_axi_bvalid(master[ariane_soc::Debug].b_valid),
.s_axi_bready(master[ariane_soc::Debug].b_ready),
.s_axi_arid(master[ariane_soc::Debug].ar_id),
.s_axi_araddr(master[ariane_soc::Debug].ar_addr[31:0]),
.s_axi_arlen(master[ariane_soc::Debug].ar_len),
.s_axi_arsize(master[ariane_soc::Debug].ar_size),
.s_axi_arburst(master[ariane_soc::Debug].ar_burst),
.s_axi_arlock(master[ariane_soc::Debug].ar_lock),
.s_axi_arcache(master[ariane_soc::Debug].ar_cache),
.s_axi_arprot(master[ariane_soc::Debug].ar_prot),
.s_axi_arregion(master[ariane_soc::Debug].ar_region),
.s_axi_arqos(master[ariane_soc::Debug].ar_qos),
.s_axi_arvalid(master[ariane_soc::Debug].ar_valid),
.s_axi_arready(master[ariane_soc::Debug].ar_ready),
.s_axi_rid(master[ariane_soc::Debug].r_id),
.s_axi_rdata(master[ariane_soc::Debug].r_data),
.s_axi_rresp(master[ariane_soc::Debug].r_resp),
.s_axi_rlast(master[ariane_soc::Debug].r_last),
.s_axi_rvalid(master[ariane_soc::Debug].r_valid),
.s_axi_rready(master[ariane_soc::Debug].r_ready),
.m_axi_awaddr(master_to_dm[0].aw_addr),
.m_axi_awlen(master_to_dm[0].aw_len),
.m_axi_awsize(master_to_dm[0].aw_size),
.m_axi_awburst(master_to_dm[0].aw_burst),
.m_axi_awlock(master_to_dm[0].aw_lock),
.m_axi_awcache(master_to_dm[0].aw_cache),
.m_axi_awprot(master_to_dm[0].aw_prot),
.m_axi_awregion(master_to_dm[0].aw_region),
.m_axi_awqos(master_to_dm[0].aw_qos),
.m_axi_awvalid(master_to_dm[0].aw_valid),
.m_axi_awready(master_to_dm[0].aw_ready),
.m_axi_wdata(master_to_dm[0].w_data ),
.m_axi_wstrb(master_to_dm[0].w_strb),
.m_axi_wlast(master_to_dm[0].w_last),
.m_axi_wvalid(master_to_dm[0].w_valid),
.m_axi_wready(master_to_dm[0].w_ready),
.m_axi_bresp(master_to_dm[0].b_resp),
.m_axi_bvalid(master_to_dm[0].b_valid),
.m_axi_bready(master_to_dm[0].b_ready),
.m_axi_araddr(master_to_dm[0].ar_addr),
.m_axi_arlen(master_to_dm[0].ar_len),
.m_axi_arsize(master_to_dm[0].ar_size),
.m_axi_arburst(master_to_dm[0].ar_burst),
.m_axi_arlock(master_to_dm[0].ar_lock),
.m_axi_arcache(master_to_dm[0].ar_cache),
.m_axi_arprot(master_to_dm[0].ar_prot),
.m_axi_arregion(master_to_dm[0].ar_region),
.m_axi_arqos(master_to_dm[0].ar_qos),
.m_axi_arvalid(master_to_dm[0].ar_valid),
.m_axi_arready(master_to_dm[0].ar_ready),
.m_axi_rdata(master_to_dm[0].r_data),
.m_axi_rresp(master_to_dm[0].r_resp),
.m_axi_rlast(master_to_dm[0].r_last),
.m_axi_rvalid(master_to_dm[0].r_valid),
.m_axi_rready(master_to_dm[0].r_ready)
);
end else begin
assign master[ariane_soc::Debug].aw_id = master_to_dm[0].aw_id;
assign master[ariane_soc::Debug].aw_addr = master_to_dm[0].aw_addr;
assign master[ariane_soc::Debug].aw_len = master_to_dm[0].aw_len;
assign master[ariane_soc::Debug].aw_size = master_to_dm[0].aw_size;
assign master[ariane_soc::Debug].aw_burst = master_to_dm[0].aw_burst;
assign master[ariane_soc::Debug].aw_lock = master_to_dm[0].aw_lock;
assign master[ariane_soc::Debug].aw_cache = master_to_dm[0].aw_cache;
assign master[ariane_soc::Debug].aw_prot = master_to_dm[0].aw_prot;
assign master[ariane_soc::Debug].aw_qos = master_to_dm[0].aw_qos;
assign master[ariane_soc::Debug].aw_atop = master_to_dm[0].aw_atop;
assign master[ariane_soc::Debug].aw_region = master_to_dm[0].aw_region;
assign master[ariane_soc::Debug].aw_user = master_to_dm[0].aw_user;
assign master[ariane_soc::Debug].aw_valid = master_to_dm[0].aw_valid;
assign master_to_dm[0].aw_ready =master[ariane_soc::Debug].aw_ready;
assign master[ariane_soc::Debug].w_data = master_to_dm[0].w_data;
assign master[ariane_soc::Debug].w_strb = master_to_dm[0].w_strb;
assign master[ariane_soc::Debug].w_last = master_to_dm[0].w_last;
assign master[ariane_soc::Debug].w_user = master_to_dm[0].w_user;
assign master[ariane_soc::Debug].w_valid = master_to_dm[0].w_valid;
assign master_to_dm[0].w_ready =master[ariane_soc::Debug].w_ready;
assign master_to_dm[0].b_id =master[ariane_soc::Debug].b_id;
assign master_to_dm[0].b_resp =master[ariane_soc::Debug].b_resp;
assign master_to_dm[0].b_user =master[ariane_soc::Debug].b_user;
assign master_to_dm[0].b_valid =master[ariane_soc::Debug].b_valid;
assign master[ariane_soc::Debug].b_ready = master_to_dm[0].b_ready;
assign master[ariane_soc::Debug].ar_id = master_to_dm[0].ar_id;
assign master[ariane_soc::Debug].ar_addr = master_to_dm[0].ar_addr;
assign master[ariane_soc::Debug].ar_len = master_to_dm[0].ar_len;
assign master[ariane_soc::Debug].ar_size = master_to_dm[0].ar_size;
assign master[ariane_soc::Debug].ar_burst = master_to_dm[0].ar_burst;
assign master[ariane_soc::Debug].ar_lock = master_to_dm[0].ar_lock;
assign master[ariane_soc::Debug].ar_cache = master_to_dm[0].ar_cache;
assign master[ariane_soc::Debug].ar_prot = master_to_dm[0].ar_prot;
assign master[ariane_soc::Debug].ar_qos = master_to_dm[0].ar_qos;
assign master[ariane_soc::Debug].ar_region = master_to_dm[0].ar_region;
assign master[ariane_soc::Debug].ar_user = master_to_dm[0].ar_user;
assign master[ariane_soc::Debug].ar_valid = master_to_dm[0].ar_valid;
assign master_to_dm[0].ar_ready =master[ariane_soc::Debug].ar_ready;
assign master_to_dm[0].r_id =master[ariane_soc::Debug].r_id;
assign master_to_dm[0].r_data =master[ariane_soc::Debug].r_data;
assign master_to_dm[0].r_resp =master[ariane_soc::Debug].r_resp;
assign master_to_dm[0].r_last =master[ariane_soc::Debug].r_last;
assign master_to_dm[0].r_user =master[ariane_soc::Debug].r_user;
assign master_to_dm[0].r_valid =master[ariane_soc::Debug].r_valid;
assign master[ariane_soc::Debug].r_ready = master_to_dm[0].r_ready;
end
logic [1:0] axi_adapter_size;
assign axi_adapter_size = (riscv::XLEN == 64) ? 2'b11 : 2'b10;
axi_adapter #(
.DATA_WIDTH ( riscv::XLEN ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( culsans_pkg::IdWidth ),
.axi_req_t ( ariane_axi::req_t ),
.axi_rsp_t ( ariane_axi::resp_t )
) i_dm_axi_master (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.req_i ( dm_master_req ),
.type_i ( ariane_axi::SINGLE_REQ ),
.amo_i ( ariane_pkg::AMO_NONE ),
.gnt_o ( dm_master_gnt ),
.addr_i ( dm_master_add ),
.we_i ( dm_master_we ),
.wdata_i ( dm_master_wdata ),
.be_i ( dm_master_be ),
.size_i ( axi_adapter_size ),
.id_i ( '0 ),
.valid_o ( dm_master_r_valid ),
.rdata_o ( dm_master_r_rdata ),
.id_o ( ),
.critical_word_o ( ),
.critical_word_valid_o ( ),
.axi_req_o ( dm_axi_m_req ),
.axi_resp_i ( dm_axi_m_resp )
);
if (riscv::XLEN==32 ) begin
logic [31 : 0] dm_master_m_awaddr;
logic [31 : 0] dm_master_m_araddr;
assign to_xbar[1].aw_addr = {32'h0000_0000, dm_master_m_awaddr};
assign to_xbar[1].ar_addr = {32'h0000_0000, dm_master_m_araddr};
logic [31 : 0] dm_master_s_rdata;
assign dm_axi_m_resp.r.data = {32'h0000_0000, dm_master_s_rdata};
assign to_xbar[1].aw_user = '0;
assign to_xbar[1].w_user = '0;
assign to_xbar[1].ar_user = '0;
assign to_xbar[1].aw_id = dm_axi_m_req.aw.id;
assign to_xbar[1].ar_id = dm_axi_m_req.ar.id;
assign to_xbar[1].aw_atop = dm_axi_m_req.aw.atop;
xlnx_axi_dwidth_converter_dm_master i_axi_dwidth_converter_dm_master(
.s_axi_aclk(clk),
.s_axi_aresetn(ndmreset_n),
.s_axi_awid(dm_axi_m_req.aw.id),
.s_axi_awaddr(dm_axi_m_req.aw.addr[31:0]),
.s_axi_awlen(dm_axi_m_req.aw.len),
.s_axi_awsize(dm_axi_m_req.aw.size),
.s_axi_awburst(dm_axi_m_req.aw.burst),
.s_axi_awlock(dm_axi_m_req.aw.lock),
.s_axi_awcache(dm_axi_m_req.aw.cache),
.s_axi_awprot(dm_axi_m_req.aw.prot),
.s_axi_awregion(dm_axi_m_req.aw.region),
.s_axi_awqos(dm_axi_m_req.aw.qos),
.s_axi_awvalid(dm_axi_m_req.aw_valid),
.s_axi_awready(dm_axi_m_resp.aw_ready),
.s_axi_wdata(dm_axi_m_req.w.data[31:0]),
.s_axi_wstrb(dm_axi_m_req.w.strb[3:0]),
.s_axi_wlast(dm_axi_m_req.w.last),
.s_axi_wvalid(dm_axi_m_req.w_valid),
.s_axi_wready(dm_axi_m_resp.w_ready),
.s_axi_bid(dm_axi_m_resp.b.id),
.s_axi_bresp(dm_axi_m_resp.b.resp),
.s_axi_bvalid(dm_axi_m_resp.b_valid),
.s_axi_bready(dm_axi_m_req.b_ready),
.s_axi_arid(dm_axi_m_req.ar.id),
.s_axi_araddr(dm_axi_m_req.ar.addr[31:0]),
.s_axi_arlen(dm_axi_m_req.ar.len),
.s_axi_arsize(dm_axi_m_req.ar.size),
.s_axi_arburst(dm_axi_m_req.ar.burst),
.s_axi_arlock(dm_axi_m_req.ar.lock),
.s_axi_arcache(dm_axi_m_req.ar.cache),
.s_axi_arprot(dm_axi_m_req.ar.prot),
.s_axi_arregion(dm_axi_m_req.ar.region),
.s_axi_arqos(dm_axi_m_req.ar.qos),
.s_axi_arvalid(dm_axi_m_req.ar_valid),
.s_axi_arready(dm_axi_m_resp.ar_ready),
.s_axi_rid(dm_axi_m_resp.r.id),
.s_axi_rdata(dm_master_s_rdata),
.s_axi_rresp(dm_axi_m_resp.r.resp),
.s_axi_rlast(dm_axi_m_resp.r.last),
.s_axi_rvalid(dm_axi_m_resp.r_valid),
.s_axi_rready(dm_axi_m_req.r_ready),
.m_axi_awaddr(dm_master_m_awaddr),
.m_axi_awlen(to_xbar[1].aw_len),
.m_axi_awsize(to_xbar[1].aw_size),
.m_axi_awburst(to_xbar[1].aw_burst),
.m_axi_awlock(to_xbar[1].aw_lock),
.m_axi_awcache(to_xbar[1].aw_cache),
.m_axi_awprot(to_xbar[1].aw_prot),
.m_axi_awregion(to_xbar[1].aw_region),
.m_axi_awqos(to_xbar[1].aw_qos),
.m_axi_awvalid(to_xbar[1].aw_valid),
.m_axi_awready(to_xbar[1].aw_ready),
.m_axi_wdata(to_xbar[1].w_data ),
.m_axi_wstrb(to_xbar[1].w_strb),
.m_axi_wlast(to_xbar[1].w_last),
.m_axi_wvalid(to_xbar[1].w_valid),
.m_axi_wready(to_xbar[1].w_ready),
.m_axi_bresp(to_xbar[1].b_resp),
.m_axi_bvalid(to_xbar[1].b_valid),
.m_axi_bready(to_xbar[1].b_ready),
.m_axi_araddr(dm_master_m_araddr),
.m_axi_arlen(to_xbar[1].ar_len),
.m_axi_arsize(to_xbar[1].ar_size),
.m_axi_arburst(to_xbar[1].ar_burst),
.m_axi_arlock(to_xbar[1].ar_lock),
.m_axi_arcache(to_xbar[1].ar_cache),
.m_axi_arprot(to_xbar[1].ar_prot),
.m_axi_arregion(to_xbar[1].ar_region),
.m_axi_arqos(to_xbar[1].ar_qos),
.m_axi_arvalid(to_xbar[1].ar_valid),
.m_axi_arready(to_xbar[1].ar_ready),
.m_axi_rdata(to_xbar[1].r_data),
.m_axi_rresp(to_xbar[1].r_resp),
.m_axi_rlast(to_xbar[1].r_last),
.m_axi_rvalid(to_xbar[1].r_valid),
.m_axi_rready(to_xbar[1].r_ready)
);
end else begin
`AXI_ASSIGN_FROM_REQ(to_xbar[1], dm_axi_m_req)
`AXI_ASSIGN_TO_RESP(dm_axi_m_resp, to_xbar[1])
end
// ---------------
// Cores
// ---------------
ariane_ace::m2s_t [culsans_pkg::NB_CORES-1:0] ace_ariane_req;
ariane_ace::s2m_t [culsans_pkg::NB_CORES-1:0] ace_ariane_resp;
ariane_pkg::rvfi_port_t [culsans_pkg::NB_CORES-1:0] rvfi;
ACE_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( culsans_pkg::IdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) core_to_CCU[culsans_pkg::NB_CORES - 1 : 0]();
SNOOP_BUS
#(
.SNOOP_ADDR_WIDTH (AxiAddrWidth),
.SNOOP_DATA_WIDTH (AxiDataWidth)
)
CCU_to_core[culsans_pkg::NB_CORES-1:0]();
logic [culsans_pkg::NB_CORES-1:0][7:0] hart_id;
for (genvar i = 0; i < culsans_pkg::NB_CORES; i++) begin
assign hart_id[i] = i;
ariane #(
.ArianeCfg ( culsans_pkg::ArianeFpgaSocCfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( culsans_pkg::IdWidth ),
.axi_ar_chan_t ( ariane_ace::ar_chan_t ),
.axi_aw_chan_t ( ariane_ace::aw_chan_t ),
.axi_w_chan_t ( ariane_axi::w_chan_t ),
.axi_req_t ( ariane_ace::m2s_t ),
.axi_rsp_t ( ariane_ace::s2m_t )
) i_ariane (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ),
.hart_id_i ( {56'h0, hart_id[i]} ),
.irq_i ( irq[2*i+1:2*i] ),
.ipi_i ( ipi[i] ),
.time_irq_i ( timer_irq[i] ),
`ifdef RVFI_PORT
.rvfi_o ( rvfi[i] ),
`endif
// Disable Debug when simulating with Spike
`ifdef SPIKE_TANDEM
.debug_req_i ( 1'b0 ),
`else
.debug_req_i ( debug_req_irq[i] ),
`endif
.axi_req_o ( ace_ariane_req[i] ),
.axi_resp_i ( ace_ariane_resp[i] )
);
`ACE_ASSIGN_FROM_REQ(core_to_CCU[i], ace_ariane_req[i])
`ACE_ASSIGN_TO_RESP(ace_ariane_resp[i], core_to_CCU[i])
`SNOOP_ASSIGN_FROM_RESP(CCU_to_core[i], ace_ariane_req[i])
`SNOOP_ASSIGN_TO_REQ(ace_ariane_resp[i], CCU_to_core[i])
end
// ---------------
// CCU
// ---------------
localparam ace_pkg::ccu_cfg_t CCU_CFG = '{
NoSlvPorts: culsans_pkg::NB_CORES,
MaxMstTrans: 2, // Probably requires update
MaxSlvTrans: 2, // Probably requires update
FallThrough: 1'b0,
LatencyMode: ace_pkg::NO_LATENCY,
AxiIdWidthSlvPorts: culsans_pkg::IdWidth,
AxiIdUsedSlvPorts: culsans_pkg::IdWidth,
UniqueIds: 1'b1,
AxiAddrWidth: AxiAddrWidth,
AxiDataWidth: AxiDataWidth
};
ace_ccu_top_intf #(
.AXI_USER_WIDTH ( AxiUserWidth ),
.Cfg ( CCU_CFG )
) i_ccu (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.test_i ( test_en ),
.slv_ports ( core_to_CCU ),
.snoop_ports ( CCU_to_core ),
.mst_ports ( to_xbar[0] )
);
// ---------------
// CLINT
// ---------------
// divide clock by two
always_ff @(posedge clk or negedge ndmreset_n) begin
if (~ndmreset_n) begin
rtc <= 0;
end else begin
rtc <= rtc ^ 1'b1;
end
end
axi_slave_req_t axi_clint_req;
axi_slave_resp_t axi_clint_resp;
clint #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.NR_CORES ( culsans_pkg::NB_CORES ),
.axi_req_t ( axi_slave_req_t ),
.axi_resp_t ( axi_slave_resp_t )
) i_clint (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.testmode_i ( test_en ),
.axi_req_i ( axi_clint_req ),
.axi_resp_o ( axi_clint_resp ),
.rtc_i ( rtc ),
.timer_irq_o ( timer_irq ),
.ipi_o ( ipi )
);
`AXI_ASSIGN_TO_REQ(axi_clint_req, master[ariane_soc::CLINT])
`AXI_ASSIGN_FROM_RESP(master[ariane_soc::CLINT], axi_clint_resp)
// ---------------
// ROM
// ---------------
axi2mem #(
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_axi2rom (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.slave ( master[ariane_soc::ROM] ),
.req_o ( rom_req ),
.we_o ( ),
.addr_o ( rom_addr ),
.be_o ( ),
.data_o ( ),
.data_i ( rom_rdata )
);
if (riscv::XLEN==32 ) begin
bootrom_32 i_bootrom (
.clk_i ( clk ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
end else begin
bootrom_64 i_bootrom (
.clk_i ( clk ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
end
// ---------------
// Peripherals
// ---------------
`ifdef KC705
logic [7:0] unused_led;
logic [3:0] unused_switches = 4'b0000;
`endif
ariane_peripherals #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidthSlaves ),
.AxiUserWidth ( AxiUserWidth ),
.InclUART ( 1'b1 ),
.InclGPIO ( 1'b1 ),
`ifdef KINTEX7
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b1 )
`elsif KC705
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b0 ) // Ethernet requires RAMB16 fpga/src/ariane-ethernet/dualmem_widen8.sv to be defined
`elsif VC707
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b0 )
`elsif VCU118
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
`endif
) i_ariane_peripherals (
.clk_i ( clk ),
.clk_200MHz_i ( ddr_clock_out ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.gpio ( master[ariane_soc::GPIO] ),
.eth_clk_i ( eth_clk ),
.ethernet ( master[ariane_soc::Ethernet] ),
.timer ( master[ariane_soc::Timer] ),
.irq_o ( irq ),
.rx_i ( rx ),
.tx_o ( tx ),
.eth_txck,
.eth_rxck,
.eth_rxctl,
.eth_rxd,
.eth_rst_n,
.eth_txctl,
.eth_txd,
.eth_mdio,
.eth_mdc,
.phy_tx_clk_i ( phy_tx_clk ),
.sd_clk_i ( sd_clk_sys ),
.spi_clk_o ( spi_clk_o ),
.spi_mosi ( spi_mosi ),
.spi_miso ( spi_miso ),
.spi_ss ( spi_ss ),
`ifdef KC705
.leds_o ( {led[3:0], unused_led[7:4]}),
.dip_switches_i ( {sw, unused_switches} )
`else
.leds_o ( led ),
.dip_switches_i ( sw )
`endif
);
// ---------------------
// Board peripherals
// ---------------------
// ---------------
// DDR
// ---------------
logic [AxiIdWidthSlaves-1:0] s_axi_awid;
logic [AxiAddrWidth-1:0] s_axi_awaddr;
logic [7:0] s_axi_awlen;
logic [2:0] s_axi_awsize;
logic [1:0] s_axi_awburst;
logic [0:0] s_axi_awlock;
logic [3:0] s_axi_awcache;
logic [2:0] s_axi_awprot;
logic [3:0] s_axi_awregion;
logic [3:0] s_axi_awqos;
logic s_axi_awvalid;
logic s_axi_awready;
logic [AxiDataWidth-1:0] s_axi_wdata;
logic [AxiDataWidth/8-1:0] s_axi_wstrb;
logic s_axi_wlast;
logic s_axi_wvalid;
logic s_axi_wready;
logic [AxiIdWidthSlaves-1:0] s_axi_bid;
logic [1:0] s_axi_bresp;
logic s_axi_bvalid;
logic s_axi_bready;
logic [AxiIdWidthSlaves-1:0] s_axi_arid;
logic [AxiAddrWidth-1:0] s_axi_araddr;
logic [7:0] s_axi_arlen;
logic [2:0] s_axi_arsize;
logic [1:0] s_axi_arburst;
logic [0:0] s_axi_arlock;
logic [3:0] s_axi_arcache;
logic [2:0] s_axi_arprot;
logic [3:0] s_axi_arregion;
logic [3:0] s_axi_arqos;
logic s_axi_arvalid;
logic s_axi_arready;
logic [AxiIdWidthSlaves-1:0] s_axi_rid;
logic [AxiDataWidth-1:0] s_axi_rdata;
logic [1:0] s_axi_rresp;
logic s_axi_rlast;
logic s_axi_rvalid;
logic s_axi_rready;
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) dram();
axi_riscv_atomics_wrap #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.slv ( master[ariane_soc::DRAM] ),
.mst ( dram )
);
`ifdef PROTOCOL_CHECKER
logic pc_status;
xlnx_protocol_checker i_xlnx_protocol_checker (
.pc_status(),
.pc_asserted(pc_status),
.aclk(clk),
.aresetn(ndmreset_n),
.pc_axi_awid (dram.aw_id),
.pc_axi_awaddr (dram.aw_addr),